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-rw-r--r--Documentation/devicetree/bindings/arm/gic.txt6
-rw-r--r--Documentation/devicetree/bindings/arm/omap/crossbar.txt18
-rw-r--r--Documentation/devicetree/bindings/arm/samsung/pmu.txt17
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt43
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu33
-rw-r--r--arch/arm/boot/dts/am4372.dtsi11
-rw-r--r--arch/arm/boot/dts/am437x-gp-evm.dts1
-rw-r--r--arch/arm/boot/dts/am437x-sk-evm.dts1
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts1
-rw-r--r--arch/arm/boot/dts/am57xx-beagle-x15.dts3
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts2
-rw-r--r--arch/arm/boot/dts/dra7.dtsi43
-rw-r--r--arch/arm/boot/dts/dra72-evm.dts1
-rw-r--r--arch/arm/boot/dts/dra72x.dtsi3
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi5
-rw-r--r--arch/arm/boot/dts/exynos3250.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi4
-rw-r--r--arch/arm/boot/dts/omap4-duovero.dtsi2
-rw-r--r--arch/arm/boot/dts/omap4-panda-common.dtsi8
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts8
-rw-r--r--arch/arm/boot/dts/omap4-var-som-om44.dtsi2
-rw-r--r--arch/arm/boot/dts/omap4.dtsi18
-rw-r--r--arch/arm/boot/dts/omap5-cm-t54.dts1
-rw-r--r--arch/arm/boot/dts/omap5-uevm.dts2
-rw-r--r--arch/arm/boot/dts/omap5.dtsi26
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi16
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi16
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi15
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi16
-rw-r--r--arch/arm/mach-exynos/exynos.c15
-rw-r--r--arch/arm/mach-exynos/suspend.c135
-rw-r--r--arch/arm/mach-omap2/omap-wakeupgen.c128
-rw-r--r--arch/arm/mach-omap2/omap-wakeupgen.h1
-rw-r--r--arch/arm/mach-omap2/omap4-common.c27
-rw-r--r--arch/arm/mach-shmobile/intc-sh73a0.c7
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c7
-rw-r--r--arch/arm/mach-tegra/iomap.h15
-rw-r--r--arch/arm/mach-tegra/irq.c209
-rw-r--r--arch/arm/mach-tegra/irq.h6
-rw-r--r--arch/arm/mach-tegra/tegra.c1
-rw-r--r--arch/arm/mach-ux500/cpu.c2
-rw-r--r--arch/arm/mach-zynq/common.c2
-rw-r--r--drivers/irqchip/Makefile1
-rw-r--r--drivers/irqchip/irq-crossbar.c210
-rw-r--r--drivers/irqchip/irq-gic.c58
-rw-r--r--drivers/irqchip/irq-tegra.c377
-rw-r--r--include/linux/irq.h1
-rw-r--r--include/linux/irqchip/arm-gic.h7
-rw-r--r--include/linux/irqchip/irq-crossbar.h11
-rw-r--r--kernel/irq/chip.c16
52 files changed, 1032 insertions, 538 deletions
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index c97484b73e72..1e0d21201d3a 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -56,11 +56,6 @@ Optional
56 regions, used when the GIC doesn't have banked registers. The offset is 56 regions, used when the GIC doesn't have banked registers. The offset is
57 cpu-offset * cpu-nr. 57 cpu-offset * cpu-nr.
58 58
59- arm,routable-irqs : Total number of gic irq inputs which are not directly
60 connected from the peripherals, but are routed dynamically
61 by a crossbar/multiplexer preceding the GIC. The GIC irq
62 input line is assigned dynamically when the corresponding
63 peripheral's crossbar line is mapped.
64Example: 59Example:
65 60
66 intc: interrupt-controller@fff11000 { 61 intc: interrupt-controller@fff11000 {
@@ -68,7 +63,6 @@ Example:
68 #interrupt-cells = <3>; 63 #interrupt-cells = <3>;
69 #address-cells = <1>; 64 #address-cells = <1>;
70 interrupt-controller; 65 interrupt-controller;
71 arm,routable-irqs = <160>;
72 reg = <0xfff11000 0x1000>, 66 reg = <0xfff11000 0x1000>,
73 <0xfff10100 0x100>; 67 <0xfff10100 0x100>;
74 }; 68 };
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 4139db353d0a..a9b28d74d902 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -9,7 +9,9 @@ inputs.
9Required properties: 9Required properties:
10- compatible : Should be "ti,irq-crossbar" 10- compatible : Should be "ti,irq-crossbar"
11- reg: Base address and the size of the crossbar registers. 11- reg: Base address and the size of the crossbar registers.
12- ti,max-irqs: Total number of irqs available at the interrupt controller. 12- interrupt-controller: indicates that this block is an interrupt controller.
13- interrupt-parent: the interrupt controller this block is connected to.
14- ti,max-irqs: Total number of irqs available at the parent interrupt controller.
13- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed. 15- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
14- ti,reg-size: Size of a individual register in bytes. Every individual 16- ti,reg-size: Size of a individual register in bytes. Every individual
15 register is assumed to be of same size. Valid sizes are 1, 2, 4. 17 register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties:
27 when the interrupt controller irq is unused (when not provided, default is 0) 29 when the interrupt controller irq is unused (when not provided, default is 0)
28 30
29Examples: 31Examples:
30 crossbar_mpu: @4a020000 { 32 crossbar_mpu: crossbar@4a002a48 {
31 compatible = "ti,irq-crossbar"; 33 compatible = "ti,irq-crossbar";
32 reg = <0x4a002a48 0x130>; 34 reg = <0x4a002a48 0x130>;
33 ti,max-irqs = <160>; 35 ti,max-irqs = <160>;
34 ti,max-crossbar-sources = <400>; 36 ti,max-crossbar-sources = <400>;
35 ti,reg-size = <2>; 37 ti,reg-size = <2>;
36 ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>; 38 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
37 ti,irqs-skip = <10 133 139 140>; 39 ti,irqs-skip = <10 133 139 140>;
38 }; 40 };
39 41
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further details.
44 46
45An interrupt consumer on an SoC using crossbar will use: 47An interrupt consumer on an SoC using crossbar will use:
46 interrupts = <GIC_SPI request_number interrupt_level> 48 interrupts = <GIC_SPI request_number interrupt_level>
47When the request number is between 0 to that described by
48"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the
49request_number is greater than "ti,max-crossbar-sources", then it is mapped as a
50quirky hardware mapping direct to GIC.
51 49
52Example: 50Example:
53 device_x@0x4a023000 { 51 device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example:
55 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 53 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
56 ... 54 ...
57 }; 55 };
58
59 device_y@0x4a033000 {
60 /* Direct mapped GIC SPI 1 used */
61 interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;
62 ...
63 };
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 67b211381f2b..2d6356d8daf4 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -29,10 +29,27 @@ Properties:
29 - clocks : list of phandles and specifiers to all input clocks listed in 29 - clocks : list of phandles and specifiers to all input clocks listed in
30 clock-names property. 30 clock-names property.
31 31
32Optional properties:
33
34Some PMUs are capable of behaving as an interrupt controller (mostly
35to wake up a suspended PMU). In which case, they can have the
36following properties:
37
38- interrupt-controller: indicate that said PMU is an interrupt controller
39
40- #interrupt-cells: must be identical to the that of the parent interrupt
41 controller.
42
43- interrupt-parent: a phandle indicating which interrupt controller
44 this PMU signals interrupts to.
45
32Example : 46Example :
33pmu_system_controller: system-controller@10040000 { 47pmu_system_controller: system-controller@10040000 {
34 compatible = "samsung,exynos5250-pmu", "syscon"; 48 compatible = "samsung,exynos5250-pmu", "syscon";
35 reg = <0x10040000 0x5000>; 49 reg = <0x10040000 0x5000>;