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-rw-r--r--include/linux/irq.h2
-rw-r--r--kernel/irq/generic-chip.c16
2 files changed, 18 insertions, 0 deletions
diff --git a/include/linux/irq.h b/include/linux/irq.h
index 0fecd95ba271..8588e5efe577 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -738,12 +738,14 @@ struct irq_chip_generic {
738 * the parent irq. Usually GPIO implementations 738 * the parent irq. Usually GPIO implementations
739 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private 739 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
740 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask 740 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
741 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
741 */ 742 */
742enum irq_gc_flags { 743enum irq_gc_flags {
743 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 744 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
744 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 745 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
745 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, 746 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
746 IRQ_GC_NO_MASK = 1 << 3, 747 IRQ_GC_NO_MASK = 1 << 3,
748 IRQ_GC_BE_IO = 1 << 4,
747}; 749};
748 750
749/* 751/*
diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index db458c68e392..61024e8abdef 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -191,6 +191,16 @@ int irq_gc_set_wake(struct irq_data *d, unsigned int on)
191 return 0; 191 return 0;
192} 192}
193 193
194static u32 irq_readl_be(void __iomem *addr)
195{
196 return ioread32be(addr);
197}
198
199static void irq_writel_be(u32 val, void __iomem *addr)
200{
201 iowrite32be(val, addr);
202}
203
194static void 204static void
195irq_init_generic_chip(struct irq_chip_generic *gc, const char *name, 205irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
196 int num_ct, unsigned int irq_base, 206 int num_ct, unsigned int irq_base,
@@ -300,7 +310,13 @@ int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
300 dgc->gc[i] = gc = tmp; 310 dgc->gc[i] = gc = tmp;
301 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip, 311 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
302 NULL, handler); 312 NULL, handler);
313
303 gc->domain = d; 314 gc->domain = d;
315 if (gcflags & IRQ_GC_BE_IO) {
316 gc->reg_readl = &irq_readl_be;
317 gc->reg_writel = &irq_writel_be;
318 }
319
304 raw_spin_lock_irqsave(&gc_lock, flags); 320 raw_spin_lock_irqsave(&gc_lock, flags);
305 list_add_tail(&gc->list, &gc_list); 321 list_add_tail(&gc->list, &gc_list);
306 raw_spin_unlock_irqrestore(&gc_lock, flags); 322 raw_spin_unlock_irqrestore(&gc_lock, flags);