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-rw-r--r--drivers/media/i2c/adv7604.c898
-rw-r--r--include/media/adv7604.h83
2 files changed, 491 insertions, 490 deletions
diff --git a/drivers/media/i2c/adv7604.c b/drivers/media/i2c/adv7604.c
index 8d455b766cc2..2def57f4e1e2 100644
--- a/drivers/media/i2c/adv7604.c
+++ b/drivers/media/i2c/adv7604.c
@@ -53,41 +53,41 @@ MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
53MODULE_LICENSE("GPL"); 53MODULE_LICENSE("GPL");
54 54
55/* ADV7604 system clock frequency */ 55/* ADV7604 system clock frequency */
56#define ADV7604_fsc (28636360) 56#define ADV76XX_FSC (28636360)
57 57
58#define ADV7604_RGB_OUT (1 << 1) 58#define ADV76XX_RGB_OUT (1 << 1)
59 59
60#define ADV7604_OP_FORMAT_SEL_8BIT (0 << 0) 60#define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
61#define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) 61#define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
62#define ADV7604_OP_FORMAT_SEL_12BIT (2 << 0) 62#define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
63 63
64#define ADV7604_OP_MODE_SEL_SDR_422 (0 << 5) 64#define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
65#define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) 65#define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
66#define ADV7604_OP_MODE_SEL_SDR_444 (2 << 5) 66#define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
67#define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) 67#define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
68#define ADV7604_OP_MODE_SEL_SDR_422_2X (4 << 5) 68#define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
69#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) 69#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
70 70
71#define ADV7604_OP_CH_SEL_GBR (0 << 5) 71#define ADV76XX_OP_CH_SEL_GBR (0 << 5)
72#define ADV7604_OP_CH_SEL_GRB (1 << 5) 72#define ADV76XX_OP_CH_SEL_GRB (1 << 5)
73#define ADV7604_OP_CH_SEL_BGR (2 << 5) 73#define ADV76XX_OP_CH_SEL_BGR (2 << 5)
74#define ADV7604_OP_CH_SEL_RGB (3 << 5) 74#define ADV76XX_OP_CH_SEL_RGB (3 << 5)
75#define ADV7604_OP_CH_SEL_BRG (4 << 5) 75#define ADV76XX_OP_CH_SEL_BRG (4 << 5)
76#define ADV7604_OP_CH_SEL_RBG (5 << 5) 76#define ADV76XX_OP_CH_SEL_RBG (5 << 5)
77 77
78#define ADV7604_OP_SWAP_CB_CR (1 << 0) 78#define ADV76XX_OP_SWAP_CB_CR (1 << 0)
79 79
80enum adv7604_type { 80enum adv76xx_type {
81 ADV7604, 81 ADV7604,
82 ADV7611, 82 ADV7611,
83}; 83};
84 84
85struct adv7604_reg_seq { 85struct adv76xx_reg_seq {
86 unsigned int reg; 86 unsigned int reg;
87 u8 val; 87 u8 val;
88}; 88};
89 89
90struct adv7604_format_info { 90struct adv76xx_format_info {
91 u32 code; 91 u32 code;
92 u8 op_ch_sel; 92 u8 op_ch_sel;
93 bool rgb_out; 93 bool rgb_out;
@@ -95,8 +95,8 @@ struct adv7604_format_info {
95 u8 op_format_sel; 95 u8 op_format_sel;
96}; 96};
97 97
98struct adv7604_chip_info { 98struct adv76xx_chip_info {
99 enum adv7604_type type; 99 enum adv76xx_type type;
100 100
101 bool has_afe; 101 bool has_afe;
102 unsigned int max_port; 102 unsigned int max_port;
@@ -111,7 +111,7 @@ struct adv7604_chip_info {
111 unsigned int fmt_change_digital_mask; 111 unsigned int fmt_change_digital_mask;
112 unsigned int cp_csc; 112 unsigned int cp_csc;
113 113
114 const struct adv7604_format_info *formats; 114 const struct adv76xx_format_info *formats;
115 unsigned int nformats; 115 unsigned int nformats;
116 116
117 void (*set_termination)(struct v4l2_subdev *sd, bool enable); 117 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
@@ -120,7 +120,7 @@ struct adv7604_chip_info {
120 unsigned int (*read_cable_det)(struct v4l2_subdev *sd); 120 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
121 121
122 /* 0 = AFE, 1 = HDMI */ 122 /* 0 = AFE, 1 = HDMI */
123 const struct adv7604_reg_seq *recommended_settings[2]; 123 const struct adv76xx_reg_seq *recommended_settings[2];
124 unsigned int num_recommended_settings[2]; 124 unsigned int num_recommended_settings[2];
125 125
126 unsigned long page_mask; 126 unsigned long page_mask;
@@ -134,22 +134,22 @@ struct adv7604_chip_info {
134 ********************************************************************** 134 **********************************************************************
135 */ 135 */
136 136
137struct adv7604_state { 137struct adv76xx_state {
138 const struct adv7604_chip_info *info; 138 const struct adv76xx_chip_info *info;
139 struct adv7604_platform_data pdata; 139 struct adv76xx_platform_data pdata;
140 140
141 struct gpio_desc *hpd_gpio[4]; 141 struct gpio_desc *hpd_gpio[4];
142 142
143 struct v4l2_subdev sd; 143 struct v4l2_subdev sd;
144 struct media_pad pads[ADV7604_PAD_MAX]; 144 struct media_pad pads[ADV76XX_PAD_MAX];
145 unsigned int source_pad; 145 unsigned int source_pad;
146 146
147 struct v4l2_ctrl_handler hdl; 147 struct v4l2_ctrl_handler hdl;
148 148
149 enum adv7604_pad selected_input; 149 enum adv76xx_pad selected_input;
150 150
151 struct v4l2_dv_timings timings; 151 struct v4l2_dv_timings timings;
152 const struct adv7604_format_info *format; 152 const struct adv76xx_format_info *format;
153 153
154 struct { 154 struct {
155 u8 edid[256]; 155 u8 edid[256];
@@ -164,7 +164,7 @@ struct adv7604_state {
164 bool restart_stdi_once; 164 bool restart_stdi_once;
165 165
166 /* i2c clients */ 166 /* i2c clients */
167 struct i2c_client *i2c_clients[ADV7604_PAGE_MAX]; 167 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
168 168
169 /* controls */ 169 /* controls */
170 struct v4l2_ctrl *detect_tx_5v_ctrl; 170 struct v4l2_ctrl *detect_tx_5v_ctrl;
@@ -174,13 +174,13 @@ struct adv7604_state {
174 struct v4l2_ctrl *rgb_quantization_range_ctrl; 174 struct v4l2_ctrl *rgb_quantization_range_ctrl;
175}; 175};
176 176
177static bool adv7604_has_afe(struct adv7604_state *state) 177static bool adv76xx_has_afe(struct adv76xx_state *state)
178{ 178{
179 return state->info->has_afe; 179 return state->info->has_afe;
180} 180}
181 181
182/* Supported CEA and DMT timings */ 182/* Supported CEA and DMT timings */
183static const struct v4l2_dv_timings adv7604_timings[] = { 183static const struct v4l2_dv_timings adv76xx_timings[] = {
184 V4L2_DV_BT_CEA_720X480P59_94, 184 V4L2_DV_BT_CEA_720X480P59_94,
185 V4L2_DV_BT_CEA_720X576P50, 185 V4L2_DV_BT_CEA_720X576P50,
186 V4L2_DV_BT_CEA_1280X720P24, 186 V4L2_DV_BT_CEA_1280X720P24,
@@ -244,14 +244,14 @@ static const struct v4l2_dv_timings adv7604_timings[] = {
244 { }, 244 { },
245}; 245};
246 246
247struct adv7604_video_standards { 247struct adv76xx_video_standards {
248 struct v4l2_dv_timings timings; 248 struct v4l2_dv_timings timings;
249 u8 vid_std; 249 u8 vid_std;
250 u8 v_freq; 250 u8 v_freq;
251}; 251};
252 252
253/* sorted by number of lines */ 253/* sorted by number of lines */
254static const struct adv7604_video_standards adv7604_prim_mode_comp[] = { 254static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
255 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 255 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
256 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 256 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
257 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 257 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
@@ -266,7 +266,7 @@ static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
266}; 266};
267 267
268/* sorted by number of lines */ 268/* sorted by number of lines */
269static const struct adv7604_video_standards adv7604_prim_mode_gr[] = { 269static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
270 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 270 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
271 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 271 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
272 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 272 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
@@ -294,7 +294,7 @@ static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
294}; 294};
295 295
296/* sorted by number of lines */ 296/* sorted by number of lines */
297static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = { 297static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
298 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 298 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
299 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 299 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
300 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 300 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
@@ -308,7 +308,7 @@ static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
308}; 308};
309 309
310/* sorted by number of lines */ 310/* sorted by number of lines */
311static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = { 311static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
312 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 312 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
313 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 313 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
314 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 314 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
@@ -329,9 +329,9 @@ static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
329 329
330/* ----------------------------------------------------------------------- */ 330/* ----------------------------------------------------------------------- */
331 331
332static inline struct adv7604_state *to_state(struct v4l2_subdev *sd) 332static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
333{ 333{
334 return container_of(sd, struct adv7604_state, sd); 334 return container_of(sd, struct adv76xx_state, sd);
335} 335}
336 336
337static inline unsigned htotal(const struct v4l2_bt_timings *t) 337static inline unsigned htotal(const struct v4l2_bt_timings *t)
@@ -361,15 +361,15 @@ static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
361 return -EIO; 361 return -EIO;
362} 362}
363 363
364static s32 adv_smbus_read_byte_data(struct adv7604_state *state, 364static s32 adv_smbus_read_byte_data(struct adv76xx_state *state,
365 enum adv7604_page page, u8 command) 365 enum adv76xx_page page, u8 command)
366{ 366{
367 return adv_smbus_read_byte_data_check(state->i2c_clients[page], 367 return adv_smbus_read_byte_data_check(state->i2c_clients[page],
368 command, true); 368 command, true);
369} 369}
370 370
371static s32 adv_smbus_write_byte_data(struct adv7604_state *state, 371static s32 adv_smbus_write_byte_data(struct adv76xx_state *state,
372 enum adv7604_page page, u8 command, 372 enum adv76xx_page page, u8 command,
373 u8 value) 373 u8 value)
374{ 374{
375 struct i2c_client *client = state->i2c_clients[page]; 375 struct i2c_client *client = state->i2c_clients[page];
@@ -392,8 +392,8 @@ static s32 adv_smbus_write_byte_data(struct adv7604_state *state,
392 return err; 392 return err;
393} 393}
394 394
395static s32 adv_smbus_write_i2c_block_data(struct adv7604_state *state, 395static s32 adv_smbus_write_i2c_block_data(struct adv76xx_state *state,
396 enum adv7604_page page, u8 command, 396 enum adv76xx_page page, u8 command,
397 unsigned length, const u8 *values) 397 unsigned length, const u8 *values)
398{ 398{
399 struct i2c_client *client = state->i2c_clients[page]; 399 struct i2c_client *client = state->i2c_clients[page];
@@ -412,16 +412,16 @@ static s32 adv_smbus_write_i2c_block_data(struct adv7604_state *state,
412 412
413static inline int io_read(struct v4l2_subdev *sd, u8 reg) 413static inline int io_read(struct v4l2_subdev *sd, u8 reg)
414{ 414{
415 struct adv7604_state *state = to_state(sd); 415 struct adv76xx_state *state = to_state(sd);
416 416
417 return adv_smbus_read_byte_data(state, ADV7604_PAGE_IO, reg); 417 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_IO, reg);
418} 418}
419 419
420static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 420static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
421{ 421{
422 struct adv7604_state *state = to_state(sd); 422 struct adv76xx_state *state = to_state(sd);
423 423
424 return adv_smbus_write_byte_data(state, ADV7604_PAGE_IO, reg, val); 424 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_IO, reg, val);
425} 425}
426 426
427static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 427static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
@@ -431,73 +431,73 @@ static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 v
431 431
432static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 432static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
433{ 433{
434 struct adv7604_state *state = to_state(sd); 434 struct adv76xx_state *state = to_state(sd);
435 435
436 return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg); 436 return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg);
437} 437}
438 438
439static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 439static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
440{ 440{
441 struct adv7604_state *state = to_state(sd); 441 struct adv76xx_state *state = to_state(sd);
442 442
443 return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val); 443 return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val);
444} 444}
445 445
446static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 446static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
447{ 447{
448 struct adv7604_state *state = to_state(sd); 448 struct adv76xx_state *state = to_state(sd);
449 449
450 return adv_smbus_read_byte_data(state, ADV7604_PAGE_CEC, reg); 450 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CEC, reg);
451} 451}
452 452
453static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 453static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
454{ 454{
455 struct adv7604_state *state = to_state(sd); 455 struct adv76xx_state *state = to_state(sd);
456 456
457 return adv_smbus_write_byte_data(state, ADV7604_PAGE_CEC, reg, val); 457 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CEC, reg, val);
458} 458}
459 459
460static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 460static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
461{ 461{
462 struct adv7604_state *state = to_state(sd); 462 struct adv76xx_state *state = to_state(sd);
463 463
464 return adv_smbus_read_byte_data(state, ADV7604_PAGE_INFOFRAME, reg); 464 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_INFOFRAME, reg);
465} 465}
466 466
467static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 467static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
468{ 468{
469 struct adv7604_state *state = to_state(sd); 469 struct adv76xx_state *state = to_state(sd);
470 470
471 return adv_smbus_write_byte_data(state, ADV7604_PAGE_INFOFRAME, 471 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_INFOFRAME,
472 reg, val); 472 reg, val);
473} 473}
474 474
475static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 475static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
476{ 476{
477 struct adv7604_state *state = to_state(sd); 477 struct adv76xx_state *state = to_state(sd);
478 478
479 return adv_smbus_read_byte_data(state, ADV7604_PAGE_AFE, reg); 479 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_AFE, reg);
480} 480}
481 481
482static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 482static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
483{ 483{
484 struct adv7604_state *state = to_state(sd); 484 struct adv76xx_state *state = to_state(sd);
485 485
486 return adv_smbus_write_byte_data(state, ADV7604_PAGE_AFE, reg, val); 486 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_AFE, reg, val);
487} 487}
488 488
489static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 489static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
490{ 490{
491 struct adv7604_state *state = to_state(sd); 491 struct adv76xx_state *state = to_state(sd);
492 492
493 return adv_smbus_read_byte_data(state, ADV7604_PAGE_REP, reg); 493 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_REP, reg);
494} 494}
495 495
496static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 496static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
497{ 497{
498 struct adv7604_state *state = to_state(sd); 498 struct adv76xx_state *state = to_state(sd);
499 499
500 return adv_smbus_write_byte_data(state, ADV7604_PAGE_REP, reg, val); 500 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_REP, reg, val);
501} 501}
502 502
503static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 503static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
@@ -507,34 +507,34 @@ static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8
507 507
508static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 508static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
509{ 509{
510 struct adv7604_state *state = to_state(sd); 510 struct adv76xx_state *state = to_state(sd);
511 511
512 return adv_smbus_read_byte_data(state, ADV7604_PAGE_EDID, reg); 512 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_EDID, reg);
513} 513}
514 514
515static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 515static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
516{ 516{
517 struct adv7604_state *state = to_state(sd); 517 struct adv76xx_state *state = to_state(sd);
518 518
519 return adv_smbus_write_byte_data(state, ADV7604_PAGE_EDID, reg, val); 519 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_EDID, reg, val);
520} 520}
521 521
522static inline int edid_write_block(struct v4l2_subdev *sd, 522static inline int edid_write_block(struct v4l2_subdev *sd,
523 unsigned len, const u8 *val) 523 unsigned len, const u8 *val)
524{ 524{
525 struct adv7604_state *state = to_state(sd); 525 struct adv76xx_state *state = to_state(sd);
526 int err = 0; 526 int err = 0;
527 int i; 527 int i;
528 528
529 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len); 529 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
530 530
531 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX) 531 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
532 err = adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_EDID, 532 err = adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_EDID,
533 i, I2C_SMBUS_BLOCK_MAX, val + i); 533 i, I2C_SMBUS_BLOCK_MAX, val + i);
534 return err; 534 return err;
535} 535}
536 536
537static void adv7604_set_hpd(struct adv7604_state *state, unsigned int hpd) 537static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
538{ 538{
539 unsigned int i; 539 unsigned int i;
540 540
@@ -545,26 +545,26 @@ static void adv7604_set_hpd(struct adv7604_state *state, unsigned int hpd)
545 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); 545 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
546 } 546 }
547 547
548 v4l2_subdev_notify(&state->sd, ADV7604_HOTPLUG, &hpd); 548 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
549} 549}
550 550
551static void adv7604_delayed_work_enable_hotplug(struct work_struct *work) 551static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
552{ 552{
553 struct delayed_work *dwork = to_delayed_work(work); 553 struct delayed_work *dwork = to_delayed_work(work);
554 struct adv7604_state *state = container_of(dwork, struct adv7604_state, 554 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
555 delayed_work_enable_hotplug); 555 delayed_work_enable_hotplug);
556 struct v4l2_subdev *sd = &state->sd; 556 struct v4l2_subdev *sd = &state->sd;
557 557
558 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); 558 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
559 559
560 adv7604_set_hpd(state, state->edid.present); 560 adv76xx_set_hpd(state, state->edid.present);
561} 561}
562 562
563static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 563static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
564{ 564{
565 struct adv7604_state *state = to_state(sd); 565 struct adv76xx_state *state = to_state(sd);
566 566
567 return adv_smbus_read_byte_data(state, ADV7604_PAGE_HDMI, reg); 567 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_HDMI, reg);
568} 568}
569 569
570static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 570static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
@@ -574,9 +574,9 @@ static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
574 574
575static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 575static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
576{ 576{
577 struct adv7604_state *state = to_state(sd); 577 struct adv76xx_state *state = to_state(sd);
578 578
579 return adv_smbus_write_byte_data(state, ADV7604_PAGE_HDMI, reg, val); 579 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_HDMI, reg, val);
580} 580}
581 581
582static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 582static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
@@ -586,16 +586,16 @@ static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8
586 586
587static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) 587static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
588{ 588{
589 struct adv7604_state *state = to_state(sd); 589 struct adv76xx_state *state = to_state(sd);
590 590
591 return adv_smbus_write_byte_data(state, ADV7604_PAGE_TEST, reg, val); 591 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_TEST, reg, val);
592} 592}
593 593
594static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 594static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
595{ 595{
596 struct adv7604_state *state = to_state(sd); 596 struct adv76xx_state *state = to_state(sd);
597 597
598 return adv_smbus_read_byte_data(state, ADV7604_PAGE_CP, reg); 598 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CP, reg);
599} 599}
600 600
601static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 601static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
@@ -605,9 +605,9 @@ static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
605 605
606static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 606static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
607{ 607{
608 struct adv7604_state *state = to_state(sd); 608 struct adv76xx_state *state = to_state(sd);
609 609
610 return adv_smbus_write_byte_data(state, ADV7604_PAGE_CP, reg, val); 610 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CP, reg, val);
611} 611}
612 612
613static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 613static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
@@ -617,25 +617,25 @@ static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 v
617 617
618static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 618static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
619{ 619{
620 struct adv7604_state *state = to_state(sd); 620 struct adv76xx_state *state = to_state(sd);
621 621
622 return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg); 622 return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg);
623} 623}
624 624
625static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 625static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
626{ 626{
627 struct adv7604_state *state = to_state(sd); 627 struct adv76xx_state *state = to_state(sd);
628 628
629 return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val); 629 return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val);
630} 630}
631 631
632#define ADV7604_REG(page, offset) (((page) << 8) | (offset)) 632#define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
633#define ADV7604_REG_SEQ_TERM 0xffff 633#define ADV76XX_REG_SEQ_TERM 0xffff
634 634
635#ifdef CONFIG_VIDEO_ADV_DEBUG 635#ifdef CONFIG_VIDEO_ADV_DEBUG
636static int adv7604_read_reg(struct v4l2_subdev *sd, unsigned int reg) 636static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
637{ 637{
638 struct adv7604_state *state = to_state(sd); 638 struct adv76xx_state *state = to_state(sd);
639 unsigned int page = reg >> 8; 639 unsigned int page = reg >> 8;
640 640
641 if (!(BIT(page) & state->info->page_mask)) 641 if (!(BIT(page) & state->info->page_mask))
@@ -647,9 +647,9 @@ static int adv7604_read_reg(struct v4l2_subdev *sd, unsigned int reg)
647} 647}
648#endif 648#endif
649 649
650static int adv7604_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) 650static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
651{ 651{
652 struct adv7604_state *state = to_state(sd); 652 struct adv76xx_state *state = to_state(sd);
653 unsigned int page = reg >> 8; 653 unsigned int page = reg >> 8;
654 654
655 if (!(BIT(page) & state->info->page_mask)) 655 if (!(BIT(page) & state->info->page_mask))
@@ -660,91 +660,91 @@ static int adv7604_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
660 return adv_smbus_write_byte_data(state, page, reg, val); 660 return adv_smbus_write_byte_data(state, page, reg, val);
661} 661}
662 662
663static void adv7604_write_reg_seq(struct v4l2_subdev *sd, 663static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
664 const struct adv7604_reg_seq *reg_seq) 664 const struct adv76xx_reg_seq *reg_seq)
665{ 665{
666 unsigned int i; 666 unsigned int i;
667 667
668 for (i = 0; reg_seq[i].reg != ADV7604_REG_SEQ_TERM; i++) 668 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
669 adv7604_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); 669 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
670} 670}
671 671
672/* ----------------------------------------------------------------------------- 672/* -----------------------------------------------------------------------------
673 * Format helpers 673 * Format helpers
674 */ 674 */
675 675
676static const struct adv7604_format_info adv7604_formats[] = { 676static const struct adv76xx_format_info adv7604_formats[] = {
677 { MEDIA_BUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, 677 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
678 ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, 678 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
679 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, 679 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
680 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, 680 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
681 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, 681 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
682 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, 682 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
683 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false, 683 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
684 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 684 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
685 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true, 685 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
686 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 686 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
687 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, 687 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
688 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, 688 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
689 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, 689 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
690 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, 690 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
691 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, 691 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
692 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 692 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
693 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, 693 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
694 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 694 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
695 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, 695 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
696 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 696 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
697 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, 697 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
698 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 698 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
699 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false, 699 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
700 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 700 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
701 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7604_OP_CH_SEL_RBG, false, true, 701 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
702 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 702 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
703 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7604_OP_CH_SEL_RGB, false, false, 703 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
704 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 704 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
705 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7604_OP_CH_SEL_RGB, false, true, 705 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
706 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 706 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
707 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false, 707 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
708 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 708 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
709 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true, 709 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
710 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 710 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
711 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false, 711 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
712 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 712 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
713 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true, 713 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
714 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 714 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
715}; 715};
716 716
717static const struct adv7604_format_info adv7611_formats[] = { 717static const struct adv76xx_format_info adv7611_formats[] = {
718 { MEDIA_BUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, 718 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
719 ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, 719 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
720 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, 720 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
721 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, 721 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
722 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, 722 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
723 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, 723 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
724 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, 724 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
725 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, 725 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
726 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, 726 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
727 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, 727 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
728 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, 728 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
729 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 729 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
730 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, 730 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
731 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 731 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
732 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, 732 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
733 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 733 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
734 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, 734 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
735 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 735 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
736 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false, 736 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
737 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 737 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
738 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true, 738 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
739 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 739 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
740 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false, 740 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
741 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 741 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
742 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true, 742 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
743 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 743 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
744}; 744};
745 745
746static const struct adv7604_format_info * 746static const struct adv76xx_format_info *
747adv7604_format_info(struct adv7604_state *state, u32 code) 747adv76xx_format_info(struct adv76xx_state *state, u32 code)
748{ 748{
749 unsigned int i; 749 unsigned int i;
750 750
@@ -760,7 +760,7 @@ adv7604_format_info(struct adv7604_state *state, u32 code)
760 760
761static inline bool is_analog_input(struct v4l2_subdev *sd) 761static inline bool is_analog_input(struct v4l2_subdev *sd)
762{ 762{
763 struct adv7604_state *state = to_state(sd); 763 struct adv76xx_state *state = to_state(sd);
764 764
765 return state->selected_input == ADV7604_PAD_VGA_RGB || 765 return state->selected_input == ADV7604_PAD_VGA_RGB ||
766 state->selected_input == ADV7604_PAD_VGA_COMP; 766 state->selected_input == ADV7604_PAD_VGA_COMP;
@@ -768,9 +768,9 @@ static inline bool is_analog_input(struct v4l2_subdev *sd)
768 768
769static inline bool is_digital_input(struct v4l2_subdev *sd) 769static inline bool is_digital_input(struct v4l2_subdev *sd)
770{ 770{
771 struct adv7604_state *state = to_state(sd); 771 struct adv76xx_state *state = to_state(sd);
772 772
773 return state->selected_input == ADV7604_PAD_HDMI_PORT_A || 773 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
774 state->selected_input == ADV7604_PAD_HDMI_PORT_B || 774 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
775 state->selected_input == ADV7604_PAD_HDMI_PORT_C || 775 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
776 state->selected_input == ADV7604_PAD_HDMI_PORT_D; 776 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
@@ -779,7 +779,7 @@ static inline bool is_digital_input(struct v4l2_subdev *sd)
779/* ----------------------------------------------------------------------- */ 779/* ----------------------------------------------------------------------- */
780 780
781#ifdef CONFIG_VIDEO_ADV_DEBUG 781#ifdef CONFIG_VIDEO_ADV_DEBUG
782static void adv7604_inv_register(struct v4l2_subdev *sd) 782static void adv76xx_inv_register(struct v4l2_subdev *sd)
783{ 783{
784 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 784 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
785 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 785 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
@@ -796,15 +796,15 @@ static void adv7604_inv_register(struct v4l2_subdev *sd)
796 v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); 796 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
797} 797}
798 798
799static int adv7604_g_register(struct v4l2_subdev *sd, 799static int adv76xx_g_register(struct v4l2_subdev *sd,
800 struct v4l2_dbg_register *reg) 800 struct v4l2_dbg_register *reg)
801{ 801{
802 int ret; 802 int ret;
803 803
804 ret = adv7604_read_reg(sd, reg->reg); 804 ret = adv76xx_read_reg(sd, reg->reg);
805 if (ret < 0) { 805 if (ret < 0) {
806 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 806 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
807 adv7604_inv_register(sd); 807 adv76xx_inv_register(sd);
808 return ret; 808 return ret;
809 } 809 }
810 810
@@ -814,15 +814,15 @@ static int adv7604_g_register(struct v4l2_subdev *sd,
814 return 0; 814 return 0;
815} 815}
816 816
817static int adv7604_s_register(struct v4l2_subdev *sd, 817static int adv76xx_s_register(struct v4l2_subdev *sd,
818 const struct v4l2_dbg_register *reg) 818 const struct v4l2_dbg_register *reg)
819{ 819{
820 int ret; 820 int ret;
821 821
822 ret = adv7604_write_reg(sd, reg->reg, reg->val); 822 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
823 if (ret < 0) { 823 if (ret < 0) {
824 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 824 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
825 adv7604_inv_register(sd); 825 adv76xx_inv_register(sd);
826 return ret; 826 return ret;
827 } 827 }
828 828
@@ -847,10 +847,10 @@ static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
847 return value & 1; 847 return value & 1;
848} 848}
849 849
850static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 850static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
851{ 851{
852 struct adv7604_state *state = to_state(sd); 852 struct adv76xx_state *state = to_state(sd);
853 const struct adv7604_chip_info *info = state->info; 853 const struct adv76xx_chip_info *info = state->info;
854 854
855 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 855 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
856 info->read_cable_det(sd)); 856 info->read_cable_det(sd));
@@ -858,7 +858,7 @@ static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
858 858
859static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 859static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
860 u8 prim_mode, 860 u8 prim_mode,
861 const struct adv7604_video_standards *predef_vid_timings, 861 const struct adv76xx_video_standards *predef_vid_timings,
862 const struct v4l2_dv_timings *timings) 862 const struct v4l2_dv_timings *timings)
863{ 863{
864 int i; 864 int i;
@@ -879,12 +879,12 @@ static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
879static int configure_predefined_video_timings(struct v4l2_subdev *sd, 879static int configure_predefined_video_timings(struct v4l2_subdev *sd,
880 struct v4l2_dv_timings *timings) 880 struct v4l2_dv_timings *timings)
881{ 881{
882 struct adv7604_state *state = to_state(sd); 882 struct adv76xx_state *state = to_state(sd);
883 int err; 883 int err;
884 884
885 v4l2_dbg(1, debug, sd, "%s", __func__); 885 v4l2_dbg(1, debug, sd, "%s", __func__);
886 886
887 if (adv7604_has_afe(state)) { 887 if (adv76xx_has_afe(state)) {
888 /* reset to default values */ 888 /* reset to default values */
889 io_write(sd, 0x16, 0x43); 889 io_write(sd, 0x16, 0x43);
890 io_write(sd, 0x17, 0x5a); 890 io_write(sd, 0x17, 0x5a);
@@ -910,10 +910,10 @@ static int configure_predefined_video_timings(struct v4l2_subdev *sd,
910 0x02, adv7604_prim_mode_gr, timings); 910 0x02, adv7604_prim_mode_gr, timings);
911 } else if (is_digital_input(sd)) { 911 } else if (is_digital_input(sd)) {
912 err = find_and_set_predefined_video_timings(sd, 912 err = find_and_set_predefined_video_timings(sd,
913 0x05, adv7604_prim_mode_hdmi_comp, timings); 913 0x05, adv76xx_prim_mode_hdmi_comp, timings);
914 if (err) 914 if (err)
915 err = find_and_set_predefined_video_timings(sd, 915 err = find_and_set_predefined_video_timings(sd,
916 0x06, adv7604_prim_mode_hdmi_gr, timings); 916 0x06, adv76xx_prim_mode_hdmi_gr, timings);
917 } else { 917 } else {
918 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 918 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
919 __func__, state->selected_input); 919 __func__, state->selected_input);
@@ -927,7 +927,7 @@ static int configure_predefined_video_timings(struct v4l2_subdev *sd,
927static void configure_custom_video_timings(struct v4l2_subdev *sd, 927static void configure_custom_video_timings(struct v4l2_subdev *sd,
928 const struct v4l2_bt_timings *bt) 928 const struct v4l2_bt_timings *bt)
929{ 929{
930 struct adv7604_state *state = to_state(sd); 930 struct adv76xx_state *state = to_state(sd);
931 u32 width = htotal(bt); 931 u32 width = htotal(bt);
932 u32 height = vtotal(bt); 932 u32 height = vtotal(bt);
933 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 933 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
@@ -935,7 +935,7 @@ static void configure_custom_video_timings(struct v4l2_subdev *sd,
935 u16 cp_start_vbi = height - bt->vfrontporch; 935 u16 cp_start_vbi = height - bt->vfrontporch;
936 u16 cp_end_vbi = bt->vsync + bt->vbackporch; 936 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
937 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 937 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
938 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; 938 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
939 const u8 pll[2] = { 939 const u8 pll[2] = {
940 0xc0 | ((width >> 8) & 0x1f), 940 0xc0 | ((width >> 8) & 0x1f),
941 width & 0xff 941 width & 0xff
@@ -953,7 +953,7 @@ static void configure_custom_video_timings(struct v4l2_subdev *sd,
953 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 953 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
954 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 954 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
955 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 955 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
956 if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_IO, 956 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_IO,
957 0x16, 2, pll)) 957 0x16, 2, pll))
958 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 958 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
959 959
@@ -984,9 +984,9 @@ static void configure_custom_video_timings(struct v4l2_subdev *sd,
984 cp_write(sd, 0xac, (height & 0x0f) << 4); 984 cp_write(sd, 0xac, (height & 0x0f) << 4);
985} 985}
986 986
987static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 987static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
988{ 988{
989 struct adv7604_state *state = to_state(sd); 989 struct adv76xx_state *state = to_state(sd);
990 u8 offset_buf[4]; 990 u8 offset_buf[4];
991 991
992 if (auto_offset) { 992 if (auto_offset) {
@@ -1005,14 +1005,14 @@ static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 off
1005 offset_buf[3] = offset_c & 0x0ff; 1005 offset_buf[3] = offset_c & 0x0ff;
1006 1006
1007 /* Registers must be written in this order with no i2c access in between */ 1007 /* Registers must be written in this order with no i2c access in between */
1008 if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP, 1008 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP,
1009 0x77, 4, offset_buf)) 1009 0x77, 4, offset_buf))
1010 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 1010 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1011} 1011}
1012 1012
1013static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 1013static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1014{ 1014{
1015 struct adv7604_state *state = to_state(sd); 1015 struct adv76xx_state *state = to_state(sd);
1016 u8 gain_buf[4]; 1016 u8 gain_buf[4];
1017 u8 gain_man = 1; 1017 u8 gain_man = 1;
1018 u8 agc_mode_man = 1; 1018 u8 agc_mode_man = 1;
@@ -1035,14 +1035,14 @@ static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a,
1035 gain_buf[3] = ((gain_c & 0x0ff)); 1035 gain_buf[3] = ((gain_c & 0x0ff));
1036 1036
1037 /* Registers must be written in this order with no i2c access in between */ 1037 /* Registers must be written in this order with no i2c access in between */
1038 if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP, 1038 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP,
1039 0x73, 4, gain_buf)) 1039 0x73, 4, gain_buf))
1040 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 1040 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1041} 1041}
1042 1042
1043static void set_rgb_quantization_range(struct v4l2_subdev *sd) 1043static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1044{ 1044{
1045 struct adv7604_state *state = to_state(sd); 1045 struct adv76xx_state *state = to_state(sd);
1046 bool rgb_output = io_read(sd, 0x02) & 0x02; 1046 bool rgb_output = io_read(sd, 0x02) & 0x02;
1047 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1047 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1048 1048
@@ -1050,8 +1050,8 @@ static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1050 __func__, state->rgb_quantization_range, 1050 __func__, state->rgb_quantization_range,
1051 rgb_output, hdmi_signal); 1051 rgb_output, hdmi_signal);
1052 1052
1053 adv7604_set_gain(sd, true, 0x0, 0x0, 0x0); 1053 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1054 adv7604_set_offset(sd, true, 0x0, 0x0, 0x0); 1054 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
1055 1055
1056 switch (state->rgb_quantization_range) { 1056 switch (state->rgb_quantization_range) {
1057 case V4L2_DV_RGB_RANGE_AUTO: 1057 case V4L2_DV_RGB_RANGE_AUTO:
@@ -1087,10 +1087,10 @@ static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1087 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1087 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1088 1088
1089 if (is_digital_input(sd) && rgb_output) { 1089 if (is_digital_input(sd) && rgb_output) {
1090 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40); 1090 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1091 } else { 1091 } else {
1092 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1092 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1093 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70); 1093 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1094 } 1094 }
1095 } 1095 }
1096 break; 1096 break;
@@ -1120,21 +1120,21 @@ static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1120 1120
1121 /* Adjust gain/offset for DVI-D signals only */ 1121 /* Adjust gain/offset for DVI-D signals only */
1122 if (rgb_output) { 1122 if (rgb_output) {
1123 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40); 1123 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1124 } else { 1124 } else {
1125 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1125 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1126 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70); 1126 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1127 } 1127 }
1128 break; 1128 break;
1129 } 1129 }
1130} 1130}
1131 1131
1132static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl) 1132static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
1133{ 1133{
1134 struct v4l2_subdev *sd = 1134 struct v4l2_subdev *sd =
1135 &container_of(ctrl->handler, struct adv7604_state, hdl)->sd; 1135 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1136 1136
1137 struct adv7604_state *state = to_state(sd); 1137 struct adv76xx_state *state = to_state(sd);
1138 1138
1139 switch (ctrl->id) { 1139 switch (ctrl->id) {
1140 case V4L2_CID_BRIGHTNESS: 1140 case V4L2_CID_BRIGHTNESS:
@@ -1154,7 +1154,7 @@ static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
1154 set_rgb_quantization_range(sd); 1154 set_rgb_quantization_range(sd);
1155 return 0; 1155 return 0;
1156 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1156 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1157 if (!adv7604_has_afe(state)) 1157 if (!adv76xx_has_afe(state))
1158 return -EINVAL; 1158 return -EINVAL;
1159 /* Set the analog sampling phase. This is needed to find the 1159 /* Set the analog sampling phase. This is needed to find the
1160 best sampling phase for analog video: an application or 1160 best sampling phase for analog video: an application or
@@ -1186,15 +1186,15 @@ static inline bool no_power(struct v4l2_subdev *sd)
1186 1186
1187static inline bool no_signal_tmds(struct v4l2_subdev *sd) 1187static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1188{ 1188{
1189 struct adv7604_state *state = to_state(sd); 1189 struct adv76xx_state *state = to_state(sd);
1190 1190
1191 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); 1191 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1192} 1192}
1193 1193
1194static inline bool no_lock_tmds(struct v4l2_subdev *sd) 1194static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1195{ 1195{
1196 struct adv7604_state *state = to_state(sd); 1196 struct adv76xx_state *state = to_state(sd);
1197 const struct adv7604_chip_info *info = state->info; 1197 const struct adv76xx_chip_info *info = state->info;
1198 1198
1199 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; 1199 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1200} 1200}
@@ -1206,13 +1206,13 @@ static inline bool is_hdmi(struct v4l2_subdev *sd)
1206 1206
1207static inline bool no_lock_sspd(struct v4l2_subdev *sd) 1207static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1208{ 1208{
1209 struct adv7604_state *state = to_state(sd); 1209 struct adv76xx_state *state = to_state(sd);
1210 1210
1211 /* 1211 /*
1212 * Chips without a AFE don't expose registers for the SSPD, so just assume 1212 * Chips without a AFE don't expose registers for the SSPD, so just assume
1213 * that we have a lock. 1213 * that we have a lock.
1214 */ 1214 */
1215 if (adv7604_has_afe(state)) 1215 if (adv76xx_has_afe(state))
1216 return false; 1216 return false;
1217 1217
1218 /* TODO channel 2 */ 1218 /* TODO channel 2 */
@@ -1244,9 +1244,9 @@ static inline bool no_signal(struct v4l2_subdev *sd)
1244 1244
1245static inline bool no_lock_cp(struct v4l2_subdev *sd) 1245static inline bool no_lock_cp(struct v4l2_subdev *sd)
1246{ 1246{
1247 struct adv7604_state *state = to_state(sd); 1247 struct adv76xx_state *state = to_state(sd);
1248 1248
1249 if (!adv7604_has_afe(state)) 1249 if (!adv76xx_has_afe(state))
1250 return false; 1250 return false;
1251 1251
1252 /* CP has detected a non standard number of lines on the incoming 1252 /* CP has detected a non standard number of lines on the incoming
@@ -1259,7 +1259,7 @@ static inline bool in_free_run(struct v4l2_subdev *sd)
1259 return cp_read(sd, 0xff) & 0x10; 1259 return cp_read(sd, 0xff) & 0x10;
1260} 1260}
1261 1261
1262static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status) 1262static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
1263{ 1263{
1264 *status = 0; 1264 *status = 0;
1265 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; 1265 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
@@ -1285,22 +1285,22 @@ static int stdi2dv_timings(struct v4l2_subdev *sd,
1285 struct stdi_readback *stdi, 1285 struct stdi_readback *stdi,
1286 struct v4l2_dv_timings *timings) 1286 struct v4l2_dv_timings *timings)
1287{ 1287{
1288 struct adv7604_state *state = to_state(sd); 1288 struct adv76xx_state *state = to_state(sd);
1289 u32 hfreq = (ADV7604_fsc * 8) / stdi->bl; 1289 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
1290 u32 pix_clk; 1290 u32 pix_clk;
1291 int i; 1291 int i;
1292 1292
1293 for (i = 0; adv7604_timings[i].bt.height; i++) { 1293 for (i = 0; adv76xx_timings[i].bt.height; i++) {
1294 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1) 1294 if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1)
1295 continue; 1295 continue;
1296 if (adv7604_timings[i].bt.vsync != stdi->lcvs) 1296 if (adv76xx_timings[i].bt.vsync != stdi->lcvs)
1297 continue; 1297 continue;
1298 1298
1299 pix_clk = hfreq * htotal(&adv7604_timings[i].bt); 1299 pix_clk = hfreq * htotal(&adv76xx_timings[i].bt);
1300 1300
1301 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) && 1301 if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) &&
1302 (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) { 1302 (pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) {
1303 *timings = adv7604_timings[i]; 1303 *timings = adv76xx_timings[i];
1304 return 0; 1304 return 0;
1305 } 1305 }
1306 } 1306 }
@@ -1326,8 +1326,8 @@ static int stdi2dv_timings(struct v4l2_subdev *sd,
1326 1326
1327static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1327static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1328{ 1328{
1329 struct adv7604_state *state = to_state(sd); 1329 struct adv76xx_state *state = to_state(sd);
1330 const struct adv7604_chip_info *info = state->info; 1330 const struct adv76xx_chip_info *info = state->info;
1331 u8 polarity; 1331 u8 polarity;
1332 1332
1333 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 1333 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
@@ -1341,7 +1341,7 @@ static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1341 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1341 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1342 stdi->interlaced = io_read(sd, 0x12) & 0x10; 1342 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1343 1343
1344 if (adv7604_has_afe(state)) { 1344 if (adv76xx_has_afe(state)) {
1345 /* read SSPD */ 1345 /* read SSPD */
1346 polarity = cp_read(sd, 0xb5); 1346 polarity = cp_read(sd, 0xb5);
1347 if ((polarity & 0x03) == 0x01) { 1347 if ((polarity & 0x03) == 0x01) {
@@ -1380,26 +1380,26 @@ static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1380 return 0; 1380 return 0;
1381} 1381}
1382 1382
1383static int adv7604_enum_dv_timings(struct v4l2_subdev *sd, 1383static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
1384 struct v4l2_enum_dv_timings *timings) 1384 struct v4l2_enum_dv_timings *timings)
1385{ 1385{
1386 struct adv7604_state *state = to_state(sd); 1386 struct adv76xx_state *state = to_state(sd);
1387 1387
1388 if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1) 1388 if (timings->index >= ARRAY_SIZE(adv76xx_timings) - 1)
1389 return -EINVAL; 1389 return -EINVAL;
1390 1390
1391 if (timings->pad >= state->source_pad) 1391 if (timings->pad >= state->source_pad)
1392 return -EINVAL; 1392 return -EINVAL;
1393 1393
1394 memset(timings->reserved, 0, sizeof(timings->reserved)); 1394 memset(timings->reserved, 0, sizeof(timings->reserved));
1395 timings->timings = adv7604_timings[timings->index]; 1395 timings->timings = adv76xx_timings[timings->index];
1396 return 0; 1396 return 0;
1397} 1397}
1398 1398
1399static int adv7604_dv_timings_cap(struct v4l2_subdev *sd, 1399static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
1400 struct v4l2_dv_timings_cap *cap) 1400 struct v4l2_dv_timings_cap *cap)
1401{ 1401{
1402 struct adv7604_state *state = to_state(sd); 1402 struct adv76xx_state *state = to_state(sd);
1403 1403
1404 if (cap->pad >= state->source_pad) 1404 if (cap->pad >= state->source_pad)
1405 return -EINVAL; 1405 return -EINVAL;
@@ -1410,7 +1410,7 @@ static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1410 cap->bt.min_pixelclock = 25000000; 1410 cap->bt.min_pixelclock = 25000000;
1411 1411
1412 switch (cap->pad) { 1412 switch (cap->pad) {
1413 case ADV7604_PAD_HDMI_PORT_A: 1413 case ADV76XX_PAD_HDMI_PORT_A:
1414 case ADV7604_PAD_HDMI_PORT_B: 1414 case ADV7604_PAD_HDMI_PORT_B:
1415 case ADV7604_PAD_HDMI_PORT_C: 1415 case ADV7604_PAD_HDMI_PORT_C:
1416 case ADV7604_PAD_HDMI_PORT_D: 1416 case ADV7604_PAD_HDMI_PORT_D:
@@ -1431,16 +1431,16 @@ static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1431} 1431}
1432 1432
1433/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1433/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1434 if the format is listed in adv7604_timings[] */ 1434 if the format is listed in adv76xx_timings[] */
1435static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1435static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1436 struct v4l2_dv_timings *timings) 1436 struct v4l2_dv_timings *timings)
1437{ 1437{
1438 int i; 1438 int i;
1439 1439
1440 for (i = 0; adv7604_timings[i].bt.width; i++) { 1440 for (i = 0; adv76xx_timings[i].bt.width; i++) {
1441 if (v4l2_match_dv_timings(timings, &adv7604_timings[i], 1441 if (v4l2_match_dv_timings(timings, &adv76xx_timings[i],
1442 is_digital_input(sd) ? 250000 : 1000000)) { 1442 is_digital_input(sd) ? 250000 : 1000000)) {
1443 *timings = adv7604_timings[i]; 1443 *timings = adv76xx_timings[i];
1444 break; 1444 break;
1445 } 1445 }
1446 } 1446 }
@@ -1478,11 +1478,11 @@ static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1478 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; 1478 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1479} 1479}
1480 1480
1481static int adv7604_query_dv_timings(struct v4l2_subdev *sd, 1481static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
1482 struct v4l2_dv_timings *timings) 1482 struct v4l2_dv_timings *timings)
1483{ 1483{
1484 struct adv7604_state *state = to_state(sd); 1484 struct adv76xx_state *state = to_state(sd);
1485 const struct adv7604_chip_info *info = state->info; 1485 const struct adv76xx_chip_info *info = state->info;
1486 struct v4l2_bt_timings *bt = &timings->bt; 1486 struct v4l2_bt_timings *bt = &timings->bt;
1487 struct stdi_readback stdi; 1487 struct stdi_readback stdi;
1488 1488
@@ -1526,7 +1526,7 @@ static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1526 bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2; 1526 bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2;
1527 bt->il_vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2; 1527 bt->il_vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2;
1528 } 1528 }
1529 adv7604_fill_optional_dv_timings_fields(sd, timings); 1529 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1530 } else { 1530 } else {
1531 /* find format 1531 /* find format
1532 * Since LCVS values are inaccurate [REF_03, p. 275-276], 1532 * Since LCVS values are inaccurate [REF_03, p. 275-276],
@@ -1583,16 +1583,16 @@ found:
1583 } 1583 }
1584 1584
1585 if (debug > 1) 1585 if (debug > 1)
1586 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ", 1586 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
1587 timings, true); 1587 timings, true);
1588 1588
1589 return 0; 1589 return 0;
1590} 1590}
1591 1591
1592static int adv7604_s_dv_timings(struct v4l2_subdev *sd, 1592static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
1593 struct v4l2_dv_timings *timings) 1593 struct v4l2_dv_timings *timings)
1594{ 1594{
1595 struct adv7604_state *state = to_state(sd); 1595 struct adv76xx_state *state = to_state(sd);
1596 struct v4l2_bt_timings *bt; 1596 struct v4l2_bt_timings *bt;
1597 int err; 1597 int err;
1598 1598
@@ -1613,7 +1613,7 @@ static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1613 return -ERANGE; 1613 return -ERANGE;
1614 } 1614 }
1615 1615
1616 adv7604_fill_optional_dv_timings_fields(sd, timings); 1616 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1617 1617
1618 state->timings = *timings; 1618 state->timings = *timings;
1619 1619
@@ -1630,15 +1630,15 @@ static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1630 set_rgb_quantization_range(sd); 1630 set_rgb_quantization_range(sd);
1631 1631
1632 if (debug > 1) 1632 if (debug > 1)
1633 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ", 1633 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
1634 timings, true); 1634 timings, true);
1635 return 0; 1635 return 0;
1636} 1636}
1637 1637
1638static int adv7604_g_dv_timings(struct v4l2_subdev *sd, 1638static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
1639 struct v4l2_dv_timings *timings) 1639 struct v4l2_dv_timings *timings)
1640{ 1640{
1641 struct adv7604_state *state = to_state(sd); 1641 struct adv76xx_state *state = to_state(sd);
1642 1642
1643 *timings = state->timings; 1643 *timings = state->timings;
1644 return 0; 1644 return 0;
@@ -1656,7 +1656,7 @@ static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1656 1656
1657static void enable_input(struct v4l2_subdev *sd) 1657static void enable_input(struct v4l2_subdev *sd)
1658{ 1658{
1659 struct adv7604_state *state = to_state(sd); 1659 struct adv76xx_state *state = to_state(sd);
1660 1660
1661 if (is_analog_input(sd)) { 1661 if (is_analog_input(sd)) {
1662 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1662 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
@@ -1673,7 +1673,7 @@ static void enable_input(struct v4l2_subdev *sd)
1673 1673
1674static void disable_input(struct v4l2_subdev *sd) 1674static void disable_input(struct v4l2_subdev *sd)
1675{ 1675{
1676 struct adv7604_state *state = to_state(sd); 1676 struct adv76xx_state *state = to_state(sd);
1677 1677
1678 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ 1678 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1679 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ 1679 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
@@ -1683,11 +1683,11 @@ static void disable_input(struct v4l2_subdev *sd)
1683 1683
1684static void select_input(struct v4l2_subdev *sd) 1684static void select_input(struct v4l2_subdev *sd)
1685{ 1685{
1686 struct adv7604_state *state = to_state(sd); 1686 struct adv76xx_state *state = to_state(sd);
1687 const struct adv7604_chip_info *info = state->info; 1687 const struct adv76xx_chip_info *info = state->info;
1688 1688
1689 if (is_analog_input(sd)) { 1689 if (is_analog_input(sd)) {
1690 adv7604_write_reg_seq(sd, info->recommended_settings[0]); 1690 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
1691 1691
1692 afe_write(sd, 0x00, 0x08); /* power up ADC */ 1692 afe_write(sd, 0x00, 0x08); /* power up ADC */
1693 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ 1693 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
@@ -1695,9 +1695,9 @@ static void select_input(struct v4l2_subdev *sd)
1695 } else if (is_digital_input(sd)) { 1695 } else if (is_digital_input(sd)) {
1696 hdmi_write(sd, 0x00, state->selected_input & 0x03); 1696 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1697 1697
1698 adv7604_write_reg_seq(sd, info->recommended_settings[1]); 1698 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
1699 1699
1700 if (adv7604_has_afe(state)) { 1700 if (adv76xx_has_afe(state)) {
1701 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1701 afe_write(sd, 0x00, 0xff); /* power down ADC */
1702 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ 1702 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1703 afe_write(sd, 0xc8, 0x40); /* phase control */ 1703 afe_write(sd, 0xc8, 0x40); /* phase control */
@@ -1712,10 +1712,10 @@ static void select_input(struct v4l2_subdev *sd)
1712 } 1712 }
1713} 1713}
1714 1714
1715static int adv7604_s_routing(struct v4l2_subdev *sd, 1715static int adv76xx_s_routing(struct v4l2_subdev *sd,
1716 u32 input, u32 output, u32 config) 1716 u32 input, u32 output, u32 config)
1717{ 1717{
1718 struct adv7604_state *state = to_state(sd); 1718 struct adv76xx_state *state = to_state(sd);
1719 1719
1720 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", 1720 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1721 __func__, input, state->selected_input); 1721 __func__, input, state->selected_input);
@@ -1737,11 +1737,11 @@ static int adv7604_s_routing(struct v4l2_subdev *sd,
1737 return 0; 1737 return 0;
1738} 1738}
1739 1739
1740static int adv7604_enum_mbus_code(struct v4l2_subdev *sd, 1740static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
1741 struct v4l2_subdev_fh *fh, 1741 struct v4l2_subdev_fh *fh,
1742 struct v4l2_subdev_mbus_code_enum *code) 1742 struct v4l2_subdev_mbus_code_enum *code)
1743{ 1743{
1744 struct adv7604_state *state = to_state(sd); 1744 struct adv76xx_state *state = to_state(sd);
1745 1745
1746 if (code->index >= state->info->nformats) 1746 if (code->index >= state->info->nformats)
1747 return -EINVAL; 1747 return -EINVAL;
@@ -1751,7 +1751,7 @@ static int adv7604_enum_mbus_code(struct v4l2_subdev *sd,
1751 return 0; 1751 return 0;
1752} 1752}
1753 1753
1754static void adv7604_fill_format(struct adv7604_state *state, 1754static void adv76xx_fill_format(struct adv76xx_state *state,
1755 struct v4l2_mbus_framefmt *format) 1755 struct v4l2_mbus_framefmt *format)
1756{ 1756{
1757 memset(format, 0, sizeof(*format)); 1757 memset(format, 0, sizeof(*format));
@@ -1772,7 +1772,7 @@ static void adv7604_fill_format(struct adv7604_state *state,
1772 * 1772 *
1773 * The following table gives the op_ch_value from the format component order 1773 * The following table gives the op_ch_value from the format component order
1774 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 1774 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1775 * adv7604_bus_order value in row). 1775 * adv76xx_bus_order value in row).
1776 * 1776 *
1777 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 1777 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1778 * ----------+------------------------------------------------- 1778 * ----------+-------------------------------------------------
@@ -1783,11 +1783,11 @@ static void adv7604_fill_format(struct adv7604_state *state,
1783 * BRG (ROR) | BRG RBG GRB GBR RGB BGR 1783 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1784 * GBR (ROL) | RGB BGR RBG BRG GBR GRB 1784 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1785 */ 1785 */
1786static unsigned int adv7604_op_ch_sel(struct adv7604_state *state) 1786static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
1787{ 1787{
1788#define _SEL(a,b,c,d,e,f) { \ 1788#define _SEL(a,b,c,d,e,f) { \
1789 ADV7604_OP_CH_SEL_##a, ADV7604_OP_CH_SEL_##b, ADV7604_OP_CH_SEL_##c, \ 1789 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1790 ADV7604_OP_CH_SEL_##d, ADV7604_OP_CH_SEL_##e, ADV7604_OP_CH_SEL_##f } 1790 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
1791#define _BUS(x) [ADV7604_BUS_ORDER_##x] 1791#define _BUS(x) [ADV7604_BUS_ORDER_##x]
1792 1792
1793 static const unsigned int op_ch_sel[6][6] = { 1793 static const unsigned int op_ch_sel[6][6] = {
@@ -1802,28 +1802,28 @@ static unsigned int adv7604_op_ch_sel(struct adv7604_state *state)
1802 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 1802 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1803} 1803}
1804 1804
1805static void adv7604_setup_format(struct adv7604_state *state) 1805static void adv76xx_setup_format(struct adv76xx_state *state)
1806{ 1806{
1807 struct v4l2_subdev *sd = &state->sd; 1807 struct v4l2_subdev *sd = &state->sd;
1808 1808
1809 io_write_clr_set(sd, 0x02, 0x02, 1809 io_write_clr_set(sd, 0x02, 0x02,
1810 state->format->rgb_out ? ADV7604_RGB_OUT : 0); 1810 state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
1811 io_write(sd, 0x03, state->format->op_format_sel | 1811 io_write(sd, 0x03, state->format->op_format_sel |
1812 state->pdata.op_format_mode_sel); 1812 state->pdata.op_format_mode_sel);
1813 io_write_clr_set(sd, 0x04, 0xe0, adv7604_op_ch_sel(state)); 1813 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
1814 io_write_clr_set(sd, 0x05, 0x01, 1814 io_write_clr_set(sd, 0x05, 0x01,
1815 state->format->swap_cb_cr ? ADV7604_OP_SWAP_CB_CR : 0); 1815 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
1816} 1816}
1817 1817
1818static int adv7604_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, 1818static int adv76xx_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1819 struct v4l2_subdev_format *format) 1819 struct v4l2_subdev_format *format)
1820{ 1820{
1821 struct adv7604_state *state = to_state(sd); 1821 struct adv76xx_state *state = to_state(sd);
1822 1822
1823 if (format->pad != state->source_pad) 1823 if (format->pad != state->source_pad)
1824 return -EINVAL; 1824 return -EINVAL;
1825 1825
1826 adv7604_fill_format(state, &format->format); 1826 adv76xx_fill_format(state, &format->format);
1827 1827
1828 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1828 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1829 struct v4l2_mbus_framefmt *fmt; 1829 struct v4l2_mbus_framefmt *fmt;
@@ -1837,20 +1837,20 @@ static int adv7604_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1837 return 0; 1837 return 0;
1838} 1838}
1839 1839
1840static int adv7604_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, 1840static int adv76xx_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1841 struct v4l2_subdev_format *format) 1841 struct v4l2_subdev_format *format)
1842{ 1842{
1843 struct adv7604_state *state = to_state(sd); 1843 struct adv76xx_state *state = to_state(sd);
1844 const struct adv7604_format_info *info; 1844 const struct adv76xx_format_info *info;
1845 1845
1846 if (format->pad != state->source_pad) 1846 if (format->pad != state->source_pad)
1847 return -EINVAL; 1847 return -EINVAL;
1848 1848
1849 info = adv7604_format_info(state, format->format.code); 1849 info = adv76xx_format_info(state, format->format.code);
1850 if (info == NULL) 1850 if (info == NULL)
1851 info = adv7604_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 1851 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1852 1852
1853 adv7604_fill_format(state, &format->format); 1853 adv76xx_fill_format(state, &format->format);
1854 format->format.code = info->code; 1854 format->format.code = info->code;
1855 1855
1856 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1856 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
@@ -1860,16 +1860,16 @@ static int adv7604_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1860 fmt->code = format->format.code; 1860 fmt->code = format->format.code;
1861 } else { 1861 } else {
1862 state->format = info; 1862 state->format = info;
1863 adv7604_setup_format(state); 1863 adv76xx_setup_format(state);
1864 } 1864 }
1865 1865
1866 return 0; 1866 return 0;
1867} 1867}
1868 1868
1869static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 1869static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1870{ 1870{
1871 struct adv7604_state *state = to_state(sd); 1871 struct adv76xx_state *state = to_state(sd);
1872 const struct adv7604_chip_info *info = state->info; 1872 const struct adv76xx_chip_info *info = state->info;
1873 const u8 irq_reg_0x43 = io_read(sd, 0x43); 1873 const u8 irq_reg_0x43 = io_read(sd, 0x43);
1874 const u8 irq_reg_0x6b = io_read(sd, 0x6b); 1874 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1875 const u8 irq_reg_0x70 = io_read(sd, 0x70); 1875 const u8 irq_reg_0x70 = io_read(sd, 0x70);
@@ -1897,7 +1897,7 @@ static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1897 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", 1897 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1898 __func__, fmt_change, fmt_change_digital); 1898 __func__, fmt_change, fmt_change_digital);
1899 1899
1900 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL); 1900 v4l2_subdev_notify(sd, ADV76XX_FMT_CHANGE, NULL);
1901 1901
1902 if (handled) 1902 if (handled)
1903 *handled = true; 1903 *handled = true;
@@ -1916,22 +1916,22 @@ static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1916 if (tx_5v) { 1916 if (tx_5v) {
1917 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); 1917 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1918 io_write(sd, 0x71, tx_5v); 1918 io_write(sd, 0x71, tx_5v);
1919 adv7604_s_detect_tx_5v_ctrl(sd); 1919 adv76xx_s_detect_tx_5v_ctrl(sd);
1920 if (handled) 1920 if (handled)
1921 *handled = true; 1921 *handled = true;
1922 } 1922 }
1923 return 0; 1923 return 0;
1924} 1924}
1925 1925
1926static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 1926static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1927{ 1927{
1928 struct adv7604_state *state = to_state(sd); 1928 struct adv76xx_state *state = to_state(sd);
1929 u8 *data = NULL; 1929 u8 *data = NULL;
1930 1930
1931 memset(edid->reserved, 0, sizeof(edid->reserved)); 1931 memset(edid->reserved, 0, sizeof(edid->reserved));
1932 1932
1933 switch (edid->pad) { 1933 switch (edid->pad) {
1934 case ADV7604_PAD_HDMI_PORT_A: 1934 case ADV76XX_PAD_HDMI_PORT_A:
1935 case ADV7604_PAD_HDMI_PORT_B: 1935 case ADV7604_PAD_HDMI_PORT_B:
1936 case ADV7604_PAD_HDMI_PORT_C: 1936 case ADV7604_PAD_HDMI_PORT_C:
1937 case ADV7604_PAD_HDMI_PORT_D: 1937 case ADV7604_PAD_HDMI_PORT_D:
@@ -1989,10 +1989,10 @@ static int get_edid_spa_location(const u8 *edid)
1989 return -1; 1989 return -1;
1990} 1990}
1991 1991
1992static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 1992static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1993{ 1993{
1994 struct adv7604_state *state = to_state(sd); 1994 struct adv76xx_state *state = to_state(sd);
1995 const struct adv7604_chip_info *info = state->info; 1995 const struct adv76xx_chip_info *info = state->info;
1996 int spa_loc; 1996 int spa_loc;
1997 int err; 1997 int err;
1998 int i; 1998 int i;
@@ -2006,7 +2006,7 @@ static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2006 if (edid->blocks == 0) { 2006 if (edid->blocks == 0) {
2007 /* Disable hotplug and I2C access to EDID RAM from DDC port */ 2007 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2008 state->edid.present &= ~(1 << edid->pad); 2008 state->edid.present &= ~(1 << edid->pad);
2009 adv7604_set_hpd(state, state->edid.present); 2009 adv76xx_set_hpd(state, state->edid.present);
2010 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2010 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2011 2011
2012 /* Fall back to a 16:9 aspect ratio */ 2012 /* Fall back to a 16:9 aspect ratio */
@@ -2030,7 +2030,7 @@ static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2030 2030
2031 /* Disable hotplug and I2C access to EDID RAM from DDC port */ 2031 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2032 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 2032 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2033 adv7604_set_hpd(state, 0); 2033 adv76xx_set_hpd(state, 0);
2034 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); 2034 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2035 2035
2036 spa_loc = get_edid_spa_location(edid->edid); 2036 spa_loc = get_edid_spa_location(edid->edid);
@@ -2038,7 +2038,7 @@ static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2038 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */ 2038 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2039 2039
2040 switch (edid->pad) { 2040 switch (edid->pad) {
2041 case ADV7604_PAD_HDMI_PORT_A: 2041 case ADV76XX_PAD_HDMI_PORT_A:
2042 state->spa_port_a[0] = edid->edid[spa_loc]; 2042 state->spa_port_a[0] = edid->edid[spa_loc];
2043 state->spa_port_a[1] = edid->edid[spa_loc + 1]; 2043 state->spa_port_a[1] = edid->edid[spa_loc + 1];
2044 break; 2044 break;
@@ -2081,7 +2081,7 @@ static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2081 return err; 2081 return err;
2082 } 2082 }
2083 2083
2084 /* adv7604 calculates the checksums and enables I2C access to internal 2084 /* adv76xx calculates the checksums and enables I2C access to internal
2085 EDID RAM from DDC port. */ 2085 EDID RAM from DDC port. */
2086 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2086 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2087 2087
@@ -2145,10 +2145,10 @@ static void print_avi_infoframe(struct v4l2_subdev *sd)
2145 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]); 2145 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2146} 2146}
2147 2147
2148static int adv7604_log_status(struct v4l2_subdev *sd) 2148static int adv76xx_log_status(struct v4l2_subdev *sd)
2149{ 2149{
2150 struct adv7604_state *state = to_state(sd); 2150 struct adv76xx_state *state = to_state(sd);
2151 const struct adv7604_chip_info *info = state->info; 2151 const struct adv76xx_chip_info *info = state->info;
2152 struct v4l2_dv_timings timings; 2152 struct v4l2_dv_timings timings;
2153 struct stdi_readback stdi; 2153 struct stdi_readback stdi;
2154 u8 reg_io_0x02 = io_read(sd, 0x02); 2154 u8 reg_io_0x02 = io_read(sd, 0x02);
@@ -2220,7 +2220,7 @@ static int adv7604_log_status(struct v4l2_subdev *sd)
2220 stdi.lcf, stdi.bl, stdi.lcvs, 2220 stdi.lcf, stdi.bl, stdi.lcvs,
2221 stdi.interlaced ? "interlaced" : "progressive", 2221 stdi.interlaced ? "interlaced" : "progressive",
2222 stdi.hs_pol, stdi.vs_pol); 2222 stdi.hs_pol, stdi.vs_pol);
2223 if (adv7604_query_dv_timings(sd, &timings)) 2223 if (adv76xx_query_dv_timings(sd, &timings))
2224 v4l2_info(sd, "No video detected\n"); 2224 v4l2_info(sd, "No video detected\n");
2225 else 2225 else
2226 v4l2_print_dv_timings(sd->name, "Detected format: ", 2226 v4l2_print_dv_timings(sd->name, "Detected format: ",
@@ -2286,47 +2286,47 @@ static int adv7604_log_status(struct v4l2_subdev *sd)
2286 2286
2287/* ----------------------------------------------------------------------- */ 2287/* ----------------------------------------------------------------------- */
2288 2288
2289static const struct v4l2_ctrl_ops adv7604_ctrl_ops = { 2289static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2290 .s_ctrl = adv7604_s_ctrl, 2290 .s_ctrl = adv76xx_s_ctrl,
2291}; 2291};
2292 2292
2293static const struct v4l2_subdev_core_ops adv7604_core_ops = { 2293static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2294 .log_status = adv7604_log_status, 2294 .log_status = adv76xx_log_status,
2295 .interrupt_service_routine = adv7604_isr, 2295 .interrupt_service_routine = adv76xx_isr,
2296#ifdef CONFIG_VIDEO_ADV_DEBUG 2296#ifdef CONFIG_VIDEO_ADV_DEBUG
2297 .g_register = adv7604_g_register, 2297 .g_register = adv76xx_g_register,
2298 .s_register = adv7604_s_register, 2298 .s_register = adv76xx_s_register,
2299#endif 2299#endif
2300}; 2300};
2301 2301
2302static const struct v4l2_subdev_video_ops adv7604_video_ops = { 2302static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2303 .s_routing = adv7604_s_routing, 2303 .s_routing = adv76xx_s_routing,
2304 .g_input_status = adv7604_g_input_status, 2304 .g_input_status = adv76xx_g_input_status,
2305 .s_dv_timings = adv7604_s_dv_timings, 2305 .s_dv_timings = adv76xx_s_dv_timings,
2306 .g_dv_timings = adv7604_g_dv_timings, 2306 .g_dv_timings = adv76xx_g_dv_timings,
2307 .query_dv_timings = adv7604_query_dv_timings, 2307 .query_dv_timings = adv76xx_query_dv_timings,
2308}; 2308};
2309 2309
2310static const struct v4l2_subdev_pad_ops adv7604_pad_ops = { 2310static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2311 .enum_mbus_code = adv7604_enum_mbus_code, 2311 .enum_mbus_code = adv76xx_enum_mbus_code,
2312 .get_fmt = adv7604_get_format, 2312 .get_fmt = adv76xx_get_format,
2313 .set_fmt = adv7604_set_format, 2313 .set_fmt = adv76xx_set_format,
2314 .get_edid = adv7604_get_edid, 2314 .get_edid = adv76xx_get_edid,
2315 .set_edid = adv7604_set_edid, 2315 .set_edid = adv76xx_set_edid,
2316 .dv_timings_cap = adv7604_dv_timings_cap, 2316 .dv_timings_cap = adv76xx_dv_timings_cap,
2317 .enum_dv_timings = adv7604_enum_dv_timings, 2317 .enum_dv_timings = adv76xx_enum_dv_timings,
2318}; 2318};
2319 2319
2320static const struct v4l2_subdev_ops adv7604_ops = { 2320static const struct v4l2_subdev_ops adv76xx_ops = {
2321 .core = &adv7604_core_ops, 2321 .core = &adv76xx_core_ops,
2322 .video = &adv7604_video_ops, 2322 .video = &adv76xx_video_ops,
2323 .pad = &adv7604_pad_ops, 2323 .pad = &adv76xx_pad_ops,
2324}; 2324};
2325 2325
2326/* -------------------------- custom ctrls ---------------------------------- */ 2326/* -------------------------- custom ctrls ---------------------------------- */
2327 2327
2328static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { 2328static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2329 .ops = &adv7604_ctrl_ops, 2329 .ops = &adv76xx_ctrl_ops,
2330 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 2330 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2331 .name = "Analog Sampling Phase", 2331 .name = "Analog Sampling Phase",
2332 .type = V4L2_CTRL_TYPE_INTEGER, 2332 .type = V4L2_CTRL_TYPE_INTEGER,
@@ -2336,8 +2336,8 @@ static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2336 .def = 0, 2336 .def = 0,
2337}; 2337};
2338 2338
2339static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = { 2339static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2340 .ops = &adv7604_ctrl_ops, 2340 .ops = &adv76xx_ctrl_ops,
2341 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 2341 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2342 .name = "Free Running Color, Manual", 2342 .name = "Free Running Color, Manual",
2343 .type = V4L2_CTRL_TYPE_BOOLEAN, 2343 .type = V4L2_CTRL_TYPE_BOOLEAN,
@@ -2347,8 +2347,8 @@ static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
2347 .def = false, 2347 .def = false,
2348}; 2348};
2349 2349
2350static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = { 2350static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2351 .ops = &adv7604_ctrl_ops, 2351 .ops = &adv76xx_ctrl_ops,
2352 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 2352 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2353 .name = "Free Running Color", 2353 .name = "Free Running Color",
2354 .type = V4L2_CTRL_TYPE_INTEGER, 2354 .type = V4L2_CTRL_TYPE_INTEGER,
@@ -2360,11 +2360,11 @@ static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
2360 2360
2361/* ----------------------------------------------------------------------- */ 2361/* ----------------------------------------------------------------------- */
2362 2362
2363static int adv7604_core_init(struct v4l2_subdev *sd) 2363static int adv76xx_core_init(struct v4l2_subdev *sd)
2364{ 2364{
2365 struct adv7604_state *state = to_state(sd); 2365 struct adv76xx_state *state = to_state(sd);
2366 const struct adv7604_chip_info *info = state->info; 2366 const struct adv76xx_chip_info *info = state->info;
2367 struct adv7604_platform_data *pdata = &state->pdata; 2367 struct adv76xx_platform_data *pdata = &state->pdata;
2368 2368
2369 hdmi_write(sd, 0x48, 2369 hdmi_write(sd, 0x48,
2370 (pdata->disable_pwrdnb ? 0x80 : 0) | 2370 (pdata->disable_pwrdnb ? 0x80 : 0) |
@@ -2392,7 +2392,7 @@ static int adv7604_core_init(struct v4l2_subdev *sd)
2392 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | 2392 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2393 pdata->insert_av_codes << 2 | 2393 pdata->insert_av_codes << 2 |
2394 pdata->replicate_av_codes << 1); 2394 pdata->replicate_av_codes << 1);
2395 adv7604_setup_format(state); 2395 adv76xx_setup_format(state);
2396 2396
2397 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ 2397 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
2398 2398
@@ -2422,7 +2422,7 @@ static int adv7604_core_init(struct v4l2_subdev *sd)
2422 /* TODO from platform data */ 2422 /* TODO from platform data */
2423 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 2423 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2424 2424
2425 if (adv7604_has_afe(state)) { 2425 if (adv76xx_has_afe(state)) {
2426 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 2426 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2427 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); 2427 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2428 } 2428 }
@@ -2447,7 +2447,7 @@ static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2447 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ 2447 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2448} 2448}
2449 2449
2450static void adv7604_unregister_clients(struct adv7604_state *state) 2450static void adv76xx_unregister_clients(struct adv76xx_state *state)
2451{ 2451{
2452 unsigned int i; 2452 unsigned int i;
2453 2453
@@ -2457,7 +2457,7 @@ static void adv7604_unregister_clients(struct adv7604_state *state)
2457 } 2457 }
2458} 2458}
2459 2459
2460static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd, 2460static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
2461 u8 addr, u8 io_reg) 2461 u8 addr, u8 io_reg)
2462{ 2462{
2463 struct i2c_client *client = v4l2_get_subdevdata(sd); 2463 struct i2c_client *client = v4l2_get_subdevdata(sd);
@@ -2467,74 +2467,74 @@ static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
2467 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); 2467 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2468} 2468}
2469 2469
2470static const struct adv7604_reg_seq adv7604_recommended_settings_afe[] = { 2470static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
2471 /* reset ADI recommended settings for HDMI: */ 2471 /* reset ADI recommended settings for HDMI: */
2472 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2472 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2473 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2473 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2474 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2474 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2475 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ 2475 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2476 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ 2476 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2477 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2477 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2478 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ 2478 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2479 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ 2479 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2480 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2480 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2481 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2481 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2482 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ 2482 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2483 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ 2483 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2484 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ 2484 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2485 2485
2486 /* set ADI recommended settings for digitizer */ 2486 /* set ADI recommended settings for digitizer */
2487 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2487 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2488 { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ 2488 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2489 { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ 2489 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2490 { ADV7604_REG(ADV7604_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ 2490 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2491 { ADV7604_REG(ADV7604_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ 2491 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2492 { ADV7604_REG(ADV7604_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ 2492 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2493 2493
2494 { ADV7604_REG_SEQ_TERM, 0 }, 2494 { ADV76XX_REG_SEQ_TERM, 0 },
2495}; 2495};
2496 2496
2497static const struct adv7604_reg_seq adv7604_recommended_settings_hdmi[] = { 2497static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
2498 /* set ADI recommended settings for HDMI: */ 2498 /* set ADI recommended settings for HDMI: */
2499 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2499 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2500 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ 2500 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2501 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ 2501 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2502 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ 2502 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2503 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2503 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2504 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ 2504 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2505 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ 2505 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2506 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2506 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2507 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2507 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2508 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ 2508 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2509 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ 2509 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2510 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ 2510 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2511 2511
2512 /* reset ADI recommended settings for digitizer */ 2512 /* reset ADI recommended settings for digitizer */
2513 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2513 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2514 { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ 2514 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2515 { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ 2515 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
2516 2516
2517 { ADV7604_REG_SEQ_TERM, 0 }, 2517 { ADV76XX_REG_SEQ_TERM, 0 },
2518}; 2518};
2519 2519
2520static const struct adv7604_reg_seq adv7611_recommended_settings_hdmi[] = { 2520static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
2521 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */ 2521 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
2522 { ADV7604_REG(ADV7604_PAGE_CP, 0x6c), 0x00 }, 2522 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2523 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x9b), 0x03 }, 2523 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2524 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x6f), 0x08 }, 2524 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2525 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x85), 0x1f }, 2525 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2526 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x87), 0x70 }, 2526 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2527 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xda }, 2527 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2528 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x01 }, 2528 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2529 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x03), 0x98 }, 2529 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2530 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4c), 0x44 }, 2530 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2531 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x04 }, 2531 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2532 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x1e }, 2532 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
2533 2533
2534 { ADV7604_REG_SEQ_TERM, 0 }, 2534 { ADV76XX_REG_SEQ_TERM, 0 },
2535}; 2535};
2536 2536
2537static const struct adv7604_chip_info adv7604_chip_info[] = { 2537static const struct adv76xx_chip_info adv76xx_chip_info[] = {
2538 [ADV7604] = { 2538 [ADV7604] = {
2539 .type = ADV7604, 2539 .type = ADV7604,
2540 .has_afe = true, 2540 .has_afe = true,
@@ -2561,18 +2561,18 @@ static const struct adv7604_chip_info adv7604_chip_info[] = {
2561 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), 2561 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2562 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), 2562 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2563 }, 2563 },
2564 .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | 2564 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2565 BIT(ADV7604_PAGE_CEC) | BIT(ADV7604_PAGE_INFOFRAME) | 2565 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
2566 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | 2566 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
2567 BIT(ADV7604_PAGE_AFE) | BIT(ADV7604_PAGE_REP) | 2567 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
2568 BIT(ADV7604_PAGE_EDID) | BIT(ADV7604_PAGE_HDMI) | 2568 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
2569 BIT(ADV7604_PAGE_TEST) | BIT(ADV7604_PAGE_CP) | 2569 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
2570 BIT(ADV7604_PAGE_VDP), 2570 BIT(ADV7604_PAGE_VDP),
2571 }, 2571 },
2572 [ADV7611] = { 2572 [ADV7611] = {
2573 .type = ADV7611, 2573 .type = ADV7611,
2574 .has_afe = false, 2574 .has_afe = false,
2575 .max_port = ADV7604_PAD_HDMI_PORT_A, 2575 .max_port = ADV76XX_PAD_HDMI_PORT_A,
2576 .num_dv_ports = 1, 2576 .num_dv_ports = 1,
2577 .edid_enable_reg = 0x74, 2577 .edid_enable_reg = 0x74,
2578 .edid_status_reg = 0x76, 2578 .edid_status_reg = 0x76,
@@ -2593,34 +2593,34 @@ static const struct adv7604_chip_info adv7604_chip_info[] = {
2593 .num_recommended_settings = { 2593 .num_recommended_settings = {
2594 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), 2594 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2595 }, 2595 },
2596 .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_CEC) | 2596 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2597 BIT(ADV7604_PAGE_INFOFRAME) | BIT(ADV7604_PAGE_AFE) | 2597 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2598 BIT(ADV7604_PAGE_REP) | BIT(ADV7604_PAGE_EDID) | 2598 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2599 BIT(ADV7604_PAGE_HDMI) | BIT(ADV7604_PAGE_CP), 2599 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
2600 }, 2600 },
2601}; 2601};
2602 2602
2603static struct i2c_device_id adv7604_i2c_id[] = { 2603static struct i2c_device_id adv76xx_i2c_id[] = {
2604 { "adv7604", (kernel_ulong_t)&adv7604_chip_info[ADV7604] }, 2604 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
2605 { "adv7611", (kernel_ulong_t)&adv7604_chip_info[ADV7611] }, 2605 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
2606 { } 2606 { }
2607}; 2607};
2608MODULE_DEVICE_TABLE(i2c, adv7604_i2c_id); 2608MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
2609 2609
2610static struct of_device_id adv7604_of_id[] __maybe_unused = { 2610static struct of_device_id adv76xx_of_id[] __maybe_unused = {
2611 { .compatible = "adi,adv7611", .data = &adv7604_chip_info[ADV7611] }, 2611 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
2612 { } 2612 { }
2613}; 2613};
2614MODULE_DEVICE_TABLE(of, adv7604_of_id); 2614MODULE_DEVICE_TABLE(of, adv76xx_of_id);
2615 2615
2616static int adv7604_parse_dt(struct adv7604_state *state) 2616static int adv76xx_parse_dt(struct adv76xx_state *state)
2617{ 2617{
2618 struct v4l2_of_endpoint bus_cfg; 2618 struct v4l2_of_endpoint bus_cfg;
2619 struct device_node *endpoint; 2619 struct device_node *endpoint;
2620 struct device_node *np; 2620 struct device_node *np;
2621 unsigned int flags; 2621 unsigned int flags;
2622 2622
2623 np = state->i2c_clients[ADV7604_PAGE_IO]->dev.of_node; 2623 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
2624 2624
2625 /* Parse the endpoint. */ 2625 /* Parse the endpoint. */
2626 endpoint = of_graph_get_next_endpoint(np, NULL); 2626 endpoint = of_graph_get_next_endpoint(np, NULL);
@@ -2647,20 +2647,20 @@ static int adv7604_parse_dt(struct adv7604_state *state)
2647 } 2647 }
2648 2648
2649 /* Disable the interrupt for now as no DT-based board uses it. */ 2649 /* Disable the interrupt for now as no DT-based board uses it. */
2650 state->pdata.int1_config = ADV7604_INT1_CONFIG_DISABLED; 2650 state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
2651 2651
2652 /* Use the default I2C addresses. */ 2652 /* Use the default I2C addresses. */
2653 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42; 2653 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
2654 state->pdata.i2c_addresses[ADV7604_PAGE_CEC] = 0x40; 2654 state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40;
2655 state->pdata.i2c_addresses[ADV7604_PAGE_INFOFRAME] = 0x3e; 2655 state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e;
2656 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38; 2656 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2657 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c; 2657 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
2658 state->pdata.i2c_addresses[ADV7604_PAGE_AFE] = 0x26; 2658 state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26;
2659 state->pdata.i2c_addresses[ADV7604_PAGE_REP] = 0x32; 2659 state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32;
2660 state->pdata.i2c_addresses[ADV7604_PAGE_EDID] = 0x36; 2660 state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36;
2661 state->pdata.i2c_addresses[ADV7604_PAGE_HDMI] = 0x34; 2661 state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34;
2662 state->pdata.i2c_addresses[ADV7604_PAGE_TEST] = 0x30; 2662 state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30;
2663 state->pdata.i2c_addresses[ADV7604_PAGE_CP] = 0x22; 2663 state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22;
2664 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24; 2664 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2665 2665
2666 /* Hardcode the remaining platform data fields. */ 2666 /* Hardcode the remaining platform data fields. */
@@ -2675,12 +2675,12 @@ static int adv7604_parse_dt(struct adv7604_state *state)
2675 return 0; 2675 return 0;
2676} 2676}
2677 2677
2678static int adv7604_probe(struct i2c_client *client, 2678static int adv76xx_probe(struct i2c_client *client,
2679 const struct i2c_device_id *id) 2679 const struct i2c_device_id *id)
2680{ 2680{
2681 static const struct v4l2_dv_timings cea640x480 = 2681 static const struct v4l2_dv_timings cea640x480 =
2682 V4L2_DV_BT_CEA_640X480P59_94; 2682 V4L2_DV_BT_CEA_640X480P59_94;
2683 struct adv7604_state *state; 2683 struct adv76xx_state *state;
2684 struct v4l2_ctrl_handler *hdl; 2684 struct v4l2_ctrl_handler *hdl;
2685 struct v4l2_subdev *sd; 2685 struct v4l2_subdev *sd;
2686 unsigned int i; 2686 unsigned int i;
@@ -2690,16 +2690,16 @@ static int adv7604_probe(struct i2c_client *client,
2690 /* Check if the adapter supports the needed features */ 2690 /* Check if the adapter supports the needed features */
2691 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 2691 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2692 return -EIO; 2692 return -EIO;
2693 v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n", 2693 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
2694 client->addr << 1); 2694 client->addr << 1);
2695 2695
2696 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 2696 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
2697 if (!state) { 2697 if (!state) {
2698 v4l_err(client, "Could not allocate adv7604_state memory!\n"); 2698 v4l_err(client, "Could not allocate adv76xx_state memory!\n");
2699 return -ENOMEM; 2699 return -ENOMEM;
2700 } 2700 }
2701 2701
2702 state->i2c_clients[ADV7604_PAGE_IO] = client; 2702 state->i2c_clients[ADV76XX_PAGE_IO] = client;
2703 2703
2704 /* initialize variables */ 2704 /* initialize variables */
2705 state->restart_stdi_once = true; 2705 state->restart_stdi_once = true;
@@ -2708,18 +2708,18 @@ static int adv7604_probe(struct i2c_client *client,
2708 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { 2708 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
2709 const struct of_device_id *oid; 2709 const struct of_device_id *oid;
2710 2710
2711 oid = of_match_node(adv7604_of_id, client->dev.of_node); 2711 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
2712 state->info = oid->data; 2712 state->info = oid->data;
2713 2713
2714 err = adv7604_parse_dt(state); 2714 err = adv76xx_parse_dt(state);
2715 if (err < 0) { 2715 if (err < 0) {
2716 v4l_err(client, "DT parsing error\n"); 2716 v4l_err(client, "DT parsing error\n");
2717 return err; 2717 return err;
2718 } 2718 }
2719 } else if (client->dev.platform_data) { 2719 } else if (client->dev.platform_data) {
2720 struct adv7604_platform_data *pdata = client->dev.platform_data; 2720 struct adv76xx_platform_data *pdata = client->dev.platform_data;
2721 2721
2722 state->info = (const struct adv7604_chip_info *)id->driver_data; 2722 state->info = (const struct adv76xx_chip_info *)id->driver_data;
2723 state->pdata = *pdata; 2723 state->pdata = *pdata;
2724 } else { 2724 } else {
2725 v4l_err(client, "No platform data!\n"); 2725 v4l_err(client, "No platform data!\n");
@@ -2739,10 +2739,10 @@ static int adv7604_probe(struct i2c_client *client,
2739 } 2739 }
2740 2740
2741 state->timings = cea640x480; 2741 state->timings = cea640x480;
2742 state->format = adv7604_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 2742 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
2743 2743
2744 sd = &state->sd; 2744 sd = &state->sd;
2745 v4l2_i2c_subdev_init(sd, client, &adv7604_ops); 2745 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
2746 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", 2746 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
2747 id->name, i2c_adapter_id(client->adapter), 2747 id->name, i2c_adapter_id(client->adapter),
2748 client->addr); 2748 client->addr);
@@ -2772,15 +2772,15 @@ static int adv7604_probe(struct i2c_client *client,
2772 2772
2773 /* control handlers */ 2773 /* control handlers */
2774 hdl = &state->hdl; 2774 hdl = &state->hdl;
2775 v4l2_ctrl_handler_init(hdl, adv7604_has_afe(state) ? 9 : 8); 2775 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
2776 2776
2777 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 2777 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
2778 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 2778 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2779 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 2779 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
2780 V4L2_CID_CONTRAST, 0, 255, 1, 128); 2780 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2781 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 2781 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
2782 V4L2_CID_SATURATION, 0, 255, 1, 128); 2782 V4L2_CID_SATURATION, 0, 255, 1, 128);
2783 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 2783 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
2784 V4L2_CID_HUE, 0, 128, 1, 0); 2784 V4L2_CID_HUE, 0, 128, 1, 0);
2785 2785
2786 /* private controls */ 2786 /* private controls */
@@ -2788,18 +2788,18 @@ static int adv7604_probe(struct i2c_client *client,
2788 V4L2_CID_DV_RX_POWER_PRESENT, 0, 2788 V4L2_CID_DV_RX_POWER_PRESENT, 0,
2789 (1 << state->info->num_dv_ports) - 1, 0, 0); 2789 (1 << state->info->num_dv_ports) - 1, 0, 0);
2790 state->rgb_quantization_range_ctrl = 2790 state->rgb_quantization_range_ctrl =
2791 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops, 2791 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
2792 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 2792 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2793 0, V4L2_DV_RGB_RANGE_AUTO); 2793 0, V4L2_DV_RGB_RANGE_AUTO);
2794 2794
2795 /* custom controls */ 2795 /* custom controls */
2796 if (adv7604_has_afe(state)) 2796 if (adv76xx_has_afe(state))
2797 state->analog_sampling_phase_ctrl = 2797 state->analog_sampling_phase_ctrl =
2798 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); 2798 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2799 state->free_run_color_manual_ctrl = 2799 state->free_run_color_manual_ctrl =
2800 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL); 2800 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
2801 state->free_run_color_ctrl = 2801 state->free_run_color_ctrl =
2802 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL); 2802 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
2803 2803
2804 sd->ctrl_handler = hdl; 2804 sd->ctrl_handler = hdl;
2805 if (hdl->error) { 2805 if (hdl->error) {
@@ -2808,22 +2808,22 @@ static int adv7604_probe(struct i2c_client *client,
2808 } 2808 }
2809 state->detect_tx_5v_ctrl->is_private = true; 2809 state->detect_tx_5v_ctrl->is_private = true;
2810 state->rgb_quantization_range_ctrl->is_private = true; 2810 state->rgb_quantization_range_ctrl->is_private = true;
2811 if (adv7604_has_afe(state)) 2811 if (adv76xx_has_afe(state))
2812 state->analog_sampling_phase_ctrl->is_private = true; 2812 state->analog_sampling_phase_ctrl->is_private = true;
2813 state->free_run_color_manual_ctrl->is_private = true; 2813 state->free_run_color_manual_ctrl->is_private = true;
2814 state->free_run_color_ctrl->is_private = true; 2814 state->free_run_color_ctrl->is_private = true;
2815 2815
2816 if (adv7604_s_detect_tx_5v_ctrl(sd)) { 2816 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
2817 err = -ENODEV; 2817 err = -ENODEV;
2818 goto err_hdl; 2818 goto err_hdl;
2819 } 2819 }
2820 2820
2821 for (i = 1; i < ADV7604_PAGE_MAX; ++i) { 2821 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
2822 if (!(BIT(i) & state->info->page_mask)) 2822 if (!(BIT(i) & state->info->page_mask))
2823 continue; 2823 continue;
2824 2824
2825 state->i2c_clients[i] = 2825 state->i2c_clients[i] =
2826 adv7604_dummy_client(sd, state->pdata.i2c_addresses[i], 2826 adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i],
2827 0xf2 + i); 2827 0xf2 + i);
2828 if (state->i2c_clients[i] == NULL) { 2828 if (state->i2c_clients[i] == NULL) {
2829 err = -ENOMEM; 2829 err = -ENOMEM;
@@ -2841,7 +2841,7 @@ static int adv7604_probe(struct i2c_client *client,
2841 } 2841 }
2842 2842
2843 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 2843 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2844 adv7604_delayed_work_enable_hotplug); 2844 adv76xx_delayed_work_enable_hotplug);
2845 2845
2846 state->source_pad = state->info->num_dv_ports 2846 state->source_pad = state->info->num_dv_ports
2847 + (state->info->has_afe ? 2 : 0); 2847 + (state->info->has_afe ? 2 : 0);
@@ -2854,7 +2854,7 @@ static int adv7604_probe(struct i2c_client *client,
2854 if (err) 2854 if (err)
2855 goto err_work_queues; 2855 goto err_work_queues;
2856 2856
2857 err = adv7604_core_init(sd); 2857 err = adv76xx_core_init(sd);
2858 if (err) 2858 if (err)
2859 goto err_entity; 2859 goto err_entity;
2860 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 2860 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
@@ -2872,7 +2872,7 @@ err_work_queues:
2872 cancel_delayed_work(&state->delayed_work_enable_hotplug); 2872 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2873 destroy_workqueue(state->work_queues); 2873 destroy_workqueue(state->work_queues);
2874err_i2c: 2874err_i2c:
2875 adv7604_unregister_clients(state); 2875 adv76xx_unregister_clients(state);
2876err_hdl: 2876err_hdl:
2877 v4l2_ctrl_handler_free(hdl); 2877 v4l2_ctrl_handler_free(hdl);
2878 return err; 2878 return err;
@@ -2880,32 +2880,32 @@ err_hdl:
2880 2880
2881/* ----------------------------------------------------------------------- */ 2881/* ----------------------------------------------------------------------- */
2882 2882
2883static int adv7604_remove(struct i2c_client *client) 2883static int adv76xx_remove(struct i2c_client *client)
2884{ 2884{
2885 struct v4l2_subdev *sd = i2c_get_clientdata(client); 2885 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2886 struct adv7604_state *state = to_state(sd); 2886 struct adv76xx_state *state = to_state(sd);
2887 2887
2888 cancel_delayed_work(&state->delayed_work_enable_hotplug); 2888 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2889 destroy_workqueue(state->work_queues); 2889 destroy_workqueue(state->work_queues);
2890 v4l2_async_unregister_subdev(sd); 2890 v4l2_async_unregister_subdev(sd);
2891 v4l2_device_unregister_subdev(sd); 2891 v4l2_device_unregister_subdev(sd);
2892 media_entity_cleanup(&sd->entity); 2892 media_entity_cleanup(&sd->entity);
2893 adv7604_unregister_clients(to_state(sd)); 2893 adv76xx_unregister_clients(to_state(sd));
2894 v4l2_ctrl_handler_free(sd->ctrl_handler); 2894 v4l2_ctrl_handler_free(sd->ctrl_handler);
2895 return 0; 2895 return 0;
2896} 2896}
2897 2897
2898/* ----------------------------------------------------------------------- */ 2898/* ----------------------------------------------------------------------- */
2899 2899
2900static struct i2c_driver adv7604_driver = { 2900static struct i2c_driver adv76xx_driver = {
2901 .driver = { 2901 .driver = {
2902 .owner = THIS_MODULE, 2902 .owner = THIS_MODULE,
2903 .name = "adv7604", 2903 .name = "adv7604",
2904 .of_match_table = of_match_ptr(adv7604_of_id), 2904 .of_match_table = of_match_ptr(adv76xx_of_id),
2905 }, 2905 },
2906 .probe = adv7604_probe, 2906 .probe = adv76xx_probe,
2907 .remove = adv7604_remove, 2907 .remove = adv76xx_remove,
2908 .id_table = adv7604_i2c_id, 2908 .id_table = adv76xx_i2c_id,
2909}; 2909};
2910 2910
2911module_i2c_driver(adv7604_driver); 2911module_i2c_driver(adv76xx_driver);
diff --git a/include/media/adv7604.h b/include/media/adv7604.h
index aa1c4477722d..9ecf353160c1 100644
--- a/include/media/adv7604.h
+++ b/include/media/adv7604.h
@@ -47,16 +47,16 @@ enum adv7604_bus_order {
47}; 47};
48 48
49/* Input Color Space (IO register 0x02, [7:4]) */ 49/* Input Color Space (IO register 0x02, [7:4]) */
50enum adv7604_inp_color_space { 50enum adv76xx_inp_color_space {
51 ADV7604_INP_COLOR_SPACE_LIM_RGB = 0, 51 ADV76XX_INP_COLOR_SPACE_LIM_RGB = 0,
52 ADV7604_INP_COLOR_SPACE_FULL_RGB = 1, 52 ADV76XX_INP_COLOR_SPACE_FULL_RGB = 1,
53 ADV7604_INP_COLOR_SPACE_LIM_YCbCr_601 = 2, 53 ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
54 ADV7604_INP_COLOR_SPACE_LIM_YCbCr_709 = 3, 54 ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
55 ADV7604_INP_COLOR_SPACE_XVYCC_601 = 4, 55 ADV76XX_INP_COLOR_SPACE_XVYCC_601 = 4,
56 ADV7604_INP_COLOR_SPACE_XVYCC_709 = 5, 56 ADV76XX_INP_COLOR_SPACE_XVYCC_709 = 5,
57 ADV7604_INP_COLOR_SPACE_FULL_YCbCr_601 = 6, 57 ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
58 ADV7604_INP_COLOR_SPACE_FULL_YCbCr_709 = 7, 58 ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
59 ADV7604_INP_COLOR_SPACE_AUTO = 0xf, 59 ADV76XX_INP_COLOR_SPACE_AUTO = 0xf,
60}; 60};
61 61
62/* Select output format (IO register 0x03, [4:2]) */ 62/* Select output format (IO register 0x03, [4:2]) */
@@ -66,38 +66,39 @@ enum adv7604_op_format_mode_sel {
66 ADV7604_OP_FORMAT_MODE2 = 0x08, 66 ADV7604_OP_FORMAT_MODE2 = 0x08,
67}; 67};
68 68
69enum adv7604_drive_strength { 69enum adv76xx_drive_strength {
70 ADV7604_DR_STR_MEDIUM_LOW = 1, 70 ADV76XX_DR_STR_MEDIUM_LOW = 1,
71 ADV7604_DR_STR_MEDIUM_HIGH = 2, 71 ADV76XX_DR_STR_MEDIUM_HIGH = 2,
72 ADV7604_DR_STR_HIGH = 3, 72 ADV76XX_DR_STR_HIGH = 3,
73}; 73};
74 74
75enum adv7604_int1_config { 75/* INT1 Configuration (IO register 0x40, [1:0]) */
76 ADV7604_INT1_CONFIG_OPEN_DRAIN, 76enum adv76xx_int1_config {
77 ADV7604_INT1_CONFIG_ACTIVE_LOW, 77 ADV76XX_INT1_CONFIG_OPEN_DRAIN,
78 ADV7604_INT1_CONFIG_ACTIVE_HIGH, 78 ADV76XX_INT1_CONFIG_ACTIVE_LOW,
79 ADV7604_INT1_CONFIG_DISABLED, 79 ADV76XX_INT1_CONFIG_ACTIVE_HIGH,
80 ADV76XX_INT1_CONFIG_DISABLED,
80}; 81};
81 82
82enum adv7604_page { 83enum adv76xx_page {
83 ADV7604_PAGE_IO, 84 ADV76XX_PAGE_IO,
84 ADV7604_PAGE_AVLINK, 85 ADV7604_PAGE_AVLINK,
85 ADV7604_PAGE_CEC, 86 ADV76XX_PAGE_CEC,
86 ADV7604_PAGE_INFOFRAME, 87 ADV76XX_PAGE_INFOFRAME,
87 ADV7604_PAGE_ESDP, 88 ADV7604_PAGE_ESDP,
88 ADV7604_PAGE_DPP, 89 ADV7604_PAGE_DPP,
89 ADV7604_PAGE_AFE, 90 ADV76XX_PAGE_AFE,
90 ADV7604_PAGE_REP, 91 ADV76XX_PAGE_REP,
91 ADV7604_PAGE_EDID, 92 ADV76XX_PAGE_EDID,
92 ADV7604_PAGE_HDMI, 93 ADV76XX_PAGE_HDMI,
93 ADV7604_PAGE_TEST, 94 ADV76XX_PAGE_TEST,
94 ADV7604_PAGE_CP, 95 ADV76XX_PAGE_CP,
95 ADV7604_PAGE_VDP, 96 ADV7604_PAGE_VDP,
96 ADV7604_PAGE_MAX, 97 ADV76XX_PAGE_MAX,
97}; 98};
98 99
99/* Platform dependent definition */ 100/* Platform dependent definition */
100struct adv7604_platform_data { 101struct adv76xx_platform_data {
101 /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */ 102 /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
102 unsigned disable_pwrdnb:1; 103 unsigned disable_pwrdnb:1;
103 104
@@ -116,7 +117,7 @@ struct adv7604_platform_data {
116 enum adv7604_op_format_mode_sel op_format_mode_sel; 117 enum adv7604_op_format_mode_sel op_format_mode_sel;
117 118
118 /* Configuration of the INT1 pin */ 119 /* Configuration of the INT1 pin */
119 enum adv7604_int1_config int1_config; 120 enum adv76xx_int1_config int1_config;
120 121
121 /* IO register 0x02 */ 122 /* IO register 0x02 */
122 unsigned alt_gamma:1; 123 unsigned alt_gamma:1;
@@ -134,9 +135,9 @@ struct adv7604_platform_data {
134 unsigned inv_llc_pol:1; 135 unsigned inv_llc_pol:1;
135 136
136 /* IO register 0x14 */ 137 /* IO register 0x14 */
137 enum adv7604_drive_strength dr_str_data; 138 enum adv76xx_drive_strength dr_str_data;
138 enum adv7604_drive_strength dr_str_clk; 139 enum adv76xx_drive_strength dr_str_clk;
139 enum adv7604_drive_strength dr_str_sync; 140 enum adv76xx_drive_strength dr_str_sync;
140 141
141 /* IO register 0x30 */ 142 /* IO register 0x30 */
142 unsigned output_bus_lsb_to_msb:1; 143 unsigned output_bus_lsb_to_msb:1;
@@ -145,11 +146,11 @@ struct adv7604_platform_data {
145 unsigned hdmi_free_run_mode; 146 unsigned hdmi_free_run_mode;
146 147
147 /* i2c addresses: 0 == use default */ 148 /* i2c addresses: 0 == use default */
148 u8 i2c_addresses[ADV7604_PAGE_MAX]; 149 u8 i2c_addresses[ADV76XX_PAGE_MAX];
149}; 150};
150 151
151enum adv7604_pad { 152enum adv76xx_pad {
152 ADV7604_PAD_HDMI_PORT_A = 0, 153 ADV76XX_PAD_HDMI_PORT_A = 0,
153 ADV7604_PAD_HDMI_PORT_B = 1, 154 ADV7604_PAD_HDMI_PORT_B = 1,
154 ADV7604_PAD_HDMI_PORT_C = 2, 155 ADV7604_PAD_HDMI_PORT_C = 2,
155 ADV7604_PAD_HDMI_PORT_D = 3, 156 ADV7604_PAD_HDMI_PORT_D = 3,
@@ -158,7 +159,7 @@ enum adv7604_pad {
158 /* The source pad is either 1 (ADV7611) or 6 (ADV7604) */ 159 /* The source pad is either 1 (ADV7611) or 6 (ADV7604) */
159 ADV7604_PAD_SOURCE = 6, 160 ADV7604_PAD_SOURCE = 6,
160 ADV7611_PAD_SOURCE = 1, 161 ADV7611_PAD_SOURCE = 1,
161 ADV7604_PAD_MAX = 7, 162 ADV76XX_PAD_MAX = 7,
162}; 163};
163 164
164#define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000) 165#define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000)
@@ -166,7 +167,7 @@ enum adv7604_pad {
166#define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002) 167#define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002)
167 168
168/* notify events */ 169/* notify events */
169#define ADV7604_HOTPLUG 1 170#define ADV76XX_HOTPLUG 1
170#define ADV7604_FMT_CHANGE 2 171#define ADV76XX_FMT_CHANGE 2
171 172
172#endif 173#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-20 22:51:24 -0400