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-rw-r--r--arch/arc/include/asm/arcregs.h9
-rw-r--r--arch/arc/kernel/time.c18
-rw-r--r--include/soc/arc/timers.h38
3 files changed, 42 insertions, 23 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 7a2c36e83186..da41a54ea2d7 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -20,7 +20,6 @@
20#define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */ 20#define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
21#define ARC_REG_SLC_BCR 0xce 21#define ARC_REG_SLC_BCR 0xce
22#define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */ 22#define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */
23#define ARC_REG_TIMERS_BCR 0x75
24#define ARC_REG_AP_BCR 0x76 23#define ARC_REG_AP_BCR 0x76
25#define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */ 24#define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */
26#define ARC_REG_XY_MEM_BCR 0x79 25#define ARC_REG_XY_MEM_BCR 0x79
@@ -208,13 +207,7 @@ struct bcr_fp_arcv2 {
208#endif 207#endif
209}; 208};
210 209
211struct bcr_timer { 210#include <soc/arc/timers.h>
212#ifdef CONFIG_CPU_BIG_ENDIAN
213 unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
214#else
215 unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
216#endif
217};
218 211
219struct bcr_bpu_arcompact { 212struct bcr_bpu_arcompact {
220#ifdef CONFIG_CPU_BIG_ENDIAN 213#ifdef CONFIG_CPU_BIG_ENDIAN
diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c
index ec1b896f27b2..94b9cd169374 100644
--- a/arch/arc/kernel/time.c
+++ b/arch/arc/kernel/time.c
@@ -38,22 +38,10 @@
38#include <linux/of.h> 38#include <linux/of.h>
39#include <linux/of_irq.h> 39#include <linux/of_irq.h>
40#include <asm/irq.h> 40#include <asm/irq.h>
41#include <asm/arcregs.h>
42 41
42#include <soc/arc/timers.h>
43#include <soc/arc/mcip.h> 43#include <soc/arc/mcip.h>
44 44
45/* Timer related Aux registers */
46#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
47#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
48#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
49#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
50#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
51#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
52
53#define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
54#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
55
56#define ARC_TIMER_MAX 0xFFFFFFFF
57 45
58static unsigned long arc_timer_freq; 46static unsigned long arc_timer_freq;
59 47
@@ -218,7 +206,7 @@ static int __init arc_cs_setup_timer1(struct device_node *node)
218 if (ret) 206 if (ret)
219 return ret; 207 return ret;
220 208
221 write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX); 209 write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);
222 write_aux_reg(ARC_REG_TIMER1_CNT, 0); 210 write_aux_reg(ARC_REG_TIMER1_CNT, 0);
223 write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); 211 write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
224 212
@@ -296,7 +284,7 @@ static int arc_timer_starting_cpu(unsigned int cpu)
296 284
297 evt->cpumask = cpumask_of(smp_processor_id()); 285 evt->cpumask = cpumask_of(smp_processor_id());
298 286
299 clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMER_MAX); 287 clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX);
300 enable_percpu_irq(arc_timer_irq, 0); 288 enable_percpu_irq(arc_timer_irq, 0);
301 return 0; 289 return 0;
302} 290}
diff --git a/include/soc/arc/timers.h b/include/soc/arc/timers.h
new file mode 100644
index 000000000000..a20ed2fbc432
--- /dev/null
+++ b/include/soc/arc/timers.h
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __SOC_ARC_TIMERS_H
10#define __SOC_ARC_TIMERS_H
11
12#include <soc/arc/aux.h>
13
14/* Timer related Aux registers */
15#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
16#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
17#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
18#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
19#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
20#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
21
22/* CTRL reg bits */
23#define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
24#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
25
26#define ARC_TIMERN_MAX 0xFFFFFFFF
27
28#define ARC_REG_TIMERS_BCR 0x75
29
30struct bcr_timer {
31#ifdef CONFIG_CPU_BIG_ENDIAN
32 unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
33#else
34 unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
35#endif
36};
37
38#endif