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-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/nxp/Makefile1
-rw-r--r--drivers/clk/nxp/clk-lpc18xx-cgu.c635
-rw-r--r--include/dt-bindings/clock/lpc18xx-cgu.h41
4 files changed, 678 insertions, 0 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d4bc8ed29984..256977ed050a 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -57,6 +57,7 @@ endif
57obj-$(CONFIG_PLAT_ORION) += mvebu/ 57obj-$(CONFIG_PLAT_ORION) += mvebu/
58obj-$(CONFIG_ARCH_MESON) += meson/ 58obj-$(CONFIG_ARCH_MESON) += meson/
59obj-$(CONFIG_ARCH_MXS) += mxs/ 59obj-$(CONFIG_ARCH_MXS) += mxs/
60obj-$(CONFIG_ARCH_LPC18XX) += nxp/
60obj-$(CONFIG_MACH_PISTACHIO) += pistachio/ 61obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
61obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ 62obj-$(CONFIG_COMMON_CLK_PXA) += pxa/
62obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ 63obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
diff --git a/drivers/clk/nxp/Makefile b/drivers/clk/nxp/Makefile
new file mode 100644
index 000000000000..aca9d3e4f7fe
--- /dev/null
+++ b/drivers/clk/nxp/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_ARCH_LPC18XX) += clk-lpc18xx-cgu.o
diff --git a/drivers/clk/nxp/clk-lpc18xx-cgu.c b/drivers/clk/nxp/clk-lpc18xx-cgu.c
new file mode 100644
index 000000000000..81e9e1c788f4
--- /dev/null
+++ b/drivers/clk/nxp/clk-lpc18xx-cgu.c
@@ -0,0 +1,635 @@
1/*
2 * Clk driver for NXP LPC18xx/LPC43xx Clock Generation Unit (CGU)
3 *
4 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/clk.h>
12#include <linux/clk-provider.h>
13#include <linux/delay.h>
14#include <linux/kernel.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17
18#include <dt-bindings/clock/lpc18xx-cgu.h>
19
20/* Clock Generation Unit (CGU) registers */
21#define LPC18XX_CGU_XTAL_OSC_CTRL 0x018
22#define LPC18XX_CGU_PLL0USB_STAT 0x01c
23#define LPC18XX_CGU_PLL0USB_CTRL 0x020
24#define LPC18XX_CGU_PLL0USB_MDIV 0x024
25#define LPC18XX_CGU_PLL0USB_NP_DIV 0x028
26#define LPC18XX_CGU_PLL0AUDIO_STAT 0x02c
27#define LPC18XX_CGU_PLL0AUDIO_CTRL 0x030
28#define LPC18XX_CGU_PLL0AUDIO_MDIV 0x034
29#define LPC18XX_CGU_PLL0AUDIO_NP_DIV 0x038
30#define LPC18XX_CGU_PLL0AUDIO_FRAC 0x03c
31#define LPC18XX_CGU_PLL1_STAT 0x040
32#define LPC18XX_CGU_PLL1_CTRL 0x044
33#define LPC18XX_PLL1_CTRL_FBSEL BIT(6)
34#define LPC18XX_PLL1_CTRL_DIRECT BIT(7)
35#define LPC18XX_CGU_IDIV_CTRL(n) (0x048 + (n) * sizeof(u32))
36#define LPC18XX_CGU_BASE_CLK(id) (0x05c + (id) * sizeof(u32))
37#define LPC18XX_CGU_PLL_CTRL_OFFSET 0x4
38
39/* PLL0 bits common to both audio and USB PLL */
40#define LPC18XX_PLL0_STAT_LOCK BIT(0)
41#define LPC18XX_PLL0_CTRL_PD BIT(0)
42#define LPC18XX_PLL0_CTRL_BYPASS BIT(1)
43#define LPC18XX_PLL0_CTRL_DIRECTI BIT(2)
44#define LPC18XX_PLL0_CTRL_DIRECTO BIT(3)
45#define LPC18XX_PLL0_CTRL_CLKEN BIT(4)
46#define LPC18XX_PLL0_MDIV_MDEC_MASK 0x1ffff
47#define LPC18XX_PLL0_MDIV_SELP_SHIFT 17
48#define LPC18XX_PLL0_MDIV_SELI_SHIFT 22
49#define LPC18XX_PLL0_MSEL_MAX BIT(15)
50
51/* Register value that gives PLL0 post/pre dividers equal to 1 */
52#define LPC18XX_PLL0_NP_DIVS_1 0x00302062
53
54enum {
55 CLK_SRC_OSC32,
56 CLK_SRC_IRC,
57 CLK_SRC_ENET_RX_CLK,
58 CLK_SRC_ENET_TX_CLK,
59 CLK_SRC_GP_CLKIN,
60 CLK_SRC_RESERVED1,
61 CLK_SRC_OSC,
62 CLK_SRC_PLL0USB,
63 CLK_SRC_PLL0AUDIO,
64 CLK_SRC_PLL1,
65 CLK_SRC_RESERVED2,
66 CLK_SRC_RESERVED3,
67 CLK_SRC_IDIVA,
68 CLK_SRC_IDIVB,
69 CLK_SRC_IDIVC,
70 CLK_SRC_IDIVD,
71 CLK_SRC_IDIVE,
72 CLK_SRC_MAX
73};
74
75static const char *clk_src_names[CLK_SRC_MAX] = {
76 [CLK_SRC_OSC32] = "osc32",
77 [CLK_SRC_IRC] = "irc",
78 [CLK_SRC_ENET_RX_CLK] = "enet_rx_clk",
79 [CLK_SRC_ENET_TX_CLK] = "enet_tx_clk",
80 [CLK_SRC_GP_CLKIN] = "gp_clkin",
81 [CLK_SRC_OSC] = "osc",
82 [CLK_SRC_PLL0USB] = "pll0usb",
83 [CLK_SRC_PLL0AUDIO] = "pll0audio",
84 [CLK_SRC_PLL1] = "pll1",
85 [CLK_SRC_IDIVA] = "idiva",
86 [CLK_SRC_IDIVB] = "idivb",
87 [CLK_SRC_IDIVC] = "idivc",
88 [CLK_SRC_IDIVD] = "idivd",
89 [CLK_SRC_IDIVE] = "idive",
90};
91
92static const char *clk_base_names[BASE_CLK_MAX] = {
93 [BASE_SAFE_CLK] = "base_safe_clk",
94 [BASE_USB0_CLK] = "base_usb0_clk",
95 [BASE_PERIPH_CLK] = "base_periph_clk",
96 [BASE_USB1_CLK] = "base_usb1_clk",
97 [BASE_CPU_CLK] = "base_cpu_clk",
98 [BASE_SPIFI_CLK] = "base_spifi_clk",
99 [BASE_SPI_CLK] = "base_spi_clk",
100 [BASE_PHY_RX_CLK] = "base_phy_rx_clk",
101 [BASE_PHY_TX_CLK] = "base_phy_tx_clk",
102 [BASE_APB1_CLK] = "base_apb1_clk",
103 [BASE_APB3_CLK] = "base_apb3_clk",
104 [BASE_LCD_CLK] = "base_lcd_clk",
105 [BASE_ADCHS_CLK] = "base_adchs_clk",
106 [BASE_SDIO_CLK] = "base_sdio_clk",
107 [BASE_SSP0_CLK] = "base_ssp0_clk",
108 [BASE_SSP1_CLK] = "base_ssp1_clk",
109 [BASE_UART0_CLK] = "base_uart0_clk",
110 [BASE_UART1_CLK] = "base_uart1_clk",
111 [BASE_UART2_CLK] = "base_uart2_clk",
112 [BASE_UART3_CLK] = "base_uart3_clk",
113 [BASE_OUT_CLK] = "base_out_clk",
114 [BASE_AUDIO_CLK] = "base_audio_clk",
115 [BASE_CGU_OUT0_CLK] = "base_cgu_out0_clk",
116 [BASE_CGU_OUT1_CLK] = "base_cgu_out1_clk",
117};
118
119static u32 lpc18xx_cgu_pll0_src_ids[] = {
120 CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
121 CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
122 CLK_SRC_PLL1, CLK_SRC_IDIVA, CLK_SRC_IDIVB, CLK_SRC_IDIVC,
123 CLK_SRC_IDIVD, CLK_SRC_IDIVE,
124};
125
126static u32 lpc18xx_cgu_pll1_src_ids[] = {
127 CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
128 CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
129 CLK_SRC_PLL0USB, CLK_SRC_PLL0AUDIO, CLK_SRC_IDIVA,
130 CLK_SRC_IDIVB, CLK_SRC_IDIVC, CLK_SRC_IDIVD, CLK_SRC_IDIVE,
131};
132
133static u32 lpc18xx_cgu_idiva_src_ids[] = {
134 CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
135 CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
136 CLK_SRC_PLL0USB, CLK_SRC_PLL0AUDIO, CLK_SRC_PLL1
137};
138
139static u32 lpc18xx_cgu_idivbcde_src_ids[] = {
140 CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
141 CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
142 CLK_SRC_PLL0AUDIO, CLK_SRC_PLL1, CLK_SRC_IDIVA,
143};
144
145static u32 lpc18xx_cgu_base_irc_src_ids[] = {CLK_SRC_IRC};
146
147static u32 lpc18xx_cgu_base_usb0_src_ids[] = {CLK_SRC_PLL0USB};
148
149static u32 lpc18xx_cgu_base_common_src_ids[] = {
150 CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
151 CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
152 CLK_SRC_PLL0AUDIO, CLK_SRC_PLL1, CLK_SRC_IDIVA,
153 CLK_SRC_IDIVB, CLK_SRC_IDIVC, CLK_SRC_IDIVD, CLK_SRC_IDIVE,
154};
155
156static u32 lpc18xx_cgu_base_all_src_ids[] = {
157 CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
158 CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
159 CLK_SRC_PLL0USB, CLK_SRC_PLL0AUDIO, CLK_SRC_PLL1,
160 CLK_SRC_IDIVA, CLK_SRC_IDIVB, CLK_SRC_IDIVC,
161 CLK_SRC_IDIVD, CLK_SRC_IDIVE,
162};
163
164struct lpc18xx_cgu_src_clk_div {
165 u8 clk_id;
166 u8 n_parents;
167 struct clk_divider div;
168 struct clk_mux mux;
169 struct clk_gate gate;
170};
171
172#define LPC1XX_CGU_SRC_CLK_DIV(_id, _width, _table) \
173{ \
174 .clk_id = CLK_SRC_ ##_id, \
175 .n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table), \
176 .div = { \
177 .shift = 2, \
178 .width = _width, \
179 }, \
180 .mux = { \
181 .mask = 0x1f, \
182 .shift = 24, \
183 .table = lpc18xx_cgu_ ##_table, \
184 }, \
185 .gate = { \
186 .bit_idx = 0, \
187 .flags = CLK_GATE_SET_TO_DISABLE, \
188 }, \
189}
190
191static struct lpc18xx_cgu_src_clk_div lpc18xx_cgu_src_clk_divs[] = {
192 LPC1XX_CGU_SRC_CLK_DIV(IDIVA, 2, idiva_src_ids),
193 LPC1XX_CGU_SRC_CLK_DIV(IDIVB, 4, idivbcde_src_ids),
194 LPC1XX_CGU_SRC_CLK_DIV(IDIVC, 4, idivbcde_src_ids),
195 LPC1XX_CGU_SRC_CLK_DIV(IDIVD, 4, idivbcde_src_ids),
196 LPC1XX_CGU_SRC_CLK_DIV(IDIVE, 8, idivbcde_src_ids),
197};
198
199struct lpc18xx_cgu_base_clk {
200 u8 clk_id;
201 u8 n_parents;
202 struct clk_mux mux;
203 struct clk_gate gate;
204};
205
206#define LPC1XX_CGU_BASE_CLK(_id, _table, _flags) \
207{ \
208 .clk_id = BASE_ ##_id ##_CLK, \
209 .n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table), \
210 .mux = { \
211 .mask = 0x1f, \
212 .shift = 24, \
213 .table = lpc18xx_cgu_ ##_table, \
214 .flags = _flags, \
215 }, \
216 .gate = { \
217 .bit_idx = 0, \
218 .flags = CLK_GATE_SET_TO_DISABLE, \
219 }, \
220}
221
222static struct lpc18xx_cgu_base_clk lpc18xx_cgu_base_clks[] = {
223 LPC1XX_CGU_BASE_CLK(SAFE, base_irc_src_ids, CLK_MUX_READ_ONLY),
224 LPC1XX_CGU_BASE_CLK(USB0, base_usb0_src_ids, 0),
225 LPC1XX_CGU_BASE_CLK(PERIPH, base_common_src_ids, 0),
226 LPC1XX_CGU_BASE_CLK(USB1, base_all_src_ids, 0),
227 LPC1XX_CGU_BASE_CLK(CPU, base_common_src_ids, 0),
228 LPC1XX_CGU_BASE_CLK(SPIFI, base_common_src_ids, 0),
229 LPC1XX_CGU_BASE_CLK(SPI, base_common_src_ids, 0),
230 LPC1XX_CGU_BASE_CLK(PHY_RX, base_common_src_ids, 0),
231 LPC1XX_CGU_BASE_CLK(PHY_TX, base_common_src_ids, 0),
232 LPC1XX_CGU_BASE_CLK(APB1, base_common_src_ids, 0),
233 LPC1XX_CGU_BASE_CLK(APB3, base_common_src_ids, 0),
234 LPC1XX_CGU_BASE_CLK(LCD, base_common_src_ids, 0),
235 LPC1XX_CGU_BASE_CLK(ADCHS, base_common_src_ids, 0),
236 LPC1XX_CGU_BASE_CLK(SDIO, base_common_src_ids, 0),
237 LPC1XX_CGU_BASE_CLK(SSP0, base_common_src_ids, 0),
238 LPC1XX_CGU_BASE_CLK(SSP1, base_common_src_ids, 0),
239 LPC1XX_CGU_BASE_CLK(UART0, base_common_src_ids, 0),
240 LPC1XX_CGU_BASE_CLK(UART1, base_common_src_ids, 0),
241 LPC1XX_CGU_BASE_CLK(UART2, base_common_src_ids, 0),
242 LPC1XX_CGU_BASE_CLK(UART3, base_common_src_ids, 0),
243 LPC1XX_CGU_BASE_CLK(OUT, base_all_src_ids, 0),
244 { /* 21 reserved */ },
245 { /* 22 reserved */ },
246 { /* 23 reserved */ },
247 { /* 24 reserved */ },
248 LPC1XX_CGU_BASE_CLK(AUDIO, base_common_src_ids, 0),
249 LPC1XX_CGU_BASE_CLK(CGU_OUT0, base_all_src_ids, 0),
250 LPC1XX_CGU_BASE_CLK(CGU_OUT1, base_all_src_ids, 0),
251};
252
253struct lpc18xx_pll {
254 struct clk_hw hw;
255 void __iomem *reg;
256 spinlock_t *lock;
257 u8 flags;
258};
259
260#define to_lpc_pll(hw) container_of(hw, struct lpc18xx_pll, hw)
261
262struct lpc18xx_cgu_pll_clk {
263 u8 clk_id;
264 u8 n_parents;
265 u8 reg_offset;
266 struct clk_mux mux;
267 struct clk_gate gate;
268 struct lpc18xx_pll pll;
269 const struct clk_ops *pll_ops;
270};
271
272#define LPC1XX_CGU_CLK_PLL(_id, _table, _pll_ops) \
273{ \
274 .clk_id = CLK_SRC_ ##_id, \
275 .n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table), \
276 .reg_offset = LPC18XX_CGU_ ##_id ##_STAT, \
277 .mux = { \
278 .mask = 0x1f, \
279 .shift = 24, \
280 .table = lpc18xx_cgu_ ##_table, \
281 }, \
282 .gate = { \
283 .bit_idx = 0, \
284 .flags = CLK_GATE_SET_TO_DISABLE, \
285 }, \
286 .pll_ops = &lpc18xx_ ##_pll_ops, \
287}
288
289/*
290 * PLL0 uses a special register value encoding. The compute functions below
291 * are taken or derived from the LPC1850 user manual (section 12.6.3.3).
292 */
293
294/* Compute PLL0 multiplier from decoded version */
295static u32 lpc18xx_pll0_mdec2msel(u32 x)
296{
297 int i;
298
299 switch (x) {
300 case 0x18003: return 1;
301 case 0x10003: return 2;
302 default:
303 for (i = LPC18XX_PLL0_MSEL_MAX + 1; x != 0x4000 && i > 0; i--)
304 x = ((x ^ x >> 14) & 1) | (x << 1 & 0x7fff);
305 return i;
306 }
307}
308/* Compute PLL0 decoded multiplier from binary version */
309static u32 lpc18xx_pll0_msel2mdec(u32 msel)
310{
311 u32 i, x = 0x4000;
312
313 switch (msel) {
314 case 0: return 0;
315 case 1: return 0x18003;
316 case 2: return 0x10003;
317 default:
318 for (i = msel; i <= LPC18XX_PLL0_MSEL_MAX; i++)
319 x = ((x ^ x >> 1) & 1) << 14 | (x >> 1 & 0xffff);
320 return x;
321 }
322}
323
324/* Compute PLL0 bandwidth SELI reg from multiplier */
325static u32 lpc18xx_pll0_msel2seli(u32 msel)
326{
327 u32 tmp;
328
329 if (msel > 16384) return 1;
330 if (msel > 8192) return 2;
331 if (msel > 2048) return 4;
332 if (msel >= 501) return 8;
333 if (msel >= 60) {
334 tmp = 1024 / (msel + 9);
335 return ((1024 == (tmp * (msel + 9))) == 0) ? tmp * 4 : (tmp + 1) * 4;
336 }
337
338 return (msel & 0x3c) + 4;
339}
340
341/* Compute PLL0 bandwidth SELP reg from multiplier */
342static u32 lpc18xx_pll0_msel2selp(u32 msel)
343{
344 if (msel < 60)
345 return (msel >> 1) + 1;
346
347 return 31;
348}
349
350static unsigned long lpc18xx_pll0_recalc_rate(struct clk_hw *hw,
351 unsigned long parent_rate)
352{
353 struct lpc18xx_pll *pll = to_lpc_pll(hw);
354 u32 ctrl, mdiv, msel, npdiv;
355
356 ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
357 mdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
358 npdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
359
360 if (ctrl & LPC18XX_PLL0_CTRL_BYPASS)
361 return parent_rate;
362
363 if (npdiv != LPC18XX_PLL0_NP_DIVS_1) {
364 pr_warn("%s: pre/post dividers not supported\n", __func__);
365 return 0;
366 }
367
368 msel = lpc18xx_pll0_mdec2msel(mdiv & LPC18XX_PLL0_MDIV_MDEC_MASK);
369 if (msel)
370 return 2 * msel * parent_rate;
371
372 pr_warn("%s: unable to calculate rate\n", __func__);
373
374 return 0;
375}
376
377static long lpc18xx_pll0_round_rate(struct clk_hw *hw, unsigned long rate,
378 unsigned long *prate)
379{
380 unsigned long m;
381
382 if (*prate < rate) {
383 pr_warn("%s: pll dividers not supported\n", __func__);
384 return -EINVAL;
385 }
386
387 m = DIV_ROUND_UP_ULL(*prate, rate * 2);
388 if (m <= 0 && m > LPC18XX_PLL0_MSEL_MAX) {
389 pr_warn("%s: unable to support rate %lu\n", __func__, rate);
390 return -EINVAL;
391 }
392
393 return 2 * *prate * m;
394}
395
396static int lpc18xx_pll0_set_rate(struct clk_hw *hw, unsigned long rate,
397 unsigned long parent_rate)
398{
399 struct lpc18xx_pll *pll = to_lpc_pll(hw);
400 u32 ctrl, stat, m;
401 int retry = 3;
402
403 if (parent_rate < rate) {
404 pr_warn("%s: pll dividers not supported\n", __func__);
405 return -EINVAL;
406 }
407
408 m = DIV_ROUND_UP_ULL(parent_rate, rate * 2);
409 if (m <= 0 && m > LPC18XX_PLL0_MSEL_MAX) {
410 pr_warn("%s: unable to support rate %lu\n", __func__, rate);
411 return -EINVAL;
412 }
413
414 m = lpc18xx_pll0_msel2mdec(m);
415 m |= lpc18xx_pll0_msel2selp(m) << LPC18XX_PLL0_MDIV_SELP_SHIFT;
416 m |= lpc18xx_pll0_msel2seli(m) << LPC18XX_PLL0_MDIV_SELI_SHIFT;
417
418 /* Power down PLL, disable clk output and dividers */
419 ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
420 ctrl |= LPC18XX_PLL0_CTRL_PD;
421 ctrl &= ~(LPC18XX_PLL0_CTRL_BYPASS | LPC18XX_PLL0_CTRL_DIRECTI |
422 LPC18XX_PLL0_CTRL_DIRECTO | LPC18XX_PLL0_CTRL_CLKEN);
423 clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
424
425 /* Configure new PLL settings */
426 clk_writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
427 clk_writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
428
429 /* Power up PLL and wait for lock */
430 ctrl &= ~LPC18XX_PLL0_CTRL_PD;
431 clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
432 do {
433 udelay(10);
434 stat = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT);
435 if (stat & LPC18XX_PLL0_STAT_LOCK) {
436 ctrl |= LPC18XX_PLL0_CTRL_CLKEN;
437 clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
438
439 return 0;
440 }
441 } while (retry--);
442
443 pr_warn("%s: unable to lock pll\n", __func__);
444
445 return -EINVAL;
446}
447
448static const struct clk_ops lpc18xx_pll0_ops = {
449 .recalc_rate = lpc18xx_pll0_recalc_rate,
450 .round_rate = lpc18xx_pll0_round_rate,
451 .set_rate = lpc18xx_pll0_set_rate,
452};
453
454static unsigned long lpc18xx_pll1_recalc_rate(struct clk_hw *hw,
455 unsigned long parent_rate)
456{
457 struct lpc18xx_pll *pll = to_lpc_pll(hw);
458 u16 msel, nsel, psel;
459 bool direct, fbsel;
460 u32 stat, ctrl;
461
462 stat = clk_readl(pll->reg + LPC18XX_CGU_PLL1_STAT);
463 ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL1_CTRL);
464
465 direct = (ctrl & LPC18XX_PLL1_CTRL_DIRECT) ? true : false;
466 fbsel = (ctrl & LPC18XX_PLL1_CTRL_FBSEL) ? true : false;
467
468 msel = ((ctrl >> 16) & 0xff) + 1;
469 nsel = ((ctrl >> 12) & 0x3) + 1;
470
471 if (direct || fbsel)
472 return msel * (parent_rate / nsel);
473
474 psel = (ctrl >> 8) & 0x3;
475 psel = 1 << psel;
476
477 return (msel / (2 * psel)) * (parent_rate / nsel);
478}
479
480static const struct clk_ops lpc18xx_pll1_ops = {
481 .recalc_rate = lpc18xx_pll1_recalc_rate,
482};
483
484static struct lpc18xx_cgu_pll_clk lpc18xx_cgu_src_clk_plls[] = {
485 LPC1XX_CGU_CLK_PLL(PLL0USB, pll0_src_ids, pll0_ops),
486 LPC1XX_CGU_CLK_PLL(PLL0AUDIO, pll0_src_ids, pll0_ops),
487 LPC1XX_CGU_CLK_PLL(PLL1, pll1_src_ids, pll1_ops),
488};
489
490static void lpc18xx_fill_parent_names(const char **parent, u32 *id, int size)
491{
492 int i;
493
494 for (i = 0; i < size; i++)
495 parent[i] = clk_src_names[id[i]];
496}
497
498static struct clk *lpc18xx_cgu_register_div(struct lpc18xx_cgu_src_clk_div *clk,
499 void __iomem *base, int n)
500{
501 void __iomem *reg = base + LPC18XX_CGU_IDIV_CTRL(n);
502 const char *name = clk_src_names[clk->clk_id];
503 const char *parents[CLK_SRC_MAX];
504
505 clk->div.reg = reg;
506 clk->mux.reg = reg;
507 clk->gate.reg = reg;
508
509 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents);
510
511 return clk_register_composite(NULL, name, parents, clk->n_parents,
512 &clk->mux.hw, &clk_mux_ops,
513 &clk->div.hw, &clk_divider_ops,
514 &clk->gate.hw, &clk_gate_ops, 0);
515}
516
517
518static struct clk *lpc18xx_register_base_clk(struct lpc18xx_cgu_base_clk *clk,
519 void __iomem *reg_base, int n)
520{
521 void __iomem *reg = reg_base + LPC18XX_CGU_BASE_CLK(n);
522 const char *name = clk_base_names[clk->clk_id];
523 const char *parents[CLK_SRC_MAX];
524
525 if (clk->n_parents == 0)
526 return ERR_PTR(-ENOENT);
527
528 clk->mux.reg = reg;
529 clk->gate.reg = reg;
530
531 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents);
532
533 /* SAFE_CLK can not be turned off */
534 if (n == BASE_SAFE_CLK)
535 return clk_register_composite(NULL, name, parents, clk->n_parents,
536 &clk->mux.hw, &clk_mux_ops,
537 NULL, NULL, NULL, NULL, 0);
538
539 return clk_register_composite(NULL, name, parents, clk->n_parents,
540 &clk->mux.hw, &clk_mux_ops,
541 NULL, NULL,
542 &clk->gate.hw, &clk_gate_ops, 0);
543}
544
545
546static struct clk *lpc18xx_cgu_register_pll(struct lpc18xx_cgu_pll_clk *clk,
547 void __iomem *base)
548{
549 const char *name = clk_src_names[clk->clk_id];
550 const char *parents[CLK_SRC_MAX];
551
552 clk->pll.reg = base;
553 clk->mux.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET;
554 clk->gate.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET;
555
556 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents);
557
558 return clk_register_composite(NULL, name, parents, clk->n_parents,
559 &clk->mux.hw, &clk_mux_ops,
560 &clk->pll.hw, clk->pll_ops,
561 &clk->gate.hw, &clk_gate_ops, 0);
562}
563
564static void __init lpc18xx_cgu_register_source_clks(struct device_node *np,
565 void __iomem *base)
566{
567 const char *parents[CLK_SRC_MAX];
568 struct clk *clk;
569 int i;
570
571 /* Register the internal 12 MHz RC oscillator (IRC) */
572 clk = clk_register_fixed_rate(NULL, clk_src_names[CLK_SRC_IRC],
573 NULL, CLK_IS_ROOT, 12000000);
574 if (IS_ERR(clk))
575 pr_warn("%s: failed to register irc clk\n", __func__);
576
577 /* Register crystal oscillator controlller */
578 parents[0] = of_clk_get_parent_name(np, 0);
579 clk = clk_register_gate(NULL, clk_src_names[CLK_SRC_OSC], parents[0],
580 0, base + LPC18XX_CGU_XTAL_OSC_CTRL,
581 0, CLK_GATE_SET_TO_DISABLE, NULL);
582 if (IS_ERR(clk))
583 pr_warn("%s: failed to register osc clk\n", __func__);
584
585 /* Register all PLLs */
586 for (i = 0; i < ARRAY_SIZE(lpc18xx_cgu_src_clk_plls); i++) {
587 clk = lpc18xx_cgu_register_pll(&lpc18xx_cgu_src_clk_plls[i],
588 base);
589 if (IS_ERR(clk))
590 pr_warn("%s: failed to register pll (%d)\n", __func__, i);
591 }
592
593 /* Register all clock dividers A-E */
594 for (i = 0; i < ARRAY_SIZE(lpc18xx_cgu_src_clk_divs); i++) {
595 clk = lpc18xx_cgu_register_div(&lpc18xx_cgu_src_clk_divs[i],
596 base, i);
597 if (IS_ERR(clk))
598 pr_warn("%s: failed to register div %d\n", __func__, i);
599 }
600}
601
602static struct clk *clk_base[BASE_CLK_MAX];
603static struct clk_onecell_data clk_base_data = {
604 .clks = clk_base,
605 .clk_num = BASE_CLK_MAX,
606};
607
608static void __init lpc18xx_cgu_register_base_clks(void __iomem *reg_base)
609{
610 int i;
611
612 for (i = BASE_SAFE_CLK; i < BASE_CLK_MAX; i++) {
613 clk_base[i] = lpc18xx_register_base_clk(&lpc18xx_cgu_base_clks[i],
614 reg_base, i);
615 if (IS_ERR(clk_base[i]) && PTR_ERR(clk_base[i]) != -ENOENT)
616 pr_warn("%s: register base clk %d failed\n", __func__, i);
617 }
618}
619
620static void __init lpc18xx_cgu_init(struct device_node *np)
621{
622 void __iomem *reg_base;
623
624 reg_base = of_iomap(np, 0);
625 if (!reg_base) {
626 pr_warn("%s: failed to map address range\n", __func__);
627 return;
628 }
629
630 lpc18xx_cgu_register_source_clks(np, reg_base);
631 lpc18xx_cgu_register_base_clks(reg_base);
632
633 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_base_data);
634}
635CLK_OF_DECLARE(lpc18xx_cgu, "nxp,lpc1850-cgu", lpc18xx_cgu_init);
diff --git a/include/dt-bindings/clock/lpc18xx-cgu.h b/include/dt-bindings/clock/lpc18xx-cgu.h
new file mode 100644
index 000000000000..6e57c6d2ca66
--- /dev/null
+++ b/include/dt-bindings/clock/lpc18xx-cgu.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com>
3 *
4 * This code is released using a dual license strategy: BSD/GPL
5 * You can choose the licence that better fits your requirements.
6 *
7 * Released under the terms of 3-clause BSD License
8 * Released under the terms of GNU General Public License Version 2.0
9 *
10 */
11
12/* LPC18xx/43xx base clock ids */
13#define BASE_SAFE_CLK 0
14#define BASE_USB0_CLK 1
15#define BASE_PERIPH_CLK 2
16#define BASE_USB1_CLK 3
17#define BASE_CPU_CLK 4
18#define BASE_SPIFI_CLK 5
19#define BASE_SPI_CLK 6
20#define BASE_PHY_RX_CLK 7
21#define BASE_PHY_TX_CLK 8
22#define BASE_APB1_CLK 9
23#define BASE_APB3_CLK 10
24#define BASE_LCD_CLK 11
25#define BASE_ADCHS_CLK 12
26#define BASE_SDIO_CLK 13
27#define BASE_SSP0_CLK 14
28#define BASE_SSP1_CLK 15
29#define BASE_UART0_CLK 16
30#define BASE_UART1_CLK 17
31#define BASE_UART2_CLK 18
32#define BASE_UART3_CLK 19
33#define BASE_OUT_CLK 20
34#define BASE_RES1_CLK 21
35#define BASE_RES2_CLK 22
36#define BASE_RES3_CLK 23
37#define BASE_RES4_CLK 24
38#define BASE_AUDIO_CLK 25
39#define BASE_CGU_OUT0_CLK 26
40#define BASE_CGU_OUT1_CLK 27
41#define BASE_CLK_MAX (BASE_CGU_OUT1_CLK + 1)
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-26 03:56:45 -0500