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-rw-r--r--sound/soc/codecs/rt5640.c8
-rw-r--r--sound/soc/codecs/rt5640.h2
2 files changed, 1 insertions, 9 deletions
diff --git a/sound/soc/codecs/rt5640.c b/sound/soc/codecs/rt5640.c
index 19634d0992bc..4c866135e40f 100644
--- a/sound/soc/codecs/rt5640.c
+++ b/sound/soc/codecs/rt5640.c
@@ -487,7 +487,7 @@ static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
487 487
488 val = snd_soc_read(source->codec, RT5640_GLB_CLK); 488 val = snd_soc_read(source->codec, RT5640_GLB_CLK);
489 val &= RT5640_SCLK_SRC_MASK; 489 val &= RT5640_SCLK_SRC_MASK;
490 if (val == RT5640_SCLK_SRC_PLL1 || val == RT5640_SCLK_SRC_PLL1T) 490 if (val == RT5640_SCLK_SRC_PLL1)
491 return 1; 491 return 1;
492 else 492 else
493 return 0; 493 return 0;
@@ -1694,12 +1694,6 @@ static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai,
1694 case RT5640_SCLK_S_PLL1: 1694 case RT5640_SCLK_S_PLL1:
1695 reg_val |= RT5640_SCLK_SRC_PLL1; 1695 reg_val |= RT5640_SCLK_SRC_PLL1;
1696 break; 1696 break;
1697 case RT5640_SCLK_S_PLL1_TK:
1698 reg_val |= RT5640_SCLK_SRC_PLL1T;
1699 break;
1700 case RT5640_SCLK_S_RCCLK:
1701 reg_val |= RT5640_SCLK_SRC_RCCLK;
1702 break;
1703 default: 1697 default:
1704 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); 1698 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
1705 return -EINVAL; 1699 return -EINVAL;
diff --git a/sound/soc/codecs/rt5640.h b/sound/soc/codecs/rt5640.h
index 5e8df25a13f3..cbd07b5f8060 100644
--- a/sound/soc/codecs/rt5640.h
+++ b/sound/soc/codecs/rt5640.h
@@ -976,8 +976,6 @@
976#define RT5640_SCLK_SRC_SFT 14 976#define RT5640_SCLK_SRC_SFT 14
977#define RT5640_SCLK_SRC_MCLK (0x0 << 14) 977#define RT5640_SCLK_SRC_MCLK (0x0 << 14)
978#define RT5640_SCLK_SRC_PLL1 (0x1 << 14) 978#define RT5640_SCLK_SRC_PLL1 (0x1 << 14)
979#define RT5640_SCLK_SRC_PLL1T (0x2 << 14)
980#define RT5640_SCLK_SRC_RCCLK (0x3 << 14) /* 15MHz */
981#define RT5640_PLL1_SRC_MASK (0x3 << 12) 979#define RT5640_PLL1_SRC_MASK (0x3 << 12)
982#define RT5640_PLL1_SRC_SFT 12 980#define RT5640_PLL1_SRC_SFT 12
983#define RT5640_PLL1_SRC_MCLK (0x0 << 12) 981#define RT5640_PLL1_SRC_MCLK (0x0 << 12)