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-rw-r--r--arch/x86/include/asm/cpufeatures.h508
1 files changed, 254 insertions, 254 deletions
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 74370734663c..ad1b835001cc 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -13,8 +13,8 @@
13/* 13/*
14 * Defines x86 CPU feature bits 14 * Defines x86 CPU feature bits
15 */ 15 */
16#define NCAPINTS 18 /* N 32-bit words worth of info */ 16#define NCAPINTS 18 /* N 32-bit words worth of info */
17#define NBUGINTS 1 /* N 32-bit bug flags */ 17#define NBUGINTS 1 /* N 32-bit bug flags */
18 18
19/* 19/*
20 * Note: If the comment begins with a quoted string, that string is used 20 * Note: If the comment begins with a quoted string, that string is used
@@ -28,163 +28,163 @@
28 */ 28 */
29 29
30/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ 30/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
31#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ 31#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */
32#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ 32#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */
33#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ 33#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */
34#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ 34#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */
35#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ 35#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */
36#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ 36#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
37#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ 37#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */
38#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ 38#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */
39#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ 39#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */
40#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ 40#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */
41#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ 41#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */
42#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ 42#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */
43#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ 43#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */
44#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ 44#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */
45#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ 45#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */
46 /* (plus FCMOVcc, FCOMI with FPU) */ 46 /* (plus FCMOVcc, FCOMI with FPU) */
47#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ 47#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */
48#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ 48#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
49#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ 49#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */
50#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ 50#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */
51#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ 51#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */
52#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ 52#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */
53#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ 53#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */
54#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ 54#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
55#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ 55#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */
56#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ 56#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */
57#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ 57#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */
58#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ 58#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
59#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ 59#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */
60#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ 60#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */
61#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ 61#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */
62 62
63/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ 63/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
64/* Don't duplicate feature flags which are redundant with Intel! */ 64/* Don't duplicate feature flags which are redundant with Intel! */
65#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ 65#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */
66#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ 66#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */
67#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ 67#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */
68#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ 68#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */
69#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ 69#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */
70#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ 70#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */
71#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ 71#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */
72#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ 72#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */
73#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ 73#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */
74#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ 74#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */
75 75
76/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ 76/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
77#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ 77#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */
78#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ 78#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */
79#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ 79#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */
80 80
81/* Other features, Linux-defined mapping, word 3 */ 81/* Other features, Linux-defined mapping, word 3 */
82/* This range is used for feature bits which conflict or are synthesized */ 82/* This range is used for feature bits which conflict or are synthesized */
83#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ 83#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */
84#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ 84#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
85#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ 85#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
86#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ 86#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
87/* cpu types for specific tunings: */ 87/* cpu types for specific tunings: */
88#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ 88#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */
89#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ 89#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */
90#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ 90#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */
91#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ 91#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */
92#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ 92#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
93#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ 93#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */
94#define X86_FEATURE_ART ( 3*32+10) /* Platform has always running timer (ART) */ 94#define X86_FEATURE_ART ( 3*32+10) /* Platform has always running timer (ART) */
95#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ 95#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */
96#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ 96#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */
97#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ 97#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */
98#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ 98#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */
99#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ 99#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */
100#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ 100#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */
101#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ 101#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */
102#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ 102#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */
103#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ 103#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
104#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ 104#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
105#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ 105#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
106#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ 106#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */
107#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ 107#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
108#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ 108#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
109#define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */ 109#define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */
110#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ 110#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
111#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ 111#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
112#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ 112#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
113#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ 113#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
114#define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ 114#define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */
115 115
116/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ 116/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
117#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ 117#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
118#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ 118#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */
119#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ 119#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */
120#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ 120#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */
121#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ 121#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
122#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ 122#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */
123#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ 123#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */
124#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ 124#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */
125#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ 125#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */
126#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ 126#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */
127#define X86_FEATURE_CID ( 4*32+10) /* Context ID */ 127#define X86_FEATURE_CID ( 4*32+10) /* Context ID */
128#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ 128#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */
129#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */