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-rw-r--r--MAINTAINERS2
-rw-r--r--arch/mips/Kbuild2
-rw-r--r--arch/mips/Kconfig24
-rw-r--r--arch/mips/Kconfig.debug2
-rw-r--r--arch/mips/cavium-octeon/Kconfig9
-rw-r--r--arch/mips/cavium-octeon/Platform4
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-l2c.c139
-rw-r--r--arch/mips/cavium-octeon/executive/octeon-model.c21
-rw-r--r--arch/mips/cavium-octeon/octeon-platform.c113
-rw-r--r--arch/mips/cavium-octeon/setup.c12
-rw-r--r--arch/mips/configs/generic_defconfig3
-rw-r--r--arch/mips/include/asm/cache.h5
-rw-r--r--arch/mips/include/asm/cpu-info.h3
-rw-r--r--arch/mips/include/asm/cpufeature.h26
-rw-r--r--arch/mips/include/asm/mach-rm/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2c-defs.h3193
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2c.h59
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2d-defs.h526
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2t-defs.h286
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pciercx-defs.h3225
-rw-r--r--arch/mips/include/asm/octeon/cvmx-sli-defs.h3541
-rw-r--r--arch/mips/include/asm/octeon/cvmx.h3
-rw-r--r--arch/mips/include/asm/pgalloc.h26
-rw-r--r--arch/mips/include/asm/pgtable-64.h88
-rw-r--r--arch/mips/include/asm/uasm.h88
-rw-r--r--arch/mips/kernel/cpu-probe.c7
-rw-r--r--arch/mips/kernel/mips-r2-to-r6-emul.c16
-rw-r--r--arch/mips/kernel/process.c6
-rw-r--r--arch/mips/kernel/r4k_switch.S6
-rw-r--r--arch/mips/kernel/smp-cps.c7
-rw-r--r--arch/mips/kernel/smp-mt.c49
-rw-r--r--arch/mips/kernel/smp.c20
-rw-r--r--arch/mips/lantiq/irq.c52
-rw-r--r--arch/mips/math-emu/cp1emu.c10
-rw-r--r--arch/mips/mm/fault.c16
-rw-r--r--arch/mips/mm/init.c3
-rw-r--r--arch/mips/mm/pgtable-64.c33
-rw-r--r--arch/mips/mm/tlbex.c22
-rw-r--r--arch/mips/mm/uasm-mips.c1
-rw-r--r--arch/mips/mm/uasm.c159
-rw-r--r--arch/mips/mti-malta/malta-int.c83
-rw-r--r--arch/mips/net/bpf_jit.c41
-rw-r--r--arch/mips/net/bpf_jit_asm.S23
-rw-r--r--arch/mips/pci/pcie-octeon.c4
-rw-r--r--arch/mips/sibyte/bcm1480/setup.c1
-rw-r--r--arch/mips/sibyte/sb1250/setup.c1
-rw-r--r--drivers/cpufreq/loongson2_cpufreq.c7
-rw-r--r--drivers/irqchip/Kconfig2
-rw-r--r--drivers/irqchip/irq-mips-cpu.c146
-rw-r--r--drivers/net/ethernet/broadcom/sb1250-mac.c1
50 files changed, 1209 insertions, 10909 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 12a0b416aa06..6b36037cbe8f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7923,7 +7923,7 @@ L: linux-man@vger.kernel.org
7923S: Maintained 7923S: Maintained
7924 7924
7925MARDUK (CREATOR CI40) DEVICE TREE SUPPORT 7925MARDUK (CREATOR CI40) DEVICE TREE SUPPORT
7926M: Rahul Bedarkar <rahul.bedarkar@imgtec.com> 7926M: Rahul Bedarkar <rahulbedarkar89@gmail.com>
7927L: linux-mips@linux-mips.org 7927L: linux-mips@linux-mips.org
7928S: Maintained 7928S: Maintained
7929F: arch/mips/boot/dts/img/pistachio_marduk.dts 7929F: arch/mips/boot/dts/img/pistachio_marduk.dts
diff --git a/arch/mips/Kbuild b/arch/mips/Kbuild
index 5c3f688a5232..5cef58651db0 100644
--- a/arch/mips/Kbuild
+++ b/arch/mips/Kbuild
@@ -1,7 +1,9 @@
1# Fail on warnings - also for files referenced in subdirs 1# Fail on warnings - also for files referenced in subdirs
2# -Werror can be disabled for specific files using: 2# -Werror can be disabled for specific files using:
3# CFLAGS_<file.o> := -Wno-error 3# CFLAGS_<file.o> := -Wno-error
4ifeq ($(W),)
4subdir-ccflags-y := -Werror 5subdir-ccflags-y := -Werror
6endif
5 7
6# platform specific definitions 8# platform specific definitions
7include arch/mips/Kbuild.platforms 9include arch/mips/Kbuild.platforms
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 4e9ebf65d071..2828ecde133d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -46,6 +46,7 @@ config MIPS
46 select ARCH_DISCARD_MEMBLOCK 46 select ARCH_DISCARD_MEMBLOCK
47 select GENERIC_SMP_IDLE_THREAD 47 select GENERIC_SMP_IDLE_THREAD
48 select BUILDTIME_EXTABLE_SORT 48 select BUILDTIME_EXTABLE_SORT
49 select GENERIC_CPU_AUTOPROBE
49 select GENERIC_CLOCKEVENTS 50 select GENERIC_CLOCKEVENTS
50 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC 51 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
51 select GENERIC_CMOS_UPDATE 52 select GENERIC_CMOS_UPDATE
@@ -68,6 +69,7 @@ config MIPS
68 select HANDLE_DOMAIN_IRQ 69 select HANDLE_DOMAIN_IRQ
69 select HAVE_EXIT_THREAD 70 select HAVE_EXIT_THREAD
70 select HAVE_REGS_AND_STACK_ACCESS_API 71 select HAVE_REGS_AND_STACK_ACCESS_API
72 select HAVE_COPY_THREAD_TLS
71 73
72menu "Machine selection" 74menu "Machine selection"
73 75
@@ -1039,14 +1041,6 @@ config RWSEM_GENERIC_SPINLOCK
1039config RWSEM_XCHGADD_ALGORITHM 1041config RWSEM_XCHGADD_ALGORITHM
1040 bool 1042 bool
1041 1043
1042config ARCH_HAS_ILOG2_U32
1043 bool
1044 default n
1045
1046config ARCH_HAS_ILOG2_U64
1047 bool
1048 default n
1049
1050config GENERIC_HWEIGHT 1044config GENERIC_HWEIGHT
1051 bool 1045 bool
1052 default y 1046 default y
@@ -1372,6 +1366,7 @@ config CPU_LOONGSON3
1372 select WEAK_ORDERING 1366 select WEAK_ORDERING
1373 select WEAK_REORDERING_BEYOND_LLSC 1367 select WEAK_REORDERING_BEYOND_LLSC
1374 select MIPS_PGD_C0_CONTEXT 1368 select MIPS_PGD_C0_CONTEXT
1369 select MIPS_L1_CACHE_SHIFT_6
1375 select GPIOLIB 1370 select GPIOLIB
1376 help 1371 help
1377 The Loongson 3 processor implements the MIPS64R2 instruction 1372 The Loongson 3 processor implements the MIPS64R2 instruction
@@ -2120,10 +2115,13 @@ config MIPS_VA_BITS_48
2120 bool "48 bits virtual memory" 2115 bool "48 bits virtual memory"
2121 depends on 64BIT 2116 depends on 64BIT
2122 help 2117 help
2123 Support a maximum at least 48 bits of application virtual memory. 2118 Support a maximum at least 48 bits of application virtual
2124 Default is 40 bits or less, depending on the CPU. 2119 memory. Default is 40 bits or less, depending on the CPU.
2125 This option result in a small memory overhead for page tables. 2120 For page sizes 16k and above, this option results in a small
2126 This option is only supported with 16k and 64k page sizes. 2121 memory overhead for page tables. For 4k page size, a fourth
2122 level of page tables is added which imposes both a memory
2123 overhead as well as slower TLB fault handling.
2124
2127 If unsure, say N. 2125 If unsure, say N.
2128 2126
2129choice 2127choice
@@ -2133,7 +2131,6 @@ choice
2133config PAGE_SIZE_4KB 2131config PAGE_SIZE_4KB
2134 bool "4kB" 2132 bool "4kB"
2135 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3 2133 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
2136 depends on !MIPS_VA_BITS_48
2137 help 2134 help
2138 This option select the standard 4kB Linux page size. On some 2135 This option select the standard 4kB Linux page size. On some
2139 R3000-family processors this is the only available page size. Using 2136 R3000-family processors this is the only available page size. Using
@@ -2982,6 +2979,7 @@ config HAVE_LATENCYTOP_SUPPORT
2982 2979
2983config PGTABLE_LEVELS 2980config PGTABLE_LEVELS
2984 int 2981 int
2982 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
2985 default 3 if 64BIT && !PAGE_SIZE_64KB 2983 default 3 if 64BIT && !PAGE_SIZE_64KB
2986 default 2 2984 default 2
2987 2985
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index 7f975b20b20c..42a97c59200f 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -82,7 +82,7 @@ config CMDLINE_OVERRIDE
82config SB1XXX_CORELIS 82config SB1XXX_CORELIS
83 bool "Corelis Debugger" 83 bool "Corelis Debugger"
84 depends on SIBYTE_SB1xxx_SOC 84 depends on SIBYTE_SB1xxx_SOC
85 select DEBUG_INFO 85 select DEBUG_INFO if !COMPILE_TEST
86 help 86 help
87 Select compile flags that produce code that can be processed by the 87 Select compile flags that produce code that can be processed by the
88 Corelis mksym utility and UDB Emulator. 88 Corelis mksym utility and UDB Emulator.
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index c370426a7322..5c0b56203bae 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -25,15 +25,6 @@ endif # CPU_CAVIUM_OCTEON
25 25
26if CAVIUM_OCTEON_SOC 26if CAVIUM_OCTEON_SOC
27 27
28config CAVIUM_OCTEON_2ND_KERNEL
29 bool "Build the kernel to be used as a 2nd kernel on the same chip"
30 default "n"
31 help
32 This option configures this kernel to be linked at a different
33 address and use the 2nd uart for output. This allows a kernel built
34 with this option to be run at the same time as one built without this
35 option.
36
37config CAVIUM_OCTEON_LOCK_L2 28config CAVIUM_OCTEON_LOCK_L2
38 bool "Lock often used kernel code in the L2" 29 bool "Lock often used kernel code in the L2"
39 default "y" 30 default "y"
diff --git a/arch/mips/cavium-octeon/Platform b/arch/mips/cavium-octeon/Platform
index 8a301cb12d68..45be853700e6 100644
--- a/arch/mips/cavium-octeon/Platform
+++ b/arch/mips/cavium-octeon/Platform
@@ -4,8 +4,4 @@
4platform-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon/ 4platform-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon/
5cflags-$(CONFIG_CAVIUM_OCTEON_SOC) += \ 5cflags-$(CONFIG_CAVIUM_OCTEON_SOC) += \
6 -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon 6 -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
7ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
8load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff84100000
9else
10load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff81100000 7load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff81100000
11endif
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
index 89b5273299ab..f091c9b70603 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2010 Cavium Networks 7 * Copyright (c) 2003-2017 Cavium, Inc.
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -239,6 +239,7 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
239 else { 239 else {
240 uint64_t counter = 0; 240 uint64_t counter = 0;
241 int tad; 241 int tad;
242
242 for (tad = 0; tad < CVMX_L2C_TADS; tad++) 243 for (tad = 0; tad < CVMX_L2C_TADS; tad++)
243 counter += cvmx_read_csr(CVMX_L2C_TADX_PFC0(tad)); 244 counter += cvmx_read_csr(CVMX_L2C_TADX_PFC0(tad));
244 return counter; 245 return counter;
@@ -249,6 +250,7 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
249 else { 250 else {
250 uint64_t counter = 0; 251 uint64_t counter = 0;
251 int tad; 252 int tad;
253
252 for (tad = 0; tad < CVMX_L2C_TADS; tad++) 254 for (tad = 0; tad < CVMX_L2C_TADS; tad++)
253 counter += cvmx_read_csr(CVMX_L2C_TADX_PFC1(tad)); 255 counter += cvmx_read_csr(CVMX_L2C_TADX_PFC1(tad));
254 return counter; 256 return counter;
@@ -259,6 +261,7 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
259 else { 261 else {
260 uint64_t counter = 0; 262 uint64_t counter = 0;
261 int tad; 263 int tad;
264
262 for (tad = 0; tad < CVMX_L2C_TADS; tad++) 265 for (tad = 0; tad < CVMX_L2C_TADS; tad++)
263 counter += cvmx_read_csr(CVMX_L2C_TADX_PFC2(tad)); 266 counter += cvmx_read_csr(CVMX_L2C_TADX_PFC2(tad));
264 return counter; 267 return counter;
@@ -270,6 +273,7 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
270 else { 273 else {
271 uint64_t counter = 0; 274 uint64_t counter = 0;
272 int tad; 275 int tad;
276
273 for (tad = 0; tad < CVMX_L2C_TADS; tad++) 277 for (tad = 0; tad < CVMX_L2C_TADS; tad++)
274 counter += cvmx_read_csr(CVMX_L2C_TADX_PFC3(tad)); 278 counter += cvmx_read_csr(CVMX_L2C_TADX_PFC3(tad));
275 return counter; 279 return counter;
@@ -301,7 +305,7 @@ static void fault_in(uint64_t addr, int len)
301 */ 305 */
302 CVMX_DCACHE_INVALIDATE; 306 CVMX_DCACHE_INVALIDATE;
303 while (len > 0) { 307 while (len > 0) {
304 ACCESS_ONCE(*ptr); 308 READ_ONCE(*ptr);
305 len -= CVMX_CACHE_LINE_SIZE; 309 len -= CVMX_CACHE_LINE_SIZE;
306 ptr += CVMX_CACHE_LINE_SIZE; 310 ptr += CVMX_CACHE_LINE_SIZE;
307 } 311 }
@@ -375,7 +379,9 @@ int cvmx_l2c_lock_line(uint64_t addr)
375 if (((union cvmx_l2c_cfg)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) { 379 if (((union cvmx_l2c_cfg)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {
376 int alias_shift = CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1; 380 int alias_shift = CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
377 uint64_t addr_tmp = addr ^ (addr & ((1 << alias_shift) - 1)) >> CVMX_L2_SET_BITS; 381 uint64_t addr_tmp = addr ^ (addr & ((1 << alias_shift) - 1)) >> CVMX_L2_SET_BITS;
382
378 lckbase.s.lck_base = addr_tmp >> 7; 383 lckbase.s.lck_base = addr_tmp >> 7;
384
379 } else { 385 } else {
380 lckbase.s.lck_base = addr >> 7; 386 lckbase.s.lck_base = addr >> 7;
381 } 387 }
@@ -435,6 +441,7 @@ void cvmx_l2c_flush(void)
435 /* These may look like constants, but they aren't... */ 441 /* These may look like constants, but they aren't... */
436 int assoc_shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT; 442 int assoc_shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
437 int set_shift = CVMX_L2C_IDX_ADDR_SHIFT; 443 int set_shift = CVMX_L2C_IDX_ADDR_SHIFT;
444
438 for (set = 0; set < n_set; set++) { 445 for (set = 0; set < n_set; set++) {
439 for (assoc = 0; assoc < n_assoc; assoc++) { 446 for (assoc = 0; assoc < n_assoc; assoc++) {
440 address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, 447 address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
@@ -519,89 +526,49 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len)
519union __cvmx_l2c_tag { 526union __cvmx_l2c_tag {
520 uint64_t u64; 527 uint64_t u64;
521 struct cvmx_l2c_tag_cn50xx { 528 struct cvmx_l2c_tag_cn50xx {
522#ifdef __BIG_ENDIAN_BITFIELD 529 __BITFIELD_FIELD(uint64_t reserved:40,
523 uint64_t reserved:40; 530 __BITFIELD_FIELD(uint64_t V:1, /* Line valid */
524 uint64_t V:1; /* Line valid */ 531 __BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
525 uint64_t D:1; /* Line dirty */ 532 __BITFIELD_FIELD(uint64_t L:1, /* Line locked */
526 uint64_t L:1; /* Line locked */ 533 __BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
527 uint64_t U:1; /* Use, LRU eviction */ 534 __BITFIELD_FIELD(uint64_t addr:20, /* Phys addr (33..14) */
528 uint64_t addr:20; /* Phys mem addr (33..14) */ 535 ;))))))
529#else
530 uint64_t addr:20; /* Phys mem addr (33..14) */
531 uint64_t U:1; /* Use, LRU eviction */
532 uint64_t L:1; /* Line locked */
533 uint64_t D:1; /* Line dirty */
534 uint64_t V:1; /* Line valid */
535 uint64_t reserved:40;
536#endif
537 } cn50xx; 536 } cn50xx;
538 struct cvmx_l2c_tag_cn30xx { 537 struct cvmx_l2c_tag_cn30xx {
539#ifdef __BIG_ENDIAN_BITFIELD 538 __BITFIELD_FIELD(uint64_t reserved:41,
540 uint64_t reserved:41; 539 __BITFIELD_FIELD(uint64_t V:1, /* Line valid */
541 uint64_t V:1; /* Line valid */ 540 __BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
542 uint64_t D:1; /* Line dirty */ 541 __BITFIELD_FIELD(uint64_t L:1, /* Line locked */
543 uint64_t L:1; /* Line locked */ 542 __BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
544 uint64_t U:1; /* Use, LRU eviction */ 543 __BITFIELD_FIELD(uint64_t addr:19, /* Phys addr (33..15) */
545 uint64_t addr:19; /* Phys mem addr (33..15) */ 544 ;))))))
546#else
547 uint64_t addr:19; /* Phys mem addr (33..15) */
548 uint64_t U:1; /* Use, LRU eviction */
549 uint64_t L:1; /* Line locked */
550 uint64_t D:1; /* Line dirty */
551 uint64_t V:1; /* Line valid */
552 uint64_t reserved:41;
553#endif
554 } cn30xx; 545 } cn30xx;
555 struct cvmx_l2c_tag_cn31xx { 546 struct cvmx_l2c_tag_cn31xx {
556#ifdef __BIG_ENDIAN_BITFIELD 547 __BITFIELD_FIELD(uint64_t reserved:42,
557 uint64_t reserved:42; 548 __BITFIELD_FIELD(uint64_t V:1, /* Line valid */
558 uint64_t V:1; /* Line valid */ 549 __BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
559 uint64_t D:1; /* Line dirty */ 550 __BITFIELD_FIELD(uint64_t L:1, /* Line locked */
560 uint64_t L:1; /* Line locked */ 551 __BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
561 uint64_t U:1; /* Use, LRU eviction */ 552 __BITFIELD_FIELD(uint64_t addr:18, /* Phys addr (33..16) */
562 uint64_t addr:18; /* Phys mem addr (33..16) */ 553 ;))))))
563#else
564 uint64_t addr:18; /* Phys mem addr (33..16) */
565 uint64_t U:1; /* Use, LRU eviction */
566 uint64_t L:1; /* Line locked */
567 uint64_t D:1; /* Line dirty */
568 uint64_t V:1; /* Line valid */
569 uint64_t reserved:42;
570#endif
571 } cn31xx; 554 } cn31xx;
572 struct cvmx_l2c_tag_cn38xx { 555 struct cvmx_l2c_tag_cn38xx {
573#ifdef __BIG_ENDIAN_BITFIELD 556 __BITFIELD_FIELD(uint64_t reserved:43,
574 uint64_t reserved:43; 557 __BITFIELD_FIELD(uint64_t V:1, /* Line valid */
575 uint64_t V:1; /* Line valid */ 558 __BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
576 uint64_t D:1; /* Line dirty */ 559 __BITFIELD_FIELD(uint64_t L:1, /* Line locked */
577 uint64_t L:1; /* Line locked */ 560 __BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
578 uint64_t U:1; /* Use, LRU eviction */ 561 __BITFIELD_FIELD(uint64_t addr:17, /* Phys addr (33..17) */
579 uint64_t addr:17; /* Phys mem addr (33..17) */ 562 ;))))))
580#else
581 uint64_t addr:17; /* Phys mem addr (33..17) */
582 uint64_t U:1; /* Use, LRU eviction */
583 uint64_t L:1; /* Line locked */
584 uint64_t D:1; /* Line dirty */
585 uint64_t V:1; /* Line valid */
586 uint64_t reserved:43;
587#endif
588 } cn38xx; 563 } cn38xx;
589 struct cvmx_l2c_tag_cn58xx { 564 struct cvmx_l2c_tag_cn58xx {
590#ifdef __BIG_ENDIAN_BITFIELD 565 __BITFIELD_FIELD(uint64_t reserved:44,
591 uint64_t reserved:44; 566 __BITFIELD_FIELD(uint64_t V:1, /* Line valid */
592 uint64_t V:1; /* Line valid */ 567 __BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
593 uint64_t D:1; /* Line dirty */ 568 __BITFIELD_FIELD(uint64_t L:1, /* Line locked */
594 uint64_t L:1; /* Line locked */ 569 __BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
595 uint64_t U:1; /* Use, LRU eviction */ 570 __BITFIELD_FIELD(uint64_t addr:16, /* Phys addr (33..18) */
596 uint64_t addr:16; /* Phys mem addr (33..18) */ 571 ;))))))
597#else
598 uint64_t addr:16; /* Phys mem addr (33..18) */
599 uint64_t U:1; /* Use, LRU eviction */
600 uint64_t L:1; /* Line locked */
601 uint64_t D:1; /* Line dirty */
602 uint64_t V:1; /* Line valid */
603 uint64_t reserved:44;
604#endif
605 } cn58xx; 572 } cn58xx;
606 struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */ 573 struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */
607 struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */ 574 struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */
@@ -629,8 +596,8 @@ static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
629 union __cvmx_l2c_tag tag_val; 596 union __cvmx_l2c_tag tag_val;
630 uint64_t dbg_addr = CVMX_L2C_DBG; 597 uint64_t dbg_addr = CVMX_L2C_DBG;
631 unsigned long flags; 598 unsigned long flags;
632
633 union cvmx_l2c_dbg debug_val; 599 union cvmx_l2c_dbg debug_val;
600
634 debug_val.u64 = 0; 601 debug_val.u64 = 0;
635 /* 602 /*
636 * For low core count parts, the core number is always small 603 * For low core count parts, the core number is always small
@@ -683,8 +650,8 @@ static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
683union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index) 650union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
684{ 651{
685 union cvmx_l2c_tag tag; 652 union cvmx_l2c_tag tag;
686 tag.u64 = 0;
687 653
654 tag.u64 = 0;
688 if ((int)association >= cvmx_l2c_get_num_assoc()) { 655 if ((int)association >= cvmx_l2c_get_num_assoc()) {
689 cvmx_dprintf("ERROR: cvmx_l2c_get_tag association out of range\n"); 656 cvmx_dprintf("ERROR: cvmx_l2c_get_tag association out of range\n");
690 return tag; 657 return tag;
@@ -767,10 +734,12 @@ uint32_t cvmx_l2c_address_to_index(uint64_t addr)
767 734
768 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 735 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
769 union cvmx_l2c_ctl l2c_ctl; 736 union cvmx_l2c_ctl l2c_ctl;
737
770 l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL); 738 l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
771 indxalias = !l2c_ctl.s.disidxalias; 739 indxalias = !l2c_ctl.s.disidxalias;
772 } else { 740 } else {
773 union cvmx_l2c_cfg l2c_cfg; 741 union cvmx_l2c_cfg l2c_cfg;
742
774 l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG); 743 l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
775 indxalias = l2c_cfg.s.idxalias; 744 indxalias = l2c_cfg.s.idxalias;
776 } 745 }
@@ -778,6 +747,7 @@ uint32_t cvmx_l2c_address_to_index(uint64_t addr)
778 if (indxalias) { 747 if (indxalias) {
779 if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { 748 if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
780 uint32_t a_14_12 = (idx / (CVMX_L2C_MEMBANK_SELECT_SIZE/(1<<CVMX_L2C_IDX_ADDR_SHIFT))) & 0x7; 749 uint32_t a_14_12 = (idx / (CVMX_L2C_MEMBANK_SELECT_SIZE/(1<<CVMX_L2C_IDX_ADDR_SHIFT))) & 0x7;
750
781 idx ^= idx / cvmx_l2c_get_num_sets(); 751 idx ^= idx / cvmx_l2c_get_num_sets();
782 idx ^= a_14_12; 752 idx ^= a_14_12;
783 } else { 753 } else {
@@ -801,6 +771,7 @@ int cvmx_l2c_get_cache_size_bytes(void)
801int cvmx_l2c_get_set_bits(void) 771int cvmx_l2c_get_set_bits(void)
802{ 772{
803 int l2_set_bits; 773 int l2_set_bits;
774
804 if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) 775 if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
805 l2_set_bits = 11; /* 2048 sets */ 776 l2_set_bits = 11; /* 2048 sets */
806 else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) 777 else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
@@ -828,6 +799,7 @@ int cvmx_l2c_get_num_sets(void)
828int cvmx_l2c_get_num_assoc(void) 799int cvmx_l2c_get_num_assoc(void)
829{ 800{
830 int l2_assoc; 801 int l2_assoc;
802
831 if (OCTEON_IS_MODEL(OCTEON_CN56XX) || 803 if (OCTEON_IS_MODEL(OCTEON_CN56XX) ||
832 OCTEON_IS_MODEL(OCTEON_CN52XX) || 804 OCTEON_IS_MODEL(OCTEON_CN52XX) ||
833 OCTEON_IS_MODEL(OCTEON_CN58XX) || 805 OCTEON_IS_MODEL(OCTEON_CN58XX) ||
@@ -869,16 +841,17 @@ int cvmx_l2c_get_num_assoc(void)
869 else if (mio_fus_dat3.s.l2c_crip == 1) 841 else if (mio_fus_dat3.s.l2c_crip == 1)
870 l2_assoc = 12; 842 l2_assoc = 12;
871 } else { 843 } else {
872 union cvmx_l2d_fus3 val; 844 uint64_t l2d_fus3;
873 val.u64 = cvmx_read_csr(CVMX_L2D_FUS3); 845
846 l2d_fus3 = cvmx_read_csr(CVMX_L2D_FUS3);
874 /* 847 /*
875 * Using shifts here, as bit position names are 848 * Using shifts here, as bit position names are
876 * different for each model but they all mean the 849 * different for each model but they all mean the
877 * same. 850 * same.
878 */ 851 */
879 if ((val.u64 >> 35) & 0x1) 852 if ((l2d_fus3 >> 35) & 0x1)
880 l2_assoc = l2_assoc >> 2; 853 l2_assoc = l2_assoc >> 2;
881 else if ((val.u64 >> 34) & 0x1) 854 else if ((l2d_fus3 >> 34) & 0x1)
882 l2_assoc = l2_assoc >> 1; 855 l2_assoc = l2_assoc >> 1;
883 } 856 }
884 return l2_assoc; 857 return l2_assoc;
diff --git a/arch/mips/cavium-octeon/executive/octeon-model.c b/arch/mips/cavium-octeon/executive/octeon-model.c
index d08a2bce653c..341052387b49 100644
--- a/arch/mips/cavium-octeon/executive/octeon-model.c
+++ b/arch/mips/cavium-octeon/executive/octeon-model.c
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2010 Cavium Networks 7 * Copyright (c) 2003-2017 Cavium, Inc.
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -63,16 +63,15 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
63 char pass[4]; 63 char pass[4];
64 int clock_mhz; 64 int clock_mhz;
65 const char *suffix; 65 const char *suffix;
66 union cvmx_l2d_fus3 fus3;
67 int num_cores; 66 int num_cores;
68 union cvmx_mio_fus_dat2 fus_dat2; 67 union cvmx_mio_fus_dat2 fus_dat2;
69 union cvmx_mio_fus_dat3 fus_dat3; 68 union cvmx_mio_fus_dat3 fus_dat3;
70 char fuse_model[10]; 69 char fuse_model[10];
71 uint32_t fuse_data = 0; 70 uint32_t fuse_data = 0;
71 uint64_t l2d_fus3 = 0;
72 72
73 fus3.u64 = 0;
74 if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)) 73 if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
75 fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3); 74 l2d_fus3 = (cvmx_read_csr(CVMX_L2D_FUS3) >> 34) & 0x3;
76 fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); 75 fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
77 fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3); 76 fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
78 num_cores = cvmx_octeon_num_cores(); 77 num_cores = cvmx_octeon_num_cores();
@@ -192,7 +191,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
192 /* Now figure out the family, the first two digits */ 191 /* Now figure out the family, the first two digits */
193 switch ((chip_id >> 8) & 0xff) { 192 switch ((chip_id >> 8) & 0xff) {
194 case 0: /* CN38XX, CN37XX or CN36XX */ 193 case 0: /* CN38XX, CN37XX or CN36XX */
195 if (fus3.cn38xx.crip_512k) { 194 if (l2d_fus3) {
196 /* 195 /*
197 * For some unknown reason, the 16 core one is 196 * For some unknown reason, the 16 core one is
198 * called 37 instead of 36. 197 * called 37 instead of 36.
@@ -223,7 +222,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
223 } 222 }
224 break; 223 break;
225 case 1: /* CN31XX or CN3020 */ 224 case 1: /* CN31XX or CN3020 */
226 if ((chip_id & 0x10) || fus3.cn31xx.crip_128k) 225 if ((chip_id & 0x10) || l2d_fus3)
227 family = "30"; 226 family = "30";
228 else 227 else
229 family = "31"; 228 family = "31";
@@ -246,7 +245,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
246 case 2: /* CN3010 or CN3005 */ 245 case 2: /* CN3010 or CN3005 */
247 family = "30"; 246 family = "30";
248 /* A chip with half cache is an 05 */ 247 /* A chip with half cache is an 05 */
249 if (fus3.cn30xx.crip_64k) 248 if (l2d_fus3)
250 core_model = "05"; 249 core_model = "05";
251 /* 250 /*
252 * This series of chips didn't follow the standard 251 * This series of chips didn't follow the standard
@@ -267,7 +266,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
267 case 3: /* CN58XX */ 266 case 3: /* CN58XX */
268 family = "58"; 267 family = "58";
269 /* Special case. 4 core, half cache (CP with half cache) */ 268 /* Special case. 4 core, half cache (CP with half cache) */
270 if ((num_cores == 4) && fus3.cn58xx.crip_1024k && !strncmp(suffix, "CP", 2)) 269 if ((num_cores == 4) && l2d_fus3 && !strncmp(suffix, "CP", 2))
271 core_model = "29"; 270 core_model = "29";
272 271
273 /* Pass 1 uses different encodings for pass numbers */ 272 /* Pass 1 uses different encodings for pass numbers */
@@ -290,7 +289,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
290 break; 289 break;
291 case 4: /* CN57XX, CN56XX, CN55XX, CN54XX */ 290 case 4: /* CN57XX, CN56XX, CN55XX, CN54XX */
292 if (fus_dat2.cn56xx.raid_en) { 291 if (fus_dat2.cn56xx.raid_en) {
293 if (fus3.cn56xx.crip_1024k) 292 if (l2d_fus3)
294 family = "55"; 293 family = "55";
295 else 294 else
296 family = "57"; 295 family = "57";
@@ -309,7 +308,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
309 if (fus_dat3.cn56xx.bar2_en) 308 if (fus_dat3.cn56xx.bar2_en)
310 suffix = "NSPB2"; 309 suffix = "NSPB2";
311 } 310 }
312 if (fus3.cn56xx.crip_1024k) 311 if (l2d_fus3)
313 family = "54"; 312 family = "54";
314 else 313 else
315 family = "56"; 314 family = "56";
@@ -319,7 +318,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
319 family = "50"; 318 family = "50";
320 break; 319 break;
321 case 7: /* CN52XX */ 320 case 7: /* CN52XX */
322 if (fus3.cn52xx.crip_256k) 321 if (l2d_fus3)
323 family = "51"; 322 family = "51";
324 else 323 else
325 family = "52"; 324 family = "52";
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 3375e61daa19..8505db478904 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -3,71 +3,27 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2004-2016 Cavium Networks 6 * Copyright (C) 2004-2017 Cavium, Inc.
7 * Copyright (C) 2008 Wind River Systems 7 * Copyright (C) 2008 Wind River Systems
8 */ 8 */
9 9
10#include <linux/init.h>
11#include <linux/delay.h>
12#include <linux/etherdevice.h> 10#include <linux/etherdevice.h>
13#include <linux/of_platform.h> 11#include <linux/of_platform.h>
14#include <linux/of_fdt.h> 12#include <linux/of_fdt.h>
15#include <linux/libfdt.h> 13#include <linux/libfdt.h>
16#include <linux/usb/ehci_def.h>
17#include <linux/usb/ehci_pdriver.h>
18#include <linux/usb/ohci_pdriver.h>
19 14
20#include <asm/octeon/octeon.h> 15#include <asm/octeon/octeon.h>
21#include <asm/octeon/cvmx-helper-board.h> 16#include <asm/octeon/cvmx-helper-board.h>
17
18#ifdef CONFIG_USB
19#include <linux/usb/ehci_def.h>
20#include <linux/usb/ehci_pdriver.h>
21#include <linux/usb/ohci_pdriver.h>
22#include <asm/octeon/cvmx-uctlx-defs.h> 22#include <asm/octeon/cvmx-uctlx-defs.h>
23 23
24#define CVMX_UAHCX_EHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000010ull)) 24#define CVMX_UAHCX_EHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000010ull))
25#define CVMX_UAHCX_OHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000408ull)) 25#define CVMX_UAHCX_OHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000408ull))
26 26
27/* Octeon Random Number Generator. */
28static int __init octeon_rng_device_init(void)
29{
30 struct platform_device *pd;
31 int ret = 0;
32
33 struct resource rng_resources[] = {
34 {
35 .flags = IORESOURCE_MEM,
36 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
37 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
38 }, {
39 .flags = IORESOURCE_MEM,
40 .start = cvmx_build_io_address(8, 0),
41 .end = cvmx_build_io_address(8, 0) + 0x7
42 }
43 };
44
45 pd = platform_device_alloc("octeon_rng", -1);
46 if (!pd) {
47 ret = -ENOMEM;
48 goto out;
49 }
50
51 ret = platform_device_add_resources(pd, rng_resources,
52 ARRAY_SIZE(rng_resources));
53 if (ret)
54 goto fail;
55
56 ret = platform_device_add(pd);
57 if (ret)
58 goto fail;
59
60 return ret;
61fail:
62 platform_device_put(pd);
63
64out:
65 return ret;
66}
67device_initcall(octeon_rng_device_init);
68
69#ifdef CONFIG_USB
70
71static DEFINE_MUTEX(octeon2_usb_clocks_mutex); 27static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
72 28
73static int octeon2_usb_clock_start_cnt; 29static int octeon2_usb_clock_start_cnt;
@@ -440,8 +396,49 @@ device_initcall(octeon_ohci_device_init);
440 396
441#endif /* CONFIG_USB */ 397#endif /* CONFIG_USB */
442 398
399/* Octeon Random Number Generator. */
400static int __init octeon_rng_device_init(void)
401{
402 struct platform_device *pd;
403 int ret = 0;
443 404
444static struct of_device_id __initdata octeon_ids[] = { 405 struct resource rng_resources[] = {
406 {
407 .flags = IORESOURCE_MEM,
408 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
409 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
410 }, {
411 .flags = IORESOURCE_MEM,
412 .start = cvmx_build_io_address(8, 0),
413 .end = cvmx_build_io_address(8, 0) + 0x7
414 }
415 };
416
417 pd = platform_device_alloc("octeon_rng", -1);
418 if (!pd) {
419 ret = -ENOMEM;
420 goto out;
421 }
422
423 ret = platform_device_add_resources(pd, rng_resources,
424 ARRAY_SIZE(rng_resources));
425 if (ret)
426 goto fail;
427
428 ret = platform_device_add(pd);
429 if (ret)
430 goto fail;
431
432 return ret;
433fail:
434 platform_device_put(pd);
435
436out:
437 return ret;
438}
439device_initcall(octeon_rng_device_init);
440
441const struct of_device_id octeon_ids[] __initconst = {
445 { .compatible = "simple-bus", }, 442 { .compatible = "simple-bus", },
446 { .compatible = "cavium,octeon-6335-uctl", }, 443 { .compatible = "cavium,octeon-6335-uctl", },
447 { .compatible = "cavium,octeon-5750-usbn", }, 444 { .compatible = "cavium,octeon-5750-usbn", },
@@ -481,6 +478,7 @@ static void __init octeon_fdt_set_phy(int eth, int phy_addr)
481 alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); 478 alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
482 if (alt_phy_handle) { 479 if (alt_phy_handle) {
483 u32 alt_phandle = be32_to_cpup(alt_phy_handle); 480 u32 alt_phandle = be32_to_cpup(alt_phy_handle);
481
484 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle); 482 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
485 } else { 483 } else {
486 alt_phy = -1; 484 alt_phy = -1;
@@ -579,6 +577,7 @@ static void __init octeon_fdt_rm_ethernet(int node)
579 if (phy_handle) { 577 if (phy_handle) {
580 u32 ph = be32_to_cpup(phy_handle); 578 u32 ph = be32_to_cpup(phy_handle);
581 int p = fdt_node_offset_by_phandle(initial_boot_params, ph); 579 int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
580
582 if (p >= 0) 581 if (p >= 0)
583 fdt_nop_node(initial_boot_params, p); 582 fdt_nop_node(initial_boot_params, p);
584 } 583 }
@@ -728,6 +727,7 @@ int __init octeon_prune_device_tree(void)
728 727
729 for (i = 0; i < 2; i++) { 728 for (i = 0; i < 2; i++) {
730 int mgmt; 729 int mgmt;
730
731 snprintf(name_buffer, sizeof(name_buffer), 731 snprintf(name_buffer, sizeof(name_buffer),
732 "mix%d", i); 732 "mix%d", i);
733 alias_prop = fdt_getprop(initial_boot_params, aliases, 733 alias_prop = fdt_getprop(initial_boot_params, aliases,
@@ -743,6 +743,7 @@ int __init octeon_prune_device_tree(void)
743 name_buffer); 743 name_buffer);
744 } else { 744 } else {
745 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i); 745 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
746
746 octeon_fdt_set_phy(mgmt, phy_addr); 747 octeon_fdt_set_phy(mgmt, phy_addr);
747 } 748 }
748 } 749 }
@@ -751,6 +752,7 @@ int __init octeon_prune_device_tree(void)
751 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL); 752 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
752 if (pip_path) { 753 if (pip_path) {
753 int pip = fdt_path_offset(initial_boot_params, pip_path); 754 int pip = fdt_path_offset(initial_boot_params, pip_path);
755
754 if (pip >= 0) 756 if (pip >= 0)
755 for (i = 0; i <= 4; i++) 757 for (i = 0; i <= 4; i++)
756 octeon_fdt_pip_iface(pip, i); 758 octeon_fdt_pip_iface(pip, i);
@@ -767,6 +769,7 @@ int __init octeon_prune_device_tree(void)
767 769
768 for (i = 0; i < 2; i++) { 770 for (i = 0; i < 2; i++) {
769 int i2c; 771 int i2c;
772
770 snprintf(name_buffer, sizeof(name_buffer), 773 snprintf(name_buffer, sizeof(name_buffer),
771 "twsi%d", i); 774 "twsi%d", i);
772 alias_prop = fdt_getprop(initial_boot_params, aliases, 775 alias_prop = fdt_getprop(initial_boot_params, aliases,
@@ -797,11 +800,11 @@ int __init octeon_prune_device_tree(void)
797 800
798 for (i = 0; i < 2; i++) { 801 for (i = 0; i < 2; i++) {
799 int i2c; 802 int i2c;
803
800 snprintf(name_buffer, sizeof(name_buffer), 804 snprintf(name_buffer, sizeof(name_buffer),
801 "smi%d", i); 805 "smi%d", i);
802 alias_prop = fdt_getprop(initial_boot_params, aliases, 806 alias_prop = fdt_getprop(initial_boot_params, aliases,
803 name_buffer, NULL); 807 name_buffer, NULL);
804
805 if (alias_prop) { 808 if (alias_prop) {
806 i2c = fdt_path_offset(initial_boot_params, alias_prop); 809 i2c = fdt_path_offset(initial_boot_params, alias_prop);
807 if (i2c < 0) 810 if (i2c < 0)
@@ -824,6 +827,7 @@ int __init octeon_prune_device_tree(void)
824 827
825 for (i = 0; i < 3; i++) { 828 for (i = 0; i < 3; i++) {
826 int uart; 829 int uart;
830
827 snprintf(name_buffer, sizeof(name_buffer), 831 snprintf(name_buffer, sizeof(name_buffer),
828 "uart%d", i); 832 "uart%d", i);
829 alias_prop = fdt_getprop(initial_boot_params, aliases, 833 alias_prop = fdt_getprop(initial_boot_params, aliases,
@@ -863,6 +867,7 @@ int __init octeon_prune_device_tree(void)
863 int len; 867 int len;
864 868
865 int cf = fdt_path_offset(initial_boot_params, alias_prop); 869 int cf = fdt_path_offset(initial_boot_params, alias_prop);
870
866 base_ptr = 0; 871 base_ptr = 0;
867 if (octeon_bootinfo->major_version == 1 872 if (octeon_bootinfo->major_version == 1
868 && octeon_bootinfo->minor_version >= 1) { 873 && octeon_bootinfo->minor_version >= 1) {
@@ -912,6 +917,7 @@ int __init octeon_prune_device_tree(void)
912 fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle"); 917 fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
913 if (!is_16bit) { 918 if (!is_16bit) {
914 __be32 width = cpu_to_be32(8); 919 __be32 width = cpu_to_be32(8);
920
915 fdt_setprop_inplace(initial_boot_params, cf, 921 fdt_setprop_inplace(initial_boot_params, cf,
916 "cavium,bus-width", &width, sizeof(width)); 922 "cavium,bus-width", &width, sizeof(width));
917 } 923 }
@@ -1004,6 +1010,7 @@ end_led:
1004 ; 1010 ;
1005 } 1011 }
1006 1012
1013#ifdef CONFIG_USB
1007 /* OHCI/UHCI USB */ 1014 /* OHCI/UHCI USB */
1008 alias_prop = fdt_getprop(initial_boot_params, aliases, 1015 alias_prop = fdt_getprop(initial_boot_params, aliases,
1009 "uctl", NULL); 1016 "uctl", NULL);
@@ -1036,6 +1043,7 @@ end_led:
1036 } else { 1043 } else {
1037 __be32 new_f[1]; 1044 __be32 new_f[1];
1038 enum cvmx_helper_board_usb_clock_types c; 1045 enum cvmx_helper_board_usb_clock_types c;
1046
1039 c = __cvmx_helper_board_usb_get_clock_type(); 1047 c = __cvmx_helper_board_usb_get_clock_type();
1040 switch (c) { 1048 switch (c) {
1041 case USB_CLOCK_TYPE_REF_48: 1049 case USB_CLOCK_TYPE_REF_48:
@@ -1052,6 +1060,7 @@ end_led:
1052 } 1060 }
1053 } 1061 }
1054 } 1062 }
1063#endif
1055 1064
1056 return 0; 1065 return 0;
1057} 1066}
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index d9dbeb0b165b..a8034d0dcade 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -374,14 +374,8 @@ void octeon_write_lcd(const char *s)
374 */ 374 */
375int octeon_get_boot_uart(void) 375int octeon_get_boot_uart(void)
376{ 376{
377 int uart; 377 return (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
378#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
379 uart = 1;
380#else
381 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
382 1 : 0; 378 1 : 0;
383#endif
384 return uart;
385} 379}
386 380
387/** 381/**
@@ -901,14 +895,10 @@ void __init prom_init(void)
901 } 895 }
902 896
903 if (strstr(arcs_cmdline, "console=") == NULL) { 897 if (strstr(arcs_cmdline, "console=") == NULL) {
904#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
905 strcat(arcs_cmdline, " console=ttyS0,115200");
906#else
907 if (octeon_uart == 1) 898 if (octeon_uart == 1)
908 strcat(arcs_cmdline, " console=ttyS1,115200"); 899 strcat(arcs_cmdline, " console=ttyS1,115200");
909 else 900 else
910 strcat(arcs_cmdline, " console=ttyS0,115200"); 901 strcat(arcs_cmdline, " console=ttyS0,115200");
911#endif
912 } 902 }
913 903
914 mips_hpt_frequency = octeon_get_clock_rate(); 904 mips_hpt_frequency = octeon_get_clock_rate();
diff --git a/arch/mips/configs/generic_defconfig b/arch/mips/configs/generic_defconfig
index c95d94c7838b..91aacf2ef26d 100644
--- a/arch/mips/configs/generic_defconfig
+++ b/arch/mips/configs/generic_defconfig
@@ -36,6 +36,8 @@ CONFIG_NET=y
36CONFIG_PACKET=y 36CONFIG_PACKET=y
37CONFIG_UNIX=y 37CONFIG_UNIX=y
38CONFIG_INET=y 38CONFIG_INET=y
39CONFIG_IP_PNP=y
40CONFIG_IP_PNP_DHCP=y
39CONFIG_NETFILTER=y 41CONFIG_NETFILTER=y
40# CONFIG_WIRELESS is not set 42# CONFIG_WIRELESS is not set
41CONFIG_DEVTMPFS=y 43CONFIG_DEVTMPFS=y
@@ -80,6 +82,7 @@ CONFIG_NFS_V3_ACL=y
80CONFIG_NFS_V4=y 82CONFIG_NFS_V4=y
81CONFIG_NFS_V4_1=y 83CONFIG_NFS_V4_1=y
82CONFIG_NFS_V4_2=y 84CONFIG_NFS_V4_2=y
85CONFIG_ROOT_NFS=y
83CONFIG_PRINTK_TIME=y 86CONFIG_PRINTK_TIME=y
84CONFIG_DEBUG_INFO=y 87CONFIG_DEBUG_INFO=y
85CONFIG_DEBUG_INFO_REDUCED=y 88CONFIG_DEBUG_INFO_REDUCED=y
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index b4db69fbc40c..fc67947ed658 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -9,14 +9,9 @@
9#ifndef _ASM_CACHE_H 9#ifndef _ASM_CACHE_H
10#define _ASM_CACHE_H 10#define _ASM_CACHE_H
11 11
12#include <kmalloc.h>
13
14#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT 12#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
15#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 13#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
16 14
17#define SMP_CACHE_SHIFT L1_CACHE_SHIFT
18#define SMP_CACHE_BYTES L1_CACHE_BYTES
19
20#define __read_mostly __attribute__((__section__(".data..read_mostly"))) 15#define __read_mostly __attribute__((__section__(".data..read_mostly")))
21 16
22#endif /* _ASM_CACHE_H */ 17#endif /* _ASM_CACHE_H */
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index be3b4c25f335..cd6efb07c980 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -12,10 +12,9 @@
12#ifndef __ASM_CPU_INFO_H 12#ifndef __ASM_CPU_INFO_H
13#define __ASM_CPU_INFO_H 13#define __ASM_CPU_INFO_H
14 14
15#include <linux/cache.h>
15#include <linux/types.h> 16#include <linux/types.h>
16 17
17#include <asm/cache.h>
18
19/* 18/*
20 * Descriptor for a cache 19 * Descriptor for a cache
21 */ 20 */
diff --git a/arch/mips/include/asm/cpufeature.h b/arch/mips/include/asm/cpufeature.h
new file mode 100644
index 000000000000..c63ec05313c1
--- /dev/null
+++ b/arch/mips/include/asm/cpufeature.h
@@ -0,0 +1,26 @@
1/*
2 * CPU feature definitions for module loading, used by
3 * module_cpu_feature_match(), see uapi/asm/hwcap.h for MIPS CPU features.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#ifndef __ASM_CPUFEATURE_H
12#define __ASM_CPUFEATURE_H
13
14#include <uapi/asm/hwcap.h>
15#include <asm/elf.h>
16
17#define MAX_CPU_FEATURES (8 * sizeof(elf_hwcap))
18
19#define cpu_feature(x) ilog2(HWCAP_ ## x)
20
21static inline bool cpu_have_feature(unsigned int num)
22{
23 return elf_hwcap & (1UL << num);
24}
25
26#endif /* __ASM_CPUFEATURE_H */
diff --git a/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
index 98cf40417c5d..d38be668e338 100644
--- a/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
@@ -10,8 +10,6 @@
10#ifndef __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H 10#ifndef __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H
11#define __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H 11#define __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H
12 12
13#include <cpu-feature-overrides.h>
14
15#define cpu_has_tlb 1 13#define cpu_has_tlb 1
16#define cpu_has_4kex 1 14#define cpu_has_4kex 1
17#define cpu_has_4k_cache 1 15#define cpu_has_4k_cache 1
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
index 10262cb6ff50..d045973ddb33 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2012 Cavium Networks 7 * Copyright (c) 2003-2017 Cavium, Inc.
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,3140 +28,177 @@
28#ifndef __CVMX_L2C_DEFS_H__ 28#ifndef __CVMX_L2C_DEFS_H__
29#define __CVMX_L2C_DEFS_H__ 29#define __CVMX_L2C_DEFS_H__
30 30
31#define CVMX_L2C_BIG_CTL (CVMX_ADD_IO_SEG(0x0001180080800030ull)) 31#include <uapi/asm/bitfield.h>
32#define CVMX_L2C_BST (CVMX_ADD_IO_SEG(0x00011800808007F8ull)) 32
33#define CVMX_L2C_BST0 (CVMX_ADD_IO_SEG(0x00011800800007F8ull)) 33#define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull))
34#define CVMX_L2C_BST1 (CVMX_ADD_IO_SEG(0x00011800800007F0ull))
35#define CVMX_L2C_BST2 (CVMX_ADD_IO_SEG(0x00011800800007E8ull))
36#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull) + ((block_id) & 3) * 0x40000ull)
37#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull) + ((block_id) & 3) * 0x40000ull)
38#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull) + ((block_id) & 3) * 0x40000ull)
39#define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull)) 34#define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull))
40#define CVMX_L2C_COP0_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8)
41#define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull)) 35#define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull))
42#define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull))
43#define CVMX_L2C_DUT (CVMX_ADD_IO_SEG(0x0001180080000050ull))
44#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 8191) * 8)
45#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull)
46#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull)
47#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull) + ((block_id) & 3) * 0x40000ull)
48#define CVMX_L2C_ERR_XMC (CVMX_ADD_IO_SEG(0x00011800808007D8ull))
49#define CVMX_L2C_GRPWRR0 (CVMX_ADD_IO_SEG(0x00011800800000C8ull))
50#define CVMX_L2C_GRPWRR1 (CVMX_ADD_IO_SEG(0x00011800800000D0ull))
51#define CVMX_L2C_INT_EN (CVMX_ADD_IO_SEG(0x0001180080000100ull))
52#define CVMX_L2C_INT_ENA (CVMX_ADD_IO_SEG(0x0001180080800020ull))
53#define CVMX_L2C_INT_REG (CVMX_ADD_IO_SEG(0x0001180080800018ull))
54#define CVMX_L2C_INT_STAT (CVMX_ADD_IO_SEG(0x00011800800000F8ull))
55#define CVMX_L2C_IOCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800420ull))
56#define CVMX_L2C_IORX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800428ull))
57#define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull)) 36#define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull))
58#define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull)) 37#define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull))
59#define CVMX_L2C_LFB0 (CVMX_ADD_IO_SEG(0x0001180080000038ull)) 38#define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull))
60#define CVMX_L2C_LFB1 (CVMX_ADD_IO_SEG(0x0001180080000040ull)) 39#define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + \
61#define CVMX_L2C_LFB2 (CVMX_ADD_IO_SEG(0x0001180080000048ull)) 40 ((offset) & 3) * 8)
62#define CVMX_L2C_LFB3 (CVMX_ADD_IO_SEG(0x00011800800000B8ull))
63#define CVMX_L2C_OOB (CVMX_ADD_IO_SEG(0x00011800800000D8ull))
64#define CVMX_L2C_OOB1 (CVMX_ADD_IO_SEG(0x00011800800000E0ull))
65#define CVMX_L2C_OOB2 (CVMX_ADD_IO_SEG(0x00011800800000E8ull))
66#define CVMX_L2C_OOB3 (CVMX_ADD_IO_SEG(0x00011800800000F0ull))
67#define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0) 41#define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0)
68#define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1) 42#define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1)
69#define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2) 43#define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2)
70#define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3) 44#define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3)
71#define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull))
72#define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + ((offset) & 3) * 8)
73#define CVMX_L2C_PPGRP (CVMX_ADD_IO_SEG(0x00011800800000C0ull))
74#define CVMX_L2C_QOS_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080880200ull) + ((offset) & 1) * 8)
75#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 31) * 8)
76#define CVMX_L2C_QOS_WGT (CVMX_ADD_IO_SEG(0x0001180080800008ull))
77#define CVMX_L2C_RSCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800410ull) + ((offset) & 3) * 64)
78#define CVMX_L2C_RSDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800418ull) + ((offset) & 3) * 64)
79#define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull)) 45#define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull))
80#define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull)) 46#define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull))
81#define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull)) 47#define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull))
82#define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull)) 48#define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull))
83#define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull)) 49#define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull))
84#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull) + ((block_id) & 3) * 0x40000ull) 50#define CVMX_L2C_TADX_PFCX(offset, block_id) \
85#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull) + ((block_id) & 3) * 0x40000ull) 51 (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + (((offset) & 3) + \
86#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull) + ((block_id) & 3) * 0x40000ull) 52 ((block_id) & 7) * 0x8000ull) * 8)
87#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull) + ((block_id) & 3) * 0x40000ull) 53#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + \
88#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + ((block_id) & 3) * 0x40000ull) 54 ((block_id) & 3) * 0x40000ull)
89#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull) + ((block_id) & 3) * 0x40000ull) 55#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull) + \
90#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull) + ((block_id) & 3) * 0x40000ull) 56 ((block_id) & 3) * 0x40000ull)
91#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull) + ((block_id) & 3) * 0x40000ull) 57#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull) + \
92#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull) + ((block_id) & 3) * 0x40000ull) 58 ((block_id) & 3) * 0x40000ull)
93#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull) + ((block_id) & 3) * 0x40000ull) 59#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull) + \
94#define CVMX_L2C_VER_ID (CVMX_ADD_IO_SEG(0x00011800808007E0ull)) 60 ((block_id) & 3) * 0x40000ull)
95#define CVMX_L2C_VER_IOB (CVMX_ADD_IO_SEG(0x00011800808007F0ull)) 61#define CVMX_L2C_TADX_PRF(offset) (CVMX_ADD_IO_SEG(0x0001180080A00008ull) + \
96#define CVMX_L2C_VER_MSC (CVMX_ADD_IO_SEG(0x00011800808007D0ull)) 62 ((offset) & 7) * 0x40000ull)
97#define CVMX_L2C_VER_PP (CVMX_ADD_IO_SEG(0x00011800808007E8ull)) 63#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull) + \
98#define CVMX_L2C_VIRTID_IOBX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0200ull) + ((offset) & 1) * 8) 64 ((block_id) & 3) * 0x40000ull)
99#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 31) * 8) 65#define CVMX_L2C_WPAR_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080840200ull) + \
100#define CVMX_L2C_VRT_CTL (CVMX_ADD_IO_SEG(0x0001180080800010ull)) 66 ((offset) & 1) * 8)
101#define CVMX_L2C_VRT_MEMX(offset) (CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8) 67#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + \
102#define CVMX_L2C_WPAR_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080840200ull) + ((offset) & 1) * 8) 68 ((offset) & 31) * 8)
103#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 31) * 8) 69#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
104#define CVMX_L2C_XMCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800400ull) + ((offset) & 3) * 64)
105#define CVMX_L2C_XMC_CMD (CVMX_ADD_IO_SEG(0x0001180080800028ull))
106#define CVMX_L2C_XMDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800408ull) + ((offset) & 3) * 64)
107
108union cvmx_l2c_big_ctl {
109 uint64_t u64;
110 struct cvmx_l2c_big_ctl_s {
111#ifdef __BIG_ENDIAN_BITFIELD
112 uint64_t reserved_8_63:56;
113 uint64_t maxdram:4;
114 uint64_t reserved_1_3:3;
115 uint64_t disable:1;
116#else
117 uint64_t disable:1;
118 uint64_t reserved_1_3:3;
119 uint64_t maxdram:4;
120 uint64_t reserved_8_63:56;
121#endif
122 } s;
123 struct cvmx_l2c_big_ctl_s cn61xx;
124 struct cvmx_l2c_big_ctl_s cn63xx;
125 struct cvmx_l2c_big_ctl_s cn66xx;
126 struct cvmx_l2c_big_ctl_s cn68xx;
127 struct cvmx_l2c_big_ctl_s cn68xxp1;
128 struct cvmx_l2c_big_ctl_s cnf71xx;
129};
130
131union cvmx_l2c_bst {
132 uint64_t u64;
133 struct cvmx_l2c_bst_s {
134#ifdef __BIG_ENDIAN_BITFIELD
135 uint64_t dutfl:32;
136 uint64_t rbffl:4;
137 uint64_t xbffl:4;
138 uint64_t tdpfl:4;
139 uint64_t ioccmdfl:4;
140 uint64_t iocdatfl:4;
141 uint64_t dutresfl:4;
142 uint64_t vrtfl:4;
143 uint64_t tdffl:4;
144#else
145 uint64_t tdffl:4;
146 uint64_t vrtfl:4;
147 uint64_t dutresfl:4;
148 uint64_t iocdatfl:4;
149 uint64_t ioccmdfl:4;
150 uint64_t tdpfl:4;
151 uint64_t xbffl:4;
152 uint64_t rbffl:4;
153 uint64_t dutfl:32;
154#endif
155 } s;
156 struct cvmx_l2c_bst_cn61xx {
157#ifdef __BIG_ENDIAN_BITFIELD
158 uint64_t reserved_36_63:28;
159 uint64_t dutfl:4;
160 uint64_t reserved_17_31:15;
161 uint64_t ioccmdfl:1;
162 uint64_t reserved_13_15:3;
163 uint64_t iocdatfl:1;
164 uint64_t reserved_9_11:3;
165 uint64_t dutresfl:1;
166 uint64_t reserved_5_7:3;
167 uint64_t vrtfl:1;
168 uint64_t reserved_1_3:3;
169 uint64_t tdffl:1;
170#else
171 uint64_t tdffl:1;
172 uint64_t reserved_1_3:3;
173 uint64_t vrtfl:1;
174 uint64_t reserved_5_7:3;
175 uint64_t dutresfl:1;
176 uint64_t reserved_9_11:3;
177 uint64_t iocdatfl:1;
178 uint64_t reserved_13_15:3;
179 uint64_t ioccmdfl:1;
180 uint64_t reserved_17_31:15;
181 uint64_t dutfl:4;
182 uint64_t reserved_36_63:28;
183#endif
184 } cn61xx;
185 struct cvmx_l2c_bst_cn63xx {
186#ifdef __BIG_ENDIAN_BITFIELD
187 uint64_t reserved_38_63:26;
188 uint64_t dutfl:6;
189 uint64_t reserved_17_31:15;
190 uint64_t ioccmdfl:1;
191 uint64_t reserved_13_15:3;
192 uint64_t iocdatfl:1;
193 uint64_t reserved_9_11:3;
194 uint64_t dutresfl:1;
195 uint64_t reserved_5_7:3;
196 uint64_t vrtfl:1;
197 uint64_t reserved_1_3:3;
198 uint64_t tdffl:1;
199#else
200 uint64_t tdffl:1;
201 uint64_t reserved_1_3:3;
202 uint64_t vrtfl:1;
203 uint64_t reserved_5_7:3;
204 uint64_t dutresfl:1;
205 uint64_t reserved_9_11:3;
206 uint64_t iocdatfl:1;
207 uint64_t reserved_13_15:3;
208 uint64_t ioccmdfl:1;
209 uint64_t reserved_17_31:15;
210 uint64_t dutfl:6;
211 uint64_t reserved_38_63:26;
212#endif
213 } cn63xx;
214 struct cvmx_l2c_bst_cn63xx cn63xxp1;
215 struct cvmx_l2c_bst_cn66xx {
216#ifdef __BIG_ENDIAN_BITFIELD
217 uint64_t reserved_42_63:22;
218 uint64_t dutfl:10;
219 uint64_t reserved_17_31:15;
220 uint64_t ioccmdfl:1;
221 uint64_t reserved_13_15:3;
222 uint64_t iocdatfl:1;
223 uint64_t reserved_9_11:3;
224 uint64_t dutresfl:1;
225 uint64_t reserved_5_7:3;
226 uint64_t vrtfl:1;
227 uint64_t reserved_1_3:3;
228 uint64_t tdffl:1;
229#else
230 uint64_t tdffl:1;
231 uint64_t reserved_1_3:3;
232 uint64_t vrtfl:1;
233 uint64_t reserved_5_7:3;
234 uint64_t dutresfl:1;
235 uint64_t reserved_9_11:3;
236 uint64_t iocdatfl:1;
237 uint64_t reserved_13_15:3;
238 uint64_t ioccmdfl:1;
239 uint64_t reserved_17_31:15;
240 uint64_t dutfl:10;
241 uint64_t reserved_42_63:22;
242#endif
243 } cn66xx;
244 struct cvmx_l2c_bst_s cn68xx;
245 struct cvmx_l2c_bst_s cn68xxp1;
246 struct cvmx_l2c_bst_cn61xx cnf71xx;
247};
248
249union cvmx_l2c_bst0 {
250 uint64_t u64;
251 struct cvmx_l2c_bst0_s {
252#ifdef __BIG_ENDIAN_BITFIELD
253 uint64_t reserved_24_63:40;
254 uint64_t dtbnk:1;
255 uint64_t wlb_msk:4;
256 uint64_t dtcnt:13;
257 uint64_t dt:1;
258 uint64_t stin_msk:1;
259 uint64_t wlb_dat:4;
260#else
261 uint64_t wlb_dat:4;
262 uint64_t stin_msk:1;
263 uint64_t dt:1;
264 uint64_t dtcnt:13;
265 uint64_t wlb_msk:4;
266 uint64_t dtbnk:1;
267 uint64_t reserved_24_63:40;
268#endif
269 } s;
270 struct cvmx_l2c_bst0_cn30xx {
271#ifdef __BIG_ENDIAN_BITFIELD
272 uint64_t reserved_23_63:41;
273 uint64_t wlb_msk:4;
274 uint64_t reserved_15_18:4;
275 uint64_t dtcnt:9;
276 uint64_t dt:1;
277 uint64_t reserved_4_4:1;
278 uint64_t wlb_dat:4;
279#else
280 uint64_t wlb_dat:4;
281 uint64_t reserved_4_4:1;
282 uint64_t dt:1;
283 uint64_t dtcnt:9;
284 uint64_t reserved_15_18:4;
285 uint64_t wlb_msk:4;
286 uint64_t reserved_23_63:41;
287#endif
288 } cn30xx;
289 struct cvmx_l2c_bst0_cn31xx {
290#ifdef __BIG_ENDIAN_BITFIELD
291 uint64_t reserved_23_63:41;
292 uint64_t wlb_msk:4;
293 uint64_t reserved_16_18:3;
294 uint64_t dtcnt:10;
295 uint64_t dt:1;
296 uint64_t stin_msk:1;
297 uint64_t wlb_dat:4;
298#else
299 uint64_t wlb_dat:4;
300 uint64_t stin_msk:1;
301 uint64_t dt:1;
302 uint64_t dtcnt:10;
303 uint64_t reserved_16_18:3;
304 uint64_t wlb_msk:4;
305 uint64_t reserved_23_63:41;
306#endif
307 } cn31xx;
308 struct cvmx_l2c_bst0_cn38xx {
309#ifdef __BIG_ENDIAN_BITFIELD
310 uint64_t reserved_19_63:45;
311 uint64_t dtcnt:13;
312 uint64_t dt:1;
313 uint64_t stin_msk:1;
314 uint64_t wlb_dat:4;
315#else
316 uint64_t wlb_dat:4;
317 uint64_t stin_msk:1;
318 uint64_t dt:1;
319 uint64_t dtcnt:13;
320 uint64_t reserved_19_63:45;
321#endif
322 } cn38xx;
323 struct cvmx_l2c_bst0_cn38xx cn38xxp2;
324 struct cvmx_l2c_bst0_cn50xx {
325#ifdef __BIG_ENDIAN_BITFIELD
326 uint64_t reserved_24_63:40;
327 uint64_t dtbnk:1;
328 uint64_t wlb_msk:4;
329 uint64_t reserved_16_18:3;
330 uint64_t dtcnt:10;
331 uint64_t dt:1;
332 uint64_t stin_msk:1;
333 uint64_t wlb_dat:4;
334#else
335 uint64_t wlb_dat:4;
336 uint64_t stin_msk:1;
337 uint64_t dt:1;
338 uint64_t dtcnt:10;
339 uint64_t reserved_16_18:3;
340 uint64_t wlb_msk:4;
341 uint64_t dtbnk:1;
342 uint64_t reserved_24_63:40;
343#endif
344 } cn50xx;
345 struct cvmx_l2c_bst0_cn50xx cn52xx;
346 struct cvmx_l2c_bst0_cn50xx cn52xxp1;
347 struct cvmx_l2c_bst0_s cn56xx;
348 struct cvmx_l2c_bst0_s cn56xxp1;
349 struct cvmx_l2c_bst0_s cn58xx;
350 struct cvmx_l2c_bst0_s cn58xxp1;
351};
352
353union cvmx_l2c_bst1 {
354 uint64_t u64;
355 struct cvmx_l2c_bst1_s {
356#ifdef __BIG_ENDIAN_BITFIELD
357 uint64_t reserved_9_63:55;
358 uint64_t l2t:9;
359#else
360 uint64_t l2t:9;
361 uint64_t reserved_9_63:55;
362#endif
363 } s;
364 struct cvmx_l2c_bst1_cn30xx {
365#ifdef __BIG_ENDIAN_BITFIELD
366 uint64_t reserved_16_63:48;
367 uint64_t vwdf:4;
368 uint64_t lrf:2;
369 uint64_t vab_vwcf:1;
370 uint64_t reserved_5_8:4;
371 uint64_t l2t:5;
372#else
373 uint64_t l2t:5;
374 uint64_t reserved_5_8:4;
375 uint64_t vab_vwcf:1;
376 uint64_t lrf:2;
377 uint64_t vwdf:4;
378 uint64_t reserved_16_63:48;
379#endif
380 } cn30xx;
381 struct cvmx_l2c_bst1_cn30xx cn31xx;
382 struct cvmx_l2c_bst1_cn38xx {
383#ifdef __BIG_ENDIAN_BITFIELD
384 uint64_t reserved_16_63:48;
385 uint64_t vwdf:4;
386 uint64_t lrf:2;
387 uint64_t vab_vwcf:1;
388 uint64_t l2t:9;
389#else
390 uint64_t l2t:9;
391 uint64_t vab_vwcf:1;
392 uint64_t lrf:2;
393 uint64_t vwdf:4;
394 uint64_t reserved_16_63:48;
395#endif
396 } cn38xx;
397 struct cvmx_l2c_bst1_cn38xx cn38xxp2;
398 struct cvmx_l2c_bst1_cn38xx cn50xx;
399 struct cvmx_l2c_bst1_cn52xx {
400#ifdef __BIG_ENDIAN_BITFIELD
401 uint64_t reserved_19_63:45;
402 uint64_t plc2:1;
403 uint64_t plc1:1;
404 uint64_t plc0:1;
405 uint64_t vwdf:4;
406 uint64_t reserved_11_11:1;
407 uint64_t ilc:1;
408 uint64_t vab_vwcf:1;
409 uint64_t l2t:9;
410#else
411 uint64_t l2t:9;
412 uint64_t vab_vwcf:1;
413 uint64_t ilc:1;
414 uint64_t reserved_11_11:1;
415 uint64_t vwdf:4;
416 uint64_t plc0:1;
417 uint64_t plc1:1;
418 uint64_t plc2:1;
419 uint64_t reserved_19_63:45;
420#endif
421 } cn52xx;
422 struct cvmx_l2c_bst1_cn52xx cn52xxp1;
423 struct cvmx_l2c_bst1_cn56xx {
424#ifdef __BIG_ENDIAN_BITFIELD
425 uint64_t reserved_24_63:40;
426 uint64_t plc2:1;
427 uint64_t plc1:1;
428 uint64_t plc0:1;
429 uint64_t ilc:1;
430 uint64_t vwdf1:4;
431 uint64_t vwdf0:4;
432 uint64_t vab_vwcf1:1;
433 uint64_t reserved_10_10:1;
434 uint64_t vab_vwcf0:1;
435 uint64_t l2t:9;
436#else
437 uint64_t l2t:9;
438 uint64_t vab_vwcf0:1;
439 uint64_t reserved_10_10:1;
440 uint64_t vab_vwcf1:1;
441 uint64_t vwdf0:4;
442 uint64_t vwdf1:4;
443 uint64_t ilc:1;
444 uint64_t plc0:1;
445 uint64_t plc1:1;
446 uint64_t plc2:1;
447 uint64_t reserved_24_63:40;
448#endif
449 } cn56xx;
450 struct cvmx_l2c_bst1_cn56xx cn56xxp1;
451 struct cvmx_l2c_bst1_cn38xx cn58xx;
452 struct cvmx_l2c_bst1_cn38xx cn58xxp1;
453};
454
455union cvmx_l2c_bst2 {
456 uint64_t u64;
457 struct cvmx_l2c_bst2_s {
458#ifdef __BIG_ENDIAN_BITFIELD
459 uint64_t reserved_16_63:48;
460 uint64_t mrb:4;
461 uint64_t reserved_4_11:8;
462 uint64_t ipcbst:1;
463 uint64_t picbst:1;
464 uint64_t xrdmsk:1;
465 uint64_t xrddat:1;
466#else
467 uint64_t xrddat:1;
468 uint64_t xrdmsk:1;
469 uint64_t picbst:1;
470 uint64_t ipcbst:1;
471 uint64_t reserved_4_11:8;
472 uint64_t mrb:4;
473 uint64_t reserved_16_63:48;
474#endif
475 } s;
476 struct cvmx_l2c_bst2_cn30xx {
477#ifdef __BIG_ENDIAN_BITFIELD
478 uint64_t reserved_16_63:48;
479 uint64_t mrb:4;
480 uint64_t rmdf:4;
481 uint64_t reserved_4_7:4;
482 uint64_t ipcbst:1;
483 uint64_t reserved_2_2:1;
484 uint64_t xrdmsk:1;
485 uint64_t xrddat:1;
486#else
487 uint64_t xrddat:1;
488 uint64_t xrdmsk:1;
489 uint64_t reserved_2_2:1;
490 uint64_t ipcbst:1;
491 uint64_t reserved_4_7:4;
492 uint64_t rmdf:4;
493 uint64_t mrb:4;
494 uint64_t reserved_16_63:48;
495#endif
496 } cn30xx;
497 struct cvmx_l2c_bst2_cn30xx cn31xx;
498 struct cvmx_l2c_bst2_cn38xx {
499#ifdef __BIG_ENDIAN_BITFIELD
500 uint64_t reserved_16_63:48;
501 uint64_t mrb:4;
502 uint64_t rmdf:4;
503 uint64_t rhdf:4;
504 uint64_t ipcbst:1;
505 uint64_t picbst:1;
506 uint64_t xrdmsk:1;
507 uint64_t xrddat:1;
508#else
509 uint64_t xrddat:1;
510 uint64_t xrdmsk:1;
511 uint64_t picbst:1;
512 uint64_t ipcbst:1;
513 uint64_t rhdf:4;
514 uint64_t rmdf:4;
515 uint64_t mrb:4;
516 uint64_t reserved_16_63:48;
517#endif
518 } cn38xx;
519 struct cvmx_l2c_bst2_cn38xx cn38xxp2;
520 struct cvmx_l2c_bst2_cn30xx cn50xx;
521 struct cvmx_l2c_bst2_cn30xx cn52xx;
522 struct cvmx_l2c_bst2_cn30xx cn52xxp1;
523 struct cvmx_l2c_bst2_cn56xx {
524#ifdef __BIG_ENDIAN_BITFIELD
525 uint64_t reserved_16_63:48;
526 uint64_t mrb:4;
527 uint64_t rmdb:4;
528 uint64_t rhdb:4;
529 uint64_t ipcbst:1;
530 uint64_t picbst:1;
531 uint64_t xrdmsk:1;
532 uint64_t xrddat:1;
533#else
534 uint64_t xrddat:1;
535 uint64_t xrdmsk:1;
536 uint64_t picbst:1;
537 uint64_t ipcbst:1;
538 uint64_t rhdb:4;
539 uint64_t rmdb:4;
540 uint64_t mrb:4;
541 uint64_t reserved_16_63:48;
542#endif
543 } cn56xx;
544 struct cvmx_l2c_bst2_cn56xx cn56xxp1;
545 struct cvmx_l2c_bst2_cn56xx cn58xx;
546 struct cvmx_l2c_bst2_cn56xx cn58xxp1;
547};
548
549union cvmx_l2c_bst_memx {
550 uint64_t u64;
551 struct cvmx_l2c_bst_memx_s {
552#ifdef __BIG_ENDIAN_BITFIELD
553 uint64_t start_bist:1;
554 uint64_t clear_bist:1;
555 uint64_t reserved_5_61:57;
556 uint64_t rdffl:1;
557 uint64_t vbffl:4;
558#else
559 uint64_t vbffl:4;
560 uint64_t rdffl:1;
561 uint64_t reserved_5_61:57;
562 uint64_t clear_bist:1;
563 uint64_t start_bist:1;
564#endif
565 } s;
566 struct cvmx_l2c_bst_memx_s cn61xx;
567 struct cvmx_l2c_bst_memx_s cn63xx;
568 struct cvmx_l2c_bst_memx_s cn63xxp1;
569 struct cvmx_l2c_bst_memx_s cn66xx;
570 struct cvmx_l2c_bst_memx_s cn68xx;
571 struct cvmx_l2c_bst_memx_s cn68xxp1;
572 struct cvmx_l2c_bst_memx_s cnf71xx;
573};
574
575union cvmx_l2c_bst_tdtx {
576 uint64_t u64;
577 struct cvmx_l2c_bst_tdtx_s {
578#ifdef __BIG_ENDIAN_BITFIELD
579 uint64_t reserved_32_63:32;
580 uint64_t fbfrspfl:8;
581 uint64_t sbffl:8;
582 uint64_t fbffl:8;
583 uint64_t l2dfl:8;
584#else
585 uint64_t l2dfl:8;
586 uint64_t fbffl:8;
587 uint64_t sbffl:8;
588 uint64_t fbfrspfl:8;
589 uint64_t reserved_32_63:32;
590#endif
591 } s;
592 struct cvmx_l2c_bst_tdtx_s cn61xx;
593 struct cvmx_l2c_bst_tdtx_s cn63xx;
594 struct cvmx_l2c_bst_tdtx_cn63xxp1 {
595#ifdef __BIG_ENDIAN_BITFIELD
596 uint64_t reserved_24_63:40;
597 uint64_t sbffl:8;
598 uint64_t fbffl:8;
599 uint64_t l2dfl:8;
600#else
601 uint64_t l2dfl:8;
602 uint64_t fbffl:8;
603 uint64_t sbffl:8;
604 uint64_t reserved_24_63:40;
605#endif
606 } cn63xxp1;
607 struct cvmx_l2c_bst_tdtx_s cn66xx;
608 struct cvmx_l2c_bst_tdtx_s cn68xx;
609 struct cvmx_l2c_bst_tdtx_s cn68xxp1;
610 struct cvmx_l2c_bst_tdtx_s cnf71xx;
611};
612 70
613union cvmx_l2c_bst_ttgx {
614 uint64_t u64;
615 struct cvmx_l2c_bst_ttgx_s {
616#ifdef __BIG_ENDIAN_BITFIELD
617 uint64_t reserved_17_63:47;
618 uint64_t lrufl:1;
619 uint64_t tagfl:16;
620#else
621 uint64_t tagfl:16;
622 uint64_t lrufl:1;
623 uint64_t reserved_17_63:47;
624#endif
625 } s;
626 struct cvmx_l2c_bst_ttgx_s cn61xx;
627 struct cvmx_l2c_bst_ttgx_s cn63xx;
628 struct cvmx_l2c_bst_ttgx_s cn63xxp1;
629 struct cvmx_l2c_bst_ttgx_s cn66xx;
630 struct cvmx_l2c_bst_ttgx_s cn68xx;
631 struct cvmx_l2c_bst_ttgx_s cn68xxp1;
632 struct cvmx_l2c_bst_ttgx_s cnf71xx;
633};
634 71
635union cvmx_l2c_cfg { 72union cvmx_l2c_cfg {
636 uint64_t u64; 73 uint64_t u64;
637 struct cvmx_l2c_cfg_s { 74 struct cvmx_l2c_cfg_s {
638#ifdef __BIG_ENDIAN_BITFIELD 75 __BITFIELD_FIELD(uint64_t reserved_20_63:44,
639 uint64_t reserved_20_63:44; 76 __BITFIELD_FIELD(uint64_t bstrun:1,
640 uint64_t bstrun:1; 77 __BITFIELD_FIELD(uint64_t lbist:1,
641 uint64_t lbist:1; 78 __BITFIELD_FIELD(uint64_t xor_bank:1,
642 uint64_t xor_bank:1; 79 __BITFIELD_FIELD(uint64_t dpres1:1,
643 uint64_t dpres1:1; 80 __BITFIELD_FIELD(uint64_t dpres0:1,
644 uint64_t dpres0:1; 81 __BITFIELD_FIELD(uint64_t dfill_dis:1,
645 uint64_t dfill_dis:1; 82 __BITFIELD_FIELD(uint64_t fpexp:4,
646 uint64_t fpexp:4; 83 __BITFIELD_FIELD(uint64_t fpempty:1,
647 uint64_t fpempty:1; 84 __BITFIELD_FIELD(uint64_t fpen:1,
648 uint64_t fpen:1; 85 __BITFIELD_FIELD(uint64_t idxalias:1,
649 uint64_t idxalias:1; 86 __BITFIELD_FIELD(uint64_t mwf_crd:4,
650 uint64_t mwf_crd:4; 87 __BITFIELD_FIELD(uint64_t rsp_arb_mode:1,
651 uint64_t rsp_arb_mode:1; 88 __BITFIELD_FIELD(uint64_t rfb_arb_mode:1,
652 uint64_t rfb_arb_mode:1; 89 __BITFIELD_FIELD(uint64_t lrf_arb_mode:1,
653 uint64_t lrf_arb_mode:1; 90 ;)))))))))))))))
654#else
655 uint64_t lrf_arb_mode:1;
656 uint64_t rfb_arb_mode:1;
657 uint64_t rsp_arb_mode:1;
658 uint64_t mwf_crd:4;
659 uint64_t idxalias:1;
660 uint64_t fpen:1;
661 uint64_t fpempty:1;
662 uint64_t fpexp:4;
663 uint64_t dfill_dis:1;
664 uint64_t dpres0:1;
665 uint64_t dpres1:1;
666 uint64_t xor_bank:1;
667 uint64_t lbist:1;
668 uint64_t bstrun:1;
669 uint64_t reserved_20_63:44;
670#endif
671 } s; 91 } s;
672 struct cvmx_l2c_cfg_cn30xx {
673#ifdef __BIG_ENDIAN_BITFIELD
674 uint64_t reserved_14_63:50;
675 uint64_t fpexp:4;
676 uint64_t fpempty:1;
677 uint64_t fpen:1;
678 uint64_t idxalias:1;
679 uint64_t mwf_crd:4;
680 uint64_t rsp_arb_mode:1;
681 uint64_t rfb_arb_mode:1;
682 uint64_t lrf_arb_mode:1;
683#else
684 uint64_t lrf_arb_mode:1;
685 uint64_t rfb_arb_mode:1;
686 uint64_t rsp_arb_mode:1;
687 uint64_t mwf_crd:4;
688 uint64_t idxalias:1;
689 uint64_t fpen:1;
690 uint64_t fpempty:1;
691 uint64_t fpexp:4;
692 uint64_t reserved_14_63:50;
693#endif
694 } cn30xx;
695 struct cvmx_l2c_cfg_cn30xx cn31xx;
696 struct cvmx_l2c_cfg_cn30xx cn38xx;
697 struct cvmx_l2c_cfg_cn30xx cn38xxp2;
698 struct cvmx_l2c_cfg_cn50xx {
699#ifdef __BIG_ENDIAN_BITFIELD
700 uint64_t reserved_20_63:44;
701 uint64_t bstrun:1;
702 uint64_t lbist:1;
703 uint64_t reserved_14_17:4;
704 uint64_t fpexp:4;
705 uint64_t fpempty:1;
706 uint64_t fpen:1;
707 uint64_t idxalias:1;
708 uint64_t mwf_crd:4;
709 uint64_t rsp_arb_mode:1;
710 uint64_t rfb_arb_mode:1;
711 uint64_t lrf_arb_mode:1;
712#else
713 uint64_t lrf_arb_mode:1;
714 uint64_t rfb_arb_mode:1;
715 uint64_t rsp_arb_mode:1;
716 uint64_t mwf_crd:4;
717 uint64_t idxalias:1;
718 uint64_t fpen:1;
719 uint64_t fpempty:1;
720 uint64_t fpexp:4;
721 uint64_t reserved_14_17:4;
722 uint64_t lbist:1;
723 uint64_t bstrun:1;
724 uint64_t reserved_20_63:44;
725#endif
726 } cn50xx;
727 struct cvmx_l2c_cfg_cn50xx cn52xx;
728 struct cvmx_l2c_cfg_cn50xx cn52xxp1;
729 struct cvmx_l2c_cfg_s cn56xx;
730 struct cvmx_l2c_cfg_s cn56xxp1;
731 struct cvmx_l2c_cfg_cn58xx {
732#ifdef __BIG_ENDIAN_BITFIELD
733 uint64_t reserved_20_63:44;
734 uint64_t bstrun:1;
735 uint64_t lbist:1;
736 uint64_t reserved_15_17:3;
737 uint64_t dfill_dis:1;
738 uint64_t fpexp:4;
739 uint64_t fpempty:1;
740 uint64_t fpen:1;
741 uint64_t idxalias:1;
742 uint64_t mwf_crd:4;
743 uint64_t rsp_arb_mode:1;
744 uint64_t rfb_arb_mode:1;
745 uint64_t lrf_arb_mode:1;
746#else
747 uint64_t lrf_arb_mode:1;
748 uint64_t rfb_arb_mode:1;
749 uint64_t rsp_arb_mode:1;
750 uint64_t mwf_crd:4;
751 uint64_t idxalias:1;
752 uint64_t fpen:1;
753 uint64_t fpempty:1;
754 uint64_t fpexp:4;
755 uint64_t dfill_dis:1;
756 uint64_t reserved_15_17:3;
757 uint64_t lbist:1;
758 uint64_t bstrun:1;
759 uint64_t reserved_20_63:44;
760#endif
761 } cn58xx;
762 struct cvmx_l2c_cfg_cn58xxp1 {
763#ifdef __BIG_ENDIAN_BITFIELD
764 uint64_t reserved_15_63:49;
765 uint64_t dfill_dis:1;
766 uint64_t fpexp:4;
767 uint64_t fpempty:1;
768 uint64_t fpen:1;
769 uint64_t idxalias:1;
770 uint64_t mwf_crd:4;
771 uint64_t rsp_arb_mode:1;
772 uint64_t rfb_arb_mode:1;
773 uint64_t lrf_arb_mode:1;
774#else
775 uint64_t lrf_arb_mode:1;
776 uint64_t rfb_arb_mode:1;
777 uint64_t rsp_arb_mode:1;
778 uint64_t mwf_crd:4;
779 uint64_t idxalias:1;
780 uint64_t fpen:1;
781 uint64_t fpempty:1;
782 uint64_t fpexp:4;
783 uint64_t dfill_dis:1;
784 uint64_t reserved_15_63:49;
785#endif
786 } cn58xxp1;
787};
788
789union cvmx_l2c_cop0_mapx {
790 uint64_t u64;
791 struct cvmx_l2c_cop0_mapx_s {
792#ifdef __BIG_ENDIAN_BITFIELD
793 uint64_t data:64;
794#else
795 uint64_t data:64;
796#endif
797 } s;
798 struct cvmx_l2c_cop0_mapx_s cn61xx;
799 struct cvmx_l2c_cop0_mapx_s cn63xx;
800 struct cvmx_l2c_cop0_mapx_s cn63xxp1;
801 struct cvmx_l2c_cop0_mapx_s cn66xx;
802 struct cvmx_l2c_cop0_mapx_s cn68xx;
803 struct cvmx_l2c_cop0_mapx_s cn68xxp1;
804 struct cvmx_l2c_cop0_mapx_s cnf71xx;
805}; 92};
806 93
807union cvmx_l2c_ctl { 94union cvmx_l2c_ctl {
808 uint64_t u64; 95 uint64_t u64;
809 struct cvmx_l2c_ctl_s { 96 struct cvmx_l2c_ctl_s {
810#ifdef __BIG_ENDIAN_BITFIELD 97 __BITFIELD_FIELD(uint64_t reserved_30_63:34,
811 uint64_t reserved_30_63:34; 98 __BITFIELD_FIELD(uint64_t sepcmt:1,
812 uint64_t sepcmt:1; 99 __BITFIELD_FIELD(uint64_t rdf_fast:1,
813 uint64_t rdf_fast:1; 100 __BITFIELD_FIELD(uint64_t disstgl2i:1,
814 uint64_t disstgl2i:1; 101 __BITFIELD_FIELD(uint64_t l2dfsbe:1,
815 uint64_t l2dfsbe:1; 102 __BITFIELD_FIELD(uint64_t l2dfdbe:1,
816 uint64_t l2dfdbe:1; 103 __BITFIELD_FIELD(uint64_t discclk:1,
817 uint64_t discclk:1; 104 __BITFIELD_FIELD(uint64_t maxvab:4,
818 uint64_t maxvab:4; 105 __BITFIELD_FIELD(uint64_t maxlfb:4,
819 uint64_t maxlfb:4; 106 __BITFIELD_FIELD(uint64_t rsp_arb_mode:1,
820 uint64_t rsp_arb_mode:1; 107 __BITFIELD_FIELD(uint64_t xmc_arb_mode:1,
821 uint64_t xmc_arb_mode:1; 108 __BITFIELD_FIELD(uint64_t ef_ena:1,
822 uint64_t ef_ena:1; 109 __BITFIELD_FIELD(uint64_t ef_cnt:7,
823 uint64_t ef_cnt:7; 110 __BITFIELD_FIELD(uint64_t vab_thresh:4,
824 uint64_t vab_thresh:4; 111 __BITFIELD_FIELD(uint64_t disecc:1,
825 uint64_t disecc:1; 112 __BITFIELD_FIELD(uint64_t disidxalias:1,
826 uint64_t disidxalias:1; 113 ;))))))))))))))))
827#else
828 uint64_t disidxalias:1;
829 uint64_t disecc:1;
830 uint64_t vab_thresh:4;
831 uint64_t ef_cnt:7;
832 uint64_t ef_ena:1;
833 uint64_t xmc_arb_mode:1;
834 uint64_t rsp_arb_mode:1;
835 uint64_t maxlfb:4;
836 uint64_t maxvab:4;
837 uint64_t discclk:1;
838 uint64_t l2dfdbe:1;
839 uint64_t l2dfsbe:1;
840 uint64_t disstgl2i:1;
841 uint64_t rdf_fast:1;
842 uint64_t sepcmt:1;
843 uint64_t reserved_30_63:34;
844#endif
845 } s; 114 } s;
846 struct cvmx_l2c_ctl_cn61xx {
847#ifdef __BIG_ENDIAN_BITFIELD
848 uint64_t reserved_29_63:35;
849 uint64_t rdf_fast:1;
850 uint64_t disstgl2i:1;
851 uint64_t l2dfsbe:1;
852 uint64_t l2dfdbe:1;
853 uint64_t discclk:1;
854 uint64_t maxvab:4;
855 uint64_t maxlfb:4;
856 uint64_t rsp_arb_mode:1;
857 uint64_t xmc_arb_mode:1;
858 uint64_t ef_ena:1;
859 uint64_t ef_cnt:7;
860 uint64_t vab_thresh:4;
861 uint64_t disecc:1;
862 uint64_t disidxalias:1;
863#else
864 uint64_t disidxalias:1;
865 uint64_t disecc:1;
866 uint64_t vab_thresh:4;
867 uint64_t ef_cnt:7;
868 uint64_t ef_ena:1;
869 uint64_t xmc_arb_mode:1;
870 uint64_t rsp_arb_mode:1;
871 uint64_t maxlfb:4;
872 uint64_t maxvab:4;
873 uint64_t discclk:1;
874 uint64_t l2dfdbe:1;
875 uint64_t l2dfsbe:1;
876 uint64_t disstgl2i:1;
877 uint64_t rdf_fast:1;
878 uint64_t reserved_29_63:35;
879#endif
880 } cn61xx;
881 struct cvmx_l2c_ctl_cn63xx {
882#ifdef __BIG_ENDIAN_BITFIELD
883 uint64_t reserved_28_63:36;
884 uint64_t disstgl2i:1;
885 uint64_t l2dfsbe:1;
886 uint64_t l2dfdbe:1;
887 uint64_t discclk:1;
888 uint64_t maxvab:4;
889 uint64_t maxlfb:4;
890 uint64_t rsp_arb_mode:1;
891 uint64_t xmc_arb_mode:1;
892 uint64_t ef_ena:1;
893 uint64_t ef_cnt:7;
894 uint64_t vab_thresh:4;
895 uint64_t disecc:1;
896 uint64_t disidxalias:1;
897#else
898 uint64_t disidxalias:1;
899 uint64_t disecc:1;
900 uint64_t vab_thresh:4;
901 uint64_t ef_cnt:7;
902 uint64_t ef_ena:1;
903 uint64_t xmc_arb_mode:1;
904 uint64_t rsp_arb_mode:1;
905 uint64_t maxlfb:4;
906 uint64_t maxvab:4;
907 uint64_t discclk:1;
908 uint64_t l2dfdbe:1;
909 uint64_t l2dfsbe:1;
910 uint64_t disstgl2i:1;
911 uint64_t reserved_28_63:36;
912#endif
913 } cn63xx;
914 struct cvmx_l2c_ctl_cn63xxp1 {
915#ifdef __BIG_ENDIAN_BITFIELD
916 uint64_t reserved_25_63:39;
917 uint64_t discclk:1;
918 uint64_t maxvab:4;
919 uint64_t maxlfb:4;
920 uint64_t rsp_arb_mode:1;
921 uint64_t xmc_arb_mode:1;
922 uint64_t ef_ena:1;
923 uint64_t ef_cnt:7;
924 uint64_t vab_thresh:4;
925 uint64_t disecc:1;
926 uint64_t disidxalias:1;
927#else
928 uint64_t disidxalias:1;
929 uint64_t disecc:1;
930 uint64_t vab_thresh:4;
931 uint64_t ef_cnt:7;
932 uint64_t ef_ena:1;
933 uint64_t xmc_arb_mode:1;
934 uint64_t rsp_arb_mode:1;
935 uint64_t maxlfb:4;
936 uint64_t maxvab:4;
937 uint64_t discclk:1;
938 uint64_t reserved_25_63:39;
939#endif
940 } cn63xxp1;
941 struct cvmx_l2c_ctl_cn61xx cn66xx;
942 struct cvmx_l2c_ctl_s cn68xx;
943 struct cvmx_l2c_ctl_cn63xx cn68xxp1;
944 struct cvmx_l2c_ctl_cn61xx cnf71xx;
945}; 115};
946 116
947union cvmx_l2c_dbg { 117union cvmx_l2c_dbg {
948 uint64_t u64; 118 uint64_t u64;
949 struct cvmx_l2c_dbg_s { 119 struct cvmx_l2c_dbg_s {
950#ifdef __BIG_ENDIAN_BITFIELD 120 __BITFIELD_FIELD(uint64_t reserved_15_63:49,
951 uint64_t reserved_15_63:49; 121 __BITFIELD_FIELD(uint64_t lfb_enum:4,
952 uint64_t lfb_enum:4; 122 __BITFIELD_FIELD(uint64_t lfb_dmp:1,
953 uint64_t lfb_dmp:1; 123 __BITFIELD_FIELD(uint64_t ppnum:4,
954 uint64_t ppnum:4; 124 __BITFIELD_FIELD(uint64_t set:3,
955 uint64_t set:3; 125 __BITFIELD_FIELD(uint64_t finv:1,
956 uint64_t finv:1; 126 __BITFIELD_FIELD(uint64_t l2d:1,
957 uint64_t l2d:1; 127 __BITFIELD_FIELD(uint64_t l2t:1,
958 uint64_t l2t:1; 128 ;))))))))
959#else
960 uint64_t l2t:1;
961 uint64_t l2d:1;
962 uint64_t finv:1;
963 uint64_t set:3;
964 uint64_t ppnum:4;
965 uint64_t lfb_dmp:1;
966 uint64_t lfb_enum:4;
967 uint64_t reserved_15_63:49;
968#endif
969 } s;
970 struct cvmx_l2c_dbg_cn30xx {
971#ifdef __BIG_ENDIAN_BITFIELD
972 uint64_t reserved_13_63:51;
973 uint64_t lfb_enum:2;
974 uint64_t lfb_dmp:1;
975 uint64_t reserved_7_9:3;
976 uint64_t ppnum:1;
977 uint64_t reserved_5_5:1;
978 uint64_t set:2;
979 uint64_t finv:1;
980 uint64_t l2d:1;
981 uint64_t l2t:1;
982#else
983 uint64_t l2t:1;
984 uint64_t l2d:1;
985 uint64_t finv:1;
986 uint64_t set:2;
987 uint64_t reserved_5_5:1;
988 uint64_t ppnum:1;
989 uint64_t reserved_7_9:3;
990 uint64_t lfb_dmp:1;
991 uint64_t lfb_enum:2;
992 uint64_t reserved_13_63:51;
993#endif
994 } cn30xx;
995 struct cvmx_l2c_dbg_cn31xx {
996#ifdef __BIG_ENDIAN_BITFIELD
997 uint64_t reserved_14_63:50;
998 uint64_t lfb_enum:3;
999 uint64_t lfb_dmp:1;
1000 uint64_t reserved_7_9:3;
1001 uint64_t ppnum:1;
1002 uint64_t reserved_5_5:1;
1003 uint64_t set:2;
1004 uint64_t finv:1;
1005 uint64_t l2d:1;
1006 uint64_t l2t:1;
1007#else
1008 uint64_t l2t:1;
1009 uint64_t l2d:1;
1010 uint64_t finv:1;
1011 uint64_t set:2;
1012 uint64_t reserved_5_5:1;
1013 uint64_t ppnum:1;
1014 uint64_t reserved_7_9:3;
1015 uint64_t lfb_dmp:1;
1016 uint64_t lfb_enum:3;
1017 uint64_t reserved_14_63:50;
1018#endif
1019 } cn31xx;
1020 struct cvmx_l2c_dbg_s cn38xx;
1021 struct cvmx_l2c_dbg_s cn38xxp2;
1022 struct cvmx_l2c_dbg_cn50xx {
1023#ifdef __BIG_ENDIAN_BITFIELD
1024 uint64_t reserved_14_63:50;
1025 uint64_t lfb_enum:3;
1026 uint64_t lfb_dmp:1;
1027 uint64_t reserved_7_9:3;
1028 uint64_t ppnum:1;
1029 uint64_t set:3;
1030 uint64_t finv:1;
1031 uint64_t l2d:1;
1032 uint64_t l2t:1;
1033#else
1034 uint64_t l2t:1;
1035 uint64_t l2d:1;
1036 uint64_t finv:1;
1037 uint64_t set:3;
1038 uint64_t ppnum:1;
1039 uint64_t reserved_7_9:3;
1040 uint64_t lfb_dmp:1;
1041 uint64_t lfb_enum:3;
1042 uint64_t reserved_14_63:50;
1043#endif
1044 } cn50xx;
1045 struct cvmx_l2c_dbg_cn52xx {
1046#ifdef __BIG_ENDIAN_BITFIELD
1047 uint64_t reserved_14_63:50;
1048 uint64_t lfb_enum:3;
1049 uint64_t lfb_dmp:1;
1050 uint64_t reserved_8_9:2;
1051 uint64_t ppnum:2;
1052 uint64_t set:3;
1053 uint64_t finv:1;
1054 uint64_t l2d:1;
1055 uint64_t l2t:1;
1056#else
1057 uint64_t l2t:1;
1058 uint64_t l2d:1;
1059 uint64_t finv:1;
1060 uint64_t set:3;
1061 uint64_t ppnum:2;
1062 uint64_t reserved_8_9:2;
1063 uint64_t lfb_dmp:1;
1064 uint64_t lfb_enum:3;
1065 uint64_t reserved_14_63:50;
1066#endif
1067 } cn52xx;
1068 struct cvmx_l2c_dbg_cn52xx cn52xxp1;
1069 struct cvmx_l2c_dbg_s cn56xx;
1070 struct cvmx_l2c_dbg_s cn56xxp1;
1071 struct cvmx_l2c_dbg_s cn58xx;
1072 struct cvmx_l2c_dbg_s cn58xxp1;
1073};
1074
1075union cvmx_l2c_dut {
1076 uint64_t u64;
1077 struct cvmx_l2c_dut_s {
1078#ifdef __BIG_ENDIAN_BITFIELD
1079 uint64_t reserved_32_63:32;
1080 uint64_t dtena:1;
1081 uint64_t reserved_30_30:1;
1082 uint64_t dt_vld:1;
1083 uint64_t dt_tag:29;
1084#else
1085 uint64_t dt_tag:29;
1086 uint64_t dt_vld:1;
1087 uint64_t reserved_30_30:1;
1088 uint64_t dtena:1;
1089 uint64_t reserved_32_63:32;
1090#endif
1091 } s;
1092 struct cvmx_l2c_dut_s cn30xx;
1093 struct cvmx_l2c_dut_s cn31xx;
1094 struct cvmx_l2c_dut_s cn38xx;
1095 struct cvmx_l2c_dut_s cn38xxp2;
1096 struct cvmx_l2c_dut_s cn50xx;
1097 struct cvmx_l2c_dut_s cn52xx;
1098 struct cvmx_l2c_dut_s cn52xxp1;
1099 struct cvmx_l2c_dut_s cn56xx;
1100 struct cvmx_l2c_dut_s cn56xxp1;
1101 struct cvmx_l2c_dut_s cn58xx;
1102 struct cvmx_l2c_dut_s cn58xxp1;
1103};
1104
1105union cvmx_l2c_dut_mapx {
1106 uint64_t u64;
1107 struct cvmx_l2c_dut_mapx_s {
1108#ifdef __BIG_ENDIAN_BITFIELD
1109 uint64_t reserved_38_63:26;
1110 uint64_t tag:28;
1111 uint64_t reserved_1_9:9;
1112 uint64_t valid:1;
1113#else
1114 uint64_t valid:1;
1115 uint64_t reserved_1_9:9;
1116 uint64_t tag:28;
1117 uint64_t reserved_38_63:26;
1118#endif
1119 } s;
1120 struct cvmx_l2c_dut_mapx_s cn61xx;
1121 struct cvmx_l2c_dut_mapx_s cn63xx;
1122 struct cvmx_l2c_dut_mapx_s cn63xxp1;
1123 struct cvmx_l2c_dut_mapx_s cn66xx;
1124 struct cvmx_l2c_dut_mapx_s cn68xx;
1125 struct cvmx_l2c_dut_mapx_s cn68xxp1;
1126 struct cvmx_l2c_dut_mapx_s cnf71xx;
1127};
1128
1129union cvmx_l2c_err_tdtx {
1130 uint64_t u64;
1131 struct cvmx_l2c_err_tdtx_s {
1132#ifdef __BIG_ENDIAN_BITFIELD
1133 uint64_t dbe:1;
1134 uint64_t sbe:1;
1135 uint64_t vdbe:1;
1136 uint64_t vsbe:1;
1137 uint64_t syn:10;
1138 uint64_t reserved_22_49:28;
1139 uint64_t wayidx:18;
1140 uint64_t reserved_2_3:2;
1141 uint64_t type:2;
1142#else
1143 uint64_t type:2;
1144 uint64_t reserved_2_3:2;
1145 uint64_t wayidx:18;
1146 uint64_t reserved_22_49:28;
1147 uint64_t syn:10;
1148 uint64_t vsbe:1;
1149 uint64_t vdbe:1;
1150 uint64_t sbe:1;
1151 uint64_t dbe:1;
1152#endif
1153 } s;
1154 struct cvmx_l2c_err_tdtx_cn61xx {
1155#ifdef __BIG_ENDIAN_BITFIELD
1156 uint64_t dbe:1;
1157 uint64_t sbe:1;
1158 uint64_t vdbe:1;
1159 uint64_t vsbe:1;
1160 uint64_t syn:10;
1161 uint64_t reserved_20_49:30;
1162 uint64_t wayidx:16;
1163 uint64_t reserved_2_3:2;
1164 uint64_t type:2;
1165#else
1166 uint64_t type:2;
1167 uint64_t reserved_2_3:2;
1168 uint64_t wayidx:16;
1169 uint64_t reserved_20_49:30;
1170 uint64_t syn:10;
1171 uint64_t vsbe:1;
1172 uint64_t vdbe:1;
1173 uint64_t sbe:1;
1174 uint64_t dbe:1;
1175#endif
1176 } cn61xx;
1177 struct cvmx_l2c_err_tdtx_cn63xx {
1178#ifdef __BIG_ENDIAN_BITFIELD
1179 uint64_t dbe:1;
1180 uint64_t sbe:1;
1181 uint64_t vdbe:1;
1182 uint64_t vsbe:1;
1183 uint64_t syn:10;
1184 uint64_t reserved_21_49:29;
1185 uint64_t wayidx:17;
1186 uint64_t reserved_2_3:2;
1187 uint64_t type:2;
1188#else
1189 uint64_t type:2;
1190 uint64_t reserved_2_3:2;
1191 uint64_t wayidx:17;
1192 uint64_t reserved_21_49:29;
1193 uint64_t syn:10;
1194 uint64_t vsbe:1;
1195 uint64_t vdbe:1;
1196 uint64_t sbe:1;
1197 uint64_t dbe:1;
1198#endif
1199 } cn63xx;
1200 struct cvmx_l2c_err_tdtx_cn63xx cn63xxp1;
1201 struct cvmx_l2c_err_tdtx_cn63xx cn66xx;
1202 struct cvmx_l2c_err_tdtx_s cn68xx;
1203 struct cvmx_l2c_err_tdtx_s cn68xxp1;
1204 struct cvmx_l2c_err_tdtx_cn61xx cnf71xx;
1205};
1206
1207union cvmx_l2c_err_ttgx {
1208 uint64_t u64;
1209 struct cvmx_l2c_err_ttgx_s {
1210#ifdef __BIG_ENDIAN_BITFIELD
1211 uint64_t dbe:1;
1212 uint64_t sbe:1;
1213 uint64_t noway:1;
1214 uint64_t reserved_56_60:5;
1215 uint64_t syn:6;
1216 uint64_t reserved_22_49:28;
1217 uint64_t wayidx:15;
1218 uint64_t reserved_2_6:5;
1219 uint64_t type:2;
1220#else
1221 uint64_t type:2;
1222 uint64_t reserved_2_6:5;
1223 uint64_t wayidx:15;
1224 uint64_t reserved_22_49:28;
1225 uint64_t syn:6;
1226 uint64_t reserved_56_60:5;
1227 uint64_t noway:1;
1228 uint64_t sbe:1;
1229 uint64_t dbe:1;
1230#endif
1231 } s;
1232 struct cvmx_l2c_err_ttgx_cn61xx {
1233#ifdef __BIG_ENDIAN_BITFIELD
1234 uint64_t dbe:1;
1235 uint64_t sbe:1;
1236 uint64_t noway:1;
1237 uint64_t reserved_56_60:5;
1238 uint64_t syn:6;
1239 uint64_t reserved_20_49:30;
1240 uint64_t wayidx:13;
1241 uint64_t reserved_2_6:5;
1242 uint64_t type:2;
1243#else
1244 uint64_t type:2;
1245 uint64_t reserved_2_6:5;
1246 uint64_t wayidx:13;
1247 uint64_t reserved_20_49:30;
1248 uint64_t syn:6;
1249 uint64_t reserved_56_60:5;
1250 uint64_t noway:1;
1251 uint64_t sbe:1;
1252 uint64_t dbe:1;
1253#endif
1254 } cn61xx;
1255 struct cvmx_l2c_err_ttgx_cn63xx {
1256#ifdef __BIG_ENDIAN_BITFIELD
1257 uint64_t dbe:1;
1258 uint64_t sbe:1;
1259 uint64_t noway:1;
1260 uint64_t reserved_56_60:5;
1261 uint64_t syn:6;
1262 uint64_t reserved_21_49:29;
1263 uint64_t wayidx:14;
1264 uint64_t reserved_2_6:5;
1265 uint64_t type:2;
1266#else
1267 uint64_t type:2;
1268 uint64_t reserved_2_6:5;
1269 uint64_t wayidx:14;
1270 uint64_t reserved_21_49:29;
1271 uint64_t syn:6;
1272 uint64_t reserved_56_60:5;
1273 uint64_t noway:1;
1274 uint64_t sbe:1;
1275 uint64_t dbe:1;
1276#endif
1277 } cn63xx;
1278 struct cvmx_l2c_err_ttgx_cn63xx cn63xxp1;
1279 struct cvmx_l2c_err_ttgx_cn63xx cn66xx;
1280 struct cvmx_l2c_err_ttgx_s cn68xx;
1281 struct cvmx_l2c_err_ttgx_s cn68xxp1;
1282 struct cvmx_l2c_err_ttgx_cn61xx cnf71xx;
1283};
1284
1285union cvmx_l2c_err_vbfx {
1286 uint64_t u64;
1287 struct cvmx_l2c_err_vbfx_s {
1288#ifdef __BIG_ENDIAN_BITFIELD
1289 uint64_t reserved_62_63:2;
1290 uint64_t vdbe:1;
1291 uint64_t vsbe:1;
1292 uint64_t vsyn:10;
1293 uint64_t reserved_2_49:48;
1294 uint64_t type:2;
1295#else
1296 uint64_t type:2;
1297 uint64_t reserved_2_49:48;
1298 uint64_t vsyn:10;
1299 uint64_t vsbe:1;
1300 uint64_t vdbe:1;
1301 uint64_t reserved_62_63:2;
1302#endif
1303 } s;
1304 struct cvmx_l2c_err_vbfx_s cn61xx;
1305 struct cvmx_l2c_err_vbfx_s cn63xx;
1306 struct cvmx_l2c_err_vbfx_s cn63xxp1;
1307 struct cvmx_l2c_err_vbfx_s cn66xx;
1308 struct cvmx_l2c_err_vbfx_s cn68xx;
1309 struct cvmx_l2c_err_vbfx_s cn68xxp1;
1310 struct cvmx_l2c_err_vbfx_s cnf71xx;
1311};
1312
1313union cvmx_l2c_err_xmc {
1314 uint64_t u64;
1315 struct cvmx_l2c_err_xmc_s {
1316#ifdef __BIG_ENDIAN_BITFIELD
1317 uint64_t cmd:6;
1318 uint64_t reserved_54_57:4;
1319 uint64_t sid:6;
1320 uint64_t reserved_38_47:10;
1321 uint64_t addr:38;
1322#else
1323 uint64_t addr:38;
1324 uint64_t reserved_38_47:10;
1325 uint64_t sid:6;
1326 uint64_t reserved_54_57:4;
1327 uint64_t cmd:6;
1328#endif
1329 } s;
1330 struct cvmx_l2c_err_xmc_cn61xx {
1331#ifdef __BIG_ENDIAN_BITFIELD
1332 uint64_t cmd:6;
1333 uint64_t reserved_52_57:6;
1334 uint64_t sid:4;
1335 uint64_t reserved_38_47:10;
1336 uint64_t addr:38;
1337#else
1338 uint64_t addr:38;
1339 uint64_t reserved_38_47:10;
1340 uint64_t sid:4;
1341 uint64_t reserved_52_57:6;
1342 uint64_t cmd:6;
1343#endif
1344 } cn61xx;
1345 struct cvmx_l2c_err_xmc_cn61xx cn63xx;
1346 struct cvmx_l2c_err_xmc_cn61xx cn63xxp1;
1347 struct cvmx_l2c_err_xmc_cn66xx {
1348#ifdef __BIG_ENDIAN_BITFIELD
1349 uint64_t cmd:6;
1350 uint64_t reserved_53_57:5;
1351 uint64_t sid:5;
1352 uint64_t reserved_38_47:10;
1353 uint64_t addr:38;
1354#else
1355 uint64_t addr:38;
1356 uint64_t reserved_38_47:10;
1357 uint64_t sid:5;
1358 uint64_t reserved_53_57:5;
1359 uint64_t cmd:6;
1360#endif
1361 } cn66xx;
1362 struct cvmx_l2c_err_xmc_s cn68xx;
1363 struct cvmx_l2c_err_xmc_s cn68xxp1;
1364 struct cvmx_l2c_err_xmc_cn61xx cnf71xx;
1365};
1366
1367union cvmx_l2c_grpwrr0 {
1368 uint64_t u64;
1369 struct cvmx_l2c_grpwrr0_s {
1370#ifdef __BIG_ENDIAN_BITFIELD
1371 uint64_t plc1rmsk:32;
1372 uint64_t plc0rmsk:32;
1373#else
1374 uint64_t plc0rmsk:32;
1375 uint64_t plc1rmsk:32;
1376#endif
1377 } s;
1378 struct cvmx_l2c_grpwrr0_s cn52xx;
1379 struct cvmx_l2c_grpwrr0_s cn52xxp1;
1380 struct cvmx_l2c_grpwrr0_s cn56xx;
1381 struct cvmx_l2c_grpwrr0_s cn56xxp1;
1382};
1383
1384union cvmx_l2c_grpwrr1 {
1385 uint64_t u64;
1386 struct cvmx_l2c_grpwrr1_s {
1387#ifdef __BIG_ENDIAN_BITFIELD
1388 uint64_t ilcrmsk:32;
1389 uint64_t plc2rmsk:32;
1390#else
1391 uint64_t plc2rmsk:32;
1392 uint64_t ilcrmsk:32;
1393#endif
1394 } s;
1395 struct cvmx_l2c_grpwrr1_s cn52xx;
1396 struct cvmx_l2c_grpwrr1_s cn52xxp1;
1397 struct cvmx_l2c_grpwrr1_s cn56xx;
1398 struct cvmx_l2c_grpwrr1_s cn56xxp1;
1399};
1400
1401union cvmx_l2c_int_en {
1402 uint64_t u64;
1403 struct cvmx_l2c_int_en_s {
1404#ifdef __BIG_ENDIAN_BITFIELD
1405 uint64_t reserved_9_63:55;
1406 uint64_t lck2ena:1;
1407 uint64_t lckena:1;
1408 uint64_t l2ddeden:1;
1409 uint64_t l2dsecen:1;
1410 uint64_t l2tdeden:1;
1411 uint64_t l2tsecen:1;
1412 uint64_t oob3en:1;
1413 uint64_t oob2en:1;
1414 uint64_t oob1en:1;
1415#else
1416 uint64_t oob1en:1;
1417 uint64_t oob2en:1;
1418 uint64_t oob3en:1;
1419 uint64_t l2tsecen:1;
1420 uint64_t l2tdeden:1;
1421 uint64_t l2dsecen:1;
1422 uint64_t l2ddeden:1;
1423 uint64_t lckena:1;
1424 uint64_t lck2ena:1;
1425 uint64_t reserved_9_63:55;
1426#endif
1427 } s;
1428 struct cvmx_l2c_int_en_s cn52xx;
1429 struct cvmx_l2c_int_en_s cn52xxp1;
1430 struct cvmx_l2c_int_en_s cn56xx;
1431 struct cvmx_l2c_int_en_s cn56xxp1;
1432};
1433
1434union cvmx_l2c_int_ena {
1435 uint64_t u64;
1436 struct cvmx_l2c_int_ena_s {
1437#ifdef __BIG_ENDIAN_BITFIELD
1438 uint64_t reserved_8_63:56;
1439 uint64_t bigrd:1;
1440 uint64_t bigwr:1;
1441 uint64_t vrtpe:1;
1442 uint64_t vrtadrng:1;
1443 uint64_t vrtidrng:1;
1444 uint64_t vrtwr:1;
1445 uint64_t holewr:1;
1446 uint64_t holerd:1;
1447#else
1448 uint64_t holerd:1;
1449 uint64_t holewr:1;
1450 uint64_t vrtwr:1;
1451 uint64_t vrtidrng:1;
1452 uint64_t vrtadrng:1;
1453 uint64_t vrtpe:1;
1454 uint64_t bigwr:1;
1455 uint64_t bigrd:1;
1456 uint64_t reserved_8_63:56;
1457#endif
1458 } s;
1459 struct cvmx_l2c_int_ena_s cn61xx;
1460 struct cvmx_l2c_int_ena_s cn63xx;
1461 struct cvmx_l2c_int_ena_cn63xxp1 {
1462#ifdef __BIG_ENDIAN_BITFIELD
1463 uint64_t reserved_6_63:58;
1464 uint64_t vrtpe:1;
1465 uint64_t vrtadrng:1;
1466 uint64_t vrtidrng:1;
1467 uint64_t vrtwr:1;
1468 uint64_t holewr:1;
1469 uint64_t holerd:1;
1470#else
1471 uint64_t holerd:1;
1472 uint64_t holewr:1;
1473 uint64_t vrtwr:1;
1474 uint64_t vrtidrng:1;
1475 uint64_t vrtadrng:1;
1476 uint64_t vrtpe:1;
1477 uint64_t reserved_6_63:58;
1478#endif
1479 } cn63xxp1;
1480 struct cvmx_l2c_int_ena_s cn66xx;
1481 struct cvmx_l2c_int_ena_s cn68xx;
1482 struct cvmx_l2c_int_ena_s cn68xxp1;
1483 struct cvmx_l2c_int_ena_s cnf71xx;
1484};
1485
1486union cvmx_l2c_int_reg {
1487 uint64_t u64;
1488 struct cvmx_l2c_int_reg_s {
1489#ifdef __BIG_ENDIAN_BITFIELD
1490 uint64_t reserved_20_63:44;
1491 uint64_t tad3:1;
1492 uint64_t tad2:1;
1493 uint64_t tad1:1;
1494 uint64_t tad0:1;
1495 uint64_t reserved_8_15:8;
1496 uint64_t bigrd:1;
1497 uint64_t bigwr:1;
1498 uint64_t vrtpe:1;
1499 uint64_t vrtadrng:1;
1500 uint64_t vrtidrng:1;
1501 uint64_t vrtwr:1;
1502 uint64_t holewr:1;
1503 uint64_t holerd:1;
1504#else
1505 uint64_t holerd:1;
1506 uint64_t holewr:1;
1507 uint64_t vrtwr:1;
1508 uint64_t vrtidrng:1;
1509 uint64_t vrtadrng:1;
1510 uint64_t vrtpe:1;
1511 uint64_t bigwr:1;
1512 uint64_t bigrd:1;
1513 uint64_t reserved_8_15:8;
1514 uint64_t tad0:1;
1515 uint64_t tad1:1;
1516 uint64_t tad2:1;
1517 uint64_t tad3:1;
1518 uint64_t reserved_20_63:44;
1519#endif
1520 } s;
1521 struct cvmx_l2c_int_reg_cn61xx {
1522#ifdef __BIG_ENDIAN_BITFIELD
1523 uint64_t reserved_17_63:47;
1524 uint64_t tad0:1;
1525 uint64_t reserved_8_15:8;
1526 uint64_t bigrd:1;
1527 uint64_t bigwr:1;
1528 uint64_t vrtpe:1;
1529 uint64_t vrtadrng:1;
1530 uint64_t vrtidrng:1;
1531 uint64_t vrtwr:1;
1532 uint64_t holewr:1;
1533 uint64_t holerd:1;
1534#else
1535 uint64_t holerd:1;
1536 uint64_t holewr:1;
1537 uint64_t vrtwr:1;
1538 uint64_t vrtidrng:1;
1539 uint64_t vrtadrng:1;
1540 uint64_t vrtpe:1;
1541 uint64_t bigwr:1;
1542 uint64_t bigrd:1;
1543 uint64_t reserved_8_15:8;
1544 uint64_t tad0:1;
1545 uint64_t reserved_17_63:47;
1546#endif
1547 } cn61xx;
1548 struct cvmx_l2c_int_reg_cn61xx cn63xx;
1549 struct cvmx_l2c_int_reg_cn63xxp1 {
1550#ifdef __BIG_ENDIAN_BITFIELD
1551 uint64_t reserved_17_63:47;
1552 uint64_t tad0:1;
1553 uint64_t reserved_6_15:10;
1554 uint64_t vrtpe:1;
1555 uint64_t vrtadrng:1;
1556 uint64_t vrtidrng:1;
1557 uint64_t vrtwr:1;
1558 uint64_t holewr:1;
1559 uint64_t holerd:1;
1560#else
1561 uint64_t holerd:1;
1562 uint64_t holewr:1;
1563 uint64_t vrtwr:1;
1564 uint64_t vrtidrng:1;
1565 uint64_t vrtadrng:1;
1566 uint64_t vrtpe:1;
1567 uint64_t reserved_6_15:10;
1568 uint64_t tad0:1;
1569 uint64_t reserved_17_63:47;
1570#endif
1571 } cn63xxp1;
1572 struct cvmx_l2c_int_reg_cn61xx cn66xx;
1573 struct cvmx_l2c_int_reg_s cn68xx;
1574 struct cvmx_l2c_int_reg_s cn68xxp1;
1575 struct cvmx_l2c_int_reg_cn61xx cnf71xx;
1576};
1577
1578union cvmx_l2c_int_stat {
1579 uint64_t u64;
1580 struct cvmx_l2c_int_stat_s {
1581#ifdef __BIG_ENDIAN_BITFIELD
1582 uint64_t reserved_9_63:55;
1583 uint64_t lck2:1;
1584 uint64_t lck:1;
1585 uint64_t l2dded:1;
1586 uint64_t l2dsec:1;
1587 uint64_t l2tded:1;
1588 uint64_t l2tsec:1;
1589 uint64_t oob3:1;
1590 uint64_t oob2:1;
1591 uint64_t oob1:1;
1592#else
1593 uint64_t oob1:1;
1594 uint64_t oob2:1;
1595 uint64_t oob3:1;
1596 uint64_t l2tsec:1;
1597 uint64_t l2tded:1;
1598 uint64_t l2dsec:1;
1599 uint64_t l2dded:1;
1600 uint64_t lck:1;
1601 uint64_t lck2:1;
1602 uint64_t reserved_9_63:55;
1603#endif
1604 } s;
1605 struct cvmx_l2c_int_stat_s cn52xx;
1606 struct cvmx_l2c_int_stat_s cn52xxp1;
1607 struct cvmx_l2c_int_stat_s cn56xx;
1608 struct cvmx_l2c_int_stat_s cn56xxp1;
1609};
1610
1611union cvmx_l2c_iocx_pfc {
1612 uint64_t u64;
1613 struct cvmx_l2c_iocx_pfc_s {
1614#ifdef __BIG_ENDIAN_BITFIELD
1615 uint64_t count:64;
1616#else
1617 uint64_t count:64;
1618#endif
1619 } s;
1620 struct cvmx_l2c_iocx_pfc_s cn61xx;
1621 struct cvmx_l2c_iocx_pfc_s cn63xx;
1622 struct cvmx_l2c_iocx_pfc_s cn63xxp1;
1623 struct cvmx_l2c_iocx_pfc_s cn66xx;
1624 struct cvmx_l2c_iocx_pfc_s cn68xx;
1625 struct cvmx_l2c_iocx_pfc_s cn68xxp1;
1626 struct cvmx_l2c_iocx_pfc_s cnf71xx;
1627};
1628
1629union cvmx_l2c_iorx_pfc {
1630 uint64_t u64;
1631 struct cvmx_l2c_iorx_pfc_s {
1632#ifdef __BIG_ENDIAN_BITFIELD
1633 uint64_t count:64;
1634#else
1635 uint64_t count:64;
1636#endif
1637 } s;
1638 struct cvmx_l2c_iorx_pfc_s cn61xx;
1639 struct cvmx_l2c_iorx_pfc_s cn63xx;
1640 struct cvmx_l2c_iorx_pfc_s cn63xxp1;
1641 struct cvmx_l2c_iorx_pfc_s cn66xx;
1642 struct cvmx_l2c_iorx_pfc_s cn68xx;
1643 struct cvmx_l2c_iorx_pfc_s cn68xxp1;
1644 struct cvmx_l2c_iorx_pfc_s cnf71xx;
1645};
1646
1647union cvmx_l2c_lckbase {
1648 uint64_t u64;
1649 struct cvmx_l2c_lckbase_s {
1650#ifdef __BIG_ENDIAN_BITFIELD
1651 uint64_t reserved_31_63:33;
1652 uint64_t lck_base:27;
1653 uint64_t reserved_1_3:3;
1654 uint64_t lck_ena:1;
1655#else
1656 uint64_t lck_ena:1;
1657 uint64_t reserved_1_3:3;
1658 uint64_t lck_base:27;
1659 uint64_t reserved_31_63:33;
1660#endif
1661 } s;
1662 struct cvmx_l2c_lckbase_s cn30xx;
1663 struct cvmx_l2c_lckbase_s cn31xx;
1664 struct cvmx_l2c_lckbase_s cn38xx;
1665 struct cvmx_l2c_lckbase_s cn38xxp2;
1666 struct cvmx_l2c_lckbase_s cn50xx;
1667 struct cvmx_l2c_lckbase_s cn52xx;
1668 struct cvmx_l2c_lckbase_s cn52xxp1;
1669 struct cvmx_l2c_lckbase_s cn56xx;
1670 struct cvmx_l2c_lckbase_s cn56xxp1;
1671 struct cvmx_l2c_lckbase_s cn58xx;
1672 struct cvmx_l2c_lckbase_s cn58xxp1;
1673};
1674
1675union cvmx_l2c_lckoff {
1676 uint64_t u64;
1677 struct cvmx_l2c_lckoff_s {
1678#ifdef __BIG_ENDIAN_BITFIELD
1679 uint64_t reserved_10_63:54;
1680 uint64_t lck_offset:10;
1681#else
1682 uint64_t lck_offset:10;
1683 uint64_t reserved_10_63:54;
1684#endif
1685 } s;
1686 struct cvmx_l2c_lckoff_s cn30xx;
1687 struct cvmx_l2c_lckoff_s cn31xx;
1688 struct cvmx_l2c_lckoff_s cn38xx;
1689 struct cvmx_l2c_lckoff_s cn38xxp2;
1690 struct cvmx_l2c_lckoff_s cn50xx;
1691 struct cvmx_l2c_lckoff_s cn52xx;
1692 struct cvmx_l2c_lckoff_s cn52xxp1;
1693 struct cvmx_l2c_lckoff_s cn56xx;
1694 struct cvmx_l2c_lckoff_s cn56xxp1;
1695 struct cvmx_l2c_lckoff_s cn58xx;
1696 struct cvmx_l2c_lckoff_s cn58xxp1;
1697};
1698
1699union cvmx_l2c_lfb0 {
1700 uint64_t u64;
1701 struct cvmx_l2c_lfb0_s {
1702#ifdef __BIG_ENDIAN_BITFIELD
1703 uint64_t reserved_32_63:32;
1704 uint64_t stcpnd:1;
1705 uint64_t stpnd:1;
1706 uint64_t stinv:1;
1707 uint64_t stcfl:1;
1708 uint64_t vam:1;
1709 uint64_t inxt:4;
1710 uint64_t itl:1;
1711 uint64_t ihd:1;
1712 uint64_t set:3;
1713 uint64_t vabnum:4;
1714 uint64_t sid:9;
1715 uint64_t cmd:4;
1716 uint64_t vld:1;
1717#else
1718 uint64_t vld:1;
1719 uint64_t cmd:4;
1720 uint64_t sid:9;
1721 uint64_t vabnum:4;
1722 uint64_t set:3;
1723 uint64_t ihd:1;
1724 uint64_t itl:1;
1725 uint64_t inxt:4;
1726 uint64_t vam:1;
1727 uint64_t stcfl:1;
1728 uint64_t stinv:1;
1729 uint64_t stpnd:1;
1730 uint64_t stcpnd:1;
1731 uint64_t reserved_32_63:32;
1732#endif
1733 } s;
1734 struct cvmx_l2c_lfb0_cn30xx {
1735#ifdef __BIG_ENDIAN_BITFIELD
1736 uint64_t reserved_32_63:32;
1737 uint64_t stcpnd:1;
1738 uint64_t stpnd:1;
1739 uint64_t stinv:1;
1740 uint64_t stcfl:1;
1741 uint64_t vam:1;
1742 uint64_t reserved_25_26:2;
1743 uint64_t inxt:2;
1744 uint64_t itl:1;
1745 uint64_t ihd:1;
1746 uint64_t reserved_20_20:1;
1747 uint64_t set:2;
1748 uint64_t reserved_16_17:2;
1749 uint64_t vabnum:2;
1750 uint64_t sid:9;
1751 uint64_t cmd:4;
1752 uint64_t vld:1;
1753#else
1754 uint64_t vld:1;
1755 uint64_t cmd:4;
1756 uint64_t sid:9;
1757 uint64_t vabnum:2;
1758 uint64_t reserved_16_17:2;
1759 uint64_t set:2;
1760 uint64_t reserved_20_20:1;
1761 uint64_t ihd:1;
1762 uint64_t itl:1;
1763 uint64_t inxt:2;
1764 uint64_t reserved_25_26:2;
1765 uint64_t vam:1;
1766 uint64_t stcfl:1;
1767 uint64_t stinv:1;
1768 uint64_t stpnd:1;
1769 uint64_t stcpnd:1;
1770 uint64_t reserved_32_63:32;
1771#endif
1772 } cn30xx;
1773 struct cvmx_l2c_lfb0_cn31xx {
1774#ifdef __BIG_ENDIAN_BITFIELD
1775 uint64_t reserved_32_63:32;
1776 uint64_t stcpnd:1;
1777 uint64_t stpnd:1;
1778 uint64_t stinv:1;
1779 uint64_t stcfl:1;
1780 uint64_t vam:1;
1781 uint64_t reserved_26_26:1;
1782 uint64_t inxt:3;
1783 uint64_t itl:1;
1784 uint64_t ihd:1;
1785 uint64_t reserved_20_20:1;
1786 uint64_t set:2;
1787 uint64_t reserved_17_17:1;
1788 uint64_t vabnum:3;
1789 uint64_t sid:9;
1790 uint64_t cmd:4;
1791 uint64_t vld:1;
1792#else
1793 uint64_t vld:1;
1794 uint64_t cmd:4;
1795 uint64_t sid:9;
1796 uint64_t vabnum:3;
1797 uint64_t reserved_17_17:1;
1798 uint64_t set:2;
1799 uint64_t reserved_20_20:1;
1800 uint64_t ihd:1;
1801 uint64_t itl:1;
1802 uint64_t inxt:3;
1803 uint64_t reserved_26_26:1;
1804 uint64_t vam:1;
1805 uint64_t stcfl:1;
1806 uint64_t stinv:1;
1807 uint64_t stpnd:1;
1808 uint64_t stcpnd:1;
1809 uint64_t reserved_32_63:32;
1810#endif
1811 } cn31xx;
1812 struct cvmx_l2c_lfb0_s cn38xx;
1813 struct cvmx_l2c_lfb0_s cn38xxp2;
1814 struct cvmx_l2c_lfb0_cn50xx {
1815#ifdef __BIG_ENDIAN_BITFIELD
1816 uint64_t reserved_32_63:32;
1817 uint64_t stcpnd:1;
1818 uint64_t stpnd:1;
1819 uint64_t stinv:1;
1820 uint64_t stcfl:1;
1821 uint64_t vam:1;
1822 uint64_t reserved_26_26:1;
1823 uint64_t inxt:3;
1824 uint64_t itl:1;
1825 uint64_t ihd:1;
1826 uint64_t set:3;
1827 uint64_t reserved_17_17:1;
1828 uint64_t vabnum:3;
1829 uint64_t sid:9;
1830 uint64_t cmd:4;
1831 uint64_t vld:1;
1832#else
1833 uint64_t vld:1;
1834 uint64_t cmd:4;
1835 uint64_t sid:9;
1836 uint64_t vabnum:3;
1837 uint64_t reserved_17_17:1;
1838 uint64_t set:3;
1839 uint64_t ihd:1;
1840 uint64_t itl:1;
1841 uint64_t inxt:3;
1842 uint64_t reserved_26_26:1;
1843 uint64_t vam:1;
1844 uint64_t stcfl:1;
1845 uint64_t stinv:1;
1846 uint64_t stpnd:1;
1847 uint64_t stcpnd:1;
1848 uint64_t reserved_32_63:32;
1849#endif
1850 } cn50xx;
1851 struct cvmx_l2c_lfb0_cn50xx cn52xx;
1852 struct cvmx_l2c_lfb0_cn50xx cn52xxp1;
1853 struct cvmx_l2c_lfb0_s cn56xx;
1854 struct cvmx_l2c_lfb0_s cn56xxp1;
1855 struct cvmx_l2c_lfb0_s cn58xx;
1856 struct cvmx_l2c_lfb0_s cn58xxp1;
1857};
1858
1859union cvmx_l2c_lfb1 {
1860 uint64_t u64;
1861 struct cvmx_l2c_lfb1_s {
1862#ifdef __BIG_ENDIAN_BITFIELD
1863 uint64_t reserved_19_63:45;
1864 uint64_t dsgoing:1;
1865 uint64_t bid:2;
1866 uint64_t wtrsp:1;
1867 uint64_t wtdw:1;
1868 uint64_t wtdq:1;
1869 uint64_t wtwhp:1;
1870 uint64_t wtwhf:1;
1871 uint64_t wtwrm:1;
1872 uint64_t wtstm:1;
1873 uint64_t wtrda:1;
1874 uint64_t wtstdt:1;
1875 uint64_t wtstrsp:1;
1876 uint64_t wtstrsc:1;
1877 uint64_t wtvtm:1;
1878 uint64_t wtmfl:1;
1879 uint64_t prbrty:1;
1880 uint64_t wtprb:1;
1881 uint64_t vld:1;
1882#else
1883 uint64_t vld:1;
1884 uint64_t wtprb:1;
1885 uint64_t prbrty:1;
1886 uint64_t wtmfl:1;
1887 uint64_t wtvtm:1;
1888 uint64_t wtstrsc:1;
1889 uint64_t wtstrsp:1;
1890 uint64_t wtstdt:1;
1891 uint64_t wtrda:1;
1892 uint64_t wtstm:1;
1893 uint64_t wtwrm:1;
1894 uint64_t wtwhf:1;
1895 uint64_t wtwhp:1;
1896 uint64_t wtdq:1;
1897 uint64_t wtdw:1;
1898 uint64_t wtrsp:1;
1899 uint64_t bid:2;
1900 uint64_t dsgoing:1;
1901 uint64_t reserved_19_63:45;
1902#endif
1903 } s;
1904 struct cvmx_l2c_lfb1_s cn30xx;
1905 struct cvmx_l2c_lfb1_s cn31xx;
1906 struct cvmx_l2c_lfb1_s cn38xx;
1907 struct cvmx_l2c_lfb1_s cn38xxp2;
1908 struct cvmx_l2c_lfb1_s cn50xx;
1909 struct cvmx_l2c_lfb1_s cn52xx;
1910 struct cvmx_l2c_lfb1_s cn52xxp1;
1911 struct cvmx_l2c_lfb1_s cn56xx;
1912 struct cvmx_l2c_lfb1_s cn56xxp1;
1913 struct cvmx_l2c_lfb1_s cn58xx;
1914 struct cvmx_l2c_lfb1_s cn58xxp1;
1915};
1916
1917union cvmx_l2c_lfb2 {
1918 uint64_t u64;
1919 struct cvmx_l2c_lfb2_s {
1920#ifdef __BIG_ENDIAN_BITFIELD
1921 uint64_t reserved_0_63:64;
1922#else
1923 uint64_t reserved_0_63:64;
1924#endif
1925 } s;
1926 struct cvmx_l2c_lfb2_cn30xx {
1927#ifdef __BIG_ENDIAN_BITFIELD
1928 uint64_t reserved_27_63:37;
1929 uint64_t lfb_tag:19;
1930 uint64_t lfb_idx:8;
1931#else
1932 uint64_t lfb_idx:8;
1933 uint64_t lfb_tag:19;
1934 uint64_t reserved_27_63:37;
1935#endif
1936 } cn30xx;
1937 struct cvmx_l2c_lfb2_cn31xx {
1938#ifdef __BIG_ENDIAN_BITFIELD
1939 uint64_t reserved_27_63:37;
1940 uint64_t lfb_tag:17;
1941 uint64_t lfb_idx:10;
1942#else
1943 uint64_t lfb_idx:10;
1944 uint64_t lfb_tag:17;
1945 uint64_t reserved_27_63:37;
1946#endif
1947 } cn31xx;
1948 struct cvmx_l2c_lfb2_cn31xx cn38xx;
1949 struct cvmx_l2c_lfb2_cn31xx cn38xxp2;
1950 struct cvmx_l2c_lfb2_cn50xx {
1951#ifdef __BIG_ENDIAN_BITFIELD
1952 uint64_t reserved_27_63:37;
1953 uint64_t lfb_tag:20;
1954 uint64_t lfb_idx:7;
1955#else
1956 uint64_t lfb_idx:7;
1957 uint64_t lfb_tag:20;
1958 uint64_t reserved_27_63:37;
1959#endif
1960 } cn50xx;
1961 struct cvmx_l2c_lfb2_cn52xx {
1962#ifdef __BIG_ENDIAN_BITFIELD
1963 uint64_t reserved_27_63:37;
1964 uint64_t lfb_tag:18;
1965 uint64_t lfb_idx:9;
1966#else
1967 uint64_t lfb_idx:9;
1968 uint64_t lfb_tag:18;
1969 uint64_t reserved_27_63:37;
1970#endif
1971 } cn52xx;
1972 struct cvmx_l2c_lfb2_cn52xx cn52xxp1;
1973 struct cvmx_l2c_lfb2_cn56xx {
1974#ifdef __BIG_ENDIAN_BITFIELD
1975 uint64_t reserved_27_63:37;
1976 uint64_t lfb_tag:16;
1977 uint64_t lfb_idx:11;
1978#else
1979 uint64_t lfb_idx:11;
1980 uint64_t lfb_tag:16;
1981 uint64_t reserved_27_63:37;
1982#endif
1983 } cn56xx;
1984 struct cvmx_l2c_lfb2_cn56xx cn56xxp1;
1985 struct cvmx_l2c_lfb2_cn56xx cn58xx;
1986 struct cvmx_l2c_lfb2_cn56xx cn58xxp1;
1987};
1988
1989union cvmx_l2c_lfb3 {
1990 uint64_t u64;
1991 struct cvmx_l2c_lfb3_s {
1992#ifdef __BIG_ENDIAN_BITFIELD
1993 uint64_t reserved_5_63:59;
1994 uint64_t stpartdis:1;
1995 uint64_t lfb_hwm:4;
1996#else
1997 uint64_t lfb_hwm:4;
1998 uint64_t stpartdis:1;
1999 uint64_t reserved_5_63:59;
2000#endif
2001 } s; 129 } s;
2002 struct cvmx_l2c_lfb3_cn30xx {
2003#ifdef __BIG_ENDIAN_BITFIELD
2004 uint64_t reserved_5_63:59;
2005 uint64_t stpartdis:1;
2006 uint64_t reserved_2_3:2;
2007 uint64_t lfb_hwm:2;
2008#else
2009 uint64_t lfb_hwm:2;
2010 uint64_t reserved_2_3:2;
2011 uint64_t stpartdis:1;
2012 uint64_t reserved_5_63:59;
2013#endif
2014 } cn30xx;
2015 struct cvmx_l2c_lfb3_cn31xx {
2016#ifdef __BIG_ENDIAN_BITFIELD
2017 uint64_t reserved_5_63:59;
2018 uint64_t stpartdis:1;
2019 uint64_t reserved_3_3:1;
2020 uint64_t lfb_hwm:3;
2021#else
2022 uint64_t lfb_hwm:3;
2023 uint64_t reserved_3_3:1;
2024 uint64_t stpartdis:1;
2025 uint64_t reserved_5_63:59;
2026#endif
2027 } cn31xx;
2028 struct cvmx_l2c_lfb3_s cn38xx;
2029 struct cvmx_l2c_lfb3_s cn38xxp2;
2030 struct cvmx_l2c_lfb3_cn31xx cn50xx;
2031 struct cvmx_l2c_lfb3_cn31xx cn52xx;
2032 struct cvmx_l2c_lfb3_cn31xx cn52xxp1;
2033 struct cvmx_l2c_lfb3_s cn56xx;
2034 struct cvmx_l2c_lfb3_s cn56xxp1;
2035 struct cvmx_l2c_lfb3_s cn58xx;
2036 struct cvmx_l2c_lfb3_s cn58xxp1;
2037};
2038
2039union cvmx_l2c_oob {
2040 uint64_t u64;
2041 struct cvmx_l2c_oob_s {
2042#ifdef __BIG_ENDIAN_BITFIELD
2043 uint64_t reserved_2_63:62;
2044 uint64_t dwbena:1;
2045 uint64_t stena:1;
2046#else
2047 uint64_t stena:1;
2048 uint64_t dwbena:1;
2049 uint64_t reserved_2_63:62;
2050#endif
2051 } s;
2052 struct cvmx_l2c_oob_s cn52xx;
2053 struct cvmx_l2c_oob_s cn52xxp1;
2054 struct cvmx_l2c_oob_s cn56xx;
2055 struct cvmx_l2c_oob_s cn56xxp1;
2056};
2057
2058union cvmx_l2c_oob1 {
2059 uint64_t u64;
2060 struct cvmx_l2c_oob1_s {
2061#ifdef __BIG_ENDIAN_BITFIELD
2062 uint64_t fadr:27;
2063 uint64_t fsrc:1;
2064 uint64_t reserved_34_35:2;
2065 uint64_t sadr:14;
2066 uint64_t reserved_14_19:6;
2067 uint64_t size:14;
2068#else
2069 uint64_t size:14;
2070 uint64_t reserved_14_19:6;
2071 uint64_t sadr:14;
2072 uint64_t reserved_34_35:2;
2073 uint64_t fsrc:1;
2074 uint64_t fadr:27;
2075#endif
2076 } s;
2077 struct cvmx_l2c_oob1_s cn52xx;
2078 struct cvmx_l2c_oob1_s cn52xxp1;
2079 struct cvmx_l2c_oob1_s cn56xx;
2080 struct cvmx_l2c_oob1_s cn56xxp1;
2081};
2082
2083union cvmx_l2c_oob2 {
2084 uint64_t u64;
2085 struct cvmx_l2c_oob2_s {
2086#ifdef __BIG_ENDIAN_BITFIELD
2087 uint64_t fadr:27;
2088 uint64_t fsrc:1;
2089 uint64_t reserved_34_35:2;
2090 uint64_t sadr:14;
2091 uint64_t reserved_14_19:6;
2092 uint64_t size:14;
2093#else
2094 uint64_t size:14;
2095 uint64_t reserved_14_19:6;
2096 uint64_t sadr:14;
2097 uint64_t reserved_34_35:2;
2098 uint64_t fsrc:1;
2099 uint64_t fadr:27;
2100#endif
2101 } s;
2102 struct cvmx_l2c_oob2_s cn52xx;
2103 struct cvmx_l2c_oob2_s cn52xxp1;
2104 struct cvmx_l2c_oob2_s cn56xx;
2105 struct cvmx_l2c_oob2_s cn56xxp1;
2106};
2107
2108union cvmx_l2c_oob3 {
2109 uint64_t u64;
2110 struct cvmx_l2c_oob3_s {
2111#ifdef __BIG_ENDIAN_BITFIELD
2112 uint64_t fadr:27;
2113 uint64_t fsrc:1;
2114 uint64_t reserved_34_35:2;
2115 uint64_t sadr:14;
2116 uint64_t reserved_14_19:6;
2117 uint64_t size:14;
2118#else
2119 uint64_t size:14;
2120 uint64_t reserved_14_19:6;
2121 uint64_t sadr:14;
2122 uint64_t reserved_34_35:2;
2123 uint64_t fsrc:1;
2124 uint64_t fadr:27;
2125#endif
2126 } s;
2127 struct cvmx_l2c_oob3_s cn52xx;
2128 struct cvmx_l2c_oob3_s cn52xxp1;
2129 struct cvmx_l2c_oob3_s cn56xx;
2130 struct cvmx_l2c_oob3_s cn56xxp1;
2131};
2132
2133union cvmx_l2c_pfcx {
2134 uint64_t u64;
2135 struct cvmx_l2c_pfcx_s {
2136#ifdef __BIG_ENDIAN_BITFIELD
2137 uint64_t reserved_36_63:28;
2138 uint64_t pfcnt0:36;
2139#else
2140 uint64_t pfcnt0:36;
2141 uint64_t reserved_36_63:28;
2142#endif
2143 } s;
2144 struct cvmx_l2c_pfcx_s cn30xx;
2145 struct cvmx_l2c_pfcx_s cn31xx;
2146 struct cvmx_l2c_pfcx_s cn38xx;
2147 struct cvmx_l2c_pfcx_s cn38xxp2;
2148 struct cvmx_l2c_pfcx_s cn50xx;
2149 struct cvmx_l2c_pfcx_s cn52xx;
2150 struct cvmx_l2c_pfcx_s cn52xxp1;
2151 struct cvmx_l2c_pfcx_s cn56xx;
2152 struct cvmx_l2c_pfcx_s cn56xxp1;
2153 struct cvmx_l2c_pfcx_s cn58xx;
2154 struct cvmx_l2c_pfcx_s cn58xxp1;
2155}; 130};
2156 131
2157union cvmx_l2c_pfctl { 132union cvmx_l2c_pfctl {
2158 uint64_t u64; 133 uint64_t u64;
2159 struct cvmx_l2c_pfctl_s { 134 struct cvmx_l2c_pfctl_s {
2160#ifdef __BIG_ENDIAN_BITFIELD 135 __BITFIELD_FIELD(uint64_t reserved_36_63:28,
2161 uint64_t reserved_36_63:28; 136 __BITFIELD_FIELD(uint64_t cnt3rdclr:1,
2162 uint64_t cnt3rdclr:1; 137 __BITFIELD_FIELD(uint64_t cnt2rdclr:1,
2163 uint64_t cnt2rdclr:1; 138 __BITFIELD_FIELD(uint64_t cnt1rdclr:1,
2164 uint64_t cnt1rdclr:1; 139 __BITFIELD_FIELD(uint64_t cnt0rdclr:1,
2165 uint64_t cnt0rdclr:1; 140 __BITFIELD_FIELD(uint64_t cnt3ena:1,
2166 uint64_t cnt3ena:1; 141 __BITFIELD_FIELD(uint64_t cnt3clr:1,
2167 uint64_t cnt3clr:1; 142 __BITFIELD_FIELD(uint64_t cnt3sel:6,
2168 uint64_t cnt3sel:6; 143 __BITFIELD_FIELD(uint64_t cnt2ena:1,
2169 uint64_t cnt2ena:1; 144 __BITFIELD_FIELD(uint64_t cnt2clr:1,
2170 uint64_t cnt2clr:1; 145 __BITFIELD_FIELD(uint64_t cnt2sel:6,
2171 uint64_t cnt2sel:6; 146 __BITFIELD_FIELD(uint64_t cnt1ena:1,
2172 uint64_t cnt1ena:1; 147 __BITFIELD_FIELD(uint64_t cnt1clr:1,
2173 uint64_t cnt1clr:1; 148 __BITFIELD_FIELD(uint64_t cnt1sel:6,
2174 uint64_t cnt1sel:6; 149 __BITFIELD_FIELD(uint64_t cnt0ena:1,
2175 uint64_t cnt0ena:1; 150 __BITFIELD_FIELD(uint64_t cnt0clr:1,
2176 uint64_t cnt0clr:1; 151 __BITFIELD_FIELD(uint64_t cnt0sel:6,
2177 uint64_t cnt0sel:6; 152 ;)))))))))))))))))
2178#else
2179 uint64_t cnt0sel:6;
2180 uint64_t cnt0clr:1;
2181 uint64_t cnt0ena:1;
2182 uint64_t cnt1sel:6;
2183 uint64_t cnt1clr:1;
2184 uint64_t cnt1ena:1;
2185 uint64_t cnt2sel:6;
2186 uint64_t cnt2clr:1;
2187 uint64_t cnt2ena:1;
2188 uint64_t cnt3sel:6;
2189 uint64_t cnt3clr:1;
2190 uint64_t cnt3ena:1;
2191 uint64_t cnt0rdclr:1;
2192 uint64_t cnt1rdclr:1;
2193 uint64_t cnt2rdclr:1;
2194 uint64_t cnt3rdclr:1;
2195 uint64_t reserved_36_63:28;
2196#endif
2197 } s;
2198 struct cvmx_l2c_pfctl_s cn30xx;
2199 struct cvmx_l2c_pfctl_s cn31xx;
2200 struct cvmx_l2c_pfctl_s cn38xx;
2201 struct cvmx_l2c_pfctl_s cn38xxp2;
2202 struct cvmx_l2c_pfctl_s cn50xx;
2203 struct cvmx_l2c_pfctl_s cn52xx;
2204 struct cvmx_l2c_pfctl_s cn52xxp1;
2205 struct cvmx_l2c_pfctl_s cn56xx;
2206 struct cvmx_l2c_pfctl_s cn56xxp1;
2207 struct cvmx_l2c_pfctl_s cn58xx;
2208 struct cvmx_l2c_pfctl_s cn58xxp1;
2209};
2210
2211union cvmx_l2c_ppgrp {
2212 uint64_t u64;
2213 struct cvmx_l2c_ppgrp_s {
2214#ifdef __BIG_ENDIAN_BITFIELD
2215 uint64_t reserved_24_63:40;
2216 uint64_t pp11grp:2;
2217 uint64_t pp10grp:2;
2218 uint64_t pp9grp:2;
2219 uint64_t pp8grp:2;
2220 uint64_t pp7grp:2;
2221 uint64_t pp6grp:2;
2222 uint64_t pp5grp:2;
2223 uint64_t pp4grp:2;
2224 uint64_t pp3grp:2;
2225 uint64_t pp2grp:2;
2226 uint64_t pp1grp:2;
2227 uint64_t pp0grp:2;
2228#else
2229 uint64_t pp0grp:2;
2230 uint64_t pp1grp:2;
2231 uint64_t pp2grp:2;
2232 uint64_t pp3grp:2;
2233 uint64_t pp4grp:2;
2234 uint64_t pp5grp:2;
2235 uint64_t pp6grp:2;
2236 uint64_t pp7grp:2;
2237 uint64_t pp8grp:2;
2238 uint64_t pp9grp:2;
2239 uint64_t pp10grp:2;
2240 uint64_t pp11grp:2;
2241 uint64_t reserved_24_63:40;
2242#endif
2243 } s;
2244 struct cvmx_l2c_ppgrp_cn52xx {
2245#ifdef __BIG_ENDIAN_BITFIELD
2246 uint64_t reserved_8_63:56;
2247 uint64_t pp3grp:2;
2248 uint64_t pp2grp:2;
2249 uint64_t pp1grp:2;
2250 uint64_t pp0grp:2;
2251#else
2252 uint64_t pp0grp:2;
2253 uint64_t pp1grp:2;
2254 uint64_t pp2grp:2;
2255 uint64_t pp3grp:2;
2256 uint64_t reserved_8_63:56;
2257#endif
2258 } cn52xx;
2259 struct cvmx_l2c_ppgrp_cn52xx cn52xxp1;
2260 struct cvmx_l2c_ppgrp_s cn56xx;
2261 struct cvmx_l2c_ppgrp_s cn56xxp1;
2262};
2263
2264union cvmx_l2c_qos_iobx {
2265 uint64_t u64;
2266 struct cvmx_l2c_qos_iobx_s {
2267#ifdef __BIG_ENDIAN_BITFIELD
2268 uint64_t reserved_7_63:57;
2269 uint64_t dwblvl:3;
2270 uint64_t reserved_3_3:1;
2271 uint64_t lvl:3;
2272#else
2273 uint64_t lvl:3;
2274 uint64_t reserved_3_3:1;
2275 uint64_t dwblvl:3;
2276 uint64_t reserved_7_63:57;
2277#endif
2278 } s;
2279 struct cvmx_l2c_qos_iobx_cn61xx {
2280#ifdef __BIG_ENDIAN_BITFIELD
2281 uint64_t reserved_6_63:58;
2282 uint64_t dwblvl:2;
2283 uint64_t reserved_2_3:2;
2284 uint64_t lvl:2;
2285#else
2286 uint64_t lvl:2;
2287 uint64_t reserved_2_3:2;
2288 uint64_t dwblvl:2;
2289 uint64_t reserved_6_63:58;
2290#endif
2291 } cn61xx;
2292 struct cvmx_l2c_qos_iobx_cn61xx cn63xx;
2293 struct cvmx_l2c_qos_iobx_cn61xx cn63xxp1;
2294 struct cvmx_l2c_qos_iobx_cn61xx cn66xx;
2295 struct cvmx_l2c_qos_iobx_s cn68xx;
2296 struct cvmx_l2c_qos_iobx_s cn68xxp1;
2297 struct cvmx_l2c_qos_iobx_cn61xx cnf71xx;
2298};
2299
2300union cvmx_l2c_qos_ppx {
2301 uint64_t u64;
2302 struct cvmx_l2c_qos_ppx_s {
2303#ifdef __BIG_ENDIAN_BITFIELD
2304 uint64_t reserved_3_63:61;
2305 uint64_t lvl:3;
2306#else
2307 uint64_t lvl:3;
2308 uint64_t reserved_3_63:61;
2309#endif
2310 } s;
2311 struct cvmx_l2c_qos_ppx_cn61xx {
2312#ifdef __BIG_ENDIAN_BITFIELD
2313 uint64_t reserved_2_63:62;
2314 uint64_t lvl:2;
2315#else
2316 uint64_t lvl:2;
2317 uint64_t reserved_2_63:62;
2318#endif
2319 } cn61xx;
2320 struct cvmx_l2c_qos_ppx_cn61xx cn63xx;
2321 struct cvmx_l2c_qos_ppx_cn61xx cn63xxp1;
2322 struct cvmx_l2c_qos_ppx_cn61xx cn66xx;
2323 struct cvmx_l2c_qos_ppx_s cn68xx;
2324 struct cvmx_l2c_qos_ppx_s cn68xxp1;
2325 struct cvmx_l2c_qos_ppx_cn61xx cnf71xx;
2326};
2327
2328union cvmx_l2c_qos_wgt {
2329 uint64_t u64;
2330 struct cvmx_l2c_qos_wgt_s {
2331#ifdef __BIG_ENDIAN_BITFIELD
2332 uint64_t wgt7:8;
2333 uint64_t wgt6:8;
2334 uint64_t wgt5:8;
2335 uint64_t wgt4:8;
2336 uint64_t wgt3:8;
2337 uint64_t wgt2:8;
2338 uint64_t wgt1:8;
2339 uint64_t wgt0:8;
2340#else
2341 uint64_t wgt0:8;
2342 uint64_t wgt1:8;
2343 uint64_t wgt2:8;
2344 uint64_t wgt3:8;
2345 uint64_t wgt4:8;
2346 uint64_t wgt5:8;
2347 uint64_t wgt6:8;
2348 uint64_t wgt7:8;
2349#endif
2350 } s;
2351 struct cvmx_l2c_qos_wgt_cn61xx {
2352#ifdef __BIG_ENDIAN_BITFIELD
2353 uint64_t reserved_32_63:32;
2354 uint64_t wgt3:8;
2355 uint64_t wgt2:8;
2356 uint64_t wgt1:8;
2357 uint64_t wgt0:8;
2358#else
2359 uint64_t wgt0:8;
2360 uint64_t wgt1:8;
2361 uint64_t wgt2:8;
2362 uint64_t wgt3:8;
2363 uint64_t reserved_32_63:32;
2364#endif
2365 } cn61xx;
2366 struct cvmx_l2c_qos_wgt_cn61xx cn63xx;
2367 struct cvmx_l2c_qos_wgt_cn61xx cn63xxp1;
2368 struct cvmx_l2c_qos_wgt_cn61xx cn66xx;
2369 struct cvmx_l2c_qos_wgt_s cn68xx;
2370 struct cvmx_l2c_qos_wgt_s cn68xxp1;
2371 struct cvmx_l2c_qos_wgt_cn61xx cnf71xx;
2372};
2373
2374union cvmx_l2c_rscx_pfc {
2375 uint64_t u64;
2376 struct cvmx_l2c_rscx_pfc_s {
2377#ifdef __BIG_ENDIAN_BITFIELD
2378 uint64_t count:64;
2379#else
2380 uint64_t count:64;
2381#endif
2382 } s;
2383 struct cvmx_l2c_rscx_pfc_s cn61xx;
2384 struct cvmx_l2c_rscx_pfc_s cn63xx;
2385 struct cvmx_l2c_rscx_pfc_s cn63xxp1;
2386 struct cvmx_l2c_rscx_pfc_s cn66xx;
2387 struct cvmx_l2c_rscx_pfc_s cn68xx;
2388 struct cvmx_l2c_rscx_pfc_s cn68xxp1;
2389 struct cvmx_l2c_rscx_pfc_s cnf71xx;
2390};
2391
2392union cvmx_l2c_rsdx_pfc {
2393 uint64_t u64;
2394 struct cvmx_l2c_rsdx_pfc_s {
2395#ifdef __BIG_ENDIAN_BITFIELD
2396 uint64_t count:64;
2397#else
2398 uint64_t count:64;
2399#endif
2400 } s;
2401 struct cvmx_l2c_rsdx_pfc_s cn61xx;
2402 struct cvmx_l2c_rsdx_pfc_s cn63xx;
2403 struct cvmx_l2c_rsdx_pfc_s cn63xxp1;
2404 struct cvmx_l2c_rsdx_pfc_s cn66xx;
2405 struct cvmx_l2c_rsdx_pfc_s cn68xx;
2406 struct cvmx_l2c_rsdx_pfc_s cn68xxp1;
2407 struct cvmx_l2c_rsdx_pfc_s cnf71xx;
2408};
2409
2410union cvmx_l2c_spar0 {
2411 uint64_t u64;
2412 struct cvmx_l2c_spar0_s {
2413#ifdef __BIG_ENDIAN_BITFIELD
2414 uint64_t reserved_32_63:32;
2415 uint64_t umsk3:8;
2416 uint64_t umsk2:8;
2417 uint64_t umsk1:8;
2418 uint64_t umsk0:8;
2419#else
2420 uint64_t umsk0:8;
2421 uint64_t umsk1:8;
2422 uint64_t umsk2:8;
2423 uint64_t umsk3:8;
2424 uint64_t reserved_32_63:32;
2425#endif
2426 } s;
2427 struct cvmx_l2c_spar0_cn30xx {
2428#ifdef __BIG_ENDIAN_BITFIELD
2429 uint64_t reserved_4_63:60;
2430 uint64_t umsk0:4;
2431#else
2432 uint64_t umsk0:4;
2433 uint64_t reserved_4_63:60;
2434#endif
2435 } cn30xx;
2436 struct cvmx_l2c_spar0_cn31xx {
2437#ifdef __BIG_ENDIAN_BITFIELD
2438 uint64_t reserved_12_63:52;
2439 uint64_t umsk1:4;
2440 uint64_t reserved_4_7:4;
2441 uint64_t umsk0:4;
2442#else
2443 uint64_t umsk0:4;
2444 uint64_t reserved_4_7:4;
2445 uint64_t umsk1:4;
2446 uint64_t reserved_12_63:52;
2447#endif
2448 } cn31xx;
2449 struct cvmx_l2c_spar0_s cn38xx;
2450 struct cvmx_l2c_spar0_s cn38xxp2;
2451 struct cvmx_l2c_spar0_cn50xx {
2452#ifdef __BIG_ENDIAN_BITFIELD
2453 uint64_t reserved_16_63:48;
2454 uint64_t umsk1:8;
2455 uint64_t umsk0:8;
2456#else
2457 uint64_t umsk0:8;
2458 uint64_t umsk1:8;
2459 uint64_t reserved_16_63:48;
2460#endif
2461 } cn50xx;
2462 struct cvmx_l2c_spar0_s cn52xx;
2463 struct cvmx_l2c_spar0_s cn52xxp1;
2464 struct cvmx_l2c_spar0_s cn56xx;
2465 struct cvmx_l2c_spar0_s cn56xxp1;
2466 struct cvmx_l2c_spar0_s cn58xx;
2467 struct cvmx_l2c_spar0_s cn58xxp1;
2468};
2469
2470union cvmx_l2c_spar1 {
2471 uint64_t u64;
2472 struct cvmx_l2c_spar1_s {
2473#ifdef __BIG_ENDIAN_BITFIELD
2474 uint64_t reserved_32_63:32;
2475 uint64_t umsk7:8;
2476 uint64_t umsk6:8;
2477 uint64_t umsk5:8;
2478 uint64_t umsk4:8;
2479#else
2480 uint64_t umsk4:8;
2481 uint64_t umsk5:8;
2482 uint64_t umsk6:8;
2483 uint64_t umsk7:8;
2484 uint64_t reserved_32_63:32;
2485#endif
2486 } s; 153 } s;
2487 struct cvmx_l2c_spar1_s cn38xx;
2488 struct cvmx_l2c_spar1_s cn38xxp2;
2489 struct cvmx_l2c_spar1_s cn56xx;
2490 struct cvmx_l2c_spar1_s cn56xxp1;
2491 struct cvmx_l2c_spar1_s cn58xx;
2492 struct cvmx_l2c_spar1_s cn58xxp1;
2493};
2494
2495union cvmx_l2c_spar2 {
2496 uint64_t u64;
2497 struct cvmx_l2c_spar2_s {
2498#ifdef __BIG_ENDIAN_BITFIELD
2499 uint64_t reserved_32_63:32;
2500 uint64_t umsk11:8;
2501 uint64_t umsk10:8;
2502 uint64_t umsk9:8;
2503 uint64_t umsk8:8;
2504#else
2505 uint64_t umsk8:8;
2506 uint64_t umsk9:8;
2507 uint64_t umsk10:8;
2508 uint64_t umsk11:8;
2509 uint64_t reserved_32_63:32;
2510#endif
2511 } s;
2512 struct cvmx_l2c_spar2_s cn38xx;
2513 struct cvmx_l2c_spar2_s cn38xxp2;
2514 struct cvmx_l2c_spar2_s cn56xx;
2515 struct cvmx_l2c_spar2_s cn56xxp1;
2516 struct cvmx_l2c_spar2_s cn58xx;
2517 struct cvmx_l2c_spar2_s cn58xxp1;
2518};
2519
2520union cvmx_l2c_spar3 {
2521 uint64_t u64;
2522 struct cvmx_l2c_spar3_s {
2523#ifdef __BIG_ENDIAN_BITFIELD
2524 uint64_t reserved_32_63:32;
2525 uint64_t umsk15:8;
2526 uint64_t umsk14:8;
2527 uint64_t umsk13:8;
2528 uint64_t umsk12:8;
2529#else
2530 uint64_t umsk12:8;
2531 uint64_t umsk13:8;
2532 uint64_t umsk14:8;
2533 uint64_t umsk15:8;
2534 uint64_t reserved_32_63:32;
2535#endif
2536 } s;
2537 struct cvmx_l2c_spar3_s cn38xx;
2538 struct cvmx_l2c_spar3_s cn38xxp2;
2539 struct cvmx_l2c_spar3_s cn58xx;
2540 struct cvmx_l2c_spar3_s cn58xxp1;
2541};
2542
2543union cvmx_l2c_spar4 {
2544 uint64_t u64;
2545 struct cvmx_l2c_spar4_s {
2546#ifdef __BIG_ENDIAN_BITFIELD
2547 uint64_t reserved_8_63:56;
2548 uint64_t umskiob:8;
2549#else
2550 uint64_t umskiob:8;
2551 uint64_t reserved_8_63:56;
2552#endif
2553 } s;
2554 struct cvmx_l2c_spar4_cn30xx {
2555#ifdef __BIG_ENDIAN_BITFIELD
2556 uint64_t reserved_4_63:60;
2557 uint64_t umskiob:4;
2558#else
2559 uint64_t umskiob:4;
2560 uint64_t reserved_4_63:60;
2561#endif
2562 } cn30xx;
2563 struct cvmx_l2c_spar4_cn30xx cn31xx;
2564 struct cvmx_l2c_spar4_s cn38xx;
2565 struct cvmx_l2c_spar4_s cn38xxp2;
2566 struct cvmx_l2c_spar4_s cn50xx;
2567 struct cvmx_l2c_spar4_s cn52xx;
2568 struct cvmx_l2c_spar4_s cn52xxp1;
2569 struct cvmx_l2c_spar4_s cn56xx;
2570 struct cvmx_l2c_spar4_s cn56xxp1;
2571 struct cvmx_l2c_spar4_s cn58xx;
2572 struct cvmx_l2c_spar4_s cn58xxp1;
2573};
2574
2575union cvmx_l2c_tadx_ecc0 {
2576 uint64_t u64;
2577 struct cvmx_l2c_tadx_ecc0_s {
2578#ifdef __BIG_ENDIAN_BITFIELD
2579 uint64_t reserved_58_63:6;
2580 uint64_t ow3ecc:10;
2581 uint64_t reserved_42_47:6;
2582 uint64_t ow2ecc:10;
2583 uint64_t reserved_26_31:6;
2584 uint64_t ow1ecc:10;
2585 uint64_t reserved_10_15:6;
2586 uint64_t ow0ecc:10;
2587#else
2588 uint64_t ow0ecc:10;
2589 uint64_t reserved_10_15:6;
2590 uint64_t ow1ecc:10;
2591 uint64_t reserved_26_31:6;
2592 uint64_t ow2ecc:10;
2593 uint64_t reserved_42_47:6;
2594 uint64_t ow3ecc:10;
2595 uint64_t reserved_58_63:6;
2596#endif
2597 } s;
2598 struct cvmx_l2c_tadx_ecc0_s cn61xx;
2599 struct cvmx_l2c_tadx_ecc0_s cn63xx;
2600 struct cvmx_l2c_tadx_ecc0_s cn63xxp1;
2601 struct cvmx_l2c_tadx_ecc0_s cn66xx;
2602 struct cvmx_l2c_tadx_ecc0_s cn68xx;
2603 struct cvmx_l2c_tadx_ecc0_s cn68xxp1;
2604 struct cvmx_l2c_tadx_ecc0_s cnf71xx;
2605};
2606
2607union cvmx_l2c_tadx_ecc1 {
2608 uint64_t u64;
2609 struct cvmx_l2c_tadx_ecc1_s {
2610#ifdef __BIG_ENDIAN_BITFIELD
2611 uint64_t reserved_58_63:6;
2612 uint64_t ow7ecc:10;
2613 uint64_t reserved_42_47:6;
2614 uint64_t ow6ecc:10;
2615 uint64_t reserved_26_31:6;
2616 uint64_t ow5ecc:10;
2617 uint64_t reserved_10_15:6;
2618 uint64_t ow4ecc:10;
2619#else
2620 uint64_t ow4ecc:10;
2621 uint64_t reserved_10_15:6;
2622 uint64_t ow5ecc:10;
2623 uint64_t reserved_26_31:6;
2624 uint64_t ow6ecc:10;
2625 uint64_t reserved_42_47:6;
2626 uint64_t ow7ecc:10;
2627 uint64_t reserved_58_63:6;
2628#endif
2629 } s;
2630 struct cvmx_l2c_tadx_ecc1_s cn61xx;
2631 struct cvmx_l2c_tadx_ecc1_s cn63xx;
2632 struct cvmx_l2c_tadx_ecc1_s cn63xxp1;
2633 struct cvmx_l2c_tadx_ecc1_s cn66xx;
2634 struct cvmx_l2c_tadx_ecc1_s cn68xx;
2635 struct cvmx_l2c_tadx_ecc1_s cn68xxp1;
2636 struct cvmx_l2c_tadx_ecc1_s cnf71xx;
2637};
2638
2639union cvmx_l2c_tadx_ien {
2640 uint64_t u64;
2641 struct cvmx_l2c_tadx_ien_s {
2642#ifdef __BIG_ENDIAN_BITFIELD
2643 uint64_t reserved_9_63:55;
2644 uint64_t wrdislmc:1;
2645 uint64_t rddislmc:1;
2646 uint64_t noway:1;
2647 uint64_t vbfdbe:1;
2648 uint64_t vbfsbe:1;
2649 uint64_t tagdbe:1;
2650 uint64_t tagsbe:1;
2651 uint64_t l2ddbe:1;
2652 uint64_t l2dsbe:1;
2653#else
2654 uint64_t l2dsbe:1;
2655 uint64_t l2ddbe:1;
2656 uint64_t tagsbe:1;
2657 uint64_t tagdbe:1;
2658 uint64_t vbfsbe:1;
2659 uint64_t vbfdbe:1;
2660 uint64_t noway:1;
2661 uint64_t rddislmc:1;
2662 uint64_t wrdislmc:1;
2663 uint64_t reserved_9_63:55;
2664#endif
2665 } s;
2666 struct cvmx_l2c_tadx_ien_s cn61xx;
2667 struct cvmx_l2c_tadx_ien_s cn63xx;
2668 struct cvmx_l2c_tadx_ien_cn63xxp1 {
2669#ifdef __BIG_ENDIAN_BITFIELD
2670 uint64_t reserved_7_63:57;
2671 uint64_t noway:1;
2672 uint64_t vbfdbe:1;
2673 uint64_t vbfsbe:1;
2674 uint64_t tagdbe:1;
2675 uint64_t tagsbe:1;
2676 uint64_t l2ddbe:1;
2677 uint64_t l2dsbe:1;
2678#else
2679 uint64_t l2dsbe:1;
2680 uint64_t l2ddbe:1;
2681 uint64_t tagsbe:1;
2682 uint64_t tagdbe:1;
2683 uint64_t vbfsbe:1;
2684 uint64_t vbfdbe:1;
2685 uint64_t noway:1;
2686 uint64_t reserved_7_63:57;
2687#endif
2688 } cn63xxp1;
2689 struct cvmx_l2c_tadx_ien_s cn66xx;
2690 struct cvmx_l2c_tadx_ien_s cn68xx;
2691 struct cvmx_l2c_tadx_ien_s cn68xxp1;
2692 struct cvmx_l2c_tadx_ien_s cnf71xx;
2693};
2694
2695union cvmx_l2c_tadx_int {
2696 uint64_t u64;
2697 struct cvmx_l2c_tadx_int_s {
2698#ifdef __BIG_ENDIAN_BITFIELD
2699 uint64_t reserved_9_63:55;
2700 uint64_t wrdislmc:1;
2701 uint64_t rddislmc:1;
2702 uint64_t noway:1;
2703 uint64_t vbfdbe:1;
2704 uint64_t vbfsbe:1;
2705 uint64_t tagdbe:1;
2706 uint64_t tagsbe:1;
2707 uint64_t l2ddbe:1;
2708 uint64_t l2dsbe:1;
2709#else
2710 uint64_t l2dsbe:1;
2711 uint64_t l2ddbe:1;
2712 uint64_t tagsbe:1;
2713 uint64_t tagdbe:1;
2714 uint64_t vbfsbe:1;
2715 uint64_t vbfdbe:1;
2716 uint64_t noway:1;
2717 uint64_t rddislmc:1;
2718 uint64_t wrdislmc:1;
2719 uint64_t reserved_9_63:55;
2720#endif
2721 } s;
2722 struct cvmx_l2c_tadx_int_s cn61xx;
2723 struct cvmx_l2c_tadx_int_s cn63xx;
2724 struct cvmx_l2c_tadx_int_s cn66xx;
2725 struct cvmx_l2c_tadx_int_s cn68xx;
2726 struct cvmx_l2c_tadx_int_s cn68xxp1;
2727 struct cvmx_l2c_tadx_int_s cnf71xx;
2728};
2729
2730union cvmx_l2c_tadx_pfc0 {
2731 uint64_t u64;
2732 struct cvmx_l2c_tadx_pfc0_s {
2733#ifdef __BIG_ENDIAN_BITFIELD
2734 uint64_t count:64;
2735#else
2736 uint64_t count:64;
2737#endif
2738 } s;
2739 struct cvmx_l2c_tadx_pfc0_s cn61xx;
2740 struct cvmx_l2c_tadx_pfc0_s cn63xx;
2741 struct cvmx_l2c_tadx_pfc0_s cn63xxp1;
2742 struct cvmx_l2c_tadx_pfc0_s cn66xx;
2743 struct cvmx_l2c_tadx_pfc0_s cn68xx;
2744 struct cvmx_l2c_tadx_pfc0_s cn68xxp1;
2745 struct cvmx_l2c_tadx_pfc0_s cnf71xx;
2746};
2747
2748union cvmx_l2c_tadx_pfc1 {
2749 uint64_t u64;
2750 struct cvmx_l2c_tadx_pfc1_s {
2751#ifdef __BIG_ENDIAN_BITFIELD
2752 uint64_t count:64;
2753#else
2754 uint64_t count:64;
2755#endif
2756 } s;
2757 struct cvmx_l2c_tadx_pfc1_s cn61xx;
2758 struct cvmx_l2c_tadx_pfc1_s cn63xx;
2759 struct cvmx_l2c_tadx_pfc1_s cn63xxp1;
2760 struct cvmx_l2c_tadx_pfc1_s cn66xx;
2761 struct cvmx_l2c_tadx_pfc1_s cn68xx;
2762 struct cvmx_l2c_tadx_pfc1_s cn68xxp1;
2763 struct cvmx_l2c_tadx_pfc1_s cnf71xx;
2764};
2765
2766union cvmx_l2c_tadx_pfc2 {
2767 uint64_t u64;
2768 struct cvmx_l2c_tadx_pfc2_s {
2769#ifdef __BIG_ENDIAN_BITFIELD
2770 uint64_t count:64;
2771#else
2772 uint64_t count:64;
2773#endif
2774 } s;
2775 struct cvmx_l2c_tadx_pfc2_s cn61xx;
2776 struct cvmx_l2c_tadx_pfc2_s cn63xx;
2777 struct cvmx_l2c_tadx_pfc2_s cn63xxp1;
2778 struct cvmx_l2c_tadx_pfc2_s cn66xx;
2779 struct cvmx_l2c_tadx_pfc2_s cn68xx;
2780 struct cvmx_l2c_tadx_pfc2_s cn68xxp1;
2781 struct cvmx_l2c_tadx_pfc2_s cnf71xx;
2782};
2783
2784union cvmx_l2c_tadx_pfc3 {
2785 uint64_t u64;
2786 struct cvmx_l2c_tadx_pfc3_s {
2787#ifdef __BIG_ENDIAN_BITFIELD
2788 uint64_t count:64;
2789#else
2790 uint64_t count:64;
2791#endif
2792 } s;
2793 struct cvmx_l2c_tadx_pfc3_s cn61xx;
2794 struct cvmx_l2c_tadx_pfc3_s cn63xx;
2795 struct cvmx_l2c_tadx_pfc3_s cn63xxp1;
2796 struct cvmx_l2c_tadx_pfc3_s cn66xx;
2797 struct cvmx_l2c_tadx_pfc3_s cn68xx;
2798 struct cvmx_l2c_tadx_pfc3_s cn68xxp1;
2799 struct cvmx_l2c_tadx_pfc3_s cnf71xx;
2800}; 154};
2801 155
2802union cvmx_l2c_tadx_prf { 156union cvmx_l2c_tadx_prf {
2803 uint64_t u64; 157 uint64_t u64;
2804 struct cvmx_l2c_tadx_prf_s { 158 struct cvmx_l2c_tadx_prf_s {
2805#ifdef __BIG_ENDIAN_BITFIELD 159 __BITFIELD_FIELD(uint64_t reserved_32_63:32,
2806 uint64_t reserved_32_63:32; 160 __BITFIELD_FIELD(uint64_t cnt3sel:8,
2807 uint64_t cnt3sel:8; 161 __BITFIELD_FIELD(uint64_t cnt2sel:8,
2808 uint64_t cnt2sel:8; 162 __BITFIELD_FIELD(uint64_t cnt1sel:8,
2809 uint64_t cnt1sel:8; 163 __BITFIELD_FIELD(uint64_t cnt0sel:8,
2810 uint64_t cnt0sel:8; 164 ;)))))
2811#else
2812 uint64_t cnt0sel:8;
2813 uint64_t cnt1sel:8;
2814 uint64_t cnt2sel:8;
2815 uint64_t cnt3sel:8;
2816 uint64_t reserved_32_63:32;
2817#endif
2818 } s; 165 } s;
2819 struct cvmx_l2c_tadx_prf_s cn61xx;
2820 struct cvmx_l2c_tadx_prf_s cn63xx;
2821 struct cvmx_l2c_tadx_prf_s cn63xxp1;
2822 struct cvmx_l2c_tadx_prf_s cn66xx;
2823 struct cvmx_l2c_tadx_prf_s cn68xx;
2824 struct cvmx_l2c_tadx_prf_s cn68xxp1;
2825 struct cvmx_l2c_tadx_prf_s cnf71xx;
2826}; 166};
2827 167
2828union cvmx_l2c_tadx_tag { 168union cvmx_l2c_tadx_tag {
2829 uint64_t u64; 169 uint64_t u64;
2830 struct cvmx_l2c_tadx_tag_s { 170 struct cvmx_l2c_tadx_tag_s {
2831#ifdef __BIG_ENDIAN_BITFIELD 171 __BITFIELD_FIELD(uint64_t reserved_46_63:18,
2832 uint64_t reserved_46_63:18; 172 __BITFIELD_FIELD(uint64_t ecc:6,
2833 uint64_t ecc:6; 173 __BITFIELD_FIELD(uint64_t reserved_36_39:4,
2834 uint64_t reserved_36_39:4; 174 __BITFIELD_FIELD(uint64_t tag:19,
2835 uint64_t tag:19; 175 __BITFIELD_FIELD(uint64_t reserved_4_16:13,
2836 uint64_t reserved_4_16:13; 176 __BITFIELD_FIELD(uint64_t use:1,
2837 uint64_t use:1; 177 __BITFIELD_FIELD(uint64_t valid:1,
2838 uint64_t valid:1; 178 __BITFIELD_FIELD(uint64_t dirty:1,
2839 uint64_t dirty:1; 179 __BITFIELD_FIELD(uint64_t lock:1,
2840 uint64_t lock:1; 180 ;)))))))))
2841#else
2842 uint64_t lock:1;
2843 uint64_t dirty:1;
2844 uint64_t valid:1;
2845 uint64_t use:1;
2846 uint64_t reserved_4_16:13;
2847 uint64_t tag:19;
2848 uint64_t reserved_36_39:4;
2849 uint64_t ecc:6;
2850 uint64_t reserved_46_63:18;
2851#endif
2852 } s;
2853 struct cvmx_l2c_tadx_tag_s cn61xx;
2854 struct cvmx_l2c_tadx_tag_s cn63xx;
2855 struct cvmx_l2c_tadx_tag_s cn63xxp1;
2856 struct cvmx_l2c_tadx_tag_s cn66xx;
2857 struct cvmx_l2c_tadx_tag_s cn68xx;
2858 struct cvmx_l2c_tadx_tag_s cn68xxp1;
2859 struct cvmx_l2c_tadx_tag_s cnf71xx;
2860};
2861
2862union cvmx_l2c_ver_id {
2863 uint64_t u64;
2864 struct cvmx_l2c_ver_id_s {
2865#ifdef __BIG_ENDIAN_BITFIELD
2866 uint64_t mask:64;
2867#else
2868 uint64_t mask:64;
2869#endif
2870 } s;
2871 struct cvmx_l2c_ver_id_s cn61xx;
2872 struct cvmx_l2c_ver_id_s cn63xx;
2873 struct cvmx_l2c_ver_id_s cn63xxp1;
2874 struct cvmx_l2c_ver_id_s cn66xx;
2875 struct cvmx_l2c_ver_id_s cn68xx;
2876 struct cvmx_l2c_ver_id_s cn68xxp1;
2877 struct cvmx_l2c_ver_id_s cnf71xx;
2878};
2879
2880union cvmx_l2c_ver_iob {
2881 uint64_t u64;
2882 struct cvmx_l2c_ver_iob_s {
2883#ifdef __BIG_ENDIAN_BITFIELD
2884 uint64_t reserved_2_63:62;
2885 uint64_t mask:2;
2886#else
2887 uint64_t mask:2;
2888 uint64_t reserved_2_63:62;
2889#endif
2890 } s;
2891 struct cvmx_l2c_ver_iob_cn61xx {
2892#ifdef __BIG_ENDIAN_BITFIELD
2893 uint64_t reserved_1_63:63;
2894 uint64_t mask:1;
2895#else
2896 uint64_t mask:1;
2897 uint64_t reserved_1_63:63;
2898#endif
2899 } cn61xx;
2900 struct cvmx_l2c_ver_iob_cn61xx cn63xx;
2901 struct cvmx_l2c_ver_iob_cn61xx cn63xxp1;
2902 struct cvmx_l2c_ver_iob_cn61xx cn66xx;
2903 struct cvmx_l2c_ver_iob_s cn68xx;
2904 struct cvmx_l2c_ver_iob_s cn68xxp1;
2905 struct cvmx_l2c_ver_iob_cn61xx cnf71xx;
2906};
2907
2908union cvmx_l2c_ver_msc {
2909 uint64_t u64;
2910 struct cvmx_l2c_ver_msc_s {
2911#ifdef __BIG_ENDIAN_BITFIELD
2912 uint64_t reserved_2_63:62;
2913 uint64_t invl2:1;
2914 uint64_t dwb:1;
2915#else
2916 uint64_t dwb:1;
2917 uint64_t invl2:1;
2918 uint64_t reserved_2_63:62;
2919#endif
2920 } s; 181 } s;
2921 struct cvmx_l2c_ver_msc_s cn61xx;
2922 struct cvmx_l2c_ver_msc_s cn63xx;
2923 struct cvmx_l2c_ver_msc_s cn66xx;
2924 struct cvmx_l2c_ver_msc_s cn68xx;
2925 struct cvmx_l2c_ver_msc_s cn68xxp1;
2926 struct cvmx_l2c_ver_msc_s cnf71xx;
2927}; 182};
2928 183
2929union cvmx_l2c_ver_pp { 184union cvmx_l2c_lckbase {
2930 uint64_t u64;
2931 struct cvmx_l2c_ver_pp_s {
2932#ifdef __BIG_ENDIAN_BITFIELD
2933 uint64_t reserved_32_63:32;
2934 uint64_t mask:32;
2935#else
2936 uint64_t mask:32;
2937 uint64_t reserved_32_63:32;
2938#endif
2939 } s;
2940 struct cvmx_l2c_ver_pp_cn61xx {
2941#ifdef __BIG_ENDIAN_BITFIELD
2942 uint64_t reserved_4_63:60;
2943 uint64_t mask:4;
2944#else
2945 uint64_t mask:4;
2946 uint64_t reserved_4_63:60;
2947#endif
2948 } cn61xx;
2949 struct cvmx_l2c_ver_pp_cn63xx {
2950#ifdef __BIG_ENDIAN_BITFIELD
2951 uint64_t reserved_6_63:58;
2952 uint64_t mask:6;
2953#else
2954 uint64_t mask:6;
2955 uint64_t reserved_6_63:58;
2956#endif
2957 } cn63xx;
2958 struct cvmx_l2c_ver_pp_cn63xx cn63xxp1;
2959 struct cvmx_l2c_ver_pp_cn66xx {
2960#ifdef __BIG_ENDIAN_BITFIELD
2961 uint64_t reserved_10_63:54;
2962 uint64_t mask:10;
2963#else
2964 uint64_t mask:10;
2965 uint64_t reserved_10_63:54;
2966#endif
2967 } cn66xx;
2968 struct cvmx_l2c_ver_pp_s cn68xx;
2969 struct cvmx_l2c_ver_pp_s cn68xxp1;
2970 struct cvmx_l2c_ver_pp_cn61xx cnf71xx;
2971};
2972
2973union cvmx_l2c_virtid_iobx {
2974 uint64_t u64;
2975 struct cvmx_l2c_virtid_iobx_s {
2976#ifdef __BIG_ENDIAN_BITFIELD
2977 uint64_t reserved_14_63:50;
2978 uint64_t dwbid:6;
2979 uint64_t reserved_6_7:2;
2980 uint64_t id:6;
2981#else
2982 uint64_t id:6;
2983 uint64_t reserved_6_7:2;
2984 uint64_t dwbid:6;
2985 uint64_t reserved_14_63:50;
2986#endif
2987 } s;
2988 struct cvmx_l2c_virtid_iobx_s cn61xx;
2989 struct cvmx_l2c_virtid_iobx_s cn63xx;
2990 struct cvmx_l2c_virtid_iobx_s cn63xxp1;
2991 struct cvmx_l2c_virtid_iobx_s cn66xx;
2992 struct cvmx_l2c_virtid_iobx_s cn68xx;
2993 struct cvmx_l2c_virtid_iobx_s cn68xxp1;
2994 struct cvmx_l2c_virtid_iobx_s cnf71xx;
2995};
2996
2997union cvmx_l2c_virtid_ppx {
2998 uint64_t u64;
2999 struct cvmx_l2c_virtid_ppx_s {
3000#ifdef __BIG_ENDIAN_BITFIELD
3001 uint64_t reserved_6_63:58;
3002 uint64_t id:6;
3003#else
3004 uint64_t id:6;
3005 uint64_t reserved_6_63:58;
3006#endif
3007 } s;
3008 struct cvmx_l2c_virtid_ppx_s cn61xx;
3009 struct cvmx_l2c_virtid_ppx_s cn63xx;
3010 struct cvmx_l2c_virtid_ppx_s cn63xxp1;
3011 struct cvmx_l2c_virtid_ppx_s cn66xx;
3012 struct cvmx_l2c_virtid_ppx_s cn68xx;
3013 struct cvmx_l2c_virtid_ppx_s cn68xxp1;
3014 struct cvmx_l2c_virtid_ppx_s cnf71xx;
3015};
3016
3017union cvmx_l2c_vrt_ctl {
3018 uint64_t u64;
3019 struct cvmx_l2c_vrt_ctl_s {
3020#ifdef __BIG_ENDIAN_BITFIELD
3021 uint64_t reserved_9_63:55;
3022 uint64_t ooberr:1;
3023 uint64_t reserved_7_7:1;
3024 uint64_t memsz:3;
3025 uint64_t numid:3;
3026 uint64_t enable:1;
3027#else
3028 uint64_t enable:1;
3029 uint64_t numid:3;
3030 uint64_t memsz:3;
3031 uint64_t reserved_7_7:1;
3032 uint64_t ooberr:1;
3033 uint64_t reserved_9_63:55;
3034#endif
3035 } s;
3036 struct cvmx_l2c_vrt_ctl_s cn61xx;
3037 struct cvmx_l2c_vrt_ctl_s cn63xx;
3038 struct cvmx_l2c_vrt_ctl_s cn63xxp1;
3039 struct cvmx_l2c_vrt_ctl_s cn66xx;
3040 struct cvmx_l2c_vrt_ctl_s cn68xx;
3041 struct cvmx_l2c_vrt_ctl_s cn68xxp1;
3042 struct cvmx_l2c_vrt_ctl_s cnf71xx;
3043};
3044
3045union cvmx_l2c_vrt_memx {
3046 uint64_t u64;
3047 struct cvmx_l2c_vrt_memx_s {
3048#ifdef __BIG_ENDIAN_BITFIELD
3049 uint64_t reserved_36_63:28;
3050 uint64_t parity:4;
3051 uint64_t data:32;
3052#else
3053 uint64_t data:32;
3054 uint64_t parity:4;
3055 uint64_t reserved_36_63:28;
3056#endif
3057 } s;
3058 struct cvmx_l2c_vrt_memx_s cn61xx;
3059 struct cvmx_l2c_vrt_memx_s cn63xx;
3060 struct cvmx_l2c_vrt_memx_s cn63xxp1;
3061 struct cvmx_l2c_vrt_memx_s cn66xx;
3062 struct cvmx_l2c_vrt_memx_s cn68xx;
3063 struct cvmx_l2c_vrt_memx_s cn68xxp1;
3064 struct cvmx_l2c_vrt_memx_s cnf71xx;
3065};
3066
3067union cvmx_l2c_wpar_iobx {
3068 uint64_t u64;
3069 struct cvmx_l2c_wpar_iobx_s {
3070#ifdef __BIG_ENDIAN_BITFIELD
3071 uint64_t reserved_16_63:48;
3072 uint64_t mask:16;
3073#else
3074 uint64_t mask:16;
3075 uint64_t reserved_16_63:48;
3076#endif
3077 } s;
3078 struct cvmx_l2c_wpar_iobx_s cn61xx;
3079 struct cvmx_l2c_wpar_iobx_s cn63xx;
3080 struct cvmx_l2c_wpar_iobx_s cn63xxp1;
3081 struct cvmx_l2c_wpar_iobx_s cn66xx;
3082 struct cvmx_l2c_wpar_iobx_s cn68xx;
3083 struct cvmx_l2c_wpar_iobx_s cn68xxp1;
3084 struct cvmx_l2c_wpar_iobx_s cnf71xx;
3085};
3086
3087union cvmx_l2c_wpar_ppx {
3088 uint64_t u64;
3089 struct cvmx_l2c_wpar_ppx_s {
3090#ifdef __BIG_ENDIAN_BITFIELD
3091 uint64_t reserved_16_63:48;
3092 uint64_t mask:16;
3093#else
3094 uint64_t mask:16;
3095 uint64_t reserved_16_63:48;
3096#endif
3097 } s;
3098 struct cvmx_l2c_wpar_ppx_s cn61xx;
3099 struct cvmx_l2c_wpar_ppx_s cn63xx;
3100 struct cvmx_l2c_wpar_ppx_s cn63xxp1;
3101 struct cvmx_l2c_wpar_ppx_s cn66xx;
3102 struct cvmx_l2c_wpar_ppx_s cn68xx;
3103 struct cvmx_l2c_wpar_ppx_s cn68xxp1;
3104 struct cvmx_l2c_wpar_ppx_s cnf71xx;
3105};
3106
3107union cvmx_l2c_xmcx_pfc {
3108 uint64_t u64;
3109 struct cvmx_l2c_xmcx_pfc_s {
3110#ifdef __BIG_ENDIAN_BITFIELD
3111 uint64_t count:64;
3112#else
3113 uint64_t count:64;
3114#endif
3115 } s;
3116 struct cvmx_l2c_xmcx_pfc_s cn61xx;
3117 struct cvmx_l2c_xmcx_pfc_s cn63xx;
3118 struct cvmx_l2c_xmcx_pfc_s cn63xxp1;
3119 struct cvmx_l2c_xmcx_pfc_s cn66xx;
3120 struct cvmx_l2c_xmcx_pfc_s cn68xx;
3121 struct cvmx_l2c_xmcx_pfc_s cn68xxp1;
3122 struct cvmx_l2c_xmcx_pfc_s cnf71xx;
3123};
3124
3125union cvmx_l2c_xmc_cmd {
3126 uint64_t u64; 185 uint64_t u64;
3127 struct cvmx_l2c_xmc_cmd_s { 186 struct cvmx_l2c_lckbase_s {
3128#ifdef __BIG_ENDIAN_BITFIELD 187 __BITFIELD_FIELD(uint64_t reserved_31_63:33,
3129 uint64_t inuse:1; 188 __BITFIELD_FIELD(uint64_t lck_base:27,
3130 uint64_t cmd:6; 189 __BITFIELD_FIELD(uint64_t reserved_1_3:3,
3131 uint64_t reserved_38_56:19; 190 __BITFIELD_FIELD(uint64_t lck_ena:1,
3132 uint64_t addr:38; 191 ;))))
3133#else
3134 uint64_t addr:38;
3135 uint64_t reserved_38_56:19;
3136 uint64_t cmd:6;
3137 uint64_t inuse:1;
3138#endif
3139 } s; 192 } s;
3140 struct cvmx_l2c_xmc_cmd_s cn61xx;
3141 struct cvmx_l2c_xmc_cmd_s cn63xx;
3142 struct cvmx_l2c_xmc_cmd_s cn63xxp1;
3143 struct cvmx_l2c_xmc_cmd_s cn66xx;
3144 struct cvmx_l2c_xmc_cmd_s cn68xx;
3145 struct cvmx_l2c_xmc_cmd_s cn68xxp1;
3146 struct cvmx_l2c_xmc_cmd_s cnf71xx;
3147}; 193};
3148 194
3149union cvmx_l2c_xmdx_pfc { 195union cvmx_l2c_lckoff {
3150 uint64_t u64; 196 uint64_t u64;
3151 struct cvmx_l2c_xmdx_pfc_s { 197 struct cvmx_l2c_lckoff_s {
3152#ifdef __BIG_ENDIAN_BITFIELD 198 __BITFIELD_FIELD(uint64_t reserved_10_63:54,
3153 uint64_t count:64; 199 __BITFIELD_FIELD(uint64_t lck_offset:10,
3154#else 200 ;))
3155 uint64_t count:64;
3156#endif
3157 } s; 201 } s;
3158 struct cvmx_l2c_xmdx_pfc_s cn61xx;
3159 struct cvmx_l2c_xmdx_pfc_s cn63xx;
3160 struct cvmx_l2c_xmdx_pfc_s cn63xxp1;
3161 struct cvmx_l2c_xmdx_pfc_s cn66xx;
3162 struct cvmx_l2c_xmdx_pfc_s cn68xx;
3163 struct cvmx_l2c_xmdx_pfc_s cn68xxp1;
3164 struct cvmx_l2c_xmdx_pfc_s cnf71xx;
3165}; 202};
3166 203
3167#endif 204#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h
index ddb429210a0e..02c4479a90c8 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2c.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2c.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2010 Cavium Networks 7 * Copyright (c) 2003-2017 Cavium, Inc.
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -33,48 +33,39 @@
33#ifndef __CVMX_L2C_H__ 33#ifndef __CVMX_L2C_H__
34#define __CVMX_L2C_H__ 34#define __CVMX_L2C_H__
35 35
36#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */ 36#include <uapi/asm/bitfield.h>
37#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro, use function */
38#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */
39 37
38#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro */
39#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro */
40#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro */
40 41
41#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */ 42/* Based on 128 byte cache line size */
43#define CVMX_L2C_IDX_ADDR_SHIFT 7
42#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1) 44#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
43 45
44/* Defines for index aliasing computations */ 46/* Defines for index aliasing computations */
45#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits()) 47#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + \
48 cvmx_l2c_get_set_bits())
46#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) 49#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
47#define CVMX_L2C_MEMBANK_SELECT_SIZE 4096 50#define CVMX_L2C_MEMBANK_SELECT_SIZE 4096
48 51
49/* Defines for Virtualizations, valid only from Octeon II onwards. */ 52/* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
50#define CVMX_L2C_VRT_MAX_VIRTID_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 64 : 0) 53#define CVMX_L2C_TADS 1
51#define CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 32 : 0)
52 54
53union cvmx_l2c_tag { 55union cvmx_l2c_tag {
54 uint64_t u64; 56 uint64_t u64;
55 struct { 57 struct {
56#ifdef __BIG_ENDIAN_BITFIELD 58 __BITFIELD_FIELD(uint64_t reserved:28,
57 uint64_t reserved:28; 59 __BITFIELD_FIELD(uint64_t V:1,
58 uint64_t V:1; /* Line valid */ 60 __BITFIELD_FIELD(uint64_t D:1,
59 uint64_t D:1; /* Line dirty */ 61 __BITFIELD_FIELD(uint64_t L:1,
60 uint64_t L:1; /* Line locked */ 62 __BITFIELD_FIELD(uint64_t U:1,
61 uint64_t U:1; /* Use, LRU eviction */ 63 __BITFIELD_FIELD(uint64_t addr:32,
62 uint64_t addr:32; /* Phys mem (not all bits valid) */ 64 ;))))))
63#else
64 uint64_t addr:32; /* Phys mem (not all bits valid) */
65 uint64_t U:1; /* Use, LRU eviction */
66 uint64_t L:1; /* Line locked */
67 uint64_t D:1; /* Line dirty */
68 uint64_t V:1; /* Line valid */
69 uint64_t reserved:28;
70#endif
71 } s; 65 } s;
72}; 66};
73 67
74/* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */ 68/* L2C Performance Counter events. */
75#define CVMX_L2C_TADS 1
76
77 /* L2C Performance Counter events. */
78enum cvmx_l2c_event { 69enum cvmx_l2c_event {
79 CVMX_L2C_EVENT_CYCLES = 0, 70 CVMX_L2C_EVENT_CYCLES = 0,
80 CVMX_L2C_EVENT_INSTRUCTION_MISS = 1, 71 CVMX_L2C_EVENT_INSTRUCTION_MISS = 1,
@@ -175,7 +166,8 @@ enum cvmx_l2c_tad_event {
175 * 166 *
176 * @note The routine does not clear the counter. 167 * @note The routine does not clear the counter.
177 */ 168 */
178void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event, uint32_t clear_on_read); 169void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event,
170 uint32_t clear_on_read);
179 171
180/** 172/**
181 * Read the given L2 Cache performance counter. The counter must be configured 173 * Read the given L2 Cache performance counter. The counter must be configured
@@ -307,8 +299,11 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
307union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index); 299union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index);
308 300
309/* Wrapper providing a deprecated old function name */ 301/* Wrapper providing a deprecated old function name */
310static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index) __attribute__((deprecated)); 302static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
311static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index) 303 uint32_t index)
304 __attribute__((deprecated));
305static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
306 uint32_t index)
312{ 307{
313 return cvmx_l2c_get_tag(association, index); 308 return cvmx_l2c_get_tag(association, index);
314} 309}
diff --git a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
deleted file mode 100644
index 11a456215638..000000000000
--- a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
+++ /dev/null
@@ -1,526 +0,0 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2012 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_L2D_DEFS_H__
29#define __CVMX_L2D_DEFS_H__
30
31#define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull))
32#define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull))
33#define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull))
34#define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull))
35#define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull))
36#define CVMX_L2D_FADR (CVMX_ADD_IO_SEG(0x0001180080000018ull))
37#define CVMX_L2D_FSYN0 (CVMX_ADD_IO_SEG(0x0001180080000020ull))
38#define CVMX_L2D_FSYN1 (CVMX_ADD_IO_SEG(0x0001180080000028ull))
39#define CVMX_L2D_FUS0 (CVMX_ADD_IO_SEG(0x00011800800007A0ull))
40#define CVMX_L2D_FUS1 (CVMX_ADD_IO_SEG(0x00011800800007A8ull))
41#define CVMX_L2D_FUS2 (CVMX_ADD_IO_SEG(0x00011800800007B0ull))
42#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
43
44union cvmx_l2d_bst0 {
45 uint64_t u64;
46 struct cvmx_l2d_bst0_s {
47#ifdef __BIG_ENDIAN_BITFIELD
48 uint64_t reserved_35_63:29;
49 uint64_t ftl:1;
50 uint64_t q0stat:34;
51#else
52 uint64_t q0stat:34;
53 uint64_t ftl:1;
54 uint64_t reserved_35_63:29;
55#endif
56 } s;
57 struct cvmx_l2d_bst0_s cn30xx;
58 struct cvmx_l2d_bst0_s cn31xx;
59 struct cvmx_l2d_bst0_s cn38xx;
60 struct cvmx_l2d_bst0_s cn38xxp2;
61 struct cvmx_l2d_bst0_s cn50xx;
62 struct cvmx_l2d_bst0_s cn52xx;
63 struct cvmx_l2d_bst0_s cn52xxp1;
64 struct cvmx_l2d_bst0_s cn56xx;
65 struct cvmx_l2d_bst0_s cn56xxp1;
66 struct cvmx_l2d_bst0_s cn58xx;
67 struct cvmx_l2d_bst0_s cn58xxp1;
68};
69
70union cvmx_l2d_bst1 {
71 uint64_t u64;
72 struct cvmx_l2d_bst1_s {
73#ifdef __BIG_ENDIAN_BITFIELD
74 uint64_t reserved_34_63:30;
75 uint64_t q1stat:34;
76#else
77 uint64_t q1stat:34;
78 uint64_t reserved_34_63:30;
79#endif
80 } s;
81 struct cvmx_l2d_bst1_s cn30xx;
82 struct cvmx_l2d_bst1_s cn31xx;
83 struct cvmx_l2d_bst1_s cn38xx;
84 struct cvmx_l2d_bst1_s cn38xxp2;
85 struct cvmx_l2d_bst1_s cn50xx;
86 struct cvmx_l2d_bst1_s cn52xx;
87 struct cvmx_l2d_bst1_s cn52xxp1;
88 struct cvmx_l2d_bst1_s cn56xx;
89 struct cvmx_l2d_bst1_s cn56xxp1;
90 struct cvmx_l2d_bst1_s cn58xx;
91 struct cvmx_l2d_bst1_s cn58xxp1;
92};
93
94union cvmx_l2d_bst2 {
95 uint64_t u64;
96 struct cvmx_l2d_bst2_s {
97#ifdef __BIG_ENDIAN_BITFIELD
98 uint64_t reserved_34_63:30;
99 uint64_t q2stat:34;
100#else
101 uint64_t q2stat:34;
102 uint64_t reserved_34_63:30;
103#endif
104 } s;
105 struct cvmx_l2d_bst2_s cn30xx;
106 struct cvmx_l2d_bst2_s cn31xx;
107 struct cvmx_l2d_bst2_s cn38xx;
108 struct cvmx_l2d_bst2_s cn38xxp2;
109 struct cvmx_l2d_bst2_s cn50xx;
110 struct cvmx_l2d_bst2_s cn52xx;
111 struct cvmx_l2d_bst2_s cn52xxp1;
112 struct cvmx_l2d_bst2_s cn56xx;
113 struct cvmx_l2d_bst2_s cn56xxp1;
114 struct cvmx_l2d_bst2_s cn58xx;
115 struct cvmx_l2d_bst2_s cn58xxp1;
116};
117
118union cvmx_l2d_bst3 {
119 uint64_t u64;
120 struct cvmx_l2d_bst3_s {
121#ifdef __BIG_ENDIAN_BITFIELD
122 uint64_t reserved_34_63:30;
123 uint64_t q3stat:34;
124#else
125 uint64_t q3stat:34;
126 uint64_t reserved_34_63:30;
127#endif
128 } s;
129 struct cvmx_l2d_bst3_s cn30xx;
130 struct cvmx_l2d_bst3_s cn31xx;
131 struct cvmx_l2d_bst3_s cn38xx;
132 struct cvmx_l2d_bst3_s cn38xxp2;
133 struct cvmx_l2d_bst3_s cn50xx;
134 struct cvmx_l2d_bst3_s cn52xx;
135 struct cvmx_l2d_bst3_s cn52xxp1;
136 struct cvmx_l2d_bst3_s cn56xx;
137 struct cvmx_l2d_bst3_s cn56xxp1;
138 struct cvmx_l2d_bst3_s cn58xx;
139 struct cvmx_l2d_bst3_s cn58xxp1;
140};
141
142union cvmx_l2d_err {
143 uint64_t u64;
144 struct cvmx_l2d_err_s {
145#ifdef __BIG_ENDIAN_BITFIELD
146 uint64_t reserved_6_63:58;
147 uint64_t bmhclsel:1;
148 uint64_t ded_err:1;
149 uint64_t sec_err:1;
150 uint64_t ded_intena:1;
151 uint64_t sec_intena:1;
152 uint64_t ecc_ena:1;
153#else
154 uint64_t ecc_ena:1;
155 uint64_t sec_intena:1;
156 uint64_t ded_intena:1;
157 uint64_t sec_err:1;
158 uint64_t ded_err:1;
159 uint64_t bmhclsel:1;
160 uint64_t reserved_6_63:58;
161#endif
162 } s;
163 struct cvmx_l2d_err_s cn30xx;
164 struct cvmx_l2d_err_s cn31xx;
165 struct cvmx_l2d_err_s cn38xx;
166 struct cvmx_l2d_err_s cn38xxp2;
167 struct cvmx_l2d_err_s cn50xx;
168 struct cvmx_l2d_err_s cn52xx;
169 struct cvmx_l2d_err_s cn52xxp1;
170 struct cvmx_l2d_err_s cn56xx;
171 struct cvmx_l2d_err_s cn56xxp1;
172 struct cvmx_l2d_err_s cn58xx;
173 struct cvmx_l2d_err_s cn58xxp1;
174};
175
176union cvmx_l2d_fadr {
177 uint64_t u64;
178 struct cvmx_l2d_fadr_s {
179#ifdef __BIG_ENDIAN_BITFIELD
180 uint64_t reserved_19_63:45;
181 uint64_t fadru:1;
182 uint64_t fowmsk:4;
183 uint64_t fset:3;
184 uint64_t fadr:11;
185#else
186 uint64_t fadr:11;
187 uint64_t fset:3;
188 uint64_t fowmsk:4;
189 uint64_t fadru:1;
190 uint64_t reserved_19_63:45;
191#endif
192 } s;
193 struct cvmx_l2d_fadr_cn30xx {
194#ifdef __BIG_ENDIAN_BITFIELD
195 uint64_t reserved_18_63:46;
196 uint64_t fowmsk:4;
197 uint64_t reserved_13_13:1;
198 uint64_t fset:2;
199 uint64_t reserved_9_10:2;
200 uint64_t fadr:9;
201#else
202 uint64_t fadr:9;
203 uint64_t reserved_9_10:2;
204 uint64_t fset:2;
205 uint64_t reserved_13_13:1;
206 uint64_t fowmsk:4;
207 uint64_t reserved_18_63:46;
208#endif
209 } cn30xx;
210 struct cvmx_l2d_fadr_cn31xx {
211#ifdef __BIG_ENDIAN_BITFIELD
212 uint64_t reserved_18_63:46;
213 uint64_t fowmsk:4;
214 uint64_t reserved_13_13:1;
215 uint64_t fset:2;
216 uint64_t reserved_10_10:1;
217 uint64_t fadr:10;
218#else
219 uint64_t fadr:10;
220 uint64_t reserved_10_10:1;
221 uint64_t fset:2;
222 uint64_t reserved_13_13:1;
223 uint64_t fowmsk:4;
224 uint64_t reserved_18_63:46;
225#endif
226 } cn31xx;
227 struct cvmx_l2d_fadr_cn38xx {
228#ifdef __BIG_ENDIAN_BITFIELD
229 uint64_t reserved_18_63:46;
230 uint64_t fowmsk:4;
231 uint64_t fset:3;
232 uint64_t fadr:11;
233#else
234 uint64_t fadr:11;
235 uint64_t fset:3;
236 uint64_t fowmsk:4;
237 uint64_t reserved_18_63:46;
238#endif
239 } cn38xx;
240 struct cvmx_l2d_fadr_cn38xx cn38xxp2;
241 struct cvmx_l2d_fadr_cn50xx {
242#ifdef __BIG_ENDIAN_BITFIELD
243 uint64_t reserved_18_63:46;
244 uint64_t fowmsk:4;
245 uint64_t fset:3;
246 uint64_t reserved_8_10:3;
247 uint64_t fadr:8;
248#else
249 uint64_t fadr:8;
250 uint64_t reserved_8_10:3;
251 uint64_t fset:3;
252 uint64_t fowmsk:4;
253 uint64_t reserved_18_63:46;
254#endif
255 } cn50xx;
256 struct cvmx_l2d_fadr_cn52xx {
257#ifdef __BIG_ENDIAN_BITFIELD
258 uint64_t reserved_18_63:46;
259 uint64_t fowmsk:4;
260 uint64_t fset:3;
261 uint64_t reserved_10_10:1;
262 uint64_t fadr:10;
263#else
264 uint64_t fadr:10;
265 uint64_t reserved_10_10:1;
266 uint64_t fset:3;
267 uint64_t fowmsk:4;
268 uint64_t reserved_18_63:46;
269#endif
270 } cn52xx;
271 struct cvmx_l2d_fadr_cn52xx cn52xxp1;
272 struct cvmx_l2d_fadr_s cn56xx;
273 struct cvmx_l2d_fadr_s cn56xxp1;
274 struct cvmx_l2d_fadr_s cn58xx;
275 struct cvmx_l2d_fadr_s cn58xxp1;
276};
277
278union cvmx_l2d_fsyn0 {
279 uint64_t u64;
280 struct cvmx_l2d_fsyn0_s {
281#ifdef __BIG_ENDIAN_BITFIELD
282 uint64_t reserved_20_63:44;
283 uint64_t fsyn_ow1:10;
284 uint64_t fsyn_ow0:10;
285#else
286 uint64_t fsyn_ow0:10;
287 uint64_t fsyn_ow1:10;
288 uint64_t reserved_20_63:44;
289#endif
290 } s;
291 struct cvmx_l2d_fsyn0_s cn30xx;
292 struct cvmx_l2d_fsyn0_s cn31xx;
293 struct cvmx_l2d_fsyn0_s cn38xx;
294 struct cvmx_l2d_fsyn0_s cn38xxp2;
295 struct cvmx_l2d_fsyn0_s cn50xx;
296 struct cvmx_l2d_fsyn0_s cn52xx;
297 struct cvmx_l2d_fsyn0_s cn52xxp1;
298 struct cvmx_l2d_fsyn0_s cn56xx;
299 struct cvmx_l2d_fsyn0_s cn56xxp1;
300 struct cvmx_l2d_fsyn0_s cn58xx;
301 struct cvmx_l2d_fsyn0_s cn58xxp1;
302};
303
304union cvmx_l2d_fsyn1 {
305 uint64_t u64;
306 struct cvmx_l2d_fsyn1_s {
307#ifdef __BIG_ENDIAN_BITFIELD
308 uint64_t reserved_20_63:44;
309 uint64_t fsyn_ow3:10;
310 uint64_t fsyn_ow2:10;
311#else
312 uint64_t fsyn_ow2:10;
313 uint64_t fsyn_ow3:10;
314 uint64_t reserved_20_63:44;
315#endif
316 } s;
317 struct cvmx_l2d_fsyn1_s cn30xx;
318 struct cvmx_l2d_fsyn1_s cn31xx;
319 struct cvmx_l2d_fsyn1_s cn38xx;
320 struct cvmx_l2d_fsyn1_s cn38xxp2;
321 struct cvmx_l2d_fsyn1_s cn50xx;
322 struct cvmx_l2d_fsyn1_s cn52xx;
323 struct cvmx_l2d_fsyn1_s cn52xxp1;
324 struct cvmx_l2d_fsyn1_s cn56xx;
325 struct cvmx_l2d_fsyn1_s cn56xxp1;
326 struct cvmx_l2d_fsyn1_s cn58xx;
327 struct cvmx_l2d_fsyn1_s cn58xxp1;
328};
329
330union cvmx_l2d_fus0 {
331 uint64_t u64;
332 struct cvmx_l2d_fus0_s {
333#ifdef __BIG_ENDIAN_BITFIELD
334 uint64_t reserved_34_63:30;
335 uint64_t q0fus:34;
336#else
337 uint64_t q0fus:34;
338 uint64_t reserved_34_63:30;
339#endif
340 } s;
341 struct cvmx_l2d_fus0_s cn30xx;
342 struct cvmx_l2d_fus0_s cn31xx;
343 struct cvmx_l2d_fus0_s cn38xx;
344 struct cvmx_l2d_fus0_s cn38xxp2;
345 struct cvmx_l2d_fus0_s cn50xx;
346 struct cvmx_l2d_fus0_s cn52xx;
347 struct cvmx_l2d_fus0_s cn52xxp1;
348 struct cvmx_l2d_fus0_s cn56xx;
349 struct cvmx_l2d_fus0_s cn56xxp1;
350 struct cvmx_l2d_fus0_s cn58xx;
351 struct cvmx_l2d_fus0_s cn58xxp1;
352};
353
354union cvmx_l2d_fus1 {
355 uint64_t u64;
356 struct cvmx_l2d_fus1_s {
357#ifdef __BIG_ENDIAN_BITFIELD
358 uint64_t reserved_34_63:30;
359 uint64_t q1fus:34;
360#else
361 uint64_t q1fus:34;
362 uint64_t reserved_34_63:30;
363#endif
364 } s;
365 struct cvmx_l2d_fus1_s cn30xx;
366 struct cvmx_l2d_fus1_s cn31xx;
367 struct cvmx_l2d_fus1_s cn38xx;
368 struct cvmx_l2d_fus1_s cn38xxp2;
369 struct cvmx_l2d_fus1_s cn50xx;
370 struct cvmx_l2d_fus1_s cn52xx;
371 struct cvmx_l2d_fus1_s cn52xxp1;
372 struct cvmx_l2d_fus1_s cn56xx;
373 struct cvmx_l2d_fus1_s cn56xxp1;
374 struct cvmx_l2d_fus1_s cn58xx;
375 struct cvmx_l2d_fus1_s cn58xxp1;
376};
377
378union cvmx_l2d_fus2 {
379 uint64_t u64;
380 struct cvmx_l2d_fus2_s {
381#ifdef __BIG_ENDIAN_BITFIELD
382 uint64_t reserved_34_63:30;
383 uint64_t q2fus:34;
384#else
385 uint64_t q2fus:34;
386 uint64_t reserved_34_63:30;
387#endif
388 } s;
389 struct cvmx_l2d_fus2_s cn30xx;
390 struct cvmx_l2d_fus2_s cn31xx;
391 struct cvmx_l2d_fus2_s cn38xx;
392 struct cvmx_l2d_fus2_s cn38xxp2;
393 struct cvmx_l2d_fus2_s cn50xx;
394 struct cvmx_l2d_fus2_s cn52xx;
395 struct cvmx_l2d_fus2_s cn52xxp1;
396 struct cvmx_l2d_fus2_s cn56xx;
397 struct cvmx_l2d_fus2_s cn56xxp1;
398 struct cvmx_l2d_fus2_s cn58xx;
399 struct cvmx_l2d_fus2_s cn58xxp1;
400};
401
402union cvmx_l2d_fus3 {
403 uint64_t u64;
404 struct cvmx_l2d_fus3_s {
405#ifdef __BIG_ENDIAN_BITFIELD
406 uint64_t reserved_40_63:24;
407 uint64_t ema_ctl:3;
408 uint64_t reserved_34_36:3;
409 uint64_t q3fus:34;
410#else
411 uint64_t q3fus:34;
412 uint64_t reserved_34_36:3;
413 uint64_t ema_ctl:3;
414 uint64_t reserved_40_63:24;
415#endif
416 } s;
417 struct cvmx_l2d_fus3_cn30xx {
418#ifdef __BIG_ENDIAN_BITFIELD
419 uint64_t reserved_35_63:29;
420 uint64_t crip_64k:1;
421 uint64_t q3fus:34;
422#else
423 uint64_t q3fus:34;
424 uint64_t crip_64k:1;
425 uint64_t reserved_35_63:29;
426#endif
427 } cn30xx;
428 struct cvmx_l2d_fus3_cn31xx {
429#ifdef __BIG_ENDIAN_BITFIELD
430 uint64_t reserved_35_63:29;
431 uint64_t crip_128k:1;
432 uint64_t q3fus:34;
433#else
434 uint64_t q3fus:34;
435 uint64_t crip_128k:1;
436 uint64_t reserved_35_63:29;
437#endif
438 } cn31xx;
439 struct cvmx_l2d_fus3_cn38xx {
440#ifdef __BIG_ENDIAN_BITFIELD
441 uint64_t reserved_36_63:28;
442 uint64_t crip_256k:1;
443 uint64_t crip_512k:1;
444 uint64_t q3fus:34;
445#else
446 uint64_t q3fus:34;
447 uint64_t crip_512k:1;
448 uint64_t crip_256k:1;
449 uint64_t reserved_36_63:28;
450#endif
451 } cn38xx;
452 struct cvmx_l2d_fus3_cn38xx cn38xxp2;
453 struct cvmx_l2d_fus3_cn50xx {
454#ifdef __BIG_ENDIAN_BITFIELD
455 uint64_t reserved_40_63:24;
456 uint64_t ema_ctl:3;
457 uint64_t reserved_36_36:1;
458 uint64_t crip_32k:1;
459 uint64_t crip_64k:1;
460 uint64_t q3fus:34;
461#else
462 uint64_t q3fus:34;
463 uint64_t crip_64k:1;
464 uint64_t crip_32k:1;
465 uint64_t reserved_36_36:1;
466 uint64_t ema_ctl:3;
467 uint64_t reserved_40_63:24;
468#endif
469 } cn50xx;
470 struct cvmx_l2d_fus3_cn52xx {
471#ifdef __BIG_ENDIAN_BITFIELD
472 uint64_t reserved_40_63:24;
473 uint64_t ema_ctl:3;
474 uint64_t reserved_36_36:1;
475 uint64_t crip_128k:1;
476 uint64_t crip_256k:1;
477 uint64_t q3fus:34;
478#else
479 uint64_t q3fus:34;
480 uint64_t crip_256k:1;
481 uint64_t crip_128k:1;
482 uint64_t reserved_36_36:1;
483 uint64_t ema_ctl:3;
484 uint64_t reserved_40_63:24;
485#endif
486 } cn52xx;
487 struct cvmx_l2d_fus3_cn52xx cn52xxp1;
488 struct cvmx_l2d_fus3_cn56xx {
489#ifdef __BIG_ENDIAN_BITFIELD
490 uint64_t reserved_40_63:24;
491 uint64_t ema_ctl:3;
492 uint64_t reserved_36_36:1;
493 uint64_t crip_512k:1;
494 uint64_t crip_1024k:1;
495 uint64_t q3fus:34;
496#else
497 uint64_t q3fus:34;
498 uint64_t crip_1024k:1;
499 uint64_t crip_512k:1;
500 uint64_t reserved_36_36:1;
501 uint64_t ema_ctl:3;
502 uint64_t reserved_40_63:24;
503#endif
504 } cn56xx;
505 struct cvmx_l2d_fus3_cn56xx cn56xxp1;
506 struct cvmx_l2d_fus3_cn58xx {
507#ifdef __BIG_ENDIAN_BITFIELD
508 uint64_t reserved_39_63:25;
509 uint64_t ema_ctl:2;
510 uint64_t reserved_36_36:1;
511 uint64_t crip_512k:1;
512 uint64_t crip_1024k:1;
513 uint64_t q3fus:34;
514#else
515 uint64_t q3fus:34;
516 uint64_t crip_1024k:1;
517 uint64_t crip_512k:1;
518 uint64_t reserved_36_36:1;
519 uint64_t ema_ctl:2;
520 uint64_t reserved_39_63:25;
521#endif
522 } cn58xx;
523 struct cvmx_l2d_fus3_cn58xx cn58xxp1;
524};
525
526#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
index 83ce22c080e6..fe50671fd1bb 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2012 Cavium Networks 7 * Copyright (c) 2003-2017 Cavium, Inc.
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,210 +28,116 @@
28#ifndef __CVMX_L2T_DEFS_H__ 28#ifndef __CVMX_L2T_DEFS_H__
29#define __CVMX_L2T_DEFS_H__ 29#define __CVMX_L2T_DEFS_H__
30 30
31#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull)) 31#include <uapi/asm/bitfield.h>
32
33#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull))
34
32 35
33union cvmx_l2t_err { 36union cvmx_l2t_err {
34 uint64_t u64; 37 uint64_t u64;
35 struct cvmx_l2t_err_s { 38 struct cvmx_l2t_err_s {
36#ifdef __BIG_ENDIAN_BITFIELD 39 __BITFIELD_FIELD(uint64_t reserved_29_63:35,
37 uint64_t reserved_29_63:35; 40 __BITFIELD_FIELD(uint64_t fadru:1,
38 uint64_t fadru:1; 41 __BITFIELD_FIELD(uint64_t lck_intena2:1,
39 uint64_t lck_intena2:1; 42 __BITFIELD_FIELD(uint64_t lckerr2:1,
40 uint64_t lckerr2:1; 43 __BITFIELD_FIELD(uint64_t lck_intena:1,
41 uint64_t lck_intena:1; 44 __BITFIELD_FIELD(uint64_t lckerr:1,
42 uint64_t lckerr:1; 45 __BITFIELD_FIELD(uint64_t fset:3,
43 uint64_t fset:3; 46 __BITFIELD_FIELD(uint64_t fadr:10,
44 uint64_t fadr:10; 47 __BITFIELD_FIELD(uint64_t fsyn:6,
45 uint64_t fsyn:6; 48 __BITFIELD_FIELD(uint64_t ded_err:1,
46 uint64_t ded_err:1; 49 __BITFIELD_FIELD(uint64_t sec_err:1,
47 uint64_t sec_err:1; 50 __BITFIELD_FIELD(uint64_t ded_intena:1,
48 uint64_t ded_intena:1; 51 __BITFIELD_FIELD(uint64_t sec_intena:1,
49 uint64_t sec_intena:1; 52 __BITFIELD_FIELD(uint64_t ecc_ena:1,
50 uint64_t ecc_ena:1; 53 ;))))))))))))))
51#else
52 uint64_t ecc_ena:1;
53 uint64_t sec_intena:1;
54 uint64_t ded_intena:1;
55 uint64_t sec_err:1;
56 uint64_t ded_err:1;
57 uint64_t fsyn:6;
58 uint64_t fadr:10;
59 uint64_t fset:3;
60 uint64_t lckerr:1;
61 uint64_t lck_intena:1;
62 uint64_t lckerr2:1;
63 uint64_t lck_intena2:1;
64 uint64_t fadru:1;
65 uint64_t reserved_29_63:35;
66#endif
67 } s; 54 } s;
68 struct cvmx_l2t_err_cn30xx { 55 struct cvmx_l2t_err_cn30xx {
69#ifdef __BIG_ENDIAN_BITFIELD 56 __BITFIELD_FIELD(uint64_t reserved_28_63:36,
70 uint64_t reserved_28_63:36; 57 __BITFIELD_FIELD(uint64_t lck_intena2:1,
71 uint64_t lck_intena2:1; 58 __BITFIELD_FIELD(uint64_t lckerr2:1,
72 uint64_t lckerr2:1; 59 __BITFIELD_FIELD(uint64_t lck_intena:1,
73 uint64_t lck_intena:1; 60 __BITFIELD_FIELD(uint64_t lckerr:1,
74 uint64_t lckerr:1; 61 __BITFIELD_FIELD(uint64_t reserved_23_23:1,
75 uint64_t reserved_23_23:1; 62 __BITFIELD_FIELD(uint64_t fset:2,
76 uint64_t fset:2; 63 __BITFIELD_FIELD(uint64_t reserved_19_20:2,
77 uint64_t reserved_19_20:2; 64 __BITFIELD_FIELD(uint64_t fadr:8,
78 uint64_t fadr:8; 65 __BITFIELD_FIELD(uint64_t fsyn:6,
79 uint64_t fsyn:6; 66 __BITFIELD_FIELD(uint64_t ded_err:1,
80 uint64_t ded_err:1; 67 __BITFIELD_FIELD(uint64_t sec_err:1,
81 uint64_t sec_err:1; 68 __BITFIELD_FIELD(uint64_t ded_intena:1,
82 uint64_t ded_intena:1; 69 __BITFIELD_FIELD(uint64_t sec_intena:1,
83 uint64_t sec_intena:1; 70 __BITFIELD_FIELD(uint64_t ecc_ena:1,
84 uint64_t ecc_ena:1; 71 ;)))))))))))))))
85#else
86 uint64_t ecc_ena:1;
87 uint64_t sec_intena:1;
88 uint64_t ded_intena:1;
89 uint64_t sec_err:1;
90 uint64_t ded_err:1;
91 uint64_t fsyn:6;
92 uint64_t fadr:8;
93 uint64_t reserved_19_20:2;
94 uint64_t fset:2;
95 uint64_t reserved_23_23:1;
96 uint64_t lckerr:1;
97 uint64_t lck_intena:1;
98 uint64_t lckerr2:1;
99 uint64_t lck_intena2:1;
100 uint64_t reserved_28_63:36;
101#endif
102 } cn30xx; 72 } cn30xx;
103 struct cvmx_l2t_err_cn31xx { 73 struct cvmx_l2t_err_cn31xx {
104#ifdef __BIG_ENDIAN_BITFIELD 74 __BITFIELD_FIELD(uint64_t reserved_28_63:36,
105 uint64_t reserved_28_63:36; 75 __BITFIELD_FIELD(uint64_t lck_intena2:1,
106 uint64_t lck_intena2:1; 76 __BITFIELD_FIELD(uint64_t lckerr2:1,
107 uint64_t lckerr2:1; 77 __BITFIELD_FIELD(uint64_t lck_intena:1,
108 uint64_t lck_intena:1; 78 __BITFIELD_FIELD(uint64_t lckerr:1,
109 uint64_t lckerr:1; 79 __BITFIELD_FIELD(uint64_t reserved_23_23:1,
110 uint64_t reserved_23_23:1; 80 __BITFIELD_FIELD(uint64_t fset:2,
111 uint64_t fset:2; 81 __BITFIELD_FIELD(uint64_t reserved_20_20:1,
112 uint64_t reserved_20_20:1; 82 __BITFIELD_FIELD(uint64_t fadr:9,
113 uint64_t fadr:9; 83 __BITFIELD_FIELD(uint64_t fsyn:6,
114 uint64_t fsyn:6; 84 __BITFIELD_FIELD(uint64_t ded_err:1,
115 uint64_t ded_err:1; 85 __BITFIELD_FIELD(uint64_t sec_err:1,
116 uint64_t sec_err:1; 86 __BITFIELD_FIELD(uint64_t ded_intena:1,
117 uint64_t ded_intena:1; 87 __BITFIELD_FIELD(uint64_t sec_intena:1,
118 uint64_t sec_intena:1; 88 __BITFIELD_FIELD(uint64_t ecc_ena:1,
119 uint64_t ecc_ena:1; 89 ;)))))))))))))))
120#else
121 uint64_t ecc_ena:1;
122 uint64_t sec_intena:1;
123 uint64_t ded_intena:1;
124 uint64_t sec_err:1;
125 uint64_t ded_err:1;
126 uint64_t fsyn:6;
127 uint64_t fadr:9;
128 uint64_t reserved_20_20:1;
129 uint64_t fset:2;
130 uint64_t reserved_23_23:1;
131 uint64_t lckerr:1;
132 uint64_t lck_intena:1;
133 uint64_t lckerr2:1;
134 uint64_t lck_intena2:1;
135 uint64_t reserved_28_63:36;
136#endif
137 } cn31xx; 90 } cn31xx;
138 struct cvmx_l2t_err_cn38xx { 91 struct cvmx_l2t_err_cn38xx {
139#ifdef __BIG_ENDIAN_BITFIELD 92 __BITFIELD_FIELD(uint64_t reserved_28_63:36,
140 uint64_t reserved_28_63:36; 93 __BITFIELD_FIELD(uint64_t lck_intena2:1,
141 uint64_t lck_intena2:1; 94 __BITFIELD_FIELD(uint64_t lckerr2:1,
142 uint64_t lckerr2:1; 95 __BITFIELD_FIELD(uint64_t lck_intena:1,
143 uint64_t lck_intena:1; 96 __BITFIELD_FIELD(uint64_t lckerr:1,
144 uint64_t lckerr:1; 97 __BITFIELD_FIELD(uint64_t fset:3,
145 uint64_t fset:3; 98 __BITFIELD_FIELD(uint64_t fadr:10,
146 uint64_t fadr:10; 99 __BITFIELD_FIELD(uint64_t fsyn:6,
147 uint64_t fsyn:6; 100 __BITFIELD_FIELD(uint64_t ded_err:1,
148 uint64_t ded_err:1; 101 __BITFIELD_FIELD(uint64_t sec_err:1,
149 uint64_t sec_err:1; 102 __BITFIELD_FIELD(uint64_t ded_intena:1,
150 uint64_t ded_intena:1; 103 __BITFIELD_FIELD(uint64_t sec_intena:1,
151 uint64_t sec_intena:1; 104 __BITFIELD_FIELD(uint64_t ecc_ena:1,
152 uint64_t ecc_ena:1; 105 ;)))))))))))))
153#else
154 uint64_t ecc_ena:1;
155 uint64_t sec_intena:1;
156 uint64_t ded_intena:1;
157 uint64_t sec_err:1;
158 uint64_t ded_err:1;
159 uint64_t fsyn:6;
160 uint64_t fadr:10;
161 uint64_t fset:3;
162 uint64_t lckerr:1;
163 uint64_t lck_intena:1;
164 uint64_t lckerr2:1;
165 uint64_t lck_intena2:1;
166 uint64_t reserved_28_63:36;
167#endif
168 } cn38xx; 106 } cn38xx;
169 struct cvmx_l2t_err_cn38xx cn38xxp2; 107 struct cvmx_l2t_err_cn38xx cn38xxp2;
170 struct cvmx_l2t_err_cn50xx { 108 struct cvmx_l2t_err_cn50xx {
171#ifdef __BIG_ENDIAN_BITFIELD 109 __BITFIELD_FIELD(uint64_t reserved_28_63:36,
172 uint64_t reserved_28_63:36; 110 __BITFIELD_FIELD(uint64_t lck_intena2:1,
173 uint64_t lck_intena2:1; 111 __BITFIELD_FIELD(uint64_t lckerr2:1,
174 uint64_t lckerr2:1; 112 __BITFIELD_FIELD(uint64_t lck_intena:1,
175 uint64_t lck_intena:1; 113 __BITFIELD_FIELD(uint64_t lckerr:1,
176 uint64_t lckerr:1; 114 __BITFIELD_FIELD(uint64_t fset:3,
177 uint64_t fset:3; 115 __BITFIELD_FIELD(uint64_t reserved_18_20:3,
178 uint64_t reserved_18_20:3; 116 __BITFIELD_FIELD(uint64_t fadr:7,
179 uint64_t fadr:7; 117 __BITFIELD_FIELD(uint64_t fsyn:6,
180 uint64_t fsyn:6; 118 __BITFIELD_FIELD(uint64_t ded_err:1,
181 uint64_t ded_err:1; 119 __BITFIELD_FIELD(uint64_t sec_err:1,
182 uint64_t sec_err:1; 120 __BITFIELD_FIELD(uint64_t ded_intena:1,
183 uint64_t ded_intena:1; 121 __BITFIELD_FIELD(uint64_t sec_intena:1,
184 uint64_t sec_intena:1; 122 __BITFIELD_FIELD(uint64_t ecc_ena:1,
185 uint64_t ecc_ena:1; 123 ;))))))))))))))
186#else
187 uint64_t ecc_ena:1;
188 uint64_t sec_intena:1;
189 uint64_t ded_intena:1;
190 uint64_t sec_err:1;
191 uint64_t ded_err:1;
192 uint64_t fsyn:6;
193 uint64_t fadr:7;
194 uint64_t reserved_18_20:3;
195 uint64_t fset:3;
196 uint64_t lckerr:1;
197 uint64_t lck_intena:1;
198 uint64_t lckerr2:1;
199 uint64_t lck_intena2:1;
200 uint64_t reserved_28_63:36;
201#endif
202 } cn50xx; 124 } cn50xx;
203 struct cvmx_l2t_err_cn52xx { 125 struct cvmx_l2t_err_cn52xx {
204#ifdef __BIG_ENDIAN_BITFIELD 126 __BITFIELD_FIELD(uint64_t reserved_28_63:36,
205 uint64_t reserved_28_63:36; 127 __BITFIELD_FIELD(uint64_t lck_intena2:1,
206 uint64_t lck_intena2:1; 128 __BITFIELD_FIELD(uint64_t lckerr2:1,
207 uint64_t lckerr2:1; 129 __BITFIELD_FIELD(uint64_t lck_intena:1,
208 uint64_t lck_intena:1; 130 __BITFIELD_FIELD(uint64_t lckerr:1,
209 uint64_t lckerr:1; 131 __BITFIELD_FIELD(uint64_t fset:3,
210 uint64_t fset:3; 132 __BITFIELD_FIELD(uint64_t reserved_20_20:1,
211 uint64_t reserved_20_20:1; 133 __BITFIELD_FIELD(uint64_t fadr:9,
212 uint64_t fadr:9; 134 __BITFIELD_FIELD(uint64_t fsyn:6,
213 uint64_t fsyn:6; 135 __BITFIELD_FIELD(uint64_t ded_err:1,
214 uint64_t ded_err:1; 136 __BITFIELD_FIELD(uint64_t sec_err:1,
215 uint64_t sec_err:1; 137 __BITFIELD_FIELD(uint64_t ded_intena:1,
216 uint64_t ded_intena:1; 138 __BITFIELD_FIELD(uint64_t sec_intena:1,
217 uint64_t sec_intena:1; 139 __BITFIELD_FIELD(uint64_t ecc_ena:1,
218 uint64_t ecc_ena:1; 140 ;))))))))))))))
219#else
220 uint64_t ecc_ena:1;
221 uint64_t sec_intena:1;
222 uint64_t ded_intena:1;
223 uint64_t sec_err:1;
224 uint64_t ded_err:1;
225 uint64_t fsyn:6;
226 uint64_t fadr:9;
227 uint64_t reserved_20_20:1;
228 uint64_t fset:3;
229 uint64_t lckerr:1;
230 uint64_t lck_intena:1;
231 uint64_t lckerr2:1;
232 uint64_t lck_intena2:1;
233 uint64_t reserved_28_63:36;
234#endif
235 } cn52xx; 141 } cn52xx;
236 struct cvmx_l2t_err_cn52xx cn52xxp1; 142 struct cvmx_l2t_err_cn52xx cn52xxp1;
237 struct cvmx_l2t_err_s cn56xx; 143 struct cvmx_l2t_err_s cn56xx;
diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
index 4bce393391e2..e2dce1acf029 100644
--- a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2012 Cavium Networks 7 * Copyright (c) 2003-2017 Cavium, Inc.
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,3148 +28,341 @@
28#ifndef __CVMX_PCIERCX_DEFS_H__ 28#ifndef __CVMX_PCIERCX_DEFS_H__
29#define __CVMX_PCIERCX_DEFS_H__ 29#define __CVMX_PCIERCX_DEFS_H__
30 30
31#define CVMX_PCIERCX_CFG000(block_id) (0x0000000000000000ull) 31#include <uapi/asm/bitfield.h>
32
32#define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull) 33#define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull)
33#define CVMX_PCIERCX_CFG002(block_id) (0x0000000000000008ull)
34#define CVMX_PCIERCX_CFG003(block_id) (0x000000000000000Cull)
35#define CVMX_PCIERCX_CFG004(block_id) (0x0000000000000010ull)
36#define CVMX_PCIERCX_CFG005(block_id) (0x0000000000000014ull)
37#define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull) 34#define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull)
38#define CVMX_PCIERCX_CFG007(block_id) (0x000000000000001Cull)
39#define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull) 35#define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull)
40#define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull) 36#define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull)
41#define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull) 37#define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull)
42#define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull) 38#define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull)
43#define CVMX_PCIERCX_CFG012(block_id) (0x0000000000000030ull)
44#define CVMX_PCIERCX_CFG013(block_id) (0x0000000000000034ull)
45#define CVMX_PCIERCX_CFG014(block_id) (0x0000000000000038ull)
46#define CVMX_PCIERCX_CFG015(block_id) (0x000000000000003Cull)
47#define CVMX_PCIERCX_CFG016(block_id) (0x0000000000000040ull)
48#define CVMX_PCIERCX_CFG017(block_id) (0x0000000000000044ull)
49#define CVMX_PCIERCX_CFG020(block_id) (0x0000000000000050ull)
50#define CVMX_PCIERCX_CFG021(block_id) (0x0000000000000054ull)
51#define CVMX_PCIERCX_CFG022(block_id) (0x0000000000000058ull)
52#define CVMX_PCIERCX_CFG023(block_id) (0x000000000000005Cull)
53#define CVMX_PCIERCX_CFG028(block_id) (0x0000000000000070ull)
54#define CVMX_PCIERCX_CFG029(block_id) (0x0000000000000074ull)
55#define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull) 39#define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull)
56#define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull) 40#define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull)
57#define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull) 41#define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull)
58#define CVMX_PCIERCX_CFG033(block_id) (0x0000000000000084ull)
59#define CVMX_PCIERCX_CFG034(block_id) (0x0000000000000088ull) 42#define CVMX_PCIERCX_CFG034(block_id) (0x0000000000000088ull)
60#define CVMX_PCIERCX_CFG035(block_id) (0x000000000000008Cull) 43#define CVMX_PCIERCX_CFG035(block_id) (0x000000000000008Cull)
61#define CVMX_PCIERCX_CFG036(block_id) (0x0000000000000090ull)
62#define CVMX_PCIERCX_CFG037(block_id) (0x0000000000000094ull)
63#define CVMX_PCIERCX_CFG038(block_id) (0x0000000000000098ull)
64#define CVMX_PCIERCX_CFG039(block_id) (0x000000000000009Cull)
65#define CVMX_PCIERCX_CFG040(block_id) (0x00000000000000A0ull) 44#define CVMX_PCIERCX_CFG040(block_id) (0x00000000000000A0ull)
66#define CVMX_PCIERCX_CFG041(block_id) (0x00000000000000A4ull)
67#define CVMX_PCIERCX_CFG042(block_id) (0x00000000000000A8ull)
68#define CVMX_PCIERCX_CFG064(block_id) (0x0000000000000100ull)
69#define CVMX_PCIERCX_CFG065(block_id) (0x0000000000000104ull)
70#define CVMX_PCIERCX_CFG066(block_id) (0x0000000000000108ull) 45#define CVMX_PCIERCX_CFG066(block_id) (0x0000000000000108ull)
71#define CVMX_PCIERCX_CFG067(block_id) (0x000000000000010Cull)
72#define CVMX_PCIERCX_CFG068(block_id) (0x0000000000000110ull)
73#define CVMX_PCIERCX_CFG069(block_id) (0x0000000000000114ull) 46#define CVMX_PCIERCX_CFG069(block_id) (0x0000000000000114ull)
74#define CVMX_PCIERCX_CFG070(block_id) (0x0000000000000118ull) 47#define CVMX_PCIERCX_CFG070(block_id) (0x0000000000000118ull)
75#define CVMX_PCIERCX_CFG071(block_id) (0x000000000000011Cull)
76#define CVMX_PCIERCX_CFG072(block_id) (0x0000000000000120ull)
77#define CVMX_PCIERCX_CFG073(block_id) (0x0000000000000124ull)
78#define CVMX_PCIERCX_CFG074(block_id) (0x0000000000000128ull)
79#define CVMX_PCIERCX_CFG075(block_id) (0x000000000000012Cull) 48#define CVMX_PCIERCX_CFG075(block_id) (0x000000000000012Cull)
80#define CVMX_PCIERCX_CFG076(block_id) (0x0000000000000130ull)
81#define CVMX_PCIERCX_CFG077(block_id) (0x0000000000000134ull)
82#define CVMX_PCIERCX_CFG448(block_id) (0x0000000000000700ull) 49#define CVMX_PCIERCX_CFG448(block_id) (0x0000000000000700ull)
83#define CVMX_PCIERCX_CFG449(block_id) (0x0000000000000704ull)
84#define CVMX_PCIERCX_CFG450(block_id) (0x0000000000000708ull)
85#define CVMX_PCIERCX_CFG451(block_id) (0x000000000000070Cull)
86#define CVMX_PCIERCX_CFG452(block_id) (0x0000000000000710ull) 50#define CVMX_PCIERCX_CFG452(block_id) (0x0000000000000710ull)
87#define CVMX_PCIERCX_CFG453(block_id) (0x0000000000000714ull)
88#define CVMX_PCIERCX_CFG454(block_id) (0x0000000000000718ull)
89#define CVMX_PCIERCX_CFG455(block_id) (0x000000000000071Cull) 51#define CVMX_PCIERCX_CFG455(block_id) (0x000000000000071Cull)
90#define CVMX_PCIERCX_CFG456(block_id) (0x0000000000000720ull)
91#define CVMX_PCIERCX_CFG458(block_id) (0x0000000000000728ull)
92#define CVMX_PCIERCX_CFG459(block_id) (0x000000000000072Cull)
93#define CVMX_PCIERCX_CFG460(block_id) (0x0000000000000730ull)
94#define CVMX_PCIERCX_CFG461(block_id) (0x0000000000000734ull)
95#define CVMX_PCIERCX_CFG462(block_id) (0x0000000000000738ull)
96#define CVMX_PCIERCX_CFG463(block_id) (0x000000000000073Cull)
97#define CVMX_PCIERCX_CFG464(block_id) (0x0000000000000740ull)
98#define CVMX_PCIERCX_CFG465(block_id) (0x0000000000000744ull)
99#define CVMX_PCIERCX_CFG466(block_id) (0x0000000000000748ull)
100#define CVMX_PCIERCX_CFG467(block_id) (0x000000000000074Cull)
101#define CVMX_PCIERCX_CFG468(block_id) (0x0000000000000750ull)
102#define CVMX_PCIERCX_CFG490(block_id) (0x00000000000007A8ull)
103#define CVMX_PCIERCX_CFG491(block_id) (0x00000000000007ACull)
104#define CVMX_PCIERCX_CFG492(block_id) (0x00000000000007B0ull)
105#define CVMX_PCIERCX_CFG515(block_id) (0x000000000000080Cull) 52#define CVMX_PCIERCX_CFG515(block_id) (0x000000000000080Cull)
106#define CVMX_PCIERCX_CFG516(block_id) (0x0000000000000810ull)
107#define CVMX_PCIERCX_CFG517(block_id) (0x0000000000000814ull)
108
109union cvmx_pciercx_cfg000 {
110 uint32_t u32;
111 struct cvmx_pciercx_cfg000_s {
112#ifdef __BIG_ENDIAN_BITFIELD
113 uint32_t devid:16;
114 uint32_t vendid:16;
115#else
116 uint32_t vendid:16;
117 uint32_t devid:16;
118#endif
119 } s;
120 struct cvmx_pciercx_cfg000_s cn52xx;
121 struct cvmx_pciercx_cfg000_s cn52xxp1;
122 struct cvmx_pciercx_cfg000_s cn56xx;
123 struct cvmx_pciercx_cfg000_s cn56xxp1;
124 struct cvmx_pciercx_cfg000_s cn61xx;
125 struct cvmx_pciercx_cfg000_s cn63xx;
126 struct cvmx_pciercx_cfg000_s cn63xxp1;
127 struct cvmx_pciercx_cfg000_s cn66xx;
128 struct cvmx_pciercx_cfg000_s cn68xx;
129 struct cvmx_pciercx_cfg000_s cn68xxp1;
130 struct cvmx_pciercx_cfg000_s cnf71xx;
131};
132 53
133union cvmx_pciercx_cfg001 { 54union cvmx_pciercx_cfg001 {
134 uint32_t u32; 55 uint32_t u32;
135 struct cvmx_pciercx_cfg001_s { 56 struct cvmx_pciercx_cfg001_s {
136#ifdef __BIG_ENDIAN_BITFIELD 57 __BITFIELD_FIELD(uint32_t dpe:1,
137 uint32_t dpe:1; 58 __BITFIELD_FIELD(uint32_t sse:1,
138 uint32_t sse:1; 59 __BITFIELD_FIELD(uint32_t rma:1,
139 uint32_t rma:1; 60 __BITFIELD_FIELD(uint32_t rta:1,
140 uint32_t rta:1; 61 __BITFIELD_FIELD(uint32_t sta:1,
141 uint32_t sta:1; 62 __BITFIELD_FIELD(uint32_t devt:2,
142 uint32_t devt:2; 63 __BITFIELD_FIELD(uint32_t mdpe:1,
143 uint32_t mdpe:1; 64 __BITFIELD_FIELD(uint32_t fbb:1,
144 uint32_t fbb:1; 65 __BITFIELD_FIELD(uint32_t reserved_22_22:1,
145 uint32_t reserved_22_22:1; 66 __BITFIELD_FIELD(uint32_t m66:1,
146 uint32_t m66:1; 67 __BITFIELD_FIELD(uint32_t cl:1,
147 uint32_t cl:1; 68 __BITFIELD_FIELD(uint32_t i_stat:1,
148 uint32_t i_stat:1; 69 __BITFIELD_FIELD(uint32_t reserved_11_18:8,
149 uint32_t reserved_11_18:8; 70 __BITFIELD_FIELD(uint32_t i_dis:1,
150 uint32_t i_dis:1; 71 __BITFIELD_FIELD(uint32_t fbbe:1,
151 uint32_t fbbe:1; 72 __BITFIELD_FIELD(uint32_t see:1,
152 uint32_t see:1; 73 __BITFIELD_FIELD(uint32_t ids_wcc:1,
153 uint32_t ids_wcc:1; 74 __BITFIELD_FIELD(uint32_t per:1,
154 uint32_t per:1; 75 __BITFIELD_FIELD(uint32_t vps:1,
155 uint32_t vps:1; 76 __BITFIELD_FIELD(uint32_t mwice:1,
156 uint32_t mwice:1; 77 __BITFIELD_FIELD(uint32_t scse:1,
157 uint32_t scse:1; 78 __BITFIELD_FIELD(uint32_t me:1,
158 uint32_t me:1; 79 __BITFIELD_FIELD(uint32_t msae:1,
159 uint32_t msae:1; 80 __BITFIELD_FIELD(uint32_t isae:1,
160 uint32_t isae:1; 81 ;))))))))))))))))))))))))
161#else
162 uint32_t isae:1;
163 uint32_t msae:1;
164 uint32_t me:1;
165 uint32_t scse:1;
166 uint32_t mwice:1;
167 uint32_t vps:1;
168 uint32_t per:1;
169 uint32_t ids_wcc:1;
170 uint32_t see:1;
171 uint32_t fbbe:1;
172 uint32_t i_dis:1;
173 uint32_t reserved_11_18:8;
174 uint32_t i_stat:1;
175 uint32_t cl:1;
176 uint32_t m66:1;
177 uint32_t reserved_22_22:1;
178 uint32_t fbb:1;
179 uint32_t mdpe:1;
180 uint32_t devt:2;
181 uint32_t sta:1;
182 uint32_t rta:1;
183 uint32_t rma:1;
184 uint32_t sse:1;
185 uint32_t dpe:1;
186#endif
187 } s;
188 struct cvmx_pciercx_cfg001_s cn52xx;
189 struct cvmx_pciercx_cfg001_s cn52xxp1;
190 struct cvmx_pciercx_cfg001_s cn56xx;
191 struct cvmx_pciercx_cfg001_s cn56xxp1;
192 struct cvmx_pciercx_cfg001_s cn61xx;
193 struct cvmx_pciercx_cfg001_s cn63xx;
194 struct cvmx_pciercx_cfg001_s cn63xxp1;
195 struct cvmx_pciercx_cfg001_s cn66xx;
196 struct cvmx_pciercx_cfg001_s cn68xx;
197 struct cvmx_pciercx_cfg001_s cn68xxp1;
198 struct cvmx_pciercx_cfg001_s cnf71xx;
199};
200
201union cvmx_pciercx_cfg002 {
202 uint32_t u32;
203 struct cvmx_pciercx_cfg002_s {
204#ifdef __BIG_ENDIAN_BITFIELD
205 uint32_t bcc:8;
206 uint32_t sc:8;
207 uint32_t pi:8;
208 uint32_t rid:8;
209#else
210 uint32_t rid:8;
211 uint32_t pi:8;
212 uint32_t sc:8;
213 uint32_t bcc:8;
214#endif
215 } s;
216 struct cvmx_pciercx_cfg002_s cn52xx;
217 struct cvmx_pciercx_cfg002_s cn52xxp1;
218 struct cvmx_pciercx_cfg002_s cn56xx;
219 struct cvmx_pciercx_cfg002_s cn56xxp1;
220 struct cvmx_pciercx_cfg002_s cn61xx;
221 struct cvmx_pciercx_cfg002_s cn63xx;
222 struct cvmx_pciercx_cfg002_s cn63xxp1;
223 struct cvmx_pciercx_cfg002_s cn66xx;
224 struct cvmx_pciercx_cfg002_s cn68xx;
225 struct cvmx_pciercx_cfg002_s cn68xxp1;
226 struct cvmx_pciercx_cfg002_s cnf71xx;
227};
228
229union cvmx_pciercx_cfg003 {
230 uint32_t u32;
231 struct cvmx_pciercx_cfg003_s {
232#ifdef __BIG_ENDIAN_BITFIELD
233 uint32_t bist:8;
234 uint32_t mfd:1;
235 uint32_t chf:7;
236 uint32_t lt:8;
237 uint32_t cls:8;
238#else
239 uint32_t cls:8;
240 uint32_t lt:8;
241 uint32_t chf:7;
242 uint32_t mfd:1;
243 uint32_t bist:8;
244#endif
245 } s;
246 struct cvmx_pciercx_cfg003_s cn52xx;
247 struct cvmx_pciercx_cfg003_s cn52xxp1;
248 struct cvmx_pciercx_cfg003_s cn56xx;
249 struct cvmx_pciercx_cfg003_s cn56xxp1;
250 struct cvmx_pciercx_cfg003_s cn61xx;
251 struct cvmx_pciercx_cfg003_s cn63xx;
252 struct cvmx_pciercx_cfg003_s cn63xxp1;
253 struct cvmx_pciercx_cfg003_s cn66xx;
254 struct cvmx_pciercx_cfg003_s cn68xx;
255 struct cvmx_pciercx_cfg003_s cn68xxp1;
256 struct cvmx_pciercx_cfg003_s cnf71xx;
257};
258
259union cvmx_pciercx_cfg004 {
260 uint32_t u32;
261 struct cvmx_pciercx_cfg004_s {
262#ifdef __BIG_ENDIAN_BITFIELD
263 uint32_t reserved_0_31:32;
264#else
265 uint32_t reserved_0_31:32;
266#endif
267 } s; 82 } s;
268 struct cvmx_pciercx_cfg004_s cn52xx;
269 struct cvmx_pciercx_cfg004_s cn52xxp1;
270 struct cvmx_pciercx_cfg004_s cn56xx;
271 struct cvmx_pciercx_cfg004_s cn56xxp1;
272 struct cvmx_pciercx_cfg004_s cn61xx;
273 struct cvmx_pciercx_cfg004_s cn63xx;
274 struct cvmx_pciercx_cfg004_s cn63xxp1;
275 struct cvmx_pciercx_cfg004_s cn66xx;
276 struct cvmx_pciercx_cfg004_s cn68xx;
277 struct cvmx_pciercx_cfg004_s cn68xxp1;
278 struct cvmx_pciercx_cfg004_s cnf71xx;
279};
280
281union cvmx_pciercx_cfg005 {
282 uint32_t u32;
283 struct cvmx_pciercx_cfg005_s {
284#ifdef __BIG_ENDIAN_BITFIELD
285 uint32_t reserved_0_31:32;
286#else
287 uint32_t reserved_0_31:32;
288#endif
289 } s;
290 struct cvmx_pciercx_cfg005_s cn52xx;
291 struct cvmx_pciercx_cfg005_s cn52xxp1;
292 struct cvmx_pciercx_cfg005_s cn56xx;
293 struct cvmx_pciercx_cfg005_s cn56xxp1;
294 struct cvmx_pciercx_cfg005_s cn61xx;
295 struct cvmx_pciercx_cfg005_s cn63xx;
296 struct cvmx_pciercx_cfg005_s cn63xxp1;
297 struct cvmx_pciercx_cfg005_s cn66xx;
298 struct cvmx_pciercx_cfg005_s cn68xx;
299 struct cvmx_pciercx_cfg005_s cn68xxp1;
300 struct cvmx_pciercx_cfg005_s cnf71xx;
301}; 83};
302 84
303union cvmx_pciercx_cfg006 { 85union cvmx_pciercx_cfg006 {
304 uint32_t u32; 86 uint32_t u32;
305 struct cvmx_pciercx_cfg006_s { 87 struct cvmx_pciercx_cfg006_s {
306#ifdef __BIG_ENDIAN_BITFIELD 88 __BITFIELD_FIELD(uint32_t slt:8,
307 uint32_t slt:8; 89 __BITFIELD_FIELD(uint32_t subbnum:8,
308 uint32_t subbnum:8; 90 __BITFIELD_FIELD(uint32_t sbnum:8,
309 uint32_t sbnum:8; 91 __BITFIELD_FIELD(uint32_t pbnum:8,
310 uint32_t pbnum:8; 92 ;))))
311#else
312 uint32_t pbnum:8;
313 uint32_t sbnum:8;
314 uint32_t subbnum:8;
315 uint32_t slt:8;
316#endif
317 } s;
318 struct cvmx_pciercx_cfg006_s cn52xx;
319 struct cvmx_pciercx_cfg006_s cn52xxp1;
320 struct cvmx_pciercx_cfg006_s cn56xx;
321 struct cvmx_pciercx_cfg006_s cn56xxp1;
322 struct cvmx_pciercx_cfg006_s cn61xx;
323 struct cvmx_pciercx_cfg006_s cn63xx;
324 struct cvmx_pciercx_cfg006_s cn63xxp1;
325 struct cvmx_pciercx_cfg006_s cn66xx;
326 struct cvmx_pciercx_cfg006_s cn68xx;
327 struct cvmx_pciercx_cfg006_s cn68xxp1;
328 struct cvmx_pciercx_cfg006_s cnf71xx;
329};
330
331union cvmx_pciercx_cfg007 {
332 uint32_t u32;
333 struct cvmx_pciercx_cfg007_s {
334#ifdef __BIG_ENDIAN_BITFIELD
335 uint32_t dpe:1;
336 uint32_t sse:1;
337 uint32_t rma:1;
338 uint32_t rta:1;
339 uint32_t sta:1;
340 uint32_t devt:2;
341 uint32_t mdpe:1;
342 uint32_t fbb:1;
343 uint32_t reserved_22_22:1;
344 uint32_t m66:1;
345 uint32_t reserved_16_20:5;
346 uint32_t lio_limi:4;
347 uint32_t reserved_9_11:3;
348 uint32_t io32b:1;
349 uint32_t lio_base:4;
350 uint32_t reserved_1_3:3;
351 uint32_t io32a:1;
352#else
353 uint32_t io32a:1;
354 uint32_t reserved_1_3:3;
355 uint32_t lio_base:4;
356 uint32_t io32b:1;
357 uint32_t reserved_9_11:3;
358 uint32_t lio_limi:4;
359 uint32_t reserved_16_20:5;
360 uint32_t m66:1;
361 uint32_t reserved_22_22:1;
362 uint32_t fbb:1;
363 uint32_t mdpe:1;
364 uint32_t devt:2;
365 uint32_t sta:1;
366 uint32_t rta:1;
367 uint32_t rma:1;
368 uint32_t sse:1;
369 uint32_t dpe:1;
370#endif
371 } s; 93 } s;
372 struct cvmx_pciercx_cfg007_s cn52xx;
373 struct cvmx_pciercx_cfg007_s cn52xxp1;
374 struct cvmx_pciercx_cfg007_s cn56xx;
375 struct cvmx_pciercx_cfg007_s cn56xxp1;
376 struct cvmx_pciercx_cfg007_s cn61xx;
377 struct cvmx_pciercx_cfg007_s cn63xx;
378 struct cvmx_pciercx_cfg007_s cn63xxp1;
379 struct cvmx_pciercx_cfg007_s cn66xx;
380 struct cvmx_pciercx_cfg007_s cn68xx;
381 struct cvmx_pciercx_cfg007_s cn68xxp1;
382 struct cvmx_pciercx_cfg007_s cnf71xx;
383}; 94};
384 95
385union cvmx_pciercx_cfg008 { 96union cvmx_pciercx_cfg008 {
386 uint32_t u32; 97 uint32_t u32;
387 struct cvmx_pciercx_cfg008_s { 98 struct cvmx_pciercx_cfg008_s {
388#ifdef __BIG_ENDIAN_BITFIELD 99 __BITFIELD_FIELD(uint32_t ml_addr:12,
389 uint32_t ml_addr:12; 100 __BITFIELD_FIELD(uint32_t reserved_16_19:4,
390 uint32_t reserved_16_19:4; 101 __BITFIELD_FIELD(uint32_t mb_addr:12,
391 uint32_t mb_addr:12; 102 __BITFIELD_FIELD(uint32_t reserved_0_3:4,
392 uint32_t reserved_0_3:4; 103 ;))))
393#else
394 uint32_t reserved_0_3:4;
395 uint32_t mb_addr:12;
396 uint32_t reserved_16_19:4;
397 uint32_t ml_addr:12;
398#endif
399 } s; 104 } s;
400 struct cvmx_pciercx_cfg008_s cn52xx;
401 struct cvmx_pciercx_cfg008_s cn52xxp1;
402 struct cvmx_pciercx_cfg008_s cn56xx;
403 struct cvmx_pciercx_cfg008_s cn56xxp1;
404 struct cvmx_pciercx_cfg008_s cn61xx;
405 struct cvmx_pciercx_cfg008_s cn63xx;
406 struct cvmx_pciercx_cfg008_s cn63xxp1;
407 struct cvmx_pciercx_cfg008_s cn66xx;
408 struct cvmx_pciercx_cfg008_s cn68xx;
409 struct cvmx_pciercx_cfg008_s cn68xxp1;
410 struct cvmx_pciercx_cfg008_s cnf71xx;
411}; 105};
412 106
413union cvmx_pciercx_cfg009 { 107union cvmx_pciercx_cfg009 {
414 uint32_t u32; 108 uint32_t u32;
415 struct cvmx_pciercx_cfg009_s { 109 struct cvmx_pciercx_cfg009_s {
416#ifdef __BIG_ENDIAN_BITFIELD 110 __BITFIELD_FIELD(uint32_t lmem_limit:12,
417 uint32_t lmem_limit:12; 111 __BITFIELD_FIELD(uint32_t reserved_17_19:3,
418 uint32_t reserved_17_19:3; 112 __BITFIELD_FIELD(uint32_t mem64b:1,
419 uint32_t mem64b:1; 113 __BITFIELD_FIELD(uint32_t lmem_base:12,
420 uint32_t lmem_base:12; 114 __BITFIELD_FIELD(uint32_t reserved_1_3:3,
421 uint32_t reserved_1_3:3; 115 __BITFIELD_FIELD(uint32_t mem64a:1,
422 uint32_t mem64a:1; 116 ;))))))
423#else
424 uint32_t mem64a:1;
425 uint32_t reserved_1_3:3;
426 uint32_t lmem_base:12;
427 uint32_t mem64b:1;
428 uint32_t reserved_17_19:3;
429 uint32_t lmem_limit:12;
430#endif
431 } s; 117 } s;
432 struct cvmx_pciercx_cfg009_s cn52xx;
433 struct cvmx_pciercx_cfg009_s cn52xxp1;
434 struct cvmx_pciercx_cfg009_s cn56xx;
435 struct cvmx_pciercx_cfg009_s cn56xxp1;
436 struct cvmx_pciercx_cfg009_s cn61xx;
437 struct cvmx_pciercx_cfg009_s cn63xx;
438 struct cvmx_pciercx_cfg009_s cn63xxp1;
439 struct cvmx_pciercx_cfg009_s cn66xx;
440 struct cvmx_pciercx_cfg009_s cn68xx;
441 struct cvmx_pciercx_cfg009_s cn68xxp1;
442 struct cvmx_pciercx_cfg009_s cnf71xx;
443}; 118};
444 119
445union cvmx_pciercx_cfg010 { 120union cvmx_pciercx_cfg010 {
446 uint32_t u32; 121 uint32_t u32;
447 struct cvmx_pciercx_cfg010_s { 122 struct cvmx_pciercx_cfg010_s {
448#ifdef __BIG_ENDIAN_BITFIELD 123 uint32_t umem_base;
449 uint32_t umem_base:32;
450#else
451 uint32_t umem_base:32;
452#endif
453 } s; 124 } s;
454 struct cvmx_pciercx_cfg010_s cn52xx;
455 struct cvmx_pciercx_cfg010_s cn52xxp1;
456 struct cvmx_pciercx_cfg010_s cn56xx;
457 struct cvmx_pciercx_cfg010_s cn56xxp1;
458 struct cvmx_pciercx_cfg010_s cn61xx;
459 struct cvmx_pciercx_cfg010_s cn63xx;
460 struct cvmx_pciercx_cfg010_s cn63xxp1;
461 struct cvmx_pciercx_cfg010_s cn66xx;
462 struct cvmx_pciercx_cfg010_s cn68xx;
463 struct cvmx_pciercx_cfg010_s cn68xxp1;
464 struct cvmx_pciercx_cfg010_s cnf71xx;
465}; 125};
466 126
467union cvmx_pciercx_cfg011 { 127union cvmx_pciercx_cfg011 {
468 uint32_t u32; 128 uint32_t u32;
469 struct cvmx_pciercx_cfg011_s { 129 struct cvmx_pciercx_cfg011_s {
470#ifdef __BIG_ENDIAN_BITFIELD 130 uint32_t umem_limit;
471 uint32_t umem_limit:32;
472#else
473 uint32_t umem_limit:32;
474#endif
475 } s;
476 struct cvmx_pciercx_cfg011_s cn52xx;
477 struct cvmx_pciercx_cfg011_s cn52xxp1;
478 struct cvmx_pciercx_cfg011_s cn56xx;
479 struct cvmx_pciercx_cfg011_s cn56xxp1;
480 struct cvmx_pciercx_cfg011_s cn61xx;
481 struct cvmx_pciercx_cfg011_s cn63xx;
482 struct cvmx_pciercx_cfg011_s cn63xxp1;
483 struct cvmx_pciercx_cfg011_s cn66xx;
484 struct cvmx_pciercx_cfg011_s cn68xx;
485 struct cvmx_pciercx_cfg011_s cn68xxp1;
486 struct cvmx_pciercx_cfg011_s cnf71xx;
487};
488
489union cvmx_pciercx_cfg012 {
490 uint32_t u32;
491 struct cvmx_pciercx_cfg012_s {
492#ifdef __BIG_ENDIAN_BITFIELD
493 uint32_t uio_limit:16;
494 uint32_t uio_base:16;
495#else
496 uint32_t uio_base:16;
497 uint32_t uio_limit:16;
498#endif
499 } s; 131 } s;
500 struct cvmx_pciercx_cfg012_s cn52xx;
501 struct cvmx_pciercx_cfg012_s cn52xxp1;
502 struct cvmx_pciercx_cfg012_s cn56xx;
503 struct cvmx_pciercx_cfg012_s cn56xxp1;
504 struct cvmx_pciercx_cfg012_s cn61xx;
505 struct cvmx_pciercx_cfg012_s cn63xx;
506 struct cvmx_pciercx_cfg012_s cn63xxp1;
507 struct cvmx_pciercx_cfg012_s cn66xx;
508 struct cvmx_pciercx_cfg012_s cn68xx;
509 struct cvmx_pciercx_cfg012_s cn68xxp1;
510 struct cvmx_pciercx_cfg012_s cnf71xx;
511};
512
513union cvmx_pciercx_cfg013 {
514 uint32_t u32;
515 struct cvmx_pciercx_cfg013_s {
516#ifdef __BIG_ENDIAN_BITFIELD
517 uint32_t reserved_8_31:24;
518 uint32_t cp:8;
519#else
520 uint32_t cp:8;
521 uint32_t reserved_8_31:24;
522#endif
523 } s;
524 struct cvmx_pciercx_cfg013_s cn52xx;
525 struct cvmx_pciercx_cfg013_s cn52xxp1;
526 struct cvmx_pciercx_cfg013_s cn56xx;
527 struct cvmx_pciercx_cfg013_s cn56xxp1;
528 struct cvmx_pciercx_cfg013_s cn61xx;
529 struct cvmx_pciercx_cfg013_s cn63xx;
530 struct cvmx_pciercx_cfg013_s cn63xxp1;
531 struct cvmx_pciercx_cfg013_s cn66xx;
532 struct cvmx_pciercx_cfg013_s cn68xx;
533 struct cvmx_pciercx_cfg013_s cn68xxp1;
534 struct cvmx_pciercx_cfg013_s cnf71xx;
535};
536
537union cvmx_pciercx_cfg014 {
538 uint32_t u32;
539 struct cvmx_pciercx_cfg014_s {
540#ifdef __BIG_ENDIAN_BITFIELD
541 uint32_t reserved_0_31:32;
542#else
543 uint32_t reserved_0_31:32;
544#endif
545 } s;
546 struct cvmx_pciercx_cfg014_s cn52xx;
547 struct cvmx_pciercx_cfg014_s cn52xxp1;
548 struct cvmx_pciercx_cfg014_s cn56xx;
549 struct cvmx_pciercx_cfg014_s cn56xxp1;
550 struct cvmx_pciercx_cfg014_s cn61xx;
551 struct cvmx_pciercx_cfg014_s cn63xx;
552 struct cvmx_pciercx_cfg014_s cn63xxp1;
553 struct cvmx_pciercx_cfg014_s cn66xx;
554 struct cvmx_pciercx_cfg014_s cn68xx;
555 struct cvmx_pciercx_cfg014_s cn68xxp1;
556 struct cvmx_pciercx_cfg014_s cnf71xx;
557};
558
559union cvmx_pciercx_cfg015 {
560 uint32_t u32;
561 struct cvmx_pciercx_cfg015_s {
562#ifdef __BIG_ENDIAN_BITFIELD
563 uint32_t reserved_28_31:4;
564 uint32_t dtsees:1;
565 uint32_t dts:1;
566 uint32_t sdt:1;
567 uint32_t pdt:1;
568 uint32_t fbbe:1;
569 uint32_t sbrst:1;
570 uint32_t mam:1;
571 uint32_t vga16d:1;
572 uint32_t vgae:1;
573 uint32_t isae:1;
574 uint32_t see:1;
575 uint32_t pere:1;
576 uint32_t inta:8;
577 uint32_t il:8;
578#else
579 uint32_t il:8;
580 uint32_t inta:8;
581 uint32_t pere:1;
582 uint32_t see:1;
583 uint32_t isae:1;
584 uint32_t vgae:1;
585 uint32_t vga16d:1;
586 uint32_t mam:1;
587 uint32_t sbrst:1;
588 uint32_t fbbe:1;
589 uint32_t pdt:1;
590 uint32_t sdt:1;
591 uint32_t dts:1;
592 uint32_t dtsees:1;
593 uint32_t reserved_28_31:4;
594#endif
595 } s;
596 struct cvmx_pciercx_cfg015_s cn52xx;
597 struct cvmx_pciercx_cfg015_s cn52xxp1;
598 struct cvmx_pciercx_cfg015_s cn56xx;
599 struct cvmx_pciercx_cfg015_s cn56xxp1;
600 struct cvmx_pciercx_cfg015_s cn61xx;
601 struct cvmx_pciercx_cfg015_s cn63xx;
602 struct cvmx_pciercx_cfg015_s cn63xxp1;
603 struct cvmx_pciercx_cfg015_s cn66xx;
604 struct cvmx_pciercx_cfg015_s cn68xx;
605 struct cvmx_pciercx_cfg015_s cn68xxp1;
606 struct cvmx_pciercx_cfg015_s cnf71xx;
607};
608
609union cvmx_pciercx_cfg016 {
610 uint32_t u32;
611 struct cvmx_pciercx_cfg016_s {
612#ifdef __BIG_ENDIAN_BITFIELD
613 uint32_t pmes:5;
614 uint32_t d2s:1;
615 uint32_t d1s:1;
616 uint32_t auxc:3;
617 uint32_t dsi:1;
618 uint32_t reserved_20_20:1;
619 uint32_t pme_clock:1;
620 uint32_t pmsv:3;
621 uint32_t ncp:8;
622 uint32_t pmcid:8;
623#else
624 uint32_t pmcid:8;
625 uint32_t ncp:8;
626 uint32_t pmsv:3;
627 uint32_t pme_clock:1;
628 uint32_t reserved_20_20:1;
629 uint32_t dsi:1;
630 uint32_t auxc:3;
631 uint32_t d1s:1;
632 uint32_t d2s:1;
633 uint32_t pmes:5;
634#endif
635 } s;
636 struct cvmx_pciercx_cfg016_s cn52xx;
637 struct cvmx_pciercx_cfg016_s cn52xxp1;
638 struct cvmx_pciercx_cfg016_s cn56xx;
639 struct cvmx_pciercx_cfg016_s cn56xxp1;
640 struct cvmx_pciercx_cfg016_s cn61xx;
641 struct cvmx_pciercx_cfg016_s cn63xx;
642 struct cvmx_pciercx_cfg016_s cn63xxp1;
643 struct cvmx_pciercx_cfg016_s cn66xx;
644 struct cvmx_pciercx_cfg016_s cn68xx;
645 struct cvmx_pciercx_cfg016_s cn68xxp1;
646 struct cvmx_pciercx_cfg016_s cnf71xx;
647};
648
649union cvmx_pciercx_cfg017 {
650 uint32_t u32;
651 struct cvmx_pciercx_cfg017_s {
652#ifdef __BIG_ENDIAN_BITFIELD
653 uint32_t pmdia:8;
654 uint32_t bpccee:1;
655 uint32_t bd3h:1;
656 uint32_t reserved_16_21:6;
657 uint32_t pmess:1;
658 uint32_t pmedsia:2;
659 uint32_t pmds:4;
660 uint32_t pmeens:1;
661 uint32_t reserved_4_7:4;
662 uint32_t nsr:1;
663 uint32_t reserved_2_2:1;
664 uint32_t ps:2;
665#else
666 uint32_t ps:2;
667 uint32_t reserved_2_2:1;
668 uint32_t nsr:1;
669 uint32_t reserved_4_7:4;
670 uint32_t pmeens:1;
671 uint32_t pmds:4;
672 uint32_t pmedsia:2;
673 uint32_t pmess:1;
674 uint32_t reserved_16_21:6;
675 uint32_t bd3h:1;
676 uint32_t bpccee:1;
677 uint32_t pmdia:8;
678#endif
679 } s;
680 struct cvmx_pciercx_cfg017_s cn52xx;
681 struct cvmx_pciercx_cfg017_s cn52xxp1;
682 struct cvmx_pciercx_cfg017_s cn56xx;
683 struct cvmx_pciercx_cfg017_s cn56xxp1;
684 struct cvmx_pciercx_cfg017_s cn61xx;
685 struct cvmx_pciercx_cfg017_s cn63xx;
686 struct cvmx_pciercx_cfg017_s cn63xxp1;
687 struct cvmx_pciercx_cfg017_s cn66xx;
688 struct cvmx_pciercx_cfg017_s cn68xx;
689 struct cvmx_pciercx_cfg017_s cn68xxp1;
690 struct cvmx_pciercx_cfg017_s cnf71xx;
691};
692
693union cvmx_pciercx_cfg020 {
694 uint32_t u32;
695 struct cvmx_pciercx_cfg020_s {
696#ifdef __BIG_ENDIAN_BITFIELD
697 uint32_t reserved_25_31:7;
698 uint32_t pvm:1;
699 uint32_t m64:1;
700 uint32_t mme:3;
701 uint32_t mmc:3;
702 uint32_t msien:1;
703 uint32_t ncp:8;
704 uint32_t msicid:8;
705#else
706 uint32_t msicid:8;
707 uint32_t ncp:8;
708 uint32_t msien:1;
709 uint32_t mmc:3;
710 uint32_t mme:3;
711 uint32_t m64:1;
712 uint32_t pvm:1;
713 uint32_t reserved_25_31:7;
714#endif
715 } s;
716 struct cvmx_pciercx_cfg020_cn52xx {
717#ifdef __BIG_ENDIAN_BITFIELD
718 uint32_t reserved_24_31:8;
719 uint32_t m64:1;
720 uint32_t mme:3;
721 uint32_t mmc:3;
722 uint32_t msien:1;
723 uint32_t ncp:8;
724 uint32_t msicid:8;
725#else
726 uint32_t msicid:8;
727 uint32_t ncp:8;
728 uint32_t msien:1;
729 uint32_t mmc:3;
730 uint32_t mme:3;
731 uint32_t m64:1;
732 uint32_t reserved_24_31:8;
733#endif
734 } cn52xx;
735 struct cvmx_pciercx_cfg020_cn52xx cn52xxp1;
736 struct cvmx_pciercx_cfg020_cn52xx cn56xx;
737 struct cvmx_pciercx_cfg020_cn52xx cn56xxp1;
738 struct cvmx_pciercx_cfg020_s cn61xx;
739 struct cvmx_pciercx_cfg020_cn52xx cn63xx;
740 struct cvmx_pciercx_cfg020_cn52xx cn63xxp1;
741 struct cvmx_pciercx_cfg020_cn52xx cn66xx;
742 struct cvmx_pciercx_cfg020_cn52xx cn68xx;
743 struct cvmx_pciercx_cfg020_cn52xx cn68xxp1;
744 struct cvmx_pciercx_cfg020_s cnf71xx;
745};
746
747union cvmx_pciercx_cfg021 {
748 uint32_t u32;
749 struct cvmx_pciercx_cfg021_s {
750#ifdef __BIG_ENDIAN_BITFIELD
751 uint32_t lmsi:30;
752 uint32_t reserved_0_1:2;
753#else
754 uint32_t reserved_0_1:2;
755 uint32_t lmsi:30;
756#endif
757 } s;
758 struct cvmx_pciercx_cfg021_s cn52xx;
759 struct cvmx_pciercx_cfg021_s cn52xxp1;
760 struct cvmx_pciercx_cfg021_s cn56xx;
761 struct cvmx_pciercx_cfg021_s cn56xxp1;
762 struct cvmx_pciercx_cfg021_s cn61xx;
763 struct cvmx_pciercx_cfg021_s cn63xx;
764 struct cvmx_pciercx_cfg021_s cn63xxp1;
765 struct cvmx_pciercx_cfg021_s cn66xx;
766 struct cvmx_pciercx_cfg021_s cn68xx;
767 struct cvmx_pciercx_cfg021_s cn68xxp1;
768 struct cvmx_pciercx_cfg021_s cnf71xx;
769};
770
771union cvmx_pciercx_cfg022 {
772 uint32_t u32;
773 struct cvmx_pciercx_cfg022_s {
774#ifdef __BIG_ENDIAN_BITFIELD
775 uint32_t umsi:32;
776#else
777 uint32_t umsi:32;
778#endif
779 } s;
780 struct cvmx_pciercx_cfg022_s cn52xx;
781 struct cvmx_pciercx_cfg022_s cn52xxp1;
782 struct cvmx_pciercx_cfg022_s cn56xx;
783 struct cvmx_pciercx_cfg022_s cn56xxp1;
784 struct cvmx_pciercx_cfg022_s cn61xx;
785 struct cvmx_pciercx_cfg022_s cn63xx;
786 struct cvmx_pciercx_cfg022_s cn63xxp1;
787 struct cvmx_pciercx_cfg022_s cn66xx;
788 struct cvmx_pciercx_cfg022_s cn68xx;
789 struct cvmx_pciercx_cfg022_s cn68xxp1;
790 struct cvmx_pciercx_cfg022_s cnf71xx;
791};
792
793union cvmx_pciercx_cfg023 {
794 uint32_t u32;
795 struct cvmx_pciercx_cfg023_s {
796#ifdef __BIG_ENDIAN_BITFIELD
797 uint32_t reserved_16_31:16;
798 uint32_t msimd:16;
799#else
800 uint32_t msimd:16;
801 uint32_t reserved_16_31:16;
802#endif
803 } s;
804 struct cvmx_pciercx_cfg023_s cn52xx;
805 struct cvmx_pciercx_cfg023_s cn52xxp1;
806 struct cvmx_pciercx_cfg023_s cn56xx;
807 struct cvmx_pciercx_cfg023_s cn56xxp1;
808 struct cvmx_pciercx_cfg023_s cn61xx;
809 struct cvmx_pciercx_cfg023_s cn63xx;
810 struct cvmx_pciercx_cfg023_s cn63xxp1;
811 struct cvmx_pciercx_cfg023_s cn66xx;
812 struct cvmx_pciercx_cfg023_s cn68xx;
813 struct cvmx_pciercx_cfg023_s cn68xxp1;
814 struct cvmx_pciercx_cfg023_s cnf71xx;
815};
816
817union cvmx_pciercx_cfg028 {
818 uint32_t u32;
819 struct cvmx_pciercx_cfg028_s {
820#ifdef __BIG_ENDIAN_BITFIELD
821 uint32_t reserved_30_31:2;
822 uint32_t imn:5;
823 uint32_t si:1;
824 uint32_t dpt:4;
825 uint32_t pciecv:4;
826 uint32_t ncp:8;
827 uint32_t pcieid:8;
828#else
829 uint32_t pcieid:8;
830 uint32_t ncp:8;
831 uint32_t pciecv:4;
832 uint32_t dpt:4;
833 uint32_t si:1;
834 uint32_t imn:5;
835 uint32_t reserved_30_31:2;
836#endif
837 } s;
838 struct cvmx_pciercx_cfg028_s cn52xx;
839 struct cvmx_pciercx_cfg028_s cn52xxp1;
840 struct cvmx_pciercx_cfg028_s cn56xx;
841 struct cvmx_pciercx_cfg028_s cn56xxp1;
842 struct cvmx_pciercx_cfg028_s cn61xx;
843 struct cvmx_pciercx_cfg028_s cn63xx;
844 struct cvmx_pciercx_cfg028_s cn63xxp1;
845 struct cvmx_pciercx_cfg028_s cn66xx;
846 struct cvmx_pciercx_cfg028_s cn68xx;
847 struct cvmx_pciercx_cfg028_s cn68xxp1;
848 struct cvmx_pciercx_cfg028_s cnf71xx;
849};
850
851union cvmx_pciercx_cfg029 {
852 uint32_t u32;
853 struct cvmx_pciercx_cfg029_s {
854#ifdef __BIG_ENDIAN_BITFIELD
855 uint32_t reserved_28_31:4;
856 uint32_t cspls:2;
857 uint32_t csplv:8;
858 uint32_t reserved_16_17:2;
859 uint32_t rber:1;
860 uint32_t reserved_12_14:3;
861 uint32_t el1al:3;
862 uint32_t el0al:3;
863 uint32_t etfs:1;
864 uint32_t pfs:2;
865 uint32_t mpss:3;
866#else
867 uint32_t mpss:3;
868 uint32_t pfs:2;
869 uint32_t etfs:1;
870 uint32_t el0al:3;
871 uint32_t el1al:3;
872 uint32_t reserved_12_14:3;
873 uint32_t rber:1;
874 uint32_t reserved_16_17:2;
875 uint32_t csplv:8;
876 uint32_t cspls:2;
877 uint32_t reserved_28_31:4;
878#endif
879 } s;
880 struct cvmx_pciercx_cfg029_s cn52xx;
881 struct cvmx_pciercx_cfg029_s cn52xxp1;
882 struct cvmx_pciercx_cfg029_s cn56xx;
883 struct cvmx_pciercx_cfg029_s cn56xxp1;
884 struct cvmx_pciercx_cfg029_s cn61xx;
885 struct cvmx_pciercx_cfg029_s cn63xx;
886 struct cvmx_pciercx_cfg029_s cn63xxp1;
887 struct cvmx_pciercx_cfg029_s cn66xx;
888 struct cvmx_pciercx_cfg029_s cn68xx;
889 struct cvmx_pciercx_cfg029_s cn68xxp1;
890 struct cvmx_pciercx_cfg029_s cnf71xx;
891}; 132};
892 133
893union cvmx_pciercx_cfg030 { 134union cvmx_pciercx_cfg030 {
894 uint32_t u32; 135 uint32_t u32;
895 struct cvmx_pciercx_cfg030_s { 136 struct cvmx_pciercx_cfg030_s {
896#ifdef __BIG_ENDIAN_BITFIELD 137 __BITFIELD_FIELD(uint32_t reserved_22_31:10,
897 uint32_t reserved_22_31:10; 138 __BITFIELD_FIELD(uint32_t tp:1,
898 uint32_t tp:1; 139 __BITFIELD_FIELD(uint32_t ap_d:1,
899 uint32_t ap_d:1; 140 __BITFIELD_FIELD(uint32_t ur_d:1,
900 uint32_t ur_d:1; 141 __BITFIELD_FIELD(uint32_t fe_d:1,
901 uint32_t fe_d:1; 142 __BITFIELD_FIELD(uint32_t nfe_d:1,
902 uint32_t nfe_d:1; 143 __BITFIELD_FIELD(uint32_t ce_d:1,
903 uint32_t ce_d:1; 144 __BITFIELD_FIELD(uint32_t reserved_15_15:1,
904 uint32_t reserved_15_15:1; 145 __BITFIELD_FIELD(uint32_t mrrs:3,
905 uint32_t mrrs:3; 146 __BITFIELD_FIELD(uint32_t ns_en:1,
906 uint32_t ns_en:1; 147 __BITFIELD_FIELD(uint32_t ap_en:1,
907 uint32_t ap_en:1; 148 __BITFIELD_FIELD(uint32_t pf_en:1,
908 uint32_t pf_en:1; 149 __BITFIELD_FIELD(uint32_t etf_en:1,
909 uint32_t etf_en:1; 150 __BITFIELD_FIELD(uint32_t mps:3,
910 uint32_t mps:3; 151 __BITFIELD_FIELD(uint32_t ro_en:1,
911 uint32_t ro_en:1; 152 __BITFIELD_FIELD(uint32_t ur_en:1,
912 uint32_t ur_en:1; 153 __BITFIELD_FIELD(uint32_t fe_en:1,
913 uint32_t fe_en:1; 154 __BITFIELD_FIELD(uint32_t nfe_en:1,
914 uint32_t nfe_en:1; 155 __BITFIELD_FIELD(uint32_t ce_en:1,
915 uint32_t ce_en:1; 156 ;)))))))))))))))))))
916#else
917 uint32_t ce_en:1;
918 uint32_t nfe_en:1;
919 uint32_t fe_en:1;
920 uint32_t ur_en:1;
921 uint32_t ro_en:1;
922 uint32_t mps:3;
923 uint32_t etf_en:1;
924 uint32_t pf_en:1;
925 uint32_t ap_en:1;
926 uint32_t ns_en:1;
927 uint32_t mrrs:3;
928 uint32_t reserved_15_15:1;
929 uint32_t ce_d:1;
930 uint32_t nfe_d:1;
931 uint32_t fe_d:1;
932 uint32_t ur_d:1;
933 uint32_t ap_d:1;
934 uint32_t tp:1;
935 uint32_t reserved_22_31:10;
936#endif
937 } s; 157 } s;
938 struct cvmx_pciercx_cfg030_s cn52xx;
939 struct cvmx_pciercx_cfg030_s cn52xxp1;
940 struct cvmx_pciercx_cfg030_s cn56xx;
941 struct cvmx_pciercx_cfg030_s cn56xxp1;
942 struct cvmx_pciercx_cfg030_s cn61xx;
943 struct cvmx_pciercx_cfg030_s cn63xx;
944 struct cvmx_pciercx_cfg030_s cn63xxp1;
945 struct cvmx_pciercx_cfg030_s cn66xx;
946 struct cvmx_pciercx_cfg030_s cn68xx;
947 struct cvmx_pciercx_cfg030_s cn68xxp1;
948 struct cvmx_pciercx_cfg030_s cnf71xx;
949}; 158};
950 159
951union cvmx_pciercx_cfg031 { 160union cvmx_pciercx_cfg031 {
952 uint32_t u32; 161 uint32_t u32;
953 struct cvmx_pciercx_cfg031_s { 162 struct cvmx_pciercx_cfg031_s {
954#ifdef __BIG_ENDIAN_BITFIELD 163 __BITFIELD_FIELD(uint32_t pnum:8,
955 uint32_t pnum:8; 164 __BITFIELD_FIELD(uint32_t reserved_23_23:1,
956 uint32_t reserved_23_23:1; 165 __BITFIELD_FIELD(uint32_t aspm:1,
957 uint32_t aspm:1; 166 __BITFIELD_FIELD(uint32_t lbnc:1,
958 uint32_t lbnc:1; 167 __BITFIELD_FIELD(uint32_t dllarc:1,
959 uint32_t dllarc:1; 168 __BITFIELD_FIELD(uint32_t sderc:1,
960 uint32_t sderc:1; 169 __BITFIELD_FIELD(uint32_t cpm:1,
961 uint32_t cpm:1; 170 __BITFIELD_FIELD(uint32_t l1el:3,
962 uint32_t l1el:3; 171 __BITFIELD_FIELD(uint32_t l0el:3,
963 uint32_t l0el:3; 172 __BITFIELD_FIELD(uint32_t aslpms:2,
964 uint32_t aslpms:2; 173 __BITFIELD_FIELD(uint32_t mlw:6,
965 uint32_t mlw:6; 174 __BITFIELD_FIELD(uint32_t mls:4,
966 uint32_t mls:4; 175 ;))))))))))))
967#else
968 uint32_t mls:4;
969 uint32_t mlw:6;
970 uint32_t aslpms:2;
971 uint32_t l0el:3;
972 uint32_t l1el:3;
973 uint32_t cpm:1;
974 uint32_t sderc:1;
975 uint32_t dllarc:1;
976 uint32_t lbnc:1;
977 uint32_t aspm:1;
978 uint32_t reserved_23_23:1;
979 uint32_t pnum:8;
980#endif
981 } s; 176 } s;
982 struct cvmx_pciercx_cfg031_cn52xx {
983#ifdef __BIG_ENDIAN_BITFIELD
984 uint32_t pnum:8;
985 uint32_t reserved_22_23:2;
986 uint32_t lbnc:1;
987 uint32_t dllarc:1;
988 uint32_t sderc:1;
989 uint32_t cpm:1;
990 uint32_t l1el:3;
991 uint32_t l0el:3;
992 uint32_t aslpms:2;
993 uint32_t mlw:6;
994 uint32_t mls:4;
995#else
996 uint32_t mls:4;
997 uint32_t mlw:6;
998 uint32_t aslpms:2;
999 uint32_t l0el:3;
1000 uint32_t l1el:3;
1001 uint32_t cpm:1;
1002 uint32_t sderc:1;
1003 uint32_t dllarc:1;
1004 uint32_t lbnc:1;
1005 uint32_t reserved_22_23:2;
1006 uint32_t pnum:8;
1007#endif
1008 } cn52xx;
1009 struct cvmx_pciercx_cfg031_cn52xx cn52xxp1;
1010 struct cvmx_pciercx_cfg031_cn52xx cn56xx;
1011 struct cvmx_pciercx_cfg031_cn52xx cn56xxp1;
1012 struct cvmx_pciercx_cfg031_s cn61xx;
1013 struct cvmx_pciercx_cfg031_cn52xx cn63xx;
1014 struct cvmx_pciercx_cfg031_cn52xx cn63xxp1;
1015 struct cvmx_pciercx_cfg031_s cn66xx;
1016 struct cvmx_pciercx_cfg031_s cn68xx;
1017 struct cvmx_pciercx_cfg031_cn52xx cn68xxp1;
1018 struct cvmx_pciercx_cfg031_s cnf71xx;
1019}; 177};
1020 178
1021union cvmx_pciercx_cfg032 { 179union cvmx_pciercx_cfg032 {
1022 uint32_t u32; 180 uint32_t u32;
1023 struct cvmx_pciercx_cfg032_s { 181 struct cvmx_pciercx_cfg032_s {
1024#ifdef __BIG_ENDIAN_BITFIELD 182 __BITFIELD_FIELD(uint32_t lab:1,
1025 uint32_t lab:1; 183 __BITFIELD_FIELD(uint32_t lbm:1,
1026 uint32_t lbm:1; 184 __BITFIELD_FIELD(uint32_t dlla:1,
1027 uint32_t dlla:1; 185 __BITFIELD_FIELD(uint32_t scc:1,
1028 uint32_t scc:1; 186 __BITFIELD_FIELD(uint32_t lt:1,
1029 uint32_t lt:1; 187 __BITFIELD_FIELD(uint32_t reserved_26_26:1,
1030 uint32_t reserved_26_26:1; 188 __BITFIELD_FIELD(uint32_t nlw:6,
1031 uint32_t nlw:6; 189 __BITFIELD_FIELD(uint32_t ls:4,
1032 uint32_t ls:4; 190 __BITFIELD_FIELD(uint32_t reserved_12_15:4,
1033 uint32_t reserved_12_15:4; 191 __BITFIELD_FIELD(uint32_t lab_int_enb:1,
1034 uint32_t lab_int_enb:1; 192 __BITFIELD_FIELD(uint32_t lbm_int_enb:1,
1035 uint32_t lbm_int_enb:1; 193 __BITFIELD_FIELD(uint32_t hawd:1,
1036 uint32_t hawd:1; 194 __BITFIELD_FIELD(uint32_t ecpm:1,
1037 uint32_t ecpm:1; 195 __BITFIELD_FIELD(uint32_t es:1,
1038 uint32_t es:1; 196 __BITFIELD_FIELD(uint32_t ccc:1,
1039 uint32_t ccc:1; 197 __BITFIELD_FIELD(uint32_t rl:1,
1040 uint32_t rl:1; 198 __BITFIELD_FIELD(uint32_t ld:1,
1041 uint32_t ld:1; 199 __BITFIELD_FIELD(uint32_t rcb:1,
1042 uint32_t rcb:1; 200 __BITFIELD_FIELD(uint32_t reserved_2_2:1,
1043 uint32_t reserved_2_2:1; 201 __BITFIELD_FIELD(uint32_t aslpc:2,
1044 uint32_t aslpc:2; 202 ;))))))))))))))))))))
1045#else
1046 uint32_t aslpc:2;
1047 uint32_t reserved_2_2:1;
1048 uint32_t rcb:1;
1049 uint32_t ld:1;
1050 uint32_t rl:1;
1051 uint32_t ccc:1;
1052 uint32_t es:1;
1053 uint32_t ecpm:1;
1054 uint32_t hawd:1;
1055 uint32_t lbm_int_enb:1;
1056 uint32_t lab_int_enb:1;
1057 uint32_t reserved_12_15:4;
1058 uint32_t ls:4;
1059 uint32_t nlw:6;
1060 uint32_t reserved_26_26:1;
1061 uint32_t lt:1;
1062 uint32_t scc:1;
1063 uint32_t dlla:1;
1064 uint32_t lbm:1;
1065 uint32_t lab:1;
1066#endif
1067 } s;
1068 struct cvmx_pciercx_cfg032_s cn52xx;
1069 struct cvmx_pciercx_cfg032_s cn52xxp1;
1070 struct cvmx_pciercx_cfg032_s cn56xx;
1071 struct cvmx_pciercx_cfg032_s cn56xxp1;
1072 struct cvmx_pciercx_cfg032_s cn61xx;
1073 struct cvmx_pciercx_cfg032_s cn63xx;
1074 struct cvmx_pciercx_cfg032_s cn63xxp1;
1075 struct cvmx_pciercx_cfg032_s cn66xx;
1076 struct cvmx_pciercx_cfg032_s cn68xx;
1077 struct cvmx_pciercx_cfg032_s cn68xxp1;
1078 struct cvmx_pciercx_cfg032_s cnf71xx;
1079};
1080
1081union cvmx_pciercx_cfg033 {
1082 uint32_t u32;
1083 struct cvmx_pciercx_cfg033_s {
1084#ifdef __BIG_ENDIAN_BITFIELD
1085 uint32_t ps_num:13;
1086 uint32_t nccs:1;
1087 uint32_t emip:1;
1088 uint32_t sp_ls:2;
1089 uint32_t sp_lv:8;
1090 uint32_t hp_c:1;
1091 uint32_t hp_s:1;
1092 uint32_t pip:1;
1093 uint32_t aip:1;
1094 uint32_t mrlsp:1;
1095 uint32_t pcp:1;
1096 uint32_t abp:1;
1097#else
1098 uint32_t abp:1;
1099 uint32_t pcp:1;
1100 uint32_t mrlsp:1;
1101 uint32_t aip:1;
1102 uint32_t pip:1;
1103 uint32_t hp_s:1;
1104 uint32_t hp_c:1;
1105 uint32_t sp_lv:8;
1106 uint32_t sp_ls:2;
1107 uint32_t emip:1;
1108 uint32_t nccs:1;
1109 uint32_t ps_num:13;
1110#endif
1111 } s; 203 } s;
1112 struct cvmx_pciercx_cfg033_s cn52xx;
1113 struct cvmx_pciercx_cfg033_s cn52xxp1;
1114 struct cvmx_pciercx_cfg033_s cn56xx;
1115 struct cvmx_pciercx_cfg033_s cn56xxp1;
1116 struct cvmx_pciercx_cfg033_s cn61xx;
1117 struct cvmx_pciercx_cfg033_s cn63xx;
1118 struct cvmx_pciercx_cfg033_s cn63xxp1;
1119 struct cvmx_pciercx_cfg033_s cn66xx;
1120 struct cvmx_pciercx_cfg033_s cn68xx;
1121 struct cvmx_pciercx_cfg033_s cn68xxp1;
1122 struct cvmx_pciercx_cfg033_s cnf71xx;
1123}; 204};
1124 205
1125union cvmx_pciercx_cfg034 { 206union cvmx_pciercx_cfg034 {
1126 uint32_t u32; 207 uint32_t u32;
1127 struct cvmx_pciercx_cfg034_s { 208 struct cvmx_pciercx_cfg034_s {
1128#ifdef __BIG_ENDIAN_BITFIELD 209 __BITFIELD_FIELD(uint32_t reserved_25_31:7,
1129 uint32_t reserved_25_31:7; 210 __BITFIELD_FIELD(uint32_t dlls_c:1,
1130 uint32_t dlls_c:1; 211 __BITFIELD_FIELD(uint32_t emis:1,
1131 uint32_t emis:1; 212 __BITFIELD_FIELD(uint32_t pds:1,
1132 uint32_t pds:1; 213 __BITFIELD_FIELD(uint32_t mrlss:1,
1133 uint32_t mrlss:1; 214 __BITFIELD_FIELD(uint32_t ccint_d:1,
1134 uint32_t ccint_d:1; 215 __BITFIELD_FIELD(uint32_t pd_c:1,
1135 uint32_t pd_c:1; 216 __BITFIELD_FIELD(uint32_t mrls_c:1,
1136 uint32_t mrls_c:1; 217 __BITFIELD_FIELD(uint32_t pf_d:1,
1137 uint32_t pf_d:1; 218 __BITFIELD_FIELD(uint32_t abp_d:1,
1138 uint32_t abp_d:1; 219 __BITFIELD_FIELD(uint32_t reserved_13_15:3,
1139 uint32_t reserved_13_15:3; 220 __BITFIELD_FIELD(uint32_t dlls_en:1,
1140 uint32_t dlls_en:1; 221 __BITFIELD_FIELD(uint32_t emic:1,
1141 uint32_t emic:1; 222 __BITFIELD_FIELD(uint32_t pcc:1,
1142 uint32_t pcc:1; 223 __BITFIELD_FIELD(uint32_t pic:1,
1143 uint32_t pic:2; 224 __BITFIELD_FIELD(uint32_t aic:1,
1144 uint32_t aic:2; 225 __BITFIELD_FIELD(uint32_t hpint_en:1,
1145 uint32_t hpint_en:1; 226 __BITFIELD_FIELD(uint32_t ccint_en:1,
1146 uint32_t ccint_en:1; 227 __BITFIELD_FIELD(uint32_t pd_en:1,
1147 uint32_t pd_en:1; 228 __BITFIELD_FIELD(uint32_t mrls_en:1,
1148 uint32_t mrls_en:1; 229 __BITFIELD_FIELD(uint32_t pf_en:1,
1149 uint32_t pf_en:1; 230 __BITFIELD_FIELD(uint32_t abp_en:1,
1150 uint32_t abp_en:1; 231 ;))))))))))))))))))))))
1151#else
1152 uint32_t abp_en:1;
1153 uint32_t pf_en:1;
1154 uint32_t mrls_en:1;
1155 uint32_t pd_en:1;
1156 uint32_t ccint_en:1;
1157 uint32_t hpint_en:1;
1158 uint32_t aic:2;
1159 uint32_t pic:2;
1160 uint32_t pcc:1;
1161 uint32_t emic:1;
1162 uint32_t dlls_en:1;
1163 uint32_t reserved_13_15:3;
1164 uint32_t abp_d:1;
1165 uint32_t pf_d:1;
1166 uint32_t mrls_c:1;
1167 uint32_t pd_c:1;
1168 uint32_t ccint_d:1;
1169 uint32_t mrlss:1;
1170 uint32_t pds:1;
1171 uint32_t emis:1;
1172 uint32_t dlls_c:1;
1173 uint32_t reserved_25_31:7;
1174#endif
1175 } s; 232 } s;
1176 struct cvmx_pciercx_cfg034_s cn52xx;
1177 struct cvmx_pciercx_cfg034_s cn52xxp1;
1178 struct cvmx_pciercx_cfg034_s cn56xx;
1179 struct cvmx_pciercx_cfg034_s cn56xxp1;
1180 struct cvmx_pciercx_cfg034_s cn61xx;
1181 struct cvmx_pciercx_cfg034_s cn63xx;
1182 struct cvmx_pciercx_cfg034_s cn63xxp1;
1183 struct cvmx_pciercx_cfg034_s cn66xx;
1184 struct cvmx_pciercx_cfg034_s cn68xx;
1185 struct cvmx_pciercx_cfg034_s cn68xxp1;
1186 struct cvmx_pciercx_cfg034_s cnf71xx;
1187}; 233};
1188 234
1189union cvmx_pciercx_cfg035 { 235union cvmx_pciercx_cfg035 {
1190 uint32_t u32; 236 uint32_t u32;
1191 struct cvmx_pciercx_cfg035_s { 237 struct cvmx_pciercx_cfg035_s {
1192#ifdef __BIG_ENDIAN_BITFIELD 238 __BITFIELD_FIELD(uint32_t reserved_17_31:15,
1193 uint32_t reserved_17_31:15; 239 __BITFIELD_FIELD(uint32_t crssv:1,
1194 uint32_t crssv:1; 240 __BITFIELD_FIELD(uint32_t reserved_5_15:11,
1195 uint32_t reserved_5_15:11; 241 __BITFIELD_FIELD(uint32_t crssve:1,
1196 uint32_t crssve:1; 242 __BITFIELD_FIELD(uint32_t pmeie:1,
1197 uint32_t pmeie:1; 243 __BITFIELD_FIELD(uint32_t sefee:1,
1198 uint32_t sefee:1; 244 __BITFIELD_FIELD(uint32_t senfee:1,
1199 uint32_t senfee:1; 245 __BITFIELD_FIELD(uint32_t secee:1,
1200 uint32_t secee:1; 246 ;))))))))
1201#else
1202 uint32_t secee:1;
1203 uint32_t senfee:1;
1204 uint32_t sefee:1;
1205 uint32_t pmeie:1;
1206 uint32_t crssve:1;
1207 uint32_t reserved_5_15:11;
1208 uint32_t crssv:1;
1209 uint32_t reserved_17_31:15;
1210#endif
1211 } s;
1212 struct cvmx_pciercx_cfg035_s cn52xx;
1213 struct cvmx_pciercx_cfg035_s cn52xxp1;
1214 struct cvmx_pciercx_cfg035_s cn56xx;
1215 struct cvmx_pciercx_cfg035_s cn56xxp1;
1216 struct cvmx_pciercx_cfg035_s cn61xx;
1217 struct cvmx_pciercx_cfg035_s cn63xx;
1218 struct cvmx_pciercx_cfg035_s cn63xxp1;
1219 struct cvmx_pciercx_cfg035_s cn66xx;
1220 struct cvmx_pciercx_cfg035_s cn68xx;
1221 struct cvmx_pciercx_cfg035_s cn68xxp1;
1222 struct cvmx_pciercx_cfg035_s cnf71xx;
1223};
1224
1225union cvmx_pciercx_cfg036 {
1226 uint32_t u32;
1227 struct cvmx_pciercx_cfg036_s {
1228#ifdef __BIG_ENDIAN_BITFIELD
1229 uint32_t reserved_18_31:14;
1230 uint32_t pme_pend:1;
1231 uint32_t pme_stat:1;
1232 uint32_t pme_rid:16;
1233#else
1234 uint32_t pme_rid:16;
1235 uint32_t pme_stat:1;
1236 uint32_t pme_pend:1;
1237 uint32_t reserved_18_31:14;
1238#endif
1239 } s;
1240 struct cvmx_pciercx_cfg036_s cn52xx;
1241 struct cvmx_pciercx_cfg036_s cn52xxp1;
1242 struct cvmx_pciercx_cfg036_s cn56xx;
1243 struct cvmx_pciercx_cfg036_s cn56xxp1;
1244 struct cvmx_pciercx_cfg036_s cn61xx;
1245 struct cvmx_pciercx_cfg036_s cn63xx;
1246 struct cvmx_pciercx_cfg036_s cn63xxp1;
1247 struct cvmx_pciercx_cfg036_s cn66xx;
1248 struct cvmx_pciercx_cfg036_s cn68xx;
1249 struct cvmx_pciercx_cfg036_s cn68xxp1;
1250 struct cvmx_pciercx_cfg036_s cnf71xx;
1251};
1252
1253union cvmx_pciercx_cfg037 {
1254 uint32_t u32;
1255 struct cvmx_pciercx_cfg037_s {
1256#ifdef __BIG_ENDIAN_BITFIELD
1257 uint32_t reserved_20_31:12;
1258 uint32_t obffs:2;
1259 uint32_t reserved_12_17:6;
1260 uint32_t ltrs:1;
1261 uint32_t noroprpr:1;
1262 uint32_t atom128s:1;
1263 uint32_t atom64s:1;
1264 uint32_t atom32s:1;
1265 uint32_t atom_ops:1;
1266 uint32_t reserved_5_5:1;
1267 uint32_t ctds:1;
1268 uint32_t ctrs:4;
1269#else
1270 uint32_t ctrs:4;
1271 uint32_t ctds:1;
1272 uint32_t reserved_5_5:1;
1273 uint32_t atom_ops:1;
1274 uint32_t atom32s:1;
1275 uint32_t atom64s:1;
1276 uint32_t atom128s:1;
1277 uint32_t noroprpr:1;
1278 uint32_t ltrs:1;
1279 uint32_t reserved_12_17:6;
1280 uint32_t obffs:2;
1281 uint32_t reserved_20_31:12;
1282#endif
1283 } s;
1284 struct cvmx_pciercx_cfg037_cn52xx {
1285#ifdef __BIG_ENDIAN_BITFIELD
1286 uint32_t reserved_5_31:27;
1287 uint32_t ctds:1;
1288 uint32_t ctrs:4;
1289#else
1290 uint32_t ctrs:4;
1291 uint32_t ctds:1;
1292 uint32_t reserved_5_31:27;
1293#endif
1294 } cn52xx;
1295 struct cvmx_pciercx_cfg037_cn52xx cn52xxp1;
1296 struct cvmx_pciercx_cfg037_cn52xx cn56xx;
1297 struct cvmx_pciercx_cfg037_cn52xx cn56xxp1;
1298 struct cvmx_pciercx_cfg037_cn61xx {
1299#ifdef __BIG_ENDIAN_BITFIELD
1300 uint32_t reserved_14_31:18;
1301 uint32_t tph:2;
1302 uint32_t reserved_11_11:1;
1303 uint32_t noroprpr:1;
1304 uint32_t atom128s:1;
1305 uint32_t atom64s:1;
1306 uint32_t atom32s:1;
1307 uint32_t atom_ops:1;
1308 uint32_t ari_fw:1;
1309 uint32_t ctds:1;
1310 uint32_t ctrs:4;
1311#else
1312 uint32_t ctrs:4;
1313 uint32_t ctds:1;
1314 uint32_t ari_fw:1;
1315 uint32_t atom_ops:1;
1316 uint32_t atom32s:1;
1317 uint32_t atom64s:1;
1318 uint32_t atom128s:1;
1319 uint32_t noroprpr:1;
1320 uint32_t reserved_11_11:1;
1321 uint32_t tph:2;
1322 uint32_t reserved_14_31:18;
1323#endif
1324 } cn61xx;
1325 struct cvmx_pciercx_cfg037_cn52xx cn63xx;
1326 struct cvmx_pciercx_cfg037_cn52xx cn63xxp1;
1327 struct cvmx_pciercx_cfg037_cn66xx {
1328#ifdef __BIG_ENDIAN_BITFIELD
1329 uint32_t reserved_14_31:18;
1330 uint32_t tph:2;
1331 uint32_t reserved_11_11:1;
1332 uint32_t noroprpr:1;
1333 uint32_t atom128s:1;
1334 uint32_t atom64s:1;
1335 uint32_t atom32s:1;
1336 uint32_t atom_ops:1;
1337 uint32_t ari:1;
1338 uint32_t ctds:1;
1339 uint32_t ctrs:4;
1340#else
1341 uint32_t ctrs:4;
1342 uint32_t ctds:1;
1343 uint32_t ari:1;
1344 uint32_t atom_ops:1;
1345 uint32_t atom32s:1;
1346 uint32_t atom64s:1;
1347 uint32_t atom128s:1;
1348 uint32_t noroprpr:1;
1349 uint32_t reserved_11_11:1;
1350 uint32_t tph:2;
1351 uint32_t reserved_14_31:18;
1352#endif
1353 } cn66xx;
1354 struct cvmx_pciercx_cfg037_cn66xx cn68xx;
1355 struct cvmx_pciercx_cfg037_cn66xx cn68xxp1;
1356 struct cvmx_pciercx_cfg037_cnf71xx {
1357#ifdef __BIG_ENDIAN_BITFIELD
1358 uint32_t reserved_20_31:12;
1359 uint32_t obffs:2;
1360 uint32_t reserved_14_17:4;
1361 uint32_t tphs:2;
1362 uint32_t ltrs:1;
1363 uint32_t noroprpr:1;
1364 uint32_t atom128s:1;
1365 uint32_t atom64s:1;
1366 uint32_t atom32s:1;
1367 uint32_t atom_ops:1;
1368 uint32_t ari_fw:1;
1369 uint32_t ctds:1;
1370 uint32_t ctrs:4;
1371#else
1372 uint32_t ctrs:4;
1373 uint32_t ctds:1;
1374 uint32_t ari_fw:1;
1375 uint32_t atom_ops:1;
1376 uint32_t atom32s:1;
1377 uint32_t atom64s:1;
1378 uint32_t atom128s:1;
1379 uint32_t noroprpr:1;
1380 uint32_t ltrs:1;
1381 uint32_t tphs:2;
1382 uint32_t reserved_14_17:4;
1383 uint32_t obffs:2;
1384 uint32_t reserved_20_31:12;
1385#endif
1386 } cnf71xx;
1387};
1388
1389union cvmx_pciercx_cfg038 {
1390 uint32_t u32;
1391 struct cvmx_pciercx_cfg038_s {
1392#ifdef __BIG_ENDIAN_BITFIELD
1393 uint32_t reserved_15_31:17;
1394 uint32_t obffe:2;
1395 uint32_t reserved_11_12:2;
1396 uint32_t ltre:1;
1397 uint32_t id0_cp:1;
1398 uint32_t id0_rq:1;
1399 uint32_t atom_op_eb:1;
1400 uint32_t atom_op:1;
1401 uint32_t ari:1;
1402 uint32_t ctd:1;
1403 uint32_t ctv:4;
1404#else
1405 uint32_t ctv:4;
1406 uint32_t ctd:1;
1407 uint32_t ari:1;
1408 uint32_t atom_op:1;
1409 uint32_t atom_op_eb:1;
1410 uint32_t id0_rq:1;
1411 uint32_t id0_cp:1;
1412 uint32_t ltre:1;
1413 uint32_t reserved_11_12:2;
1414 uint32_t obffe:2;
1415 uint32_t reserved_15_31:17;
1416#endif
1417 } s; 247 } s;
1418 struct cvmx_pciercx_cfg038_cn52xx {
1419#ifdef __BIG_ENDIAN_BITFIELD
1420 uint32_t reserved_5_31:27;
1421 uint32_t ctd:1;
1422 uint32_t ctv:4;
1423#else
1424 uint32_t ctv:4;
1425 uint32_t ctd:1;
1426 uint32_t reserved_5_31:27;
1427#endif
1428 } cn52xx;
1429 struct cvmx_pciercx_cfg038_cn52xx cn52xxp1;
1430 struct cvmx_pciercx_cfg038_cn52xx cn56xx;
1431 struct cvmx_pciercx_cfg038_cn52xx cn56xxp1;
1432 struct cvmx_pciercx_cfg038_cn61xx {
1433#ifdef __BIG_ENDIAN_BITFIELD
1434 uint32_t reserved_10_31:22;
1435 uint32_t id0_cp:1;
1436 uint32_t id0_rq:1;
1437 uint32_t atom_op_eb:1;
1438 uint32_t atom_op:1;
1439 uint32_t ari:1;
1440 uint32_t ctd:1;
1441 uint32_t ctv:4;
1442#else
1443 uint32_t ctv:4;
1444 uint32_t ctd:1;
1445 uint32_t ari:1;
1446 uint32_t atom_op:1;
1447 uint32_t atom_op_eb:1;
1448 uint32_t id0_rq:1;
1449 uint32_t id0_cp:1;
1450 uint32_t reserved_10_31:22;
1451#endif
1452 } cn61xx;
1453 struct cvmx_pciercx_cfg038_cn52xx cn63xx;
1454 struct cvmx_pciercx_cfg038_cn52xx cn63xxp1;
1455 struct cvmx_pciercx_cfg038_cn61xx cn66xx;
1456 struct cvmx_pciercx_cfg038_cn61xx cn68xx;
1457 struct cvmx_pciercx_cfg038_cn61xx cn68xxp1;
1458 struct cvmx_pciercx_cfg038_s cnf71xx;
1459};
1460
1461union cvmx_pciercx_cfg039 {
1462 uint32_t u32;
1463 struct cvmx_pciercx_cfg039_s {
1464#ifdef __BIG_ENDIAN_BITFIELD
1465 uint32_t reserved_9_31:23;
1466 uint32_t cls:1;
1467 uint32_t slsv:7;
1468 uint32_t reserved_0_0:1;
1469#else
1470 uint32_t reserved_0_0:1;
1471 uint32_t slsv:7;
1472 uint32_t cls:1;
1473 uint32_t reserved_9_31:23;
1474#endif
1475 } s;
1476 struct cvmx_pciercx_cfg039_cn52xx {
1477#ifdef __BIG_ENDIAN_BITFIELD
1478 uint32_t reserved_0_31:32;
1479#else
1480 uint32_t reserved_0_31:32;
1481#endif
1482 } cn52xx;
1483 struct cvmx_pciercx_cfg039_cn52xx cn52xxp1;
1484 struct cvmx_pciercx_cfg039_cn52xx cn56xx;
1485 struct cvmx_pciercx_cfg039_cn52xx cn56xxp1;
1486 struct cvmx_pciercx_cfg039_s cn61xx;
1487 struct cvmx_pciercx_cfg039_s cn63xx;
1488 struct cvmx_pciercx_cfg039_cn52xx cn63xxp1;
1489 struct cvmx_pciercx_cfg039_s cn66xx;
1490 struct cvmx_pciercx_cfg039_s cn68xx;
1491 struct cvmx_pciercx_cfg039_s cn68xxp1;
1492 struct cvmx_pciercx_cfg039_s cnf71xx;
1493}; 248};
1494 249
1495union cvmx_pciercx_cfg040 { 250union cvmx_pciercx_cfg040 {
1496 uint32_t u32; 251 uint32_t u32;
1497 struct cvmx_pciercx_cfg040_s { 252 struct cvmx_pciercx_cfg040_s {
1498#ifdef __BIG_ENDIAN_BITFIELD 253 __BITFIELD_FIELD(uint32_t reserved_22_31:10,
1499 uint32_t reserved_17_31:15; 254 __BITFIELD_FIELD(uint32_t ler:1,
1500 uint32_t cdl:1; 255 __BITFIELD_FIELD(uint32_t ep3s:1,
1501 uint32_t reserved_13_15:3; 256 __BITFIELD_FIELD(uint32_t ep2s:1,
1502 uint32_t cde:1; 257 __BITFIELD_FIELD(uint32_t ep1s:1,
1503 uint32_t csos:1; 258 __BITFIELD_FIELD(uint32_t eqc:1,
1504 uint32_t emc:1; 259 __BITFIELD_FIELD(uint32_t cdl:1,
1505 uint32_t tm:3; 260 __BITFIELD_FIELD(uint32_t cde:4,
1506 uint32_t sde:1; 261 __BITFIELD_FIELD(uint32_t csos:1,
1507 uint32_t hasd:1; 262 __BITFIELD_FIELD(uint32_t emc:1,
1508 uint32_t ec:1; 263 __BITFIELD_FIELD(uint32_t tm:3,
1509 uint32_t tls:4; 264 __BITFIELD_FIELD(uint32_t sde:1,
1510#else 265 __BITFIELD_FIELD(uint32_t hasd:1,
1511 uint32_t tls:4; 266 __BITFIELD_FIELD(uint32_t ec:1,
1512 uint32_t ec:1; 267 __BITFIELD_FIELD(uint32_t tls:4,
1513 uint32_t hasd:1; 268 ;)))))))))))))))
1514 uint32_t sde:1;
1515 uint32_t tm:3;
1516 uint32_t emc:1;
1517 uint32_t csos:1;
1518 uint32_t cde:1;
1519 uint32_t reserved_13_15:3;
1520 uint32_t cdl:1;
1521 uint32_t reserved_17_31:15;
1522#endif
1523 } s;
1524 struct cvmx_pciercx_cfg040_cn52xx {
1525#ifdef __BIG_ENDIAN_BITFIELD
1526 uint32_t reserved_0_31:32;
1527#else
1528 uint32_t reserved_0_31:32;
1529#endif
1530 } cn52xx;
1531 struct cvmx_pciercx_cfg040_cn52xx cn52xxp1;
1532 struct cvmx_pciercx_cfg040_cn52xx cn56xx;
1533 struct cvmx_pciercx_cfg040_cn52xx cn56xxp1;
1534 struct cvmx_pciercx_cfg040_s cn61xx;
1535 struct cvmx_pciercx_cfg040_s cn63xx;
1536 struct cvmx_pciercx_cfg040_s cn63xxp1;
1537 struct cvmx_pciercx_cfg040_s cn66xx;
1538 struct cvmx_pciercx_cfg040_s cn68xx;
1539 struct cvmx_pciercx_cfg040_s cn68xxp1;
1540 struct cvmx_pciercx_cfg040_s cnf71xx;
1541};
1542
1543union cvmx_pciercx_cfg041 {
1544 uint32_t u32;
1545 struct cvmx_pciercx_cfg041_s {
1546#ifdef __BIG_ENDIAN_BITFIELD
1547 uint32_t reserved_0_31:32;
1548#else
1549 uint32_t reserved_0_31:32;
1550#endif
1551 } s;
1552 struct cvmx_pciercx_cfg041_s cn52xx;
1553 struct cvmx_pciercx_cfg041_s cn52xxp1;
1554 struct cvmx_pciercx_cfg041_s cn56xx;
1555 struct cvmx_pciercx_cfg041_s cn56xxp1;
1556 struct cvmx_pciercx_cfg041_s cn61xx;
1557 struct cvmx_pciercx_cfg041_s cn63xx;
1558 struct cvmx_pciercx_cfg041_s cn63xxp1;
1559 struct cvmx_pciercx_cfg041_s cn66xx;
1560 struct cvmx_pciercx_cfg041_s cn68xx;
1561 struct cvmx_pciercx_cfg041_s cn68xxp1;
1562 struct cvmx_pciercx_cfg041_s cnf71xx;
1563};
1564
1565union cvmx_pciercx_cfg042 {
1566 uint32_t u32;
1567 struct cvmx_pciercx_cfg042_s {
1568#ifdef __BIG_ENDIAN_BITFIELD
1569 uint32_t reserved_0_31:32;
1570#else
1571 uint32_t reserved_0_31:32;
1572#endif
1573 } s; 269 } s;
1574 struct cvmx_pciercx_cfg042_s cn52xx;
1575 struct cvmx_pciercx_cfg042_s cn52xxp1;
1576 struct cvmx_pciercx_cfg042_s cn56xx;
1577 struct cvmx_pciercx_cfg042_s cn56xxp1;
1578 struct cvmx_pciercx_cfg042_s cn61xx;
1579 struct cvmx_pciercx_cfg042_s cn63xx;
1580 struct cvmx_pciercx_cfg042_s cn63xxp1;
1581 struct cvmx_pciercx_cfg042_s cn66xx;
1582 struct cvmx_pciercx_cfg042_s cn68xx;
1583 struct cvmx_pciercx_cfg042_s cn68xxp1;
1584 struct cvmx_pciercx_cfg042_s cnf71xx;
1585};
1586
1587union cvmx_pciercx_cfg064 {
1588 uint32_t u32;
1589 struct cvmx_pciercx_cfg064_s {
1590#ifdef __BIG_ENDIAN_BITFIELD
1591 uint32_t nco:12;
1592 uint32_t cv:4;
1593 uint32_t pcieec:16;
1594#else
1595 uint32_t pcieec:16;
1596 uint32_t cv:4;
1597 uint32_t nco:12;
1598#endif
1599 } s;
1600 struct cvmx_pciercx_cfg064_s cn52xx;
1601 struct cvmx_pciercx_cfg064_s cn52xxp1;
1602 struct cvmx_pciercx_cfg064_s cn56xx;
1603 struct cvmx_pciercx_cfg064_s cn56xxp1;
1604 struct cvmx_pciercx_cfg064_s cn61xx;
1605 struct cvmx_pciercx_cfg064_s cn63xx;
1606 struct cvmx_pciercx_cfg064_s cn63xxp1;
1607 struct cvmx_pciercx_cfg064_s cn66xx;
1608 struct cvmx_pciercx_cfg064_s cn68xx;
1609 struct cvmx_pciercx_cfg064_s cn68xxp1;
1610 struct cvmx_pciercx_cfg064_s cnf71xx;
1611};
1612
1613union cvmx_pciercx_cfg065 {
1614 uint32_t u32;
1615 struct cvmx_pciercx_cfg065_s {
1616#ifdef __BIG_ENDIAN_BITFIELD
1617 uint32_t reserved_25_31:7;
1618 uint32_t uatombs:1;
1619 uint32_t reserved_23_23:1;
1620 uint32_t ucies:1;
1621 uint32_t reserved_21_21:1;
1622 uint32_t ures:1;
1623 uint32_t ecrces:1;
1624 uint32_t mtlps:1;
1625 uint32_t ros:1;
1626 uint32_t ucs:1;
1627 uint32_t cas:1;
1628 uint32_t cts:1;
1629 uint32_t fcpes:1;
1630 uint32_t ptlps:1;
1631 uint32_t reserved_6_11:6;
1632 uint32_t sdes:1;
1633 uint32_t dlpes:1;
1634 uint32_t reserved_0_3:4;
1635#else
1636 uint32_t reserved_0_3:4;
1637 uint32_t dlpes:1;
1638 uint32_t sdes:1;
1639 uint32_t reserved_6_11:6;
1640 uint32_t ptlps:1;
1641 uint32_t fcpes:1;
1642 uint32_t cts:1;
1643 uint32_t cas:1;
1644 uint32_t ucs:1;
1645 uint32_t ros:1;
1646 uint32_t mtlps:1;
1647 uint32_t ecrces:1;
1648 uint32_t ures:1;
1649 uint32_t reserved_21_21:1;
1650 uint32_t ucies:1;
1651 uint32_t reserved_23_23:1;
1652 uint32_t uatombs:1;
1653 uint32_t reserved_25_31:7;
1654#endif
1655 } s;
1656 struct cvmx_pciercx_cfg065_cn52xx {
1657#ifdef __BIG_ENDIAN_BITFIELD
1658 uint32_t reserved_21_31:11;
1659 uint32_t ures:1;
1660 uint32_t ecrces:1;
1661 uint32_t mtlps:1;
1662 uint32_t ros:1;
1663 uint32_t ucs:1;
1664 uint32_t cas:1;
1665 uint32_t cts:1;
1666 uint32_t fcpes:1;
1667 uint32_t ptlps:1;
1668 uint32_t reserved_6_11:6;
1669 uint32_t sdes:1;
1670 uint32_t dlpes:1;
1671 uint32_t reserved_0_3:4;
1672#else
1673 uint32_t reserved_0_3:4;
1674 uint32_t dlpes:1;
1675 uint32_t sdes:1;
1676 uint32_t reserved_6_11:6;
1677 uint32_t ptlps:1;
1678 uint32_t fcpes:1;
1679 uint32_t cts:1;
1680 uint32_t cas:1;
1681 uint32_t ucs:1;
1682 uint32_t ros:1;
1683 uint32_t mtlps:1;
1684 uint32_t ecrces:1;
1685 uint32_t ures:1;
1686 uint32_t reserved_21_31:11;
1687#endif
1688 } cn52xx;
1689 struct cvmx_pciercx_cfg065_cn52xx cn52xxp1;
1690 struct cvmx_pciercx_cfg065_cn52xx cn56xx;
1691 struct cvmx_pciercx_cfg065_cn52xx cn56xxp1;
1692 struct cvmx_pciercx_cfg065_cn61xx {
1693#ifdef __BIG_ENDIAN_BITFIELD
1694 uint32_t reserved_25_31:7;
1695 uint32_t uatombs:1;
1696 uint32_t reserved_21_23:3;
1697 uint32_t ures:1;
1698 uint32_t ecrces:1;
1699 uint32_t mtlps:1;
1700 uint32_t ros:1;
1701 uint32_t ucs:1;
1702 uint32_t cas:1;
1703 uint32_t cts:1;
1704 uint32_t fcpes:1;
1705 uint32_t ptlps:1;
1706 uint32_t reserved_6_11:6;
1707 uint32_t sdes:1;
1708 uint32_t dlpes:1;
1709 uint32_t reserved_0_3:4;
1710#else
1711 uint32_t reserved_0_3:4;
1712 uint32_t dlpes:1;
1713 uint32_t sdes:1;
1714 uint32_t reserved_6_11:6;
1715 uint32_t ptlps:1;
1716 uint32_t fcpes:1;
1717 uint32_t cts:1;
1718 uint32_t cas:1;
1719 uint32_t ucs:1;
1720 uint32_t ros:1;
1721 uint32_t mtlps:1;
1722 uint32_t ecrces:1;
1723 uint32_t ures:1;
1724 uint32_t reserved_21_23:3;
1725 uint32_t uatombs:1;
1726 uint32_t reserved_25_31:7;
1727#endif
1728 } cn61xx;
1729 struct cvmx_pciercx_cfg065_cn52xx cn63xx;
1730 struct cvmx_pciercx_cfg065_cn52xx cn63xxp1;
1731 struct cvmx_pciercx_cfg065_cn61xx cn66xx;
1732 struct cvmx_pciercx_cfg065_cn61xx cn68xx;
1733 struct cvmx_pciercx_cfg065_cn52xx cn68xxp1;
1734 struct cvmx_pciercx_cfg065_s cnf71xx;
1735};
1736
1737union cvmx_pciercx_cfg066 {
1738 uint32_t u32;
1739 struct cvmx_pciercx_cfg066_s {
1740#ifdef __BIG_ENDIAN_BITFIELD
1741 uint32_t reserved_25_31:7;
1742 uint32_t uatombm:1;
1743 uint32_t reserved_23_23:1;
1744 uint32_t uciem:1;
1745 uint32_t reserved_21_21:1;
1746 uint32_t urem:1;
1747 uint32_t ecrcem:1;
1748 uint32_t mtlpm:1;
1749 uint32_t rom:1;
1750 uint32_t ucm:1;
1751 uint32_t cam:1;
1752 uint32_t ctm:1;
1753 uint32_t fcpem:1;
1754 uint32_t ptlpm:1;
1755 uint32_t reserved_6_11:6;
1756 uint32_t sdem:1;
1757 uint32_t dlpem:1;
1758 uint32_t reserved_0_3:4;
1759#else
1760 uint32_t reserved_0_3:4;
1761 uint32_t dlpem:1;
1762 uint32_t sdem:1;
1763 uint32_t reserved_6_11:6;
1764 uint32_t ptlpm:1;
1765 uint32_t fcpem:1;
1766 uint32_t ctm:1;
1767 uint32_t cam:1;
1768 uint32_t ucm:1;
1769 uint32_t rom:1;
1770 uint32_t mtlpm:1;
1771 uint32_t ecrcem:1;
1772 uint32_t urem:1;
1773 uint32_t reserved_21_21:1;
1774 uint32_t uciem:1;
1775 uint32_t reserved_23_23:1;
1776 uint32_t uatombm:1;
1777 uint32_t reserved_25_31:7;
1778#endif
1779 } s;
1780 struct cvmx_pciercx_cfg066_cn52xx {
1781#ifdef __BIG_ENDIAN_BITFIELD
1782 uint32_t reserved_21_31:11;
1783 uint32_t urem:1;
1784 uint32_t ecrcem:1;
1785 uint32_t mtlpm:1;
1786 uint32_t rom:1;
1787 uint32_t ucm:1;
1788 uint32_t cam:1;
1789 uint32_t ctm:1;
1790 uint32_t fcpem:1;
1791 uint32_t ptlpm:1;
1792 uint32_t reserved_6_11:6;
1793 uint32_t sdem:1;
1794 uint32_t dlpem:1;
1795 uint32_t reserved_0_3:4;
1796#else
1797 uint32_t reserved_0_3:4;
1798 uint32_t dlpem:1;
1799 uint32_t sdem:1;
1800 uint32_t reserved_6_11:6;
1801 uint32_t ptlpm:1;
1802 uint32_t fcpem:1;
1803 uint32_t ctm:1;
1804 uint32_t cam:1;
1805 uint32_t ucm:1;
1806 uint32_t rom:1;
1807 uint32_t mtlpm:1;
1808 uint32_t ecrcem:1;
1809 uint32_t urem:1;
1810 uint32_t reserved_21_31:11;
1811#endif
1812 } cn52xx;
1813 struct cvmx_pciercx_cfg066_cn52xx cn52xxp1;
1814 struct cvmx_pciercx_cfg066_cn52xx cn56xx;
1815 struct cvmx_pciercx_cfg066_cn52xx cn56xxp1;
1816 struct cvmx_pciercx_cfg066_cn61xx {
1817#ifdef __BIG_ENDIAN_BITFIELD
1818 uint32_t reserved_25_31:7;
1819 uint32_t uatombm:1;
1820 uint32_t reserved_21_23:3;
1821 uint32_t urem:1;
1822 uint32_t ecrcem:1;
1823 uint32_t mtlpm:1;
1824 uint32_t rom:1;
1825 uint32_t ucm:1;
1826 uint32_t cam:1;
1827 uint32_t ctm:1;
1828 uint32_t fcpem:1;
1829 uint32_t ptlpm:1;
1830 uint32_t reserved_6_11:6;
1831 uint32_t sdem:1;
1832 uint32_t dlpem:1;
1833 uint32_t reserved_0_3:4;
1834#else
1835 uint32_t reserved_0_3:4;
1836 uint32_t dlpem:1;
1837 uint32_t sdem:1;
1838 uint32_t reserved_6_11:6;
1839 uint32_t ptlpm:1;
1840 uint32_t fcpem:1;
1841 uint32_t ctm:1;
1842 uint32_t cam:1;
1843 uint32_t ucm:1;
1844 uint32_t rom:1;
1845 uint32_t mtlpm:1;
1846 uint32_t ecrcem:1;
1847 uint32_t urem:1;
1848 uint32_t reserved_21_23:3;
1849 uint32_t uatombm:1;
1850 uint32_t reserved_25_31:7;
1851#endif
1852 } cn61xx;
1853 struct cvmx_pciercx_cfg066_cn52xx cn63xx;
1854 struct cvmx_pciercx_cfg066_cn52xx cn63xxp1;
1855 struct cvmx_pciercx_cfg066_cn61xx cn66xx;
1856 struct cvmx_pciercx_cfg066_cn61xx cn68xx;
1857 struct cvmx_pciercx_cfg066_cn52xx cn68xxp1;
1858 struct cvmx_pciercx_cfg066_s cnf71xx;
1859};
1860
1861union cvmx_pciercx_cfg067 {
1862 uint32_t u32;
1863 struct cvmx_pciercx_cfg067_s {
1864#ifdef __BIG_ENDIAN_BITFIELD
1865 uint32_t reserved_25_31:7;
1866 uint32_t uatombs:1;
1867 uint32_t reserved_23_23:1;
1868 uint32_t ucies:1;
1869 uint32_t reserved_21_21:1;
1870 uint32_t ures:1;
1871 uint32_t ecrces:1;
1872 uint32_t mtlps:1;
1873 uint32_t ros:1;
1874 uint32_t ucs:1;
1875 uint32_t cas:1;
1876 uint32_t cts:1;
1877 uint32_t fcpes:1;
1878 uint32_t ptlps:1;
1879 uint32_t reserved_6_11:6;
1880 uint32_t sdes:1;
1881 uint32_t dlpes:1;
1882 uint32_t reserved_0_3:4;
1883#else
1884 uint32_t reserved_0_3:4;
1885 uint32_t dlpes:1;
1886 uint32_t sdes:1;
1887 uint32_t reserved_6_11:6;
1888 uint32_t ptlps:1;
1889 uint32_t fcpes:1;
1890 uint32_t cts:1;
1891 uint32_t cas:1;
1892 uint32_t ucs:1;
1893 uint32_t ros:1;
1894 uint32_t mtlps:1;
1895 uint32_t ecrces:1;
1896 uint32_t ures:1;
1897 uint32_t reserved_21_21:1;
1898 uint32_t ucies:1;
1899 uint32_t reserved_23_23:1;
1900 uint32_t uatombs:1;
1901 uint32_t reserved_25_31:7;
1902#endif
1903 } s;
1904 struct cvmx_pciercx_cfg067_cn52xx {
1905#ifdef __BIG_ENDIAN_BITFIELD
1906 uint32_t reserved_21_31:11;
1907 uint32_t ures:1;
1908 uint32_t ecrces:1;
1909 uint32_t mtlps:1;
1910 uint32_t ros:1;
1911 uint32_t ucs:1;
1912 uint32_t cas:1;
1913 uint32_t cts:1;
1914 uint32_t fcpes:1;
1915 uint32_t ptlps:1;
1916 uint32_t reserved_6_11:6;
1917 uint32_t sdes:1;
1918 uint32_t dlpes:1;
1919 uint32_t reserved_0_3:4;
1920#else
1921 uint32_t reserved_0_3:4;
1922 uint32_t dlpes:1;
1923 uint32_t sdes:1;
1924 uint32_t reserved_6_11:6;
1925 uint32_t ptlps:1;
1926 uint32_t fcpes:1;
1927 uint32_t cts:1;
1928 uint32_t cas:1;
1929 uint32_t ucs:1;
1930 uint32_t ros:1;
1931 uint32_t mtlps:1;
1932 uint32_t ecrces:1;
1933 uint32_t ures:1;
1934 uint32_t reserved_21_31:11;
1935#endif
1936 } cn52xx;
1937 struct cvmx_pciercx_cfg067_cn52xx cn52xxp1;
1938 struct cvmx_pciercx_cfg067_cn52xx cn56xx;
1939 struct cvmx_pciercx_cfg067_cn52xx cn56xxp1;
1940 struct cvmx_pciercx_cfg067_cn61xx {
1941#ifdef __BIG_ENDIAN_BITFIELD
1942 uint32_t reserved_25_31:7;
1943 uint32_t uatombs:1;
1944 uint32_t reserved_21_23:3;
1945 uint32_t ures:1;
1946 uint32_t ecrces:1;
1947 uint32_t mtlps:1;
1948 uint32_t ros:1;
1949 uint32_t ucs:1;
1950 uint32_t cas:1;
1951 uint32_t cts:1;
1952 uint32_t fcpes:1;
1953 uint32_t ptlps:1;
1954 uint32_t reserved_6_11:6;
1955 uint32_t sdes:1;
1956 uint32_t dlpes:1;
1957 uint32_t reserved_0_3:4;
1958#else
1959 uint32_t reserved_0_3:4;
1960 uint32_t dlpes:1;
1961 uint32_t sdes:1;
1962 uint32_t reserved_6_11:6;
1963 uint32_t ptlps:1;
1964 uint32_t fcpes:1;
1965 uint32_t cts:1;
1966 uint32_t cas:1;
1967 uint32_t ucs:1;
1968 uint32_t ros:1;
1969 uint32_t mtlps:1;
1970 uint32_t ecrces:1;
1971 uint32_t ures:1;
1972 uint32_t reserved_21_23:3;
1973 uint32_t uatombs:1;
1974 uint32_t reserved_25_31:7;
1975#endif
1976 } cn61xx;
1977 struct cvmx_pciercx_cfg067_cn52xx cn63xx;
1978 struct cvmx_pciercx_cfg067_cn52xx cn63xxp1;
1979 struct cvmx_pciercx_cfg067_cn61xx cn66xx;
1980 struct cvmx_pciercx_cfg067_cn61xx cn68xx;
1981 struct cvmx_pciercx_cfg067_cn52xx cn68xxp1;
1982 struct cvmx_pciercx_cfg067_s cnf71xx;
1983};
1984
1985union cvmx_pciercx_cfg068 {
1986 uint32_t u32;
1987 struct cvmx_pciercx_cfg068_s {
1988#ifdef __BIG_ENDIAN_BITFIELD
1989 uint32_t reserved_15_31:17;
1990 uint32_t cies:1;
1991 uint32_t anfes:1;
1992 uint32_t rtts:1;
1993 uint32_t reserved_9_11:3;
1994 uint32_t rnrs:1;
1995 uint32_t bdllps:1;
1996 uint32_t btlps:1;
1997 uint32_t reserved_1_5:5;
1998 uint32_t res:1;
1999#else
2000 uint32_t res:1;
2001 uint32_t reserved_1_5:5;
2002 uint32_t btlps:1;
2003 uint32_t bdllps:1;
2004 uint32_t rnrs:1;
2005 uint32_t reserved_9_11:3;
2006 uint32_t rtts:1;
2007 uint32_t anfes:1;
2008 uint32_t cies:1;
2009 uint32_t reserved_15_31:17;
2010#endif
2011 } s;
2012 struct cvmx_pciercx_cfg068_cn52xx {
2013#ifdef __BIG_ENDIAN_BITFIELD
2014 uint32_t reserved_14_31:18;
2015 uint32_t anfes:1;
2016 uint32_t rtts:1;
2017 uint32_t reserved_9_11:3;
2018 uint32_t rnrs:1;
2019 uint32_t bdllps:1;
2020 uint32_t btlps:1;
2021 uint32_t reserved_1_5:5;
2022 uint32_t res:1;
2023#else
2024 uint32_t res:1;
2025 uint32_t reserved_1_5:5;
2026 uint32_t btlps:1;
2027 uint32_t bdllps:1;
2028 uint32_t rnrs:1;
2029 uint32_t reserved_9_11:3;
2030 uint32_t rtts:1;
2031 uint32_t anfes:1;
2032 uint32_t reserved_14_31:18;
2033#endif
2034 } cn52xx;
2035 struct cvmx_pciercx_cfg068_cn52xx cn52xxp1;
2036 struct cvmx_pciercx_cfg068_cn52xx cn56xx;
2037 struct cvmx_pciercx_cfg068_cn52xx cn56xxp1;
2038 struct cvmx_pciercx_cfg068_cn52xx cn61xx;
2039 struct cvmx_pciercx_cfg068_cn52xx cn63xx;
2040 struct cvmx_pciercx_cfg068_cn52xx cn63xxp1;
2041 struct cvmx_pciercx_cfg068_cn52xx cn66xx;
2042 struct cvmx_pciercx_cfg068_cn52xx cn68xx;
2043 struct cvmx_pciercx_cfg068_cn52xx cn68xxp1;
2044 struct cvmx_pciercx_cfg068_s cnf71xx;
2045};
2046
2047union cvmx_pciercx_cfg069 {
2048 uint32_t u32;
2049 struct cvmx_pciercx_cfg069_s {
2050#ifdef __BIG_ENDIAN_BITFIELD
2051 uint32_t reserved_15_31:17;
2052 uint32_t ciem:1;
2053 uint32_t anfem:1;
2054 uint32_t rttm:1;
2055 uint32_t reserved_9_11:3;
2056 uint32_t rnrm:1;
2057 uint32_t bdllpm:1;
2058 uint32_t btlpm:1;
2059 uint32_t reserved_1_5:5;
2060 uint32_t rem:1;
2061#else
2062 uint32_t rem:1;
2063 uint32_t reserved_1_5:5;
2064 uint32_t btlpm:1;
2065 uint32_t bdllpm:1;
2066 uint32_t rnrm:1;
2067 uint32_t reserved_9_11:3;
2068 uint32_t rttm:1;
2069 uint32_t anfem:1;
2070 uint32_t ciem:1;
2071 uint32_t reserved_15_31:17;
2072#endif
2073 } s;
2074 struct cvmx_pciercx_cfg069_cn52xx {
2075#ifdef __BIG_ENDIAN_BITFIELD
2076 uint32_t reserved_14_31:18;
2077 uint32_t anfem:1;
2078 uint32_t rttm:1;
2079 uint32_t reserved_9_11:3;
2080 uint32_t rnrm:1;
2081 uint32_t bdllpm:1;
2082 uint32_t btlpm:1;
2083 uint32_t reserved_1_5:5;
2084 uint32_t rem:1;
2085#else
2086 uint32_t rem:1;
2087 uint32_t reserved_1_5:5;
2088 uint32_t btlpm:1;
2089 uint32_t bdllpm:1;
2090 uint32_t rnrm:1;
2091 uint32_t reserved_9_11:3;
2092 uint32_t rttm:1;
2093 uint32_t anfem:1;
2094 uint32_t reserved_14_31:18;
2095#endif
2096 } cn52xx;
2097 struct cvmx_pciercx_cfg069_cn52xx cn52xxp1;
2098 struct cvmx_pciercx_cfg069_cn52xx cn56xx;
2099 struct cvmx_pciercx_cfg069_cn52xx cn56xxp1;
2100 struct cvmx_pciercx_cfg069_cn52xx cn61xx;
2101 struct cvmx_pciercx_cfg069_cn52xx cn63xx;
2102 struct cvmx_pciercx_cfg069_cn52xx cn63xxp1;
2103 struct cvmx_pciercx_cfg069_cn52xx cn66xx;
2104 struct cvmx_pciercx_cfg069_cn52xx cn68xx;
2105 struct cvmx_pciercx_cfg069_cn52xx cn68xxp1;
2106 struct cvmx_pciercx_cfg069_s cnf71xx;
2107}; 270};
2108 271
2109union cvmx_pciercx_cfg070 { 272union cvmx_pciercx_cfg070 {
2110 uint32_t u32; 273 uint32_t u32;
2111 struct cvmx_pciercx_cfg070_s { 274 struct cvmx_pciercx_cfg070_s {
2112#ifdef __BIG_ENDIAN_BITFIELD 275 __BITFIELD_FIELD(uint32_t reserved_12_31:20,
2113 uint32_t reserved_9_31:23; 276 __BITFIELD_FIELD(uint32_t tplp:1,
2114 uint32_t ce:1; 277 __BITFIELD_FIELD(uint32_t reserved_9_10:2,
2115 uint32_t cc:1; 278 __BITFIELD_FIELD(uint32_t ce:1,
2116 uint32_t ge:1; 279 __BITFIELD_FIELD(uint32_t cc:1,
2117 uint32_t gc:1; 280 __BITFIELD_FIELD(uint32_t ge:1,
2118 uint32_t fep:5; 281 __BITFIELD_FIELD(uint32_t gc:1,
2119#else 282 __BITFIELD_FIELD(uint32_t fep:5,
2120 uint32_t fep:5; 283 ;))))))))
2121 uint32_t gc:1;
2122 uint32_t ge:1;
2123 uint32_t cc:1;
2124 uint32_t ce:1;
2125 uint32_t reserved_9_31:23;
2126#endif
2127 } s;
2128 struct cvmx_pciercx_cfg070_s cn52xx;
2129 struct cvmx_pciercx_cfg070_s cn52xxp1;
2130 struct cvmx_pciercx_cfg070_s cn56xx;
2131 struct cvmx_pciercx_cfg070_s cn56xxp1;
2132 struct cvmx_pciercx_cfg070_s cn61xx;
2133 struct cvmx_pciercx_cfg070_s cn63xx;
2134 struct cvmx_pciercx_cfg070_s cn63xxp1;
2135 struct cvmx_pciercx_cfg070_s cn66xx;
2136 struct cvmx_pciercx_cfg070_s cn68xx;
2137 struct cvmx_pciercx_cfg070_s cn68xxp1;
2138 struct cvmx_pciercx_cfg070_s cnf71xx;
2139};
2140
2141union cvmx_pciercx_cfg071 {
2142 uint32_t u32;
2143 struct cvmx_pciercx_cfg071_s {
2144#ifdef __BIG_ENDIAN_BITFIELD
2145 uint32_t dword1:32;
2146#else
2147 uint32_t dword1:32;
2148#endif
2149 } s; 284 } s;
2150 struct cvmx_pciercx_cfg071_s cn52xx;
2151 struct cvmx_pciercx_cfg071_s cn52xxp1;
2152 struct cvmx_pciercx_cfg071_s cn56xx;
2153 struct cvmx_pciercx_cfg071_s cn56xxp1;
2154 struct cvmx_pciercx_cfg071_s cn61xx;
2155 struct cvmx_pciercx_cfg071_s cn63xx;
2156 struct cvmx_pciercx_cfg071_s cn63xxp1;
2157 struct cvmx_pciercx_cfg071_s cn66xx;
2158 struct cvmx_pciercx_cfg071_s cn68xx;
2159 struct cvmx_pciercx_cfg071_s cn68xxp1;
2160 struct cvmx_pciercx_cfg071_s cnf71xx;
2161};
2162
2163union cvmx_pciercx_cfg072 {
2164 uint32_t u32;
2165 struct cvmx_pciercx_cfg072_s {
2166#ifdef __BIG_ENDIAN_BITFIELD
2167 uint32_t dword2:32;
2168#else
2169 uint32_t dword2:32;
2170#endif
2171 } s;
2172 struct cvmx_pciercx_cfg072_s cn52xx;
2173 struct cvmx_pciercx_cfg072_s cn52xxp1;
2174 struct cvmx_pciercx_cfg072_s cn56xx;
2175 struct cvmx_pciercx_cfg072_s cn56xxp1;
2176 struct cvmx_pciercx_cfg072_s cn61xx;
2177 struct cvmx_pciercx_cfg072_s cn63xx;
2178 struct cvmx_pciercx_cfg072_s cn63xxp1;
2179 struct cvmx_pciercx_cfg072_s cn66xx;
2180 struct cvmx_pciercx_cfg072_s cn68xx;
2181 struct cvmx_pciercx_cfg072_s cn68xxp1;
2182 struct cvmx_pciercx_cfg072_s cnf71xx;
2183};
2184
2185union cvmx_pciercx_cfg073 {
2186 uint32_t u32;
2187 struct cvmx_pciercx_cfg073_s {
2188#ifdef __BIG_ENDIAN_BITFIELD
2189 uint32_t dword3:32;
2190#else
2191 uint32_t dword3:32;
2192#endif
2193 } s;
2194 struct cvmx_pciercx_cfg073_s cn52xx;
2195 struct cvmx_pciercx_cfg073_s cn52xxp1;
2196 struct cvmx_pciercx_cfg073_s cn56xx;
2197 struct cvmx_pciercx_cfg073_s cn56xxp1;
2198 struct cvmx_pciercx_cfg073_s cn61xx;
2199 struct cvmx_pciercx_cfg073_s cn63xx;
2200 struct cvmx_pciercx_cfg073_s cn63xxp1;
2201 struct cvmx_pciercx_cfg073_s cn66xx;
2202 struct cvmx_pciercx_cfg073_s cn68xx;
2203 struct cvmx_pciercx_cfg073_s cn68xxp1;
2204 struct cvmx_pciercx_cfg073_s cnf71xx;
2205};
2206
2207union cvmx_pciercx_cfg074 {
2208 uint32_t u32;
2209 struct cvmx_pciercx_cfg074_s {
2210#ifdef __BIG_ENDIAN_BITFIELD
2211 uint32_t dword4:32;
2212#else
2213 uint32_t dword4:32;
2214#endif
2215 } s;
2216 struct cvmx_pciercx_cfg074_s cn52xx;
2217 struct cvmx_pciercx_cfg074_s cn52xxp1;
2218 struct cvmx_pciercx_cfg074_s cn56xx;
2219 struct cvmx_pciercx_cfg074_s cn56xxp1;
2220 struct cvmx_pciercx_cfg074_s cn61xx;
2221 struct cvmx_pciercx_cfg074_s cn63xx;
2222 struct cvmx_pciercx_cfg074_s cn63xxp1;
2223 struct cvmx_pciercx_cfg074_s cn66xx;
2224 struct cvmx_pciercx_cfg074_s cn68xx;
2225 struct cvmx_pciercx_cfg074_s cn68xxp1;
2226 struct cvmx_pciercx_cfg074_s cnf71xx;
2227}; 285};
2228 286
2229union cvmx_pciercx_cfg075 { 287union cvmx_pciercx_cfg075 {
2230 uint32_t u32; 288 uint32_t u32;
2231 struct cvmx_pciercx_cfg075_s { 289 struct cvmx_pciercx_cfg075_s {
2232#ifdef __BIG_ENDIAN_BITFIELD 290 __BITFIELD_FIELD(uint32_t reserved_3_31:29,
2233 uint32_t reserved_3_31:29; 291 __BITFIELD_FIELD(uint32_t fere:1,
2234 uint32_t fere:1; 292 __BITFIELD_FIELD(uint32_t nfere:1,
2235 uint32_t nfere:1; 293 __BITFIELD_FIELD(uint32_t cere:1,
2236 uint32_t cere:1; 294 ;))))
2237#else
2238 uint32_t cere:1;
2239 uint32_t nfere:1;
2240 uint32_t fere:1;
2241 uint32_t reserved_3_31:29;
2242#endif
2243 } s;
2244 struct cvmx_pciercx_cfg075_s cn52xx;
2245 struct cvmx_pciercx_cfg075_s cn52xxp1;
2246 struct cvmx_pciercx_cfg075_s cn56xx;
2247 struct cvmx_pciercx_cfg075_s cn56xxp1;
2248 struct cvmx_pciercx_cfg075_s cn61xx;
2249 struct cvmx_pciercx_cfg075_s cn63xx;
2250 struct cvmx_pciercx_cfg075_s cn63xxp1;
2251 struct cvmx_pciercx_cfg075_s cn66xx;
2252 struct cvmx_pciercx_cfg075_s cn68xx;
2253 struct cvmx_pciercx_cfg075_s cn68xxp1;
2254 struct cvmx_pciercx_cfg075_s cnf71xx;
2255};
2256
2257union cvmx_pciercx_cfg076 {
2258 uint32_t u32;
2259 struct cvmx_pciercx_cfg076_s {
2260#ifdef __BIG_ENDIAN_BITFIELD
2261 uint32_t aeimn:5;
2262 uint32_t reserved_7_26:20;
2263 uint32_t femr:1;
2264 uint32_t nfemr:1;
2265 uint32_t fuf:1;
2266 uint32_t multi_efnfr:1;
2267 uint32_t efnfr:1;
2268 uint32_t multi_ecr:1;
2269 uint32_t ecr:1;
2270#else
2271 uint32_t ecr:1;
2272 uint32_t multi_ecr:1;
2273 uint32_t efnfr:1;
2274 uint32_t multi_efnfr:1;
2275 uint32_t fuf:1;
2276 uint32_t nfemr:1;
2277 uint32_t femr:1;
2278 uint32_t reserved_7_26:20;
2279 uint32_t aeimn:5;
2280#endif
2281 } s; 295 } s;
2282 struct cvmx_pciercx_cfg076_s cn52xx;
2283 struct cvmx_pciercx_cfg076_s cn52xxp1;
2284 struct cvmx_pciercx_cfg076_s cn56xx;
2285 struct cvmx_pciercx_cfg076_s cn56xxp1;
2286 struct cvmx_pciercx_cfg076_s cn61xx;
2287 struct cvmx_pciercx_cfg076_s cn63xx;
2288 struct cvmx_pciercx_cfg076_s cn63xxp1;
2289 struct cvmx_pciercx_cfg076_s cn66xx;
2290 struct cvmx_pciercx_cfg076_s cn68xx;
2291 struct cvmx_pciercx_cfg076_s cn68xxp1;
2292 struct cvmx_pciercx_cfg076_s cnf71xx;
2293};
2294
2295union cvmx_pciercx_cfg077 {
2296 uint32_t u32;
2297 struct cvmx_pciercx_cfg077_s {
2298#ifdef __BIG_ENDIAN_BITFIELD
2299 uint32_t efnfsi:16;
2300 uint32_t ecsi:16;
2301#else
2302 uint32_t ecsi:16;
2303 uint32_t efnfsi:16;
2304#endif
2305 } s;
2306 struct cvmx_pciercx_cfg077_s cn52xx;
2307 struct cvmx_pciercx_cfg077_s cn52xxp1;
2308 struct cvmx_pciercx_cfg077_s cn56xx;
2309 struct cvmx_pciercx_cfg077_s cn56xxp1;
2310 struct cvmx_pciercx_cfg077_s cn61xx;
2311 struct cvmx_pciercx_cfg077_s cn63xx;
2312 struct cvmx_pciercx_cfg077_s cn63xxp1;
2313 struct cvmx_pciercx_cfg077_s cn66xx;
2314 struct cvmx_pciercx_cfg077_s cn68xx;
2315 struct cvmx_pciercx_cfg077_s cn68xxp1;
2316 struct cvmx_pciercx_cfg077_s cnf71xx;
2317}; 296};
2318 297
2319union cvmx_pciercx_cfg448 { 298union cvmx_pciercx_cfg448 {
2320 uint32_t u32; 299 uint32_t u32;
2321 struct cvmx_pciercx_cfg448_s { 300 struct cvmx_pciercx_cfg448_s {
2322#ifdef __BIG_ENDIAN_BITFIELD 301 __BITFIELD_FIELD(uint32_t rtl:16,
2323 uint32_t rtl:16; 302 __BITFIELD_FIELD(uint32_t rtltl:16,
2324 uint32_t rtltl:16; 303 ;))
2325#else
2326 uint32_t rtltl:16;
2327 uint32_t rtl:16;
2328#endif
2329 } s;
2330 struct cvmx_pciercx_cfg448_s cn52xx;
2331 struct cvmx_pciercx_cfg448_s cn52xxp1;
2332 struct cvmx_pciercx_cfg448_s cn56xx;
2333 struct cvmx_pciercx_cfg448_s cn56xxp1;
2334 struct cvmx_pciercx_cfg448_s cn61xx;
2335 struct cvmx_pciercx_cfg448_s cn63xx;
2336 struct cvmx_pciercx_cfg448_s cn63xxp1;
2337 struct cvmx_pciercx_cfg448_s cn66xx;
2338 struct cvmx_pciercx_cfg448_s cn68xx;
2339 struct cvmx_pciercx_cfg448_s cn68xxp1;
2340 struct cvmx_pciercx_cfg448_s cnf71xx;
2341};
2342
2343union cvmx_pciercx_cfg449 {
2344 uint32_t u32;
2345 struct cvmx_pciercx_cfg449_s {
2346#ifdef __BIG_ENDIAN_BITFIELD
2347 uint32_t omr:32;
2348#else
2349 uint32_t omr:32;
2350#endif
2351 } s;
2352 struct cvmx_pciercx_cfg449_s cn52xx;
2353 struct cvmx_pciercx_cfg449_s cn52xxp1;
2354 struct cvmx_pciercx_cfg449_s cn56xx;
2355 struct cvmx_pciercx_cfg449_s cn56xxp1;
2356 struct cvmx_pciercx_cfg449_s cn61xx;
2357 struct cvmx_pciercx_cfg449_s cn63xx;
2358 struct cvmx_pciercx_cfg449_s cn63xxp1;
2359 struct cvmx_pciercx_cfg449_s cn66xx;
2360 struct cvmx_pciercx_cfg449_s cn68xx;
2361 struct cvmx_pciercx_cfg449_s cn68xxp1;
2362 struct cvmx_pciercx_cfg449_s cnf71xx;
2363};
2364
2365union cvmx_pciercx_cfg450 {
2366 uint32_t u32;
2367 struct cvmx_pciercx_cfg450_s {
2368#ifdef __BIG_ENDIAN_BITFIELD
2369 uint32_t lpec:8;
2370 uint32_t reserved_22_23:2;
2371 uint32_t link_state:6;
2372 uint32_t force_link:1;
2373 uint32_t reserved_8_14:7;
2374 uint32_t link_num:8;
2375#else
2376 uint32_t link_num:8;
2377 uint32_t reserved_8_14:7;
2378 uint32_t force_link:1;
2379 uint32_t link_state:6;
2380 uint32_t reserved_22_23:2;
2381 uint32_t lpec:8;
2382#endif
2383 } s;
2384 struct cvmx_pciercx_cfg450_s cn52xx;
2385 struct cvmx_pciercx_cfg450_s cn52xxp1;
2386 struct cvmx_pciercx_cfg450_s cn56xx;
2387 struct cvmx_pciercx_cfg450_s cn56xxp1;
2388 struct cvmx_pciercx_cfg450_s cn61xx;
2389 struct cvmx_pciercx_cfg450_s cn63xx;
2390 struct cvmx_pciercx_cfg450_s cn63xxp1;
2391 struct cvmx_pciercx_cfg450_s cn66xx;
2392 struct cvmx_pciercx_cfg450_s cn68xx;
2393 struct cvmx_pciercx_cfg450_s cn68xxp1;
2394 struct cvmx_pciercx_cfg450_s cnf71xx;
2395};
2396
2397union cvmx_pciercx_cfg451 {
2398 uint32_t u32;
2399 struct cvmx_pciercx_cfg451_s {
2400#ifdef __BIG_ENDIAN_BITFIELD
2401 uint32_t reserved_31_31:1;
2402 uint32_t easpml1:1;
2403 uint32_t l1el:3;
2404 uint32_t l0el:3;
2405 uint32_t n_fts_cc:8;
2406 uint32_t n_fts:8;
2407 uint32_t ack_freq:8;
2408#else
2409 uint32_t ack_freq:8;
2410 uint32_t n_fts:8;
2411 uint32_t n_fts_cc:8;
2412 uint32_t l0el:3;
2413 uint32_t l1el:3;
2414 uint32_t easpml1:1;
2415 uint32_t reserved_31_31:1;
2416#endif
2417 } s; 304 } s;
2418 struct cvmx_pciercx_cfg451_cn52xx {
2419#ifdef __BIG_ENDIAN_BITFIELD
2420 uint32_t reserved_30_31:2;
2421 uint32_t l1el:3;
2422 uint32_t l0el:3;
2423 uint32_t n_fts_cc:8;
2424 uint32_t n_fts:8;
2425 uint32_t ack_freq:8;
2426#else
2427 uint32_t ack_freq:8;
2428 uint32_t n_fts:8;
2429 uint32_t n_fts_cc:8;
2430 uint32_t l0el:3;
2431 uint32_t l1el:3;
2432 uint32_t reserved_30_31:2;
2433#endif
2434 } cn52xx;
2435 struct cvmx_pciercx_cfg451_cn52xx cn52xxp1;
2436 struct cvmx_pciercx_cfg451_cn52xx cn56xx;
2437 struct cvmx_pciercx_cfg451_cn52xx cn56xxp1;
2438 struct cvmx_pciercx_cfg451_s cn61xx;
2439 struct cvmx_pciercx_cfg451_cn52xx cn63xx;
2440 struct cvmx_pciercx_cfg451_cn52xx cn63xxp1;
2441 struct cvmx_pciercx_cfg451_s cn66xx;
2442 struct cvmx_pciercx_cfg451_s cn68xx;
2443 struct cvmx_pciercx_cfg451_s cn68xxp1;
2444 struct cvmx_pciercx_cfg451_s cnf71xx;
2445}; 305};
2446 306
2447union cvmx_pciercx_cfg452 { 307union cvmx_pciercx_cfg452 {
2448 uint32_t u32; 308 uint32_t u32;
2449 struct cvmx_pciercx_cfg452_s { 309 struct cvmx_pciercx_cfg452_s {
2450#ifdef __BIG_ENDIAN_BITFIELD 310 __BITFIELD_FIELD(uint32_t reserved_26_31:6,
2451 uint32_t reserved_26_31:6; 311 __BITFIELD_FIELD(uint32_t eccrc:1,
2452 uint32_t eccrc:1; 312 __BITFIELD_FIELD(uint32_t reserved_22_24:3,
2453 uint32_t reserved_22_24:3; 313 __BITFIELD_FIELD(uint32_t lme:6,
2454 uint32_t lme:6; 314 __BITFIELD_FIELD(uint32_t reserved_12_15:4,
2455 uint32_t reserved_8_15:8; 315 __BITFIELD_FIELD(uint32_t link_rate:4,
2456 uint32_t flm:1; 316 __BITFIELD_FIELD(uint32_t flm:1,
2457 uint32_t reserved_6_6:1; 317 __BITFIELD_FIELD(uint32_t reserved_6_6:1,
2458 uint32_t dllle:1; 318 __BITFIELD_FIELD(uint32_t dllle:1,
2459 uint32_t reserved_4_4:1; 319 __BITFIELD_FIELD(uint32_t reserved_4_4:1,
2460 uint32_t ra:1; 320 __BITFIELD_FIELD(uint32_t ra:1,
2461 uint32_t le:1; 321 __BITFIELD_FIELD(uint32_t le:1,
2462 uint32_t sd:1; 322 __BITFIELD_FIELD(uint32_t sd:1,
2463 uint32_t omr:1; 323 __BITFIELD_FIELD(uint32_t omr:1,
2464#else 324 ;))))))))))))))
2465 uint32_t omr:1;
2466 uint32_t sd:1;
2467 uint32_t le:1;
2468 uint32_t ra:1;
2469 uint32_t reserved_4_4:1;
2470 uint32_t dllle:1;
2471 uint32_t reserved_6_6:1;
2472 uint32_t flm:1;
2473 uint32_t reserved_8_15:8;
2474 uint32_t lme:6;
2475 uint32_t reserved_22_24:3;
2476 uint32_t eccrc:1;
2477 uint32_t reserved_26_31:6;
2478#endif
2479 } s; 325 } s;
2480 struct cvmx_pciercx_cfg452_s cn52xx;
2481 struct cvmx_pciercx_cfg452_s cn52xxp1;
2482 struct cvmx_pciercx_cfg452_s cn56xx;
2483 struct cvmx_pciercx_cfg452_s cn56xxp1;
2484 struct cvmx_pciercx_cfg452_cn61xx {
2485#ifdef __BIG_ENDIAN_BITFIELD
2486 uint32_t reserved_22_31:10;
2487 uint32_t lme:6;
2488 uint32_t reserved_8_15:8;
2489 uint32_t flm:1;
2490 uint32_t reserved_6_6:1;
2491 uint32_t dllle:1;
2492 uint32_t reserved_4_4:1;
2493 uint32_t ra:1;
2494 uint32_t le:1;
2495 uint32_t sd:1;
2496 uint32_t omr:1;
2497#else
2498 uint32_t omr:1;
2499 uint32_t sd:1;
2500 uint32_t le:1;
2501 uint32_t ra:1;
2502 uint32_t reserved_4_4:1;
2503 uint32_t dllle:1;
2504 uint32_t reserved_6_6:1;
2505 uint32_t flm:1;
2506 uint32_t reserved_8_15:8;
2507 uint32_t lme:6;
2508 uint32_t reserved_22_31:10;
2509#endif
2510 } cn61xx;
2511 struct cvmx_pciercx_cfg452_s cn63xx;
2512 struct cvmx_pciercx_cfg452_s cn63xxp1;
2513 struct cvmx_pciercx_cfg452_cn61xx cn66xx;
2514 struct cvmx_pciercx_cfg452_cn61xx cn68xx;
2515 struct cvmx_pciercx_cfg452_cn61xx cn68xxp1;
2516 struct cvmx_pciercx_cfg452_cn61xx cnf71xx;
2517};
2518
2519union cvmx_pciercx_cfg453 {
2520 uint32_t u32;
2521 struct cvmx_pciercx_cfg453_s {
2522#ifdef __BIG_ENDIAN_BITFIELD
2523 uint32_t dlld:1;
2524 uint32_t reserved_26_30:5;
2525 uint32_t ack_nak:1;
2526 uint32_t fcd:1;
2527 uint32_t ilst:24;
2528#else
2529 uint32_t ilst:24;
2530 uint32_t fcd:1;
2531 uint32_t ack_nak:1;
2532 uint32_t reserved_26_30:5;
2533 uint32_t dlld:1;
2534#endif
2535 } s;
2536 struct cvmx_pciercx_cfg453_s cn52xx;
2537 struct cvmx_pciercx_cfg453_s cn52xxp1;
2538 struct cvmx_pciercx_cfg453_s cn56xx;
2539 struct cvmx_pciercx_cfg453_s cn56xxp1;
2540 struct cvmx_pciercx_cfg453_s cn61xx;
2541 struct cvmx_pciercx_cfg453_s cn63xx;
2542 struct cvmx_pciercx_cfg453_s cn63xxp1;
2543 struct cvmx_pciercx_cfg453_s cn66xx;
2544 struct cvmx_pciercx_cfg453_s cn68xx;
2545 struct cvmx_pciercx_cfg453_s cn68xxp1;
2546 struct cvmx_pciercx_cfg453_s cnf71xx;
2547};
2548
2549union cvmx_pciercx_cfg454 {
2550 uint32_t u32;
2551 struct cvmx_pciercx_cfg454_s {
2552#ifdef __BIG_ENDIAN_BITFIELD
2553 uint32_t cx_nfunc:3;
2554 uint32_t tmfcwt:5;
2555 uint32_t tmanlt:5;
2556 uint32_t tmrt:5;
2557 uint32_t reserved_11_13:3;
2558 uint32_t nskps:3;
2559 uint32_t reserved_0_7:8;
2560#else
2561 uint32_t reserved_0_7:8;
2562 uint32_t nskps:3;
2563 uint32_t reserved_11_13:3;
2564 uint32_t tmrt:5;
2565 uint32_t tmanlt:5;
2566 uint32_t tmfcwt:5;
2567 uint32_t cx_nfunc:3;
2568#endif
2569 } s;
2570 struct cvmx_pciercx_cfg454_cn52xx {
2571#ifdef __BIG_ENDIAN_BITFIELD
2572 uint32_t reserved_29_31:3;
2573 uint32_t tmfcwt:5;
2574 uint32_t tmanlt:5;
2575 uint32_t tmrt:5;
2576 uint32_t reserved_11_13:3;
2577 uint32_t nskps:3;
2578 uint32_t reserved_4_7:4;
2579 uint32_t ntss:4;
2580#else
2581 uint32_t ntss:4;
2582 uint32_t reserved_4_7:4;
2583 uint32_t nskps:3;
2584 uint32_t reserved_11_13:3;
2585 uint32_t tmrt:5;
2586 uint32_t tmanlt:5;
2587 uint32_t tmfcwt:5;
2588 uint32_t reserved_29_31:3;
2589#endif
2590 } cn52xx;
2591 struct cvmx_pciercx_cfg454_cn52xx cn52xxp1;
2592 struct cvmx_pciercx_cfg454_cn52xx cn56xx;
2593 struct cvmx_pciercx_cfg454_cn52xx cn56xxp1;
2594 struct cvmx_pciercx_cfg454_cn61xx {
2595#ifdef __BIG_ENDIAN_BITFIELD
2596 uint32_t cx_nfunc:3;
2597 uint32_t tmfcwt:5;
2598 uint32_t tmanlt:5;
2599 uint32_t tmrt:5;
2600 uint32_t reserved_8_13:6;
2601 uint32_t mfuncn:8;
2602#else
2603 uint32_t mfuncn:8;
2604 uint32_t reserved_8_13:6;
2605 uint32_t tmrt:5;
2606 uint32_t tmanlt:5;
2607 uint32_t tmfcwt:5;
2608 uint32_t cx_nfunc:3;
2609#endif
2610 } cn61xx;
2611 struct cvmx_pciercx_cfg454_cn52xx cn63xx;
2612 struct cvmx_pciercx_cfg454_cn52xx cn63xxp1;
2613 struct cvmx_pciercx_cfg454_cn61xx cn66xx;
2614 struct cvmx_pciercx_cfg454_cn61xx cn68xx;
2615 struct cvmx_pciercx_cfg454_cn52xx cn68xxp1;
2616 struct cvmx_pciercx_cfg454_cn61xx cnf71xx;
2617}; 326};
2618 327
2619union cvmx_pciercx_cfg455 { 328union cvmx_pciercx_cfg455 {
2620 uint32_t u32; 329 uint32_t u32;
2621 struct cvmx_pciercx_cfg455_s { 330 struct cvmx_pciercx_cfg455_s {
2622#ifdef __BIG_ENDIAN_BITFIELD 331 __BITFIELD_FIELD(uint32_t m_cfg0_filt:1,
2623 uint32_t m_cfg0_filt:1; 332 __BITFIELD_FIELD(uint32_t m_io_filt:1,
2624 uint32_t m_io_filt:1; 333 __BITFIELD_FIELD(uint32_t msg_ctrl:1,
2625 uint32_t msg_ctrl:1; 334 __BITFIELD_FIELD(uint32_t m_cpl_ecrc_filt:1,
2626 uint32_t m_cpl_ecrc_filt:1; 335 __BITFIELD_FIELD(uint32_t m_ecrc_filt:1,
2627 uint32_t m_ecrc_filt:1; 336 __BITFIELD_FIELD(uint32_t m_cpl_len_err:1,
2628 uint32_t m_cpl_len_err:1; 337 __BITFIELD_FIELD(uint32_t m_cpl_attr_err:1,
2629 uint32_t m_cpl_attr_err:1; 338 __BITFIELD_FIELD(uint32_t m_cpl_tc_err:1,
2630 uint32_t m_cpl_tc_err:1; 339 __BITFIELD_FIELD(uint32_t m_cpl_fun_err:1,
2631 uint32_t m_cpl_fun_err:1; 340 __BITFIELD_FIELD(uint32_t m_cpl_rid_err:1,
2632 uint32_t m_cpl_rid_err:1; 341 __BITFIELD_FIELD(uint32_t m_cpl_tag_err:1,
2633 uint32_t m_cpl_tag_err:1; 342 __BITFIELD_FIELD(uint32_t m_lk_filt:1,
2634 uint32_t m_lk_filt:1; 343 __BITFIELD_FIELD(uint32_t m_cfg1_filt:1,
2635 uint32_t m_cfg1_filt:1; 344 __BITFIELD_FIELD(uint32_t m_bar_match:1,
2636 uint32_t m_bar_match:1; 345 __BITFIELD_FIELD(uint32_t m_pois_filt:1,
2637 uint32_t m_pois_filt:1; 346 __BITFIELD_FIELD(uint32_t m_fun:1,
2638 uint32_t m_fun:1; 347 __BITFIELD_FIELD(uint32_t dfcwt:1,
2639 uint32_t dfcwt:1; 348 __BITFIELD_FIELD(uint32_t reserved_11_14:4,
2640 uint32_t reserved_11_14:4; 349 __BITFIELD_FIELD(uint32_t skpiv:11,
2641 uint32_t skpiv:11; 350 ;)))))))))))))))))))
2642#else
2643 uint32_t skpiv:11;
2644 uint32_t reserved_11_14:4;
2645 uint32_t dfcwt:1;
2646 uint32_t m_fun:1;
2647 uint32_t m_pois_filt:1;
2648 uint32_t m_bar_match:1;
2649 uint32_t m_cfg1_filt:1;
2650 uint32_t m_lk_filt:1;
2651 uint32_t m_cpl_tag_err:1;
2652 uint32_t m_cpl_rid_err:1;
2653 uint32_t m_cpl_fun_err:1;
2654 uint32_t m_cpl_tc_err:1;
2655 uint32_t m_cpl_attr_err:1;
2656 uint32_t m_cpl_len_err:1;
2657 uint32_t m_ecrc_filt:1;
2658 uint32_t m_cpl_ecrc_filt:1;
2659 uint32_t msg_ctrl:1;
2660 uint32_t m_io_filt:1;
2661 uint32_t m_cfg0_filt:1;
2662#endif
2663 } s;
2664 struct cvmx_pciercx_cfg455_s cn52xx;
2665 struct cvmx_pciercx_cfg455_s cn52xxp1;
2666 struct cvmx_pciercx_cfg455_s cn56xx;
2667 struct cvmx_pciercx_cfg455_s cn56xxp1;
2668 struct cvmx_pciercx_cfg455_s cn61xx;
2669 struct cvmx_pciercx_cfg455_s cn63xx;
2670 struct cvmx_pciercx_cfg455_s cn63xxp1;
2671 struct cvmx_pciercx_cfg455_s cn66xx;
2672 struct cvmx_pciercx_cfg455_s cn68xx;
2673 struct cvmx_pciercx_cfg455_s cn68xxp1;
2674 struct cvmx_pciercx_cfg455_s cnf71xx;
2675};
2676
2677union cvmx_pciercx_cfg456 {
2678 uint32_t u32;
2679 struct cvmx_pciercx_cfg456_s {
2680#ifdef __BIG_ENDIAN_BITFIELD
2681 uint32_t reserved_4_31:28;
2682 uint32_t m_handle_flush:1;
2683 uint32_t m_dabort_4ucpl:1;
2684 uint32_t m_vend1_drp:1;
2685 uint32_t m_vend0_drp:1;
2686#else
2687 uint32_t m_vend0_drp:1;
2688 uint32_t m_vend1_drp:1;
2689 uint32_t m_dabort_4ucpl:1;
2690 uint32_t m_handle_flush:1;
2691 uint32_t reserved_4_31:28;
2692#endif
2693 } s;
2694 struct cvmx_pciercx_cfg456_cn52xx {
2695#ifdef __BIG_ENDIAN_BITFIELD
2696 uint32_t reserved_2_31:30;
2697 uint32_t m_vend1_drp:1;
2698 uint32_t m_vend0_drp:1;
2699#else
2700 uint32_t m_vend0_drp:1;
2701 uint32_t m_vend1_drp:1;
2702 uint32_t reserved_2_31:30;
2703#endif
2704 } cn52xx;
2705 struct cvmx_pciercx_cfg456_cn52xx cn52xxp1;
2706 struct cvmx_pciercx_cfg456_cn52xx cn56xx;
2707 struct cvmx_pciercx_cfg456_cn52xx cn56xxp1;
2708 struct cvmx_pciercx_cfg456_s cn61xx;
2709 struct cvmx_pciercx_cfg456_cn52xx cn63xx;
2710 struct cvmx_pciercx_cfg456_cn52xx cn63xxp1;
2711 struct cvmx_pciercx_cfg456_s cn66xx;
2712 struct cvmx_pciercx_cfg456_s cn68xx;
2713 struct cvmx_pciercx_cfg456_cn52xx cn68xxp1;
2714 struct cvmx_pciercx_cfg456_s cnf71xx;
2715};
2716
2717union cvmx_pciercx_cfg458 {
2718 uint32_t u32;
2719 struct cvmx_pciercx_cfg458_s {
2720#ifdef __BIG_ENDIAN_BITFIELD
2721 uint32_t dbg_info_l32:32;
2722#else
2723 uint32_t dbg_info_l32:32;
2724#endif
2725 } s;
2726 struct cvmx_pciercx_cfg458_s cn52xx;
2727 struct cvmx_pciercx_cfg458_s cn52xxp1;
2728 struct cvmx_pciercx_cfg458_s cn56xx;
2729 struct cvmx_pciercx_cfg458_s cn56xxp1;
2730 struct cvmx_pciercx_cfg458_s cn61xx;
2731 struct cvmx_pciercx_cfg458_s cn63xx;
2732 struct cvmx_pciercx_cfg458_s cn63xxp1;
2733 struct cvmx_pciercx_cfg458_s cn66xx;
2734 struct cvmx_pciercx_cfg458_s cn68xx;
2735 struct cvmx_pciercx_cfg458_s cn68xxp1;
2736 struct cvmx_pciercx_cfg458_s cnf71xx;
2737};
2738
2739union cvmx_pciercx_cfg459 {
2740 uint32_t u32;
2741 struct cvmx_pciercx_cfg459_s {
2742#ifdef __BIG_ENDIAN_BITFIELD
2743 uint32_t dbg_info_u32:32;
2744#else
2745 uint32_t dbg_info_u32:32;
2746#endif
2747 } s;
2748 struct cvmx_pciercx_cfg459_s cn52xx;
2749 struct cvmx_pciercx_cfg459_s cn52xxp1;
2750 struct cvmx_pciercx_cfg459_s cn56xx;
2751 struct cvmx_pciercx_cfg459_s cn56xxp1;
2752 struct cvmx_pciercx_cfg459_s cn61xx;
2753 struct cvmx_pciercx_cfg459_s cn63xx;
2754 struct cvmx_pciercx_cfg459_s cn63xxp1;
2755 struct cvmx_pciercx_cfg459_s cn66xx;
2756 struct cvmx_pciercx_cfg459_s cn68xx;
2757 struct cvmx_pciercx_cfg459_s cn68xxp1;
2758 struct cvmx_pciercx_cfg459_s cnf71xx;
2759};
2760
2761union cvmx_pciercx_cfg460 {
2762 uint32_t u32;
2763 struct cvmx_pciercx_cfg460_s {
2764#ifdef __BIG_ENDIAN_BITFIELD
2765 uint32_t reserved_20_31:12;
2766 uint32_t tphfcc:8;
2767 uint32_t tpdfcc:12;
2768#else
2769 uint32_t tpdfcc:12;
2770 uint32_t tphfcc:8;
2771 uint32_t reserved_20_31:12;
2772#endif
2773 } s;
2774 struct cvmx_pciercx_cfg460_s cn52xx;
2775 struct cvmx_pciercx_cfg460_s cn52xxp1;
2776 struct cvmx_pciercx_cfg460_s cn56xx;
2777 struct cvmx_pciercx_cfg460_s cn56xxp1;
2778 struct cvmx_pciercx_cfg460_s cn61xx;
2779 struct cvmx_pciercx_cfg460_s cn63xx;
2780 struct cvmx_pciercx_cfg460_s cn63xxp1;
2781 struct cvmx_pciercx_cfg460_s cn66xx;
2782 struct cvmx_pciercx_cfg460_s cn68xx;
2783 struct cvmx_pciercx_cfg460_s cn68xxp1;
2784 struct cvmx_pciercx_cfg460_s cnf71xx;
2785};
2786
2787union cvmx_pciercx_cfg461 {
2788 uint32_t u32;
2789 struct cvmx_pciercx_cfg461_s {
2790#ifdef __BIG_ENDIAN_BITFIELD
2791 uint32_t reserved_20_31:12;
2792 uint32_t tchfcc:8;
2793 uint32_t tcdfcc:12;
2794#else
2795 uint32_t tcdfcc:12;
2796 uint32_t tchfcc:8;
2797 uint32_t reserved_20_31:12;
2798#endif
2799 } s;
2800 struct cvmx_pciercx_cfg461_s cn52xx;
2801 struct cvmx_pciercx_cfg461_s cn52xxp1;
2802 struct cvmx_pciercx_cfg461_s cn56xx;
2803 struct cvmx_pciercx_cfg461_s cn56xxp1;
2804 struct cvmx_pciercx_cfg461_s cn61xx;
2805 struct cvmx_pciercx_cfg461_s cn63xx;
2806 struct cvmx_pciercx_cfg461_s cn63xxp1;
2807 struct cvmx_pciercx_cfg461_s cn66xx;
2808 struct cvmx_pciercx_cfg461_s cn68xx;
2809 struct cvmx_pciercx_cfg461_s cn68xxp1;
2810 struct cvmx_pciercx_cfg461_s cnf71xx;
2811};
2812
2813union cvmx_pciercx_cfg462 {
2814 uint32_t u32;
2815 struct cvmx_pciercx_cfg462_s {
2816#ifdef __BIG_ENDIAN_BITFIELD
2817 uint32_t reserved_20_31:12;
2818 uint32_t tchfcc:8;
2819 uint32_t tcdfcc:12;
2820#else
2821 uint32_t tcdfcc:12;
2822 uint32_t tchfcc:8;
2823 uint32_t reserved_20_31:12;
2824#endif
2825 } s;
2826 struct cvmx_pciercx_cfg462_s cn52xx;
2827 struct cvmx_pciercx_cfg462_s cn52xxp1;
2828 struct cvmx_pciercx_cfg462_s cn56xx;
2829 struct cvmx_pciercx_cfg462_s cn56xxp1;
2830 struct cvmx_pciercx_cfg462_s cn61xx;
2831 struct cvmx_pciercx_cfg462_s cn63xx;
2832 struct cvmx_pciercx_cfg462_s cn63xxp1;
2833 struct cvmx_pciercx_cfg462_s cn66xx;
2834 struct cvmx_pciercx_cfg462_s cn68xx;
2835 struct cvmx_pciercx_cfg462_s cn68xxp1;
2836 struct cvmx_pciercx_cfg462_s cnf71xx;
2837};
2838
2839union cvmx_pciercx_cfg463 {
2840 uint32_t u32;
2841 struct cvmx_pciercx_cfg463_s {
2842#ifdef __BIG_ENDIAN_BITFIELD
2843 uint32_t reserved_3_31:29;
2844 uint32_t rqne:1;
2845 uint32_t trbne:1;
2846 uint32_t rtlpfccnr:1;
2847#else
2848 uint32_t rtlpfccnr:1;
2849 uint32_t trbne:1;
2850 uint32_t rqne:1;
2851 uint32_t reserved_3_31:29;
2852#endif
2853 } s;
2854 struct cvmx_pciercx_cfg463_s cn52xx;
2855 struct cvmx_pciercx_cfg463_s cn52xxp1;
2856 struct cvmx_pciercx_cfg463_s cn56xx;
2857 struct cvmx_pciercx_cfg463_s cn56xxp1;
2858 struct cvmx_pciercx_cfg463_s cn61xx;
2859 struct cvmx_pciercx_cfg463_s cn63xx;
2860 struct cvmx_pciercx_cfg463_s cn63xxp1;
2861 struct cvmx_pciercx_cfg463_s cn66xx;
2862 struct cvmx_pciercx_cfg463_s cn68xx;
2863 struct cvmx_pciercx_cfg463_s cn68xxp1;
2864 struct cvmx_pciercx_cfg463_s cnf71xx;
2865};
2866
2867union cvmx_pciercx_cfg464 {
2868 uint32_t u32;
2869 struct cvmx_pciercx_cfg464_s {
2870#ifdef __BIG_ENDIAN_BITFIELD
2871 uint32_t wrr_vc3:8;
2872 uint32_t wrr_vc2:8;
2873 uint32_t wrr_vc1:8;
2874 uint32_t wrr_vc0:8;
2875#else
2876 uint32_t wrr_vc0:8;
2877 uint32_t wrr_vc1:8;
2878 uint32_t wrr_vc2:8;
2879 uint32_t wrr_vc3:8;
2880#endif
2881 } s;
2882 struct cvmx_pciercx_cfg464_s cn52xx;
2883 struct cvmx_pciercx_cfg464_s cn52xxp1;
2884 struct cvmx_pciercx_cfg464_s cn56xx;
2885 struct cvmx_pciercx_cfg464_s cn56xxp1;
2886 struct cvmx_pciercx_cfg464_s cn61xx;
2887 struct cvmx_pciercx_cfg464_s cn63xx;
2888 struct cvmx_pciercx_cfg464_s cn63xxp1;
2889 struct cvmx_pciercx_cfg464_s cn66xx;
2890 struct cvmx_pciercx_cfg464_s cn68xx;
2891 struct cvmx_pciercx_cfg464_s cn68xxp1;
2892 struct cvmx_pciercx_cfg464_s cnf71xx;
2893};
2894
2895union cvmx_pciercx_cfg465 {
2896 uint32_t u32;
2897 struct cvmx_pciercx_cfg465_s {
2898#ifdef __BIG_ENDIAN_BITFIELD
2899 uint32_t wrr_vc7:8;
2900 uint32_t wrr_vc6:8;
2901 uint32_t wrr_vc5:8;
2902 uint32_t wrr_vc4:8;
2903#else
2904 uint32_t wrr_vc4:8;
2905 uint32_t wrr_vc5:8;
2906 uint32_t wrr_vc6:8;
2907 uint32_t wrr_vc7:8;
2908#endif
2909 } s;
2910 struct cvmx_pciercx_cfg465_s cn52xx;
2911 struct cvmx_pciercx_cfg465_s cn52xxp1;
2912 struct cvmx_pciercx_cfg465_s cn56xx;
2913 struct cvmx_pciercx_cfg465_s cn56xxp1;
2914 struct cvmx_pciercx_cfg465_s cn61xx;
2915 struct cvmx_pciercx_cfg465_s cn63xx;
2916 struct cvmx_pciercx_cfg465_s cn63xxp1;
2917 struct cvmx_pciercx_cfg465_s cn66xx;
2918 struct cvmx_pciercx_cfg465_s cn68xx;
2919 struct cvmx_pciercx_cfg465_s cn68xxp1;
2920 struct cvmx_pciercx_cfg465_s cnf71xx;
2921};
2922
2923union cvmx_pciercx_cfg466 {
2924 uint32_t u32;
2925 struct cvmx_pciercx_cfg466_s {
2926#ifdef __BIG_ENDIAN_BITFIELD
2927 uint32_t rx_queue_order:1;
2928 uint32_t type_ordering:1;
2929 uint32_t reserved_24_29:6;
2930 uint32_t queue_mode:3;
2931 uint32_t reserved_20_20:1;
2932 uint32_t header_credits:8;
2933 uint32_t data_credits:12;
2934#else
2935 uint32_t data_credits:12;
2936 uint32_t header_credits:8;
2937 uint32_t reserved_20_20:1;
2938 uint32_t queue_mode:3;
2939 uint32_t reserved_24_29:6;
2940 uint32_t type_ordering:1;
2941 uint32_t rx_queue_order:1;
2942#endif
2943 } s;
2944 struct cvmx_pciercx_cfg466_s cn52xx;
2945 struct cvmx_pciercx_cfg466_s cn52xxp1;
2946 struct cvmx_pciercx_cfg466_s cn56xx;
2947 struct cvmx_pciercx_cfg466_s cn56xxp1;
2948 struct cvmx_pciercx_cfg466_s cn61xx;
2949 struct cvmx_pciercx_cfg466_s cn63xx;
2950 struct cvmx_pciercx_cfg466_s cn63xxp1;
2951 struct cvmx_pciercx_cfg466_s cn66xx;
2952 struct cvmx_pciercx_cfg466_s cn68xx;
2953 struct cvmx_pciercx_cfg466_s cn68xxp1;
2954 struct cvmx_pciercx_cfg466_s cnf71xx;
2955};
2956
2957union cvmx_pciercx_cfg467 {
2958 uint32_t u32;
2959 struct cvmx_pciercx_cfg467_s {
2960#ifdef __BIG_ENDIAN_BITFIELD
2961 uint32_t reserved_24_31:8;
2962 uint32_t queue_mode:3;
2963 uint32_t reserved_20_20:1;
2964 uint32_t header_credits:8;
2965 uint32_t data_credits:12;
2966#else
2967 uint32_t data_credits:12;
2968 uint32_t header_credits:8;
2969 uint32_t reserved_20_20:1;
2970 uint32_t queue_mode:3;
2971 uint32_t reserved_24_31:8;
2972#endif
2973 } s;
2974 struct cvmx_pciercx_cfg467_s cn52xx;
2975 struct cvmx_pciercx_cfg467_s cn52xxp1;
2976 struct cvmx_pciercx_cfg467_s cn56xx;
2977 struct cvmx_pciercx_cfg467_s cn56xxp1;
2978 struct cvmx_pciercx_cfg467_s cn61xx;
2979 struct cvmx_pciercx_cfg467_s cn63xx;
2980 struct cvmx_pciercx_cfg467_s cn63xxp1;
2981 struct cvmx_pciercx_cfg467_s cn66xx;
2982 struct cvmx_pciercx_cfg467_s cn68xx;
2983 struct cvmx_pciercx_cfg467_s cn68xxp1;
2984 struct cvmx_pciercx_cfg467_s cnf71xx;
2985};
2986
2987union cvmx_pciercx_cfg468 {
2988 uint32_t u32;
2989 struct cvmx_pciercx_cfg468_s {
2990#ifdef __BIG_ENDIAN_BITFIELD
2991 uint32_t reserved_24_31:8;
2992 uint32_t queue_mode:3;
2993 uint32_t reserved_20_20:1;
2994 uint32_t header_credits:8;
2995 uint32_t data_credits:12;
2996#else
2997 uint32_t data_credits:12;
2998 uint32_t header_credits:8;
2999 uint32_t reserved_20_20:1;
3000 uint32_t queue_mode:3;
3001 uint32_t reserved_24_31:8;
3002#endif
3003 } s;
3004 struct cvmx_pciercx_cfg468_s cn52xx;
3005 struct cvmx_pciercx_cfg468_s cn52xxp1;
3006 struct cvmx_pciercx_cfg468_s cn56xx;
3007 struct cvmx_pciercx_cfg468_s cn56xxp1;
3008 struct cvmx_pciercx_cfg468_s cn61xx;
3009 struct cvmx_pciercx_cfg468_s cn63xx;
3010 struct cvmx_pciercx_cfg468_s cn63xxp1;
3011 struct cvmx_pciercx_cfg468_s cn66xx;
3012 struct cvmx_pciercx_cfg468_s cn68xx;
3013 struct cvmx_pciercx_cfg468_s cn68xxp1;
3014 struct cvmx_pciercx_cfg468_s cnf71xx;
3015};
3016
3017union cvmx_pciercx_cfg490 {
3018 uint32_t u32;
3019 struct cvmx_pciercx_cfg490_s {
3020#ifdef __BIG_ENDIAN_BITFIELD
3021 uint32_t reserved_26_31:6;
3022 uint32_t header_depth:10;
3023 uint32_t reserved_14_15:2;
3024 uint32_t data_depth:14;
3025#else
3026 uint32_t data_depth:14;
3027 uint32_t reserved_14_15:2;
3028 uint32_t header_depth:10;
3029 uint32_t reserved_26_31:6;
3030#endif
3031 } s; 351 } s;
3032 struct cvmx_pciercx_cfg490_s cn52xx;
3033 struct cvmx_pciercx_cfg490_s cn52xxp1;
3034 struct cvmx_pciercx_cfg490_s cn56xx;
3035 struct cvmx_pciercx_cfg490_s cn56xxp1;
3036 struct cvmx_pciercx_cfg490_s cn61xx;
3037 struct cvmx_pciercx_cfg490_s cn63xx;
3038 struct cvmx_pciercx_cfg490_s cn63xxp1;
3039 struct cvmx_pciercx_cfg490_s cn66xx;
3040 struct cvmx_pciercx_cfg490_s cn68xx;
3041 struct cvmx_pciercx_cfg490_s cn68xxp1;
3042 struct cvmx_pciercx_cfg490_s cnf71xx;
3043};
3044
3045union cvmx_pciercx_cfg491 {
3046 uint32_t u32;
3047 struct cvmx_pciercx_cfg491_s {
3048#ifdef __BIG_ENDIAN_BITFIELD
3049 uint32_t reserved_26_31:6;
3050 uint32_t header_depth:10;
3051 uint32_t reserved_14_15:2;
3052 uint32_t data_depth:14;
3053#else
3054 uint32_t data_depth:14;
3055 uint32_t reserved_14_15:2;
3056 uint32_t header_depth:10;
3057 uint32_t reserved_26_31:6;
3058#endif
3059 } s;
3060 struct cvmx_pciercx_cfg491_s cn52xx;
3061 struct cvmx_pciercx_cfg491_s cn52xxp1;
3062 struct cvmx_pciercx_cfg491_s cn56xx;
3063 struct cvmx_pciercx_cfg491_s cn56xxp1;
3064 struct cvmx_pciercx_cfg491_s cn61xx;
3065 struct cvmx_pciercx_cfg491_s cn63xx;
3066 struct cvmx_pciercx_cfg491_s cn63xxp1;
3067 struct cvmx_pciercx_cfg491_s cn66xx;
3068 struct cvmx_pciercx_cfg491_s cn68xx;
3069 struct cvmx_pciercx_cfg491_s cn68xxp1;
3070 struct cvmx_pciercx_cfg491_s cnf71xx;
3071};
3072
3073union cvmx_pciercx_cfg492 {
3074 uint32_t u32;
3075 struct cvmx_pciercx_cfg492_s {
3076#ifdef __BIG_ENDIAN_BITFIELD
3077 uint32_t reserved_26_31:6;
3078 uint32_t header_depth:10;
3079 uint32_t reserved_14_15:2;
3080 uint32_t data_depth:14;
3081#else
3082 uint32_t data_depth:14;
3083 uint32_t reserved_14_15:2;
3084 uint32_t header_depth:10;
3085 uint32_t reserved_26_31:6;
3086#endif
3087 } s;
3088 struct cvmx_pciercx_cfg492_s cn52xx;
3089 struct cvmx_pciercx_cfg492_s cn52xxp1;
3090 struct cvmx_pciercx_cfg492_s cn56xx;
3091 struct cvmx_pciercx_cfg492_s cn56xxp1;
3092 struct cvmx_pciercx_cfg492_s cn61xx;
3093 struct cvmx_pciercx_cfg492_s cn63xx;
3094 struct cvmx_pciercx_cfg492_s cn63xxp1;
3095 struct cvmx_pciercx_cfg492_s cn66xx;
3096 struct cvmx_pciercx_cfg492_s cn68xx;
3097 struct cvmx_pciercx_cfg492_s cn68xxp1;
3098 struct cvmx_pciercx_cfg492_s cnf71xx;
3099}; 352};
3100 353
3101union cvmx_pciercx_cfg515 { 354union cvmx_pciercx_cfg515 {
3102 uint32_t u32; 355 uint32_t u32;
3103 struct cvmx_pciercx_cfg515_s { 356 struct cvmx_pciercx_cfg515_s {
3104#ifdef __BIG_ENDIAN_BITFIELD 357 __BITFIELD_FIELD(uint32_t reserved_21_31:11,
3105 uint32_t reserved_21_31:11; 358 __BITFIELD_FIELD(uint32_t s_d_e:1,
3106 uint32_t s_d_e:1; 359 __BITFIELD_FIELD(uint32_t ctcrb:1,
3107 uint32_t ctcrb:1; 360 __BITFIELD_FIELD(uint32_t cpyts:1,
3108 uint32_t cpyts:1; 361 __BITFIELD_FIELD(uint32_t dsc:1,
3109 uint32_t dsc:1; 362 __BITFIELD_FIELD(uint32_t le:9,
3110 uint32_t le:9; 363 __BITFIELD_FIELD(uint32_t n_fts:8,
3111 uint32_t n_fts:8; 364 ;)))))))
3112#else
3113 uint32_t n_fts:8;
3114 uint32_t le:9;
3115 uint32_t dsc:1;
3116 uint32_t cpyts:1;
3117 uint32_t ctcrb:1;
3118 uint32_t s_d_e:1;
3119 uint32_t reserved_21_31:11;
3120#endif
3121 } s;
3122 struct cvmx_pciercx_cfg515_s cn61xx;
3123 struct cvmx_pciercx_cfg515_s cn63xx;
3124 struct cvmx_pciercx_cfg515_s cn63xxp1;
3125 struct cvmx_pciercx_cfg515_s cn66xx;
3126 struct cvmx_pciercx_cfg515_s cn68xx;
3127 struct cvmx_pciercx_cfg515_s cn68xxp1;
3128 struct cvmx_pciercx_cfg515_s cnf71xx;
3129};
3130
3131union cvmx_pciercx_cfg516 {
3132 uint32_t u32;
3133 struct cvmx_pciercx_cfg516_s {
3134#ifdef __BIG_ENDIAN_BITFIELD
3135 uint32_t phy_stat:32;
3136#else
3137 uint32_t phy_stat:32;
3138#endif
3139 } s;
3140 struct cvmx_pciercx_cfg516_s cn52xx;
3141 struct cvmx_pciercx_cfg516_s cn52xxp1;
3142 struct cvmx_pciercx_cfg516_s cn56xx;
3143 struct cvmx_pciercx_cfg516_s cn56xxp1;
3144 struct cvmx_pciercx_cfg516_s cn61xx;
3145 struct cvmx_pciercx_cfg516_s cn63xx;
3146 struct cvmx_pciercx_cfg516_s cn63xxp1;
3147 struct cvmx_pciercx_cfg516_s cn66xx;
3148 struct cvmx_pciercx_cfg516_s cn68xx;
3149 struct cvmx_pciercx_cfg516_s cn68xxp1;
3150 struct cvmx_pciercx_cfg516_s cnf71xx;
3151};
3152
3153union cvmx_pciercx_cfg517 {
3154 uint32_t u32;
3155 struct cvmx_pciercx_cfg517_s {
3156#ifdef __BIG_ENDIAN_BITFIELD
3157 uint32_t phy_ctrl:32;
3158#else
3159 uint32_t phy_ctrl:32;
3160#endif
3161 } s; 365 } s;
3162 struct cvmx_pciercx_cfg517_s cn52xx;
3163 struct cvmx_pciercx_cfg517_s cn52xxp1;
3164 struct cvmx_pciercx_cfg517_s cn56xx;
3165 struct cvmx_pciercx_cfg517_s cn56xxp1;
3166 struct cvmx_pciercx_cfg517_s cn61xx;
3167 struct cvmx_pciercx_cfg517_s cn63xx;
3168 struct cvmx_pciercx_cfg517_s cn63xxp1;
3169 struct cvmx_pciercx_cfg517_s cn66xx;
3170 struct cvmx_pciercx_cfg517_s cn68xx;
3171 struct cvmx_pciercx_cfg517_s cn68xxp1;
3172 struct cvmx_pciercx_cfg517_s cnf71xx;
3173}; 366};
3174 367
3175#endif 368#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-sli-defs.h b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
index e697c2f52a62..52cf96ea43e5 100644
--- a/arch/mips/include/asm/octeon/cvmx-sli-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2012 Cavium Networks 7 * Copyright (c) 2003-2017 Cavium, Inc.
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,3494 +28,101 @@
28#ifndef __CVMX_SLI_DEFS_H__ 28#ifndef __CVMX_SLI_DEFS_H__
29#define __CVMX_SLI_DEFS_H__ 29#define __CVMX_SLI_DEFS_H__
30 30
31#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull) 31#include <uapi/asm/bitfield.h>
32#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16) 32
33#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull) 33#define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC()
34#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull) 34static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
35#define CVMX_SLI_DBG_DATA (0x0000000000000310ull) 35{
36#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull) 36 switch (cvmx_get_octeon_family()) {
37#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16) 37 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
38#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16) 38 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
39#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16) 39 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
40#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull) 40 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
41#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16) 41 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
42#define CVMX_SLI_INT_SUM (0x0000000000000330ull) 42 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
43#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull) 43 return 0x0000000000003CB0ull;
44#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull) 44 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
45#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull) 45 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
46#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull) 46 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
47#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull) 47 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
48#define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull) 48 return 0x0000000000003CB0ull;
49#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull) 49 default:
50#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull) 50 return 0x0000000000023CB0ull;
51#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12) 51 }
52#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull) 52}
53#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)
54#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)
55#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)
56#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull)
57#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull)
58#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull)
59#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull)
60#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull)
61#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
62#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)
63#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)
64#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)
65#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)
66#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)
67#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)
68#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)
69#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull)
70#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull)
71#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
72#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
73#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
74#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
75#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
76#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
77#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
78#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
79#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
80#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16)
81#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
82#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
83#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
84#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull)
85#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull)
86#define CVMX_SLI_PKT_CTL (0x0000000000001220ull)
87#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
88#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
89#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
90#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull)
91#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)
92#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull)
93#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)
94#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull)
95#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)
96#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull)
97#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
98#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull)
99#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)
100#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull)
101#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull)
102#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
103#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull)
104#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull)
105#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull)
106#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull)
107#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull)
108#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull)
109#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)
110#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull)
111#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
112#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)
113#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16)
114#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull)
115#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull)
116#define CVMX_SLI_STATE1 (0x0000000000000620ull)
117#define CVMX_SLI_STATE2 (0x0000000000000630ull)
118#define CVMX_SLI_STATE3 (0x0000000000000640ull)
119#define CVMX_SLI_TX_PIPE (0x0000000000001230ull)
120#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull)
121#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull)
122#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull)
123#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull)
124#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull)
125#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull)
126 53
127union cvmx_sli_bist_status {
128 uint64_t u64;
129 struct cvmx_sli_bist_status_s {
130#ifdef __BIG_ENDIAN_BITFIELD
131 uint64_t reserved_32_63:32;
132 uint64_t ncb_req:1;
133 uint64_t n2p0_c:1;
134 uint64_t n2p0_o:1;
135 uint64_t n2p1_c:1;
136 uint64_t n2p1_o:1;
137 uint64_t cpl_p0:1;
138 uint64_t cpl_p1:1;
139 uint64_t reserved_19_24:6;
140 uint64_t p2n0_c0:1;
141 uint64_t p2n0_c1:1;
142 uint64_t p2n0_n:1;
143 uint64_t p2n0_p0:1;
144 uint64_t p2n0_p1:1;
145 uint64_t p2n1_c0:1;
146 uint64_t p2n1_c1:1;
147 uint64_t p2n1_n:1;
148 uint64_t p2n1_p0:1;
149 uint64_t p2n1_p1:1;
150 uint64_t reserved_6_8:3;
151 uint64_t dsi1_1:1;
152 uint64_t dsi1_0:1;
153 uint64_t dsi0_1:1;
154 uint64_t dsi0_0:1;
155 uint64_t msi:1;
156 uint64_t ncb_cmd:1;
157#else
158 uint64_t ncb_cmd:1;
159 uint64_t msi:1;
160 uint64_t dsi0_0:1;
161 uint64_t dsi0_1:1;
162 uint64_t dsi1_0:1;
163 uint64_t dsi1_1:1;
164 uint64_t reserved_6_8:3;
165 uint64_t p2n1_p1:1;
166 uint64_t p2n1_p0:1;
167 uint64_t p2n1_n:1;
168 uint64_t p2n1_c1:1;
169 uint64_t p2n1_c0:1;
170 uint64_t p2n0_p1:1;
171 uint64_t p2n0_p0:1;
172 uint64_t p2n0_n:1;
173 uint64_t p2n0_c1:1;
174 uint64_t p2n0_c0:1;
175 uint64_t reserved_19_24:6;
176 uint64_t cpl_p1:1;
177 uint64_t cpl_p0:1;
178 uint64_t n2p1_o:1;
179 uint64_t n2p1_c:1;
180 uint64_t n2p0_o:1;
181 uint64_t n2p0_c:1;
182 uint64_t ncb_req:1;
183 uint64_t reserved_32_63:32;
184#endif
185 } s;
186 struct cvmx_sli_bist_status_cn61xx {
187#ifdef __BIG_ENDIAN_BITFIELD
188 uint64_t reserved_31_63:33;
189 uint64_t n2p0_c:1;
190 uint64_t n2p0_o:1;
191 uint64_t reserved_27_28:2;
192 uint64_t cpl_p0:1;
193 uint64_t cpl_p1:1;
194 uint64_t reserved_19_24:6;
195 uint64_t p2n0_c0:1;
196 uint64_t p2n0_c1:1;
197 uint64_t p2n0_n:1;
198 uint64_t p2n0_p0:1;
199 uint64_t p2n0_p1:1;
200 uint64_t p2n1_c0:1;
201 uint64_t p2n1_c1:1;
202 uint64_t p2n1_n:1;
203 uint64_t p2n1_p0:1;
204 uint64_t p2n1_p1:1;
205 uint64_t reserved_6_8:3;
206 uint64_t dsi1_1:1;
207 uint64_t dsi1_0:1;
208 uint64_t dsi0_1:1;
209 uint64_t dsi0_0:1;
210 uint64_t msi:1;
211 uint64_t ncb_cmd:1;
212#else
213 uint64_t ncb_cmd:1;
214 uint64_t msi:1;
215 uint64_t dsi0_0:1;
216 uint64_t dsi0_1:1;
217 uint64_t dsi1_0:1;
218 uint64_t dsi1_1:1;
219 uint64_t reserved_6_8:3;
220 uint64_t p2n1_p1:1;
221 uint64_t p2n1_p0:1;
222 uint64_t p2n1_n:1;
223 uint64_t p2n1_c1:1;
224 uint64_t p2n1_c0:1;
225 uint64_t p2n0_p1:1;
226 uint64_t p2n0_p0:1;
227 uint64_t p2n0_n:1;
228 uint64_t p2n0_c1:1;
229 uint64_t p2n0_c0:1;
230 uint64_t reserved_19_24:6;
231 uint64_t cpl_p1:1;
232 uint64_t cpl_p0:1;
233 uint64_t reserved_27_28:2;
234 uint64_t n2p0_o:1;
235 uint64_t n2p0_c:1;
236 uint64_t reserved_31_63:33;
237#endif
238 } cn61xx;
239 struct cvmx_sli_bist_status_cn63xx {
240#ifdef __BIG_ENDIAN_BITFIELD
241 uint64_t reserved_31_63:33;
242 uint64_t n2p0_c:1;
243 uint64_t n2p0_o:1;
244 uint64_t n2p1_c:1;
245 uint64_t n2p1_o:1;
246 uint64_t cpl_p0:1;
247 uint64_t cpl_p1:1;
248 uint64_t reserved_19_24:6;
249 uint64_t p2n0_c0:1;
250 uint64_t p2n0_c1:1;
251 uint64_t p2n0_n:1;
252 uint64_t p2n0_p0:1;
253 uint64_t p2n0_p1:1;
254 uint64_t p2n1_c0:1;
255 uint64_t p2n1_c1:1;
256 uint64_t p2n1_n:1;
257 uint64_t p2n1_p0:1;
258 uint64_t p2n1_p1:1;
259 uint64_t reserved_6_8:3;
260 uint64_t dsi1_1:1;
261 uint64_t dsi1_0:1;
262 uint64_t dsi0_1:1;
263 uint64_t dsi0_0:1;
264 uint64_t msi:1;
265 uint64_t ncb_cmd:1;
266#else
267 uint64_t ncb_cmd:1;
268 uint64_t msi:1;
269 uint64_t dsi0_0:1;
270 uint64_t dsi0_1:1;
271 uint64_t dsi1_0:1;
272 uint64_t dsi1_1:1;
273 uint64_t reserved_6_8:3;
274 uint64_t p2n1_p1:1;
275 uint64_t p2n1_p0:1;
276 uint64_t p2n1_n:1;
277 uint64_t p2n1_c1:1;
278 uint64_t p2n1_c0:1;
279 uint64_t p2n0_p1:1;
280 uint64_t p2n0_p0:1;
281 uint64_t p2n0_n:1;
282 uint64_t p2n0_c1:1;
283 uint64_t p2n0_c0:1;
284 uint64_t reserved_19_24:6;
285 uint64_t cpl_p1:1;
286 uint64_t cpl_p0:1;
287 uint64_t n2p1_o:1;
288 uint64_t n2p1_c:1;
289 uint64_t n2p0_o:1;
290 uint64_t n2p0_c:1;
291 uint64_t reserved_31_63:33;
292#endif
293 } cn63xx;
294 struct cvmx_sli_bist_status_cn63xx cn63xxp1;
295 struct cvmx_sli_bist_status_cn61xx cn66xx;
296 struct cvmx_sli_bist_status_s cn68xx;
297 struct cvmx_sli_bist_status_s cn68xxp1;
298 struct cvmx_sli_bist_status_cn61xx cnf71xx;
299};
300 54
301union cvmx_sli_ctl_portx { 55union cvmx_sli_ctl_portx {
302 uint64_t u64; 56 uint64_t u64;
303 struct cvmx_sli_ctl_portx_s { 57 struct cvmx_sli_ctl_portx_s {
304#ifdef __BIG_ENDIAN_BITFIELD 58 __BITFIELD_FIELD(uint64_t reserved_22_63:42,
305 uint64_t reserved_22_63:42; 59 __BITFIELD_FIELD(uint64_t intd:1,
306 uint64_t intd:1; 60 __BITFIELD_FIELD(uint64_t intc:1,
307 uint64_t intc:1; 61 __BITFIELD_FIELD(uint64_t intb:1,
308 uint64_t intb:1; 62 __BITFIELD_FIELD(uint64_t inta:1,
309 uint64_t inta:1; 63 __BITFIELD_FIELD(uint64_t dis_port:1,
310 uint64_t dis_port:1; 64 __BITFIELD_FIELD(uint64_t waitl_com:1,
311 uint64_t waitl_com:1; 65 __BITFIELD_FIELD(uint64_t intd_map:2,
312 uint64_t intd_map:2; 66 __BITFIELD_FIELD(uint64_t intc_map:2,
313 uint64_t intc_map:2; 67 __BITFIELD_FIELD(uint64_t intb_map:2,
314 uint64_t intb_map:2; 68 __BITFIELD_FIELD(uint64_t inta_map:2,
315 uint64_t inta_map:2; 69 __BITFIELD_FIELD(uint64_t ctlp_ro:1,
316 uint64_t ctlp_ro:1; 70 __BITFIELD_FIELD(uint64_t reserved_6_6:1,
317 uint64_t reserved_6_6:1; 71 __BITFIELD_FIELD(uint64_t ptlp_ro:1,
318 uint64_t ptlp_ro:1; 72 __BITFIELD_FIELD(uint64_t reserved_1_4:4,
319 uint64_t reserved_1_4:4; 73 __BITFIELD_FIELD(uint64_t wait_com:1,
320 uint64_t wait_com:1; 74 ;))))))))))))))))
321#else
322 uint64_t wait_com:1;
323 uint64_t reserved_1_4:4;
324 uint64_t ptlp_ro:1;
325 uint64_t reserved_6_6:1;
326 uint64_t ctlp_ro:1;
327 uint64_t inta_map:2;
328 uint64_t intb_map:2;
329 uint64_t intc_map:2;
330 uint64_t intd_map:2;
331 uint64_t waitl_com:1;
332 uint64_t dis_port:1;
333 uint64_t inta:1;
334 uint64_t intb:1;
335 uint64_t intc:1;
336 uint64_t intd:1;
337 uint64_t reserved_22_63:42;
338#endif
339 } s;
340 struct cvmx_sli_ctl_portx_s cn61xx;
341 struct cvmx_sli_ctl_portx_s cn63xx;
342 struct cvmx_sli_ctl_portx_s cn63xxp1;
343 struct cvmx_sli_ctl_portx_s cn66xx;
344 struct cvmx_sli_ctl_portx_s cn68xx;
345 struct cvmx_sli_ctl_portx_s cn68xxp1;
346 struct cvmx_sli_ctl_portx_s cnf71xx;
347};
348
349union cvmx_sli_ctl_status {
350 uint64_t u64;
351 struct cvmx_sli_ctl_status_s {
352#ifdef __BIG_ENDIAN_BITFIELD
353 uint64_t reserved_20_63:44;
354 uint64_t p1_ntags:6;
355 uint64_t p0_ntags:6;
356 uint64_t chip_rev:8;
357#else
358 uint64_t chip_rev:8;
359 uint64_t p0_ntags:6;
360 uint64_t p1_ntags:6;
361 uint64_t reserved_20_63:44;
362#endif
363 } s;
364 struct cvmx_sli_ctl_status_cn61xx {
365#ifdef __BIG_ENDIAN_BITFIELD
366 uint64_t reserved_14_63:50;
367 uint64_t p0_ntags:6;
368 uint64_t chip_rev:8;
369#else
370 uint64_t chip_rev:8;
371 uint64_t p0_ntags:6;
372 uint64_t reserved_14_63:50;
373#endif
374 } cn61xx;
375 struct cvmx_sli_ctl_status_s cn63xx;
376 struct cvmx_sli_ctl_status_s cn63xxp1;
377 struct cvmx_sli_ctl_status_cn61xx cn66xx;
378 struct cvmx_sli_ctl_status_s cn68xx;
379 struct cvmx_sli_ctl_status_s cn68xxp1;
380 struct cvmx_sli_ctl_status_cn61xx cnf71xx;
381};
382
383union cvmx_sli_data_out_cnt {
384 uint64_t u64;
385 struct cvmx_sli_data_out_cnt_s {
386#ifdef __BIG_ENDIAN_BITFIELD
387 uint64_t reserved_44_63:20;
388 uint64_t p1_ucnt:16;
389 uint64_t p1_fcnt:6;
390 uint64_t p0_ucnt:16;
391 uint64_t p0_fcnt:6;
392#else
393 uint64_t p0_fcnt:6;
394 uint64_t p0_ucnt:16;
395 uint64_t p1_fcnt:6;
396 uint64_t p1_ucnt:16;
397 uint64_t reserved_44_63:20;
398#endif
399 } s;
400 struct cvmx_sli_data_out_cnt_s cn61xx;
401 struct cvmx_sli_data_out_cnt_s cn63xx;
402 struct cvmx_sli_data_out_cnt_s cn63xxp1;
403 struct cvmx_sli_data_out_cnt_s cn66xx;
404 struct cvmx_sli_data_out_cnt_s cn68xx;
405 struct cvmx_sli_data_out_cnt_s cn68xxp1;
406 struct cvmx_sli_data_out_cnt_s cnf71xx;
407};
408
409union cvmx_sli_dbg_data {
410 uint64_t u64;
411 struct cvmx_sli_dbg_data_s {
412#ifdef __BIG_ENDIAN_BITFIELD
413 uint64_t reserved_18_63:46;
414 uint64_t dsel_ext:1;
415 uint64_t data:17;
416#else
417 uint64_t data:17;
418 uint64_t dsel_ext:1;
419 uint64_t reserved_18_63:46;
420#endif
421 } s;
422 struct cvmx_sli_dbg_data_s cn61xx;
423 struct cvmx_sli_dbg_data_s cn63xx;
424 struct cvmx_sli_dbg_data_s cn63xxp1;
425 struct cvmx_sli_dbg_data_s cn66xx;
426 struct cvmx_sli_dbg_data_s cn68xx;
427 struct cvmx_sli_dbg_data_s cn68xxp1;
428 struct cvmx_sli_dbg_data_s cnf71xx;
429};
430
431union cvmx_sli_dbg_select {
432 uint64_t u64;
433 struct cvmx_sli_dbg_select_s {
434#ifdef __BIG_ENDIAN_BITFIELD
435 uint64_t reserved_33_63:31;
436 uint64_t adbg_sel:1;
437 uint64_t dbg_sel:32;
438#else
439 uint64_t dbg_sel:32;
440 uint64_t adbg_sel:1;
441 uint64_t reserved_33_63:31;
442#endif
443 } s;
444 struct cvmx_sli_dbg_select_s cn61xx;
445 struct cvmx_sli_dbg_select_s cn63xx;
446 struct cvmx_sli_dbg_select_s cn63xxp1;
447 struct cvmx_sli_dbg_select_s cn66xx;
448 struct cvmx_sli_dbg_select_s cn68xx;
449 struct cvmx_sli_dbg_select_s cn68xxp1;
450 struct cvmx_sli_dbg_select_s cnf71xx;
451};
452
453union cvmx_sli_dmax_cnt {
454 uint64_t u64;
455 struct cvmx_sli_dmax_cnt_s {
456#ifdef __BIG_ENDIAN_BITFIELD
457 uint64_t reserved_32_63:32;
458 uint64_t cnt:32;
459#else
460 uint64_t cnt:32;
461 uint64_t reserved_32_63:32;
462#endif
463 } s;
464 struct cvmx_sli_dmax_cnt_s cn61xx;
465 struct cvmx_sli_dmax_cnt_s cn63xx;
466 struct cvmx_sli_dmax_cnt_s cn63xxp1;
467 struct cvmx_sli_dmax_cnt_s cn66xx;
468 struct cvmx_sli_dmax_cnt_s cn68xx;
469 struct cvmx_sli_dmax_cnt_s cn68xxp1;
470 struct cvmx_sli_dmax_cnt_s cnf71xx;
471};
472
473union cvmx_sli_dmax_int_level {
474 uint64_t u64;
475 struct cvmx_sli_dmax_int_level_s {
476#ifdef __BIG_ENDIAN_BITFIELD
477 uint64_t time:32;
478 uint64_t cnt:32;
479#else
480 uint64_t cnt:32;
481 uint64_t time:32;
482#endif
483 } s;
484 struct cvmx_sli_dmax_int_level_s cn61xx;
485 struct cvmx_sli_dmax_int_level_s cn63xx;
486 struct cvmx_sli_dmax_int_level_s cn63xxp1;
487 struct cvmx_sli_dmax_int_level_s cn66xx;
488 struct cvmx_sli_dmax_int_level_s cn68xx;
489 struct cvmx_sli_dmax_int_level_s cn68xxp1;
490 struct cvmx_sli_dmax_int_level_s cnf71xx;
491};
492
493union cvmx_sli_dmax_tim {
494 uint64_t u64;
495 struct cvmx_sli_dmax_tim_s {
496#ifdef __BIG_ENDIAN_BITFIELD
497 uint64_t reserved_32_63:32;
498 uint64_t tim:32;
499#else
500 uint64_t tim:32;
501 uint64_t reserved_32_63:32;
502#endif
503 } s;
504 struct cvmx_sli_dmax_tim_s cn61xx;
505 struct cvmx_sli_dmax_tim_s cn63xx;
506 struct cvmx_sli_dmax_tim_s cn63xxp1;
507 struct cvmx_sli_dmax_tim_s cn66xx;
508 struct cvmx_sli_dmax_tim_s cn68xx;
509 struct cvmx_sli_dmax_tim_s cn68xxp1;
510 struct cvmx_sli_dmax_tim_s cnf71xx;
511};
512
513union cvmx_sli_int_enb_ciu {
514 uint64_t u64;
515 struct cvmx_sli_int_enb_ciu_s {
516#ifdef __BIG_ENDIAN_BITFIELD
517 uint64_t reserved_62_63:2;
518 uint64_t pipe_err:1;
519 uint64_t ill_pad:1;
520 uint64_t sprt3_err:1;
521 uint64_t sprt2_err:1;
522 uint64_t sprt1_err:1;
523 uint64_t sprt0_err:1;
524 uint64_t pins_err:1;
525 uint64_t pop_err:1;
526 uint64_t pdi_err:1;
527 uint64_t pgl_err:1;
528 uint64_t pin_bp:1;
529 uint64_t pout_err:1;
530 uint64_t psldbof:1;
531 uint64_t pidbof:1;
532 uint64_t reserved_38_47:10;
533 uint64_t dtime:2;
534 uint64_t dcnt:2;
535 uint64_t dmafi:2;
536 uint64_t reserved_28_31:4;
537 uint64_t m3_un_wi:1;
538 uint64_t m3_un_b0:1;
539 uint64_t m3_up_wi:1;
540 uint64_t m3_up_b0:1;
541 uint64_t m2_un_wi:1;
542 uint64_t m2_un_b0:1;
543 uint64_t m2_up_wi:1;
544 uint64_t m2_up_b0:1;
545 uint64_t reserved_18_19:2;
546 uint64_t mio_int1:1;
547 uint64_t mio_int0:1;
548 uint64_t m1_un_wi:1;
549 uint64_t m1_un_b0:1;
550 uint64_t m1_up_wi:1;
551 uint64_t m1_up_b0:1;
552 uint64_t m0_un_wi:1;
553 uint64_t m0_un_b0:1;
554 uint64_t m0_up_wi:1;
555 uint64_t m0_up_b0:1;
556 uint64_t reserved_6_7:2;
557 uint64_t ptime:1;
558 uint64_t pcnt:1;
559 uint64_t iob2big:1;
560 uint64_t bar0_to:1;
561 uint64_t reserved_1_1:1;
562 uint64_t rml_to:1;
563#else
564 uint64_t rml_to:1;
565 uint64_t reserved_1_1:1;
566 uint64_t bar0_to:1;
567 uint64_t iob2big:1;
568 uint64_t pcnt:1;
569 uint64_t ptime:1;
570 uint64_t reserved_6_7:2;
571 uint64_t m0_up_b0:1;
572 uint64_t m0_up_wi:1;
573 uint64_t m0_un_b0:1;
574 uint64_t m0_un_wi:1;
575 uint64_t m1_up_b0:1;
576 uint64_t m1_up_wi:1;
577 uint64_t m1_un_b0:1;
578 uint64_t m1_un_wi:1;
579 uint64_t mio_int0:1;
580 uint64_t mio_int1:1;
581 uint64_t reserved_18_19:2;
582 uint64_t m2_up_b0:1;
583 uint64_t m2_up_wi:1;
584 uint64_t m2_un_b0:1;
585 uint64_t m2_un_wi:1;
586 uint64_t m3_up_b0:1;
587 uint64_t m3_up_wi:1;
588 uint64_t m3_un_b0:1;
589 uint64_t m3_un_wi:1;
590 uint64_t reserved_28_31:4;
591 uint64_t dmafi:2;
592 uint64_t dcnt:2;
593 uint64_t dtime:2;
594 uint64_t reserved_38_47:10;
595 uint64_t pidbof:1;
596 uint64_t psldbof:1;
597 uint64_t pout_err:1;
598 uint64_t pin_bp:1;
599 uint64_t pgl_err:1;
600 uint64_t pdi_err:1;
601 uint64_t pop_err:1;
602 uint64_t pins_err:1;
603 uint64_t sprt0_err:1;
604 uint64_t sprt1_err:1;
605 uint64_t sprt2_err:1;
606 uint64_t sprt3_err:1;
607 uint64_t ill_pad:1;
608 uint64_t pipe_err:1;
609 uint64_t reserved_62_63:2;
610#endif
611 } s;
612 struct cvmx_sli_int_enb_ciu_cn61xx {
613#ifdef __BIG_ENDIAN_BITFIELD
614 uint64_t reserved_61_63:3;
615 uint64_t ill_pad:1;
616 uint64_t sprt3_err:1;
617 uint64_t sprt2_err:1;
618 uint64_t sprt1_err:1;
619 uint64_t sprt0_err:1;
620 uint64_t pins_err:1;
621 uint64_t pop_err:1;
622 uint64_t pdi_err:1;
623 uint64_t pgl_err:1;
624 uint64_t pin_bp:1;
625 uint64_t pout_err:1;
626 uint64_t psldbof:1;
627 uint64_t pidbof:1;
628 uint64_t reserved_38_47:10;
629 uint64_t dtime:2;
630 uint64_t dcnt:2;
631 uint64_t dmafi:2;
632 uint64_t reserved_28_31:4;
633 uint64_t m3_un_wi:1;
634 uint64_t m3_un_b0:1;
635 uint64_t m3_up_wi:1;
636 uint64_t m3_up_b0:1;
637 uint64_t m2_un_wi:1;
638 uint64_t m2_un_b0:1;
639 uint64_t m2_up_wi:1;
640 uint64_t m2_up_b0:1;
641 uint64_t reserved_18_19:2;
642 uint64_t mio_int1:1;
643 uint64_t mio_int0:1;
644 uint64_t m1_un_wi:1;
645 uint64_t m1_un_b0:1;
646 uint64_t m1_up_wi:1;
647 uint64_t m1_up_b0:1;
648 uint64_t m0_un_wi:1;
649 uint64_t m0_un_b0:1;
650 uint64_t m0_up_wi:1;
651 uint64_t m0_up_b0:1;
652 uint64_t reserved_6_7:2;
653 uint64_t ptime:1;
654 uint64_t pcnt:1;
655 uint64_t iob2big:1;
656 uint64_t bar0_to:1;
657 uint64_t reserved_1_1:1;
658 uint64_t rml_to:1;
659#else
660 uint64_t rml_to:1;
661 uint64_t reserved_1_1:1;
662 uint64_t bar0_to:1;
663 uint64_t iob2big:1;
664 uint64_t pcnt:1;
665 uint64_t ptime:1;
666 uint64_t reserved_6_7:2;
667 uint64_t m0_up_b0:1;
668 uint64_t m0_up_wi:1;
669 uint64_t m0_un_b0:1;
670 uint64_t m0_un_wi:1;
671 uint64_t m1_up_b0:1;
672 uint64_t m1_up_wi:1;
673 uint64_t m1_un_b0:1;
674 uint64_t m1_un_wi:1;
675 uint64_t mio_int0:1;
676 uint64_t mio_int1:1;
677 uint64_t reserved_18_19:2;
678 uint64_t m2_up_b0:1;
679 uint64_t m2_up_wi:1;
680 uint64_t m2_un_b0:1;
681 uint64_t m2_un_wi:1;
682 uint64_t m3_up_b0:1;
683 uint64_t m3_up_wi:1;
684 uint64_t m3_un_b0:1;
685 uint64_t m3_un_wi:1;
686 uint64_t reserved_28_31:4;
687 uint64_t dmafi:2;
688 uint64_t dcnt:2;
689 uint64_t dtime:2;
690 uint64_t reserved_38_47:10;
691 uint64_t pidbof:1;
692 uint64_t psldbof:1;
693 uint64_t pout_err:1;
694 uint64_t pin_bp:1;
695 uint64_t pgl_err:1;
696 uint64_t pdi_err:1;
697 uint64_t pop_err:1;
698 uint64_t pins_err:1;
699 uint64_t sprt0_err:1;
700 uint64_t sprt1_err:1;
701 uint64_t sprt2_err:1;
702 uint64_t sprt3_err:1;
703 uint64_t ill_pad:1;
704 uint64_t reserved_61_63:3;
705#endif
706 } cn61xx;
707 struct cvmx_sli_int_enb_ciu_cn63xx {
708#ifdef __BIG_ENDIAN_BITFIELD
709 uint64_t reserved_61_63:3;
710 uint64_t ill_pad:1;
711 uint64_t reserved_58_59:2;
712 uint64_t sprt1_err:1;
713 uint64_t sprt0_err:1;
714 uint64_t pins_err:1;
715 uint64_t pop_err:1;
716 uint64_t pdi_err:1;
717 uint64_t pgl_err:1;
718 uint64_t pin_bp:1;
719 uint64_t pout_err:1;
720 uint64_t psldbof:1;
721 uint64_t pidbof:1;
722 uint64_t reserved_38_47:10;
723 uint64_t dtime:2;
724 uint64_t dcnt:2;
725 uint64_t dmafi:2;
726 uint64_t reserved_18_31:14;
727 uint64_t mio_int1:1;
728 uint64_t mio_int0:1;
729 uint64_t m1_un_wi:1;
730 uint64_t m1_un_b0:1;
731 uint64_t m1_up_wi:1;
732 uint64_t m1_up_b0:1;
733 uint64_t m0_un_wi:1;
734 uint64_t m0_un_b0:1;
735 uint64_t m0_up_wi:1;
736 uint64_t m0_up_b0:1;
737 uint64_t reserved_6_7:2;
738 uint64_t ptime:1;
739 uint64_t pcnt:1;
740 uint64_t iob2big:1;
741 uint64_t bar0_to:1;
742 uint64_t reserved_1_1:1;
743 uint64_t rml_to:1;
744#else
745 uint64_t rml_to:1;
746 uint64_t reserved_1_1:1;
747 uint64_t bar0_to:1;
748 uint64_t iob2big:1;
749 uint64_t pcnt:1;
750 uint64_t ptime:1;
751 uint64_t reserved_6_7:2;
752 uint64_t m0_up_b0:1;
753 uint64_t m0_up_wi:1;
754 uint64_t m0_un_b0:1;
755 uint64_t m0_un_wi:1;
756 uint64_t m1_up_b0:1;
757 uint64_t m1_up_wi:1;
758 uint64_t m1_un_b0:1;
759 uint64_t m1_un_wi:1;
760 uint64_t mio_int0:1;
761 uint64_t mio_int1:1;
762 uint64_t reserved_18_31:14;
763 uint64_t dmafi:2;
764 uint64_t dcnt:2;
765 uint64_t dtime:2;
766 uint64_t reserved_38_47:10;
767 uint64_t pidbof:1;
768 uint64_t psldbof:1;
769 uint64_t pout_err:1;
770 uint64_t pin_bp:1;
771 uint64_t pgl_err:1;
772 uint64_t pdi_err:1;
773 uint64_t pop_err:1;
774 uint64_t pins_err:1;
775 uint64_t sprt0_err:1;
776 uint64_t sprt1_err:1;
777 uint64_t reserved_58_59:2;
778 uint64_t ill_pad:1;
779 uint64_t reserved_61_63:3;
780#endif
781 } cn63xx;
782 struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1;
783 struct cvmx_sli_int_enb_ciu_cn61xx cn66xx;
784 struct cvmx_sli_int_enb_ciu_cn68xx {
785#ifdef __BIG_ENDIAN_BITFIELD
786 uint64_t reserved_62_63:2;
787 uint64_t pipe_err:1;
788 uint64_t ill_pad:1;
789 uint64_t reserved_58_59:2;
790 uint64_t sprt1_err:1;
791 uint64_t sprt0_err:1;
792 uint64_t pins_err:1;
793 uint64_t pop_err:1;
794 uint64_t pdi_err:1;
795 uint64_t pgl_err:1;
796 uint64_t reserved_51_51:1;
797 uint64_t pout_err:1;
798 uint64_t psldbof:1;
799 uint64_t pidbof:1;
800 uint64_t reserved_38_47:10;
801 uint64_t dtime:2;
802 uint64_t dcnt:2;
803 uint64_t dmafi:2;
804 uint64_t reserved_18_31:14;
805 uint64_t mio_int1:1;
806 uint64_t mio_int0:1;
807 uint64_t m1_un_wi:1;
808 uint64_t m1_un_b0:1;
809 uint64_t m1_up_wi:1;
810 uint64_t m1_up_b0:1;
811 uint64_t m0_un_wi:1;
812 uint64_t m0_un_b0:1;
813 uint64_t m0_up_wi:1;
814 uint64_t m0_up_b0:1;
815 uint64_t reserved_6_7:2;
816 uint64_t ptime:1;
817 uint64_t pcnt:1;
818 uint64_t iob2big:1;
819 uint64_t bar0_to:1;
820 uint64_t reserved_1_1:1;
821 uint64_t rml_to:1;
822#else
823 uint64_t rml_to:1;
824 uint64_t reserved_1_1:1;
825 uint64_t bar0_to:1;
826 uint64_t iob2big:1;
827 uint64_t pcnt:1;
828 uint64_t ptime:1;
829 uint64_t reserved_6_7:2;
830 uint64_t m0_up_b0:1;
831 uint64_t m0_up_wi:1;
832 uint64_t m0_un_b0:1;
833 uint64_t m0_un_wi:1;
834 uint64_t m1_up_b0:1;
835 uint64_t m1_up_wi:1;
836 uint64_t m1_un_b0:1;
837 uint64_t m1_un_wi:1;
838 uint64_t mio_int0:1;
839 uint64_t mio_int1:1;
840 uint64_t reserved_18_31:14;
841 uint64_t dmafi:2;
842 uint64_t dcnt:2;
843 uint64_t dtime:2;
844 uint64_t reserved_38_47:10;
845 uint64_t pidbof:1;
846 uint64_t psldbof:1;
847 uint64_t pout_err:1;
848 uint64_t reserved_51_51:1;
849 uint64_t pgl_err:1;
850 uint64_t pdi_err:1;
851 uint64_t pop_err:1;
852 uint64_t pins_err:1;
853 uint64_t sprt0_err:1;
854 uint64_t sprt1_err:1;
855 uint64_t reserved_58_59:2;
856 uint64_t ill_pad:1;
857 uint64_t pipe_err:1;
858 uint64_t reserved_62_63:2;
859#endif
860 } cn68xx;
861 struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1;
862 struct cvmx_sli_int_enb_ciu_cn61xx cnf71xx;
863};
864
865union cvmx_sli_int_enb_portx {
866 uint64_t u64;
867 struct cvmx_sli_int_enb_portx_s {
868#ifdef __BIG_ENDIAN_BITFIELD
869 uint64_t reserved_62_63:2;
870 uint64_t pipe_err:1;
871 uint64_t ill_pad:1;
872 uint64_t sprt3_err:1;
873 uint64_t sprt2_err:1;
874 uint64_t sprt1_err:1;
875 uint64_t sprt0_err:1;
876 uint64_t pins_err:1;
877 uint64_t pop_err:1;
878 uint64_t pdi_err:1;
879 uint64_t pgl_err:1;
880 uint64_t pin_bp:1;
881 uint64_t pout_err:1;
882 uint64_t psldbof:1;
883 uint64_t pidbof:1;
884 uint64_t reserved_38_47:10;
885 uint64_t dtime:2;
886 uint64_t dcnt:2;
887 uint64_t dmafi:2;
888 uint64_t reserved_28_31:4;
889 uint64_t m3_un_wi:1;
890 uint64_t m3_un_b0:1;
891 uint64_t m3_up_wi:1;
892 uint64_t m3_up_b0:1;
893 uint64_t m2_un_wi:1;
894 uint64_t m2_un_b0:1;
895 uint64_t m2_up_wi:1;
896 uint64_t m2_up_b0:1;
897 uint64_t mac1_int:1;
898 uint64_t mac0_int:1;
899 uint64_t mio_int1:1;
900 uint64_t mio_int0:1;
901 uint64_t m1_un_wi:1;
902 uint64_t m1_un_b0:1;
903 uint64_t m1_up_wi:1;
904 uint64_t m1_up_b0:1;
905 uint64_t m0_un_wi:1;
906 uint64_t m0_un_b0:1;
907 uint64_t m0_up_wi:1;
908 uint64_t m0_up_b0:1;
909 uint64_t reserved_6_7:2;
910 uint64_t ptime:1;
911 uint64_t pcnt:1;
912 uint64_t iob2big:1;
913 uint64_t bar0_to:1;
914 uint64_t reserved_1_1:1;
915 uint64_t rml_to:1;
916#else
917 uint64_t rml_to:1;
918 uint64_t reserved_1_1:1;
919 uint64_t bar0_to:1;
920 uint64_t iob2big:1;
921 uint64_t pcnt:1;
922 uint64_t ptime:1;
923 uint64_t reserved_6_7:2;
924 uint64_t m0_up_b0:1;
925 uint64_t m0_up_wi:1;
926 uint64_t m0_un_b0:1;
927 uint64_t m0_un_wi:1;
928 uint64_t m1_up_b0:1;
929 uint64_t m1_up_wi:1;
930 uint64_t m1_un_b0:1;
931 uint64_t m1_un_wi:1;
932 uint64_t mio_int0:1;
933 uint64_t mio_int1:1;
934 uint64_t mac0_int:1;
935 uint64_t mac1_int:1;
936 uint64_t m2_up_b0:1;
937 uint64_t m2_up_wi:1;
938 uint64_t m2_un_b0:1;
939 uint64_t m2_un_wi:1;
940 uint64_t m3_up_b0:1;
941 uint64_t m3_up_wi:1;
942 uint64_t m3_un_b0:1;
943 uint64_t m3_un_wi:1;
944 uint64_t reserved_28_31:4;
945 uint64_t dmafi:2;
946 uint64_t dcnt:2;
947 uint64_t dtime:2;
948 uint64_t reserved_38_47:10;
949 uint64_t pidbof:1;
950 uint64_t psldbof:1;
951 uint64_t pout_err:1;
952 uint64_t pin_bp:1;
953 uint64_t pgl_err:1;
954 uint64_t pdi_err:1;
955 uint64_t pop_err:1;
956 uint64_t pins_err:1;
957 uint64_t sprt0_err:1;
958 uint64_t sprt1_err:1;
959 uint64_t sprt2_err:1;
960 uint64_t sprt3_err:1;
961 uint64_t ill_pad:1;
962 uint64_t pipe_err:1;
963 uint64_t reserved_62_63:2;
964#endif
965 } s;
966 struct cvmx_sli_int_enb_portx_cn61xx {
967#ifdef __BIG_ENDIAN_BITFIELD
968 uint64_t reserved_61_63:3;
969 uint64_t ill_pad:1;
970 uint64_t sprt3_err:1;
971 uint64_t sprt2_err:1;
972 uint64_t sprt1_err:1;
973 uint64_t sprt0_err:1;
974 uint64_t pins_err:1;
975 uint64_t pop_err:1;
976 uint64_t pdi_err:1;
977 uint64_t pgl_err:1;
978 uint64_t pin_bp:1;
979 uint64_t pout_err:1;
980 uint64_t psldbof:1;
981 uint64_t pidbof:1;
982 uint64_t reserved_38_47:10;
983 uint64_t dtime:2;
984 uint64_t dcnt:2;
985 uint64_t dmafi:2;
986 uint64_t reserved_28_31:4;
987 uint64_t m3_un_wi:1;
988 uint64_t m3_un_b0:1;
989 uint64_t m3_up_wi:1;
990 uint64_t m3_up_b0:1;
991 uint64_t m2_un_wi:1;
992 uint64_t m2_un_b0:1;
993 uint64_t m2_up_wi:1;
994 uint64_t m2_up_b0:1;
995 uint64_t mac1_int:1;
996 uint64_t mac0_int:1;
997 uint64_t mio_int1:1;
998 uint64_t mio_int0:1;
999 uint64_t m1_un_wi:1;
1000 uint64_t m1_un_b0:1;
1001 uint64_t m1_up_wi:1;
1002 uint64_t m1_up_b0:1;
1003 uint64_t m0_un_wi:1;
1004 uint64_t m0_un_b0:1;
1005 uint64_t m0_up_wi:1;
1006 uint64_t m0_up_b0:1;
1007 uint64_t reserved_6_7:2;
1008 uint64_t ptime:1;
1009 uint64_t pcnt:1;
1010 uint64_t iob2big:1;
1011 uint64_t bar0_to:1;
1012 uint64_t reserved_1_1:1;
1013 uint64_t rml_to:1;
1014#else
1015 uint64_t rml_to:1;
1016 uint64_t reserved_1_1:1;
1017 uint64_t bar0_to:1;
1018 uint64_t iob2big:1;
1019 uint64_t pcnt:1;
1020 uint64_t ptime:1;
1021 uint64_t reserved_6_7:2;
1022 uint64_t m0_up_b0:1;
1023 uint64_t m0_up_wi:1;
1024 uint64_t m0_un_b0:1;
1025 uint64_t m0_un_wi:1;
1026 uint64_t m1_up_b0:1;
1027 uint64_t m1_up_wi:1;
1028 uint64_t m1_un_b0:1;
1029 uint64_t m1_un_wi:1;
1030 uint64_t mio_int0:1;
1031 uint64_t mio_int1:1;
1032 uint64_t mac0_int:1;
1033 uint64_t mac1_int:1;
1034 uint64_t m2_up_b0:1;
1035 uint64_t m2_up_wi:1;
1036 uint64_t m2_un_b0:1;
1037 uint64_t m2_un_wi:1;
1038 uint64_t m3_up_b0:1;
1039 uint64_t m3_up_wi:1;
1040 uint64_t m3_un_b0:1;
1041 uint64_t m3_un_wi:1;
1042 uint64_t reserved_28_31:4;
1043 uint64_t dmafi:2;
1044 uint64_t dcnt:2;
1045 uint64_t dtime:2;
1046 uint64_t reserved_38_47:10;
1047 uint64_t pidbof:1;
1048 uint64_t psldbof:1;
1049 uint64_t pout_err:1;
1050 uint64_t pin_bp:1;
1051 uint64_t pgl_err:1;
1052 uint64_t pdi_err:1;
1053 uint64_t pop_err:1;
1054 uint64_t pins_err:1;
1055 uint64_t sprt0_err:1;
1056 uint64_t sprt1_err:1;
1057 uint64_t sprt2_err:1;
1058 uint64_t sprt3_err:1;
1059 uint64_t ill_pad:1;
1060 uint64_t reserved_61_63:3;
1061#endif
1062 } cn61xx;
1063 struct cvmx_sli_int_enb_portx_cn63xx {
1064#ifdef __BIG_ENDIAN_BITFIELD
1065 uint64_t reserved_61_63:3;
1066 uint64_t ill_pad:1;
1067 uint64_t reserved_58_59:2;
1068 uint64_t sprt1_err:1;
1069 uint64_t sprt0_err:1;
1070 uint64_t pins_err:1;
1071 uint64_t pop_err:1;
1072 uint64_t pdi_err:1;
1073 uint64_t pgl_err:1;
1074 uint64_t pin_bp:1;
1075 uint64_t pout_err:1;
1076 uint64_t psldbof:1;
1077 uint64_t pidbof:1;
1078 uint64_t reserved_38_47:10;
1079 uint64_t dtime:2;
1080 uint64_t dcnt:2;
1081 uint64_t dmafi:2;
1082 uint64_t reserved_20_31:12;
1083 uint64_t mac1_int:1;
1084 uint64_t mac0_int:1;
1085 uint64_t mio_int1:1;
1086 uint64_t mio_int0:1;
1087 uint64_t m1_un_wi:1;
1088 uint64_t m1_un_b0:1;
1089 uint64_t m1_up_wi:1;
1090 uint64_t m1_up_b0:1;
1091 uint64_t m0_un_wi:1;
1092 uint64_t m0_un_b0:1;
1093 uint64_t m0_up_wi:1;
1094 uint64_t m0_up_b0:1;
1095 uint64_t reserved_6_7:2;
1096 uint64_t ptime:1;
1097 uint64_t pcnt:1;
1098 uint64_t iob2big:1;
1099 uint64_t bar0_to:1;
1100 uint64_t reserved_1_1:1;
1101 uint64_t rml_to:1;
1102#else
1103 uint64_t rml_to:1;
1104 uint64_t reserved_1_1:1;
1105 uint64_t bar0_to:1;
1106 uint64_t iob2big:1;
1107 uint64_t pcnt:1;
1108 uint64_t ptime:1;
1109 uint64_t reserved_6_7:2;
1110 uint64_t m0_up_b0:1;
1111 uint64_t m0_up_wi:1;
1112 uint64_t m0_un_b0:1;
1113 uint64_t m0_un_wi:1;
1114 uint64_t m1_up_b0:1;
1115 uint64_t m1_up_wi:1;
1116 uint64_t m1_un_b0:1;
1117 uint64_t m1_un_wi:1;
1118 uint64_t mio_int0:1;
1119 uint64_t mio_int1:1;
1120 uint64_t mac0_int:1;
1121 uint64_t mac1_int:1;
1122 uint64_t reserved_20_31:12;
1123 uint64_t dmafi:2;
1124 uint64_t dcnt:2;
1125 uint64_t dtime:2;
1126 uint64_t reserved_38_47:10;
1127 uint64_t pidbof:1;
1128 uint64_t psldbof:1;
1129 uint64_t pout_err:1;
1130 uint64_t pin_bp:1;
1131 uint64_t pgl_err:1;
1132 uint64_t pdi_err:1;
1133 uint64_t pop_err:1;
1134 uint64_t pins_err:1;
1135 uint64_t sprt0_err:1;
1136 uint64_t sprt1_err:1;
1137 uint64_t reserved_58_59:2;
1138 uint64_t ill_pad:1;
1139 uint64_t reserved_61_63:3;
1140#endif
1141 } cn63xx;
1142 struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1;
1143 struct cvmx_sli_int_enb_portx_cn61xx cn66xx;
1144 struct cvmx_sli_int_enb_portx_cn68xx {
1145#ifdef __BIG_ENDIAN_BITFIELD
1146 uint64_t reserved_62_63:2;
1147 uint64_t pipe_err:1;
1148 uint64_t ill_pad:1;
1149 uint64_t reserved_58_59:2;
1150 uint64_t sprt1_err:1;
1151 uint64_t sprt0_err:1;
1152 uint64_t pins_err:1;
1153 uint64_t pop_err:1;
1154 uint64_t pdi_err:1;
1155 uint64_t pgl_err:1;
1156 uint64_t reserved_51_51:1;
1157 uint64_t pout_err:1;
1158 uint64_t psldbof:1;
1159 uint64_t pidbof:1;
1160 uint64_t reserved_38_47:10;
1161 uint64_t dtime:2;
1162 uint64_t dcnt:2;
1163 uint64_t dmafi:2;
1164 uint64_t reserved_20_31:12;
1165 uint64_t mac1_int:1;
1166 uint64_t mac0_int:1;
1167 uint64_t mio_int1:1;
1168 uint64_t mio_int0:1;
1169 uint64_t m1_un_wi:1;
1170 uint64_t m1_un_b0:1;
1171 uint64_t m1_up_wi:1;
1172 uint64_t m1_up_b0:1;
1173 uint64_t m0_un_wi:1;
1174 uint64_t m0_un_b0:1;
1175 uint64_t m0_up_wi:1;
1176 uint64_t m0_up_b0:1;
1177 uint64_t reserved_6_7:2;
1178 uint64_t ptime:1;
1179 uint64_t pcnt:1;
1180 uint64_t iob2big:1;
1181 uint64_t bar0_to:1;
1182 uint64_t reserved_1_1:1;
1183 uint64_t rml_to:1;
1184#else
1185 uint64_t rml_to:1;
1186 uint64_t reserved_1_1:1;
1187 uint64_t bar0_to:1;
1188 uint64_t iob2big:1;
1189 uint64_t pcnt:1;
1190 uint64_t ptime:1;
1191 uint64_t reserved_6_7:2;
1192 uint64_t m0_up_b0:1;
1193 uint64_t m0_up_wi:1;
1194 uint64_t m0_un_b0:1;
1195 uint64_t m0_un_wi:1;
1196 uint64_t m1_up_b0:1;
1197 uint64_t m1_up_wi:1;
1198 uint64_t m1_un_b0:1;
1199 uint64_t m1_un_wi:1;
1200 uint64_t mio_int0:1;
1201 uint64_t mio_int1:1;
1202 uint64_t mac0_int:1;
1203 uint64_t mac1_int:1;
1204 uint64_t reserved_20_31:12;
1205 uint64_t dmafi:2;
1206 uint64_t dcnt:2;
1207 uint64_t dtime:2;
1208 uint64_t reserved_38_47:10;
1209 uint64_t pidbof:1;
1210 uint64_t psldbof:1;
1211 uint64_t pout_err:1;
1212 uint64_t reserved_51_51:1;
1213 uint64_t pgl_err:1;
1214 uint64_t pdi_err:1;
1215 uint64_t pop_err:1;
1216 uint64_t pins_err:1;
1217 uint64_t sprt0_err:1;
1218 uint64_t sprt1_err:1;
1219 uint64_t reserved_58_59:2;
1220 uint64_t ill_pad:1;
1221 uint64_t pipe_err:1;
1222 uint64_t reserved_62_63:2;
1223#endif
1224 } cn68xx;
1225 struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1;
1226 struct cvmx_sli_int_enb_portx_cn61xx cnf71xx;
1227};
1228
1229union cvmx_sli_int_sum {
1230 uint64_t u64;
1231 struct cvmx_sli_int_sum_s {
1232#ifdef __BIG_ENDIAN_BITFIELD
1233 uint64_t reserved_62_63:2;
1234 uint64_t pipe_err:1;
1235 uint64_t ill_pad:1;
1236 uint64_t sprt3_err:1;
1237 uint64_t sprt2_err:1;
1238 uint64_t sprt1_err:1;
1239 uint64_t sprt0_err:1;
1240 uint64_t pins_err:1;
1241 uint64_t pop_err:1;
1242 uint64_t pdi_err:1;
1243 uint64_t pgl_err:1;
1244 uint64_t pin_bp:1;
1245 uint64_t pout_err:1;
1246 uint64_t psldbof:1;
1247 uint64_t pidbof:1;
1248 uint64_t reserved_38_47:10;
1249 uint64_t dtime:2;
1250 uint64_t dcnt:2;
1251 uint64_t dmafi:2;
1252 uint64_t reserved_28_31:4;
1253 uint64_t m3_un_wi:1;
1254 uint64_t m3_un_b0:1;
1255 uint64_t m3_up_wi:1;
1256 uint64_t m3_up_b0:1;
1257 uint64_t m2_un_wi:1;
1258 uint64_t m2_un_b0:1;
1259 uint64_t m2_up_wi:1;
1260 uint64_t m2_up_b0:1;
1261 uint64_t mac1_int:1;
1262 uint64_t mac0_int:1;
1263 uint64_t mio_int1:1;
1264 uint64_t mio_int0:1;
1265 uint64_t m1_un_wi:1;
1266 uint64_t m1_un_b0:1;
1267 uint64_t m1_up_wi:1;
1268 uint64_t m1_up_b0:1;
1269 uint64_t m0_un_wi:1;
1270 uint64_t m0_un_b0:1;
1271 uint64_t m0_up_wi:1;
1272 uint64_t m0_up_b0:1;
1273 uint64_t reserved_6_7:2;
1274 uint64_t ptime:1;
1275 uint64_t pcnt:1;
1276 uint64_t iob2big:1;
1277 uint64_t bar0_to:1;
1278 uint64_t reserved_1_1:1;
1279 uint64_t rml_to:1;
1280#else
1281 uint64_t rml_to:1;
1282 uint64_t reserved_1_1:1;
1283 uint64_t bar0_to:1;
1284 uint64_t iob2big:1;
1285 uint64_t pcnt:1;
1286 uint64_t ptime:1;
1287 uint64_t reserved_6_7:2;
1288 uint64_t m0_up_b0:1;
1289 uint64_t m0_up_wi:1;
1290 uint64_t m0_un_b0:1;
1291 uint64_t m0_un_wi:1;
1292 uint64_t m1_up_b0:1;
1293 uint64_t m1_up_wi:1;
1294 uint64_t m1_un_b0:1;
1295 uint64_t m1_un_wi:1;
1296 uint64_t mio_int0:1;
1297 uint64_t mio_int1:1;
1298 uint64_t mac0_int:1;
1299 uint64_t mac1_int:1;
1300 uint64_t m2_up_b0:1;
1301 uint64_t m2_up_wi:1;
1302 uint64_t m2_un_b0:1;
1303 uint64_t m2_un_wi:1;
1304 uint64_t m3_up_b0:1;
1305 uint64_t m3_up_wi:1;
1306 uint64_t m3_un_b0:1;
1307 uint64_t m3_un_wi:1;
1308 uint64_t reserved_28_31:4;
1309 uint64_t dmafi:2;
1310 uint64_t dcnt:2;
1311 uint64_t dtime:2;
1312 uint64_t reserved_38_47:10;
1313 uint64_t pidbof:1;
1314 uint64_t psldbof:1;
1315 uint64_t pout_err:1;
1316 uint64_t pin_bp:1;
1317 uint64_t pgl_err:1;
1318 uint64_t pdi_err:1;
1319 uint64_t pop_err:1;
1320 uint64_t pins_err:1;
1321 uint64_t sprt0_err:1;
1322 uint64_t sprt1_err:1;
1323 uint64_t sprt2_err:1;
1324 uint64_t sprt3_err:1;
1325 uint64_t ill_pad:1;
1326 uint64_t pipe_err:1;
1327 uint64_t reserved_62_63:2;
1328#endif
1329 } s;
1330 struct cvmx_sli_int_sum_cn61xx {
1331#ifdef __BIG_ENDIAN_BITFIELD
1332 uint64_t reserved_61_63:3;
1333 uint64_t ill_pad:1;
1334 uint64_t sprt3_err:1;
1335 uint64_t sprt2_err:1;
1336 uint64_t sprt1_err:1;
1337 uint64_t sprt0_err:1;
1338 uint64_t pins_err:1;
1339 uint64_t pop_err:1;
1340 uint64_t pdi_err:1;
1341 uint64_t pgl_err:1;
1342 uint64_t pin_bp:1;
1343 uint64_t pout_err:1;
1344 uint64_t psldbof:1;
1345 uint64_t pidbof:1;
1346 uint64_t reserved_38_47:10;
1347 uint64_t dtime:2;
1348 uint64_t dcnt:2;
1349 uint64_t dmafi:2;
1350 uint64_t reserved_28_31:4;
1351 uint64_t m3_un_wi:1;
1352 uint64_t m3_un_b0:1;
1353 uint64_t m3_up_wi:1;
1354 uint64_t m3_up_b0:1;
1355 uint64_t m2_un_wi:1;
1356 uint64_t m2_un_b0:1;
1357 uint64_t m2_up_wi:1;
1358 uint64_t m2_up_b0:1;
1359 uint64_t mac1_int:1;
1360 uint64_t mac0_int:1;
1361 uint64_t mio_int1:1;
1362 uint64_t mio_int0:1;
1363 uint64_t m1_un_wi:1;
1364 uint64_t m1_un_b0:1;
1365 uint64_t m1_up_wi:1;
1366 uint64_t m1_up_b0:1;
1367 uint64_t m0_un_wi:1;
1368 uint64_t m0_un_b0:1;
1369 uint64_t m0_up_wi:1;
1370 uint64_t m0_up_b0:1;
1371 uint64_t reserved_6_7:2;
1372 uint64_t ptime:1;
1373 uint64_t pcnt:1;
1374 uint64_t iob2big:1;
1375 uint64_t bar0_to:1;
1376 uint64_t reserved_1_1:1;
1377 uint64_t rml_to:1;
1378#else
1379 uint64_t rml_to:1;
1380 uint64_t reserved_1_1:1;
1381 uint64_t bar0_to:1;
1382 uint64_t iob2big:1;
1383 uint64_t pcnt:1;
1384 uint64_t ptime:1;
1385 uint64_t reserved_6_7:2;
1386 uint64_t m0_up_b0:1;
1387 uint64_t m0_up_wi:1;
1388 uint64_t m0_un_b0:1;
1389 uint64_t m0_un_wi:1;
1390 uint64_t m1_up_b0:1;
1391 uint64_t m1_up_wi:1;
1392 uint64_t m1_un_b0:1;
1393 uint64_t m1_un_wi:1;
1394 uint64_t mio_int0:1;
1395 uint64_t mio_int1:1;
1396 uint64_t mac0_int:1;
1397 uint64_t mac1_int:1;
1398 uint64_t m2_up_b0:1;
1399 uint64_t m2_up_wi:1;
1400 uint64_t m2_un_b0:1;
1401 uint64_t m2_un_wi:1;
1402 uint64_t m3_up_b0:1;
1403 uint64_t m3_up_wi:1;
1404 uint64_t m3_un_b0:1;
1405 uint64_t m3_un_wi:1;
1406 uint64_t reserved_28_31:4;
1407 uint64_t dmafi:2;
1408 uint64_t dcnt:2;
1409 uint64_t dtime:2;
1410 uint64_t reserved_38_47:10;
1411 uint64_t pidbof:1;
1412 uint64_t psldbof:1;
1413 uint64_t pout_err:1;
1414 uint64_t pin_bp:1;
1415 uint64_t pgl_err:1;
1416 uint64_t pdi_err:1;
1417 uint64_t pop_err:1;
1418 uint64_t pins_err:1;
1419 uint64_t sprt0_err:1;
1420 uint64_t sprt1_err:1;
1421 uint64_t sprt2_err:1;
1422 uint64_t sprt3_err:1;
1423 uint64_t ill_pad:1;
1424 uint64_t reserved_61_63:3;
1425#endif
1426 } cn61xx;
1427 struct cvmx_sli_int_sum_cn63xx {
1428#ifdef __BIG_ENDIAN_BITFIELD
1429 uint64_t reserved_61_63:3;
1430 uint64_t ill_pad:1;
1431 uint64_t reserved_58_59:2;
1432 uint64_t sprt1_err:1;
1433 uint64_t sprt0_err:1;
1434 uint64_t pins_err:1;
1435 uint64_t pop_err:1;
1436 uint64_t pdi_err:1;
1437 uint64_t pgl_err:1;
1438 uint64_t pin_bp:1;
1439 uint64_t pout_err:1;
1440 uint64_t psldbof:1;
1441 uint64_t pidbof:1;
1442 uint64_t reserved_38_47:10;
1443 uint64_t dtime:2;
1444 uint64_t dcnt:2;
1445 uint64_t dmafi:2;
1446 uint64_t reserved_20_31:12;
1447 uint64_t mac1_int:1;
1448 uint64_t mac0_int:1;
1449 uint64_t mio_int1:1;
1450 uint64_t mio_int0:1;
1451 uint64_t m1_un_wi:1;
1452 uint64_t m1_un_b0:1;
1453 uint64_t m1_up_wi:1;
1454 uint64_t m1_up_b0:1;
1455 uint64_t m0_un_wi:1;
1456 uint64_t m0_un_b0:1;
1457 uint64_t m0_up_wi:1;
1458 uint64_t m0_up_b0:1;
1459 uint64_t reserved_6_7:2;
1460 uint64_t ptime:1;
1461 uint64_t pcnt:1;
1462 uint64_t iob2big:1;
1463 uint64_t bar0_to:1;
1464 uint64_t reserved_1_1:1;
1465 uint64_t rml_to:1;
1466#else
1467 uint64_t rml_to:1;
1468 uint64_t reserved_1_1:1;
1469 uint64_t bar0_to:1;
1470 uint64_t iob2big:1;
1471 uint64_t pcnt:1;
1472 uint64_t ptime:1;
1473 uint64_t reserved_6_7:2;
1474 uint64_t m0_up_b0:1;
1475 uint64_t m0_up_wi:1;
1476 uint64_t m0_un_b0:1;
1477 uint64_t m0_un_wi:1;
1478 uint64_t m1_up_b0:1;
1479 uint64_t m1_up_wi:1;
1480 uint64_t m1_un_b0:1;
1481 uint64_t m1_un_wi:1;
1482 uint64_t mio_int0:1;
1483 uint64_t mio_int1:1;
1484 uint64_t mac0_int:1;
1485 uint64_t mac1_int:1;
1486 uint64_t reserved_20_31:12;
1487 uint64_t dmafi:2;
1488 uint64_t dcnt:2;
1489 uint64_t dtime:2;
1490 uint64_t reserved_38_47:10;
1491 uint64_t pidbof:1;
1492 uint64_t psldbof:1;
1493 uint64_t pout_err:1;
1494 uint64_t pin_bp:1;
1495 uint64_t pgl_err:1;
1496 uint64_t pdi_err:1;
1497 uint64_t pop_err:1;
1498 uint64_t pins_err:1;
1499 uint64_t sprt0_err:1;
1500 uint64_t sprt1_err:1;
1501 uint64_t reserved_58_59:2;
1502 uint64_t ill_pad:1;
1503 uint64_t reserved_61_63:3;
1504#endif
1505 } cn63xx;
1506 struct cvmx_sli_int_sum_cn63xx cn63xxp1;
1507 struct cvmx_sli_int_sum_cn61xx cn66xx;
1508 struct cvmx_sli_int_sum_cn68xx {
1509#ifdef __BIG_ENDIAN_BITFIELD
1510 uint64_t reserved_62_63:2;
1511 uint64_t pipe_err:1;
1512 uint64_t ill_pad:1;
1513 uint64_t reserved_58_59:2;
1514 uint64_t sprt1_err:1;
1515 uint64_t sprt0_err:1;
1516 uint64_t pins_err:1;
1517 uint64_t pop_err:1;
1518 uint64_t pdi_err:1;
1519 uint64_t pgl_err:1;
1520 uint64_t reserved_51_51:1;
1521 uint64_t pout_err:1;
1522 uint64_t psldbof:1;
1523 uint64_t pidbof:1;
1524 uint64_t reserved_38_47:10;
1525 uint64_t dtime:2;
1526 uint64_t dcnt:2;
1527 uint64_t dmafi:2;
1528 uint64_t reserved_20_31:12;
1529 uint64_t mac1_int:1;
1530 uint64_t mac0_int:1;
1531 uint64_t mio_int1:1;
1532 uint64_t mio_int0:1;
1533 uint64_t m1_un_wi:1;
1534 uint64_t m1_un_b0:1;
1535 uint64_t m1_up_wi:1;
1536 uint64_t m1_up_b0:1;
1537 uint64_t m0_un_wi:1;
1538 uint64_t m0_un_b0:1;
1539 uint64_t m0_up_wi:1;
1540 uint64_t m0_up_b0:1;
1541 uint64_t reserved_6_7:2;
1542 uint64_t ptime:1;
1543 uint64_t pcnt:1;
1544 uint64_t iob2big:1;
1545 uint64_t bar0_to:1;
1546 uint64_t reserved_1_1:1;
1547 uint64_t rml_to:1;
1548#else
1549 uint64_t rml_to:1;
1550 uint64_t reserved_1_1:1;
1551 uint64_t bar0_to:1;
1552 uint64_t iob2big:1;
1553 uint64_t pcnt:1;
1554 uint64_t ptime:1;
1555 uint64_t reserved_6_7:2;
1556 uint64_t m0_up_b0:1;
1557 uint64_t m0_up_wi:1;
1558 uint64_t m0_un_b0:1;
1559 uint64_t m0_un_wi:1;
1560 uint64_t m1_up_b0:1;
1561 uint64_t m1_up_wi:1;
1562 uint64_t m1_un_b0:1;
1563 uint64_t m1_un_wi:1;
1564 uint64_t mio_int0:1;
1565 uint64_t mio_int1:1;
1566 uint64_t mac0_int:1;
1567 uint64_t mac1_int:1;
1568 uint64_t reserved_20_31:12;
1569 uint64_t dmafi:2;
1570 uint64_t dcnt:2;
1571 uint64_t dtime:2;
1572 uint64_t reserved_38_47:10;
1573 uint64_t pidbof:1;
1574 uint64_t psldbof:1;
1575 uint64_t pout_err:1;
1576 uint64_t reserved_51_51:1;
1577 uint64_t pgl_err:1;
1578 uint64_t pdi_err:1;
1579 uint64_t pop_err:1;
1580 uint64_t pins_err:1;
1581 uint64_t sprt0_err:1;
1582 uint64_t sprt1_err:1;
1583 uint64_t reserved_58_59:2;
1584 uint64_t ill_pad:1;
1585 uint64_t pipe_err:1;
1586 uint64_t reserved_62_63:2;
1587#endif
1588 } cn68xx;
1589 struct cvmx_sli_int_sum_cn68xx cn68xxp1;
1590 struct cvmx_sli_int_sum_cn61xx cnf71xx;
1591};
1592
1593union cvmx_sli_last_win_rdata0 {
1594 uint64_t u64;
1595 struct cvmx_sli_last_win_rdata0_s {
1596#ifdef __BIG_ENDIAN_BITFIELD
1597 uint64_t data:64;
1598#else
1599 uint64_t data:64;
1600#endif
1601 } s; 75 } s;
1602 struct cvmx_sli_last_win_rdata0_s cn61xx;
1603 struct cvmx_sli_last_win_rdata0_s cn63xx;
1604 struct cvmx_sli_last_win_rdata0_s cn63xxp1;
1605 struct cvmx_sli_last_win_rdata0_s cn66xx;
1606 struct cvmx_sli_last_win_rdata0_s cn68xx;
1607 struct cvmx_sli_last_win_rdata0_s cn68xxp1;
1608 struct cvmx_sli_last_win_rdata0_s cnf71xx;
1609};
1610
1611union cvmx_sli_last_win_rdata1 {
1612 uint64_t u64;
1613 struct cvmx_sli_last_win_rdata1_s {
1614#ifdef __BIG_ENDIAN_BITFIELD
1615 uint64_t data:64;
1616#else
1617 uint64_t data:64;
1618#endif
1619 } s;
1620 struct cvmx_sli_last_win_rdata1_s cn61xx;
1621 struct cvmx_sli_last_win_rdata1_s cn63xx;
1622 struct cvmx_sli_last_win_rdata1_s cn63xxp1;
1623 struct cvmx_sli_last_win_rdata1_s cn66xx;
1624 struct cvmx_sli_last_win_rdata1_s cn68xx;
1625 struct cvmx_sli_last_win_rdata1_s cn68xxp1;
1626 struct cvmx_sli_last_win_rdata1_s cnf71xx;
1627};
1628
1629union cvmx_sli_last_win_rdata2 {
1630 uint64_t u64;
1631 struct cvmx_sli_last_win_rdata2_s {
1632#ifdef __BIG_ENDIAN_BITFIELD
1633 uint64_t data:64;
1634#else
1635 uint64_t data:64;
1636#endif
1637 } s;
1638 struct cvmx_sli_last_win_rdata2_s cn61xx;
1639 struct cvmx_sli_last_win_rdata2_s cn66xx;
1640 struct cvmx_sli_last_win_rdata2_s cnf71xx;
1641};
1642
1643union cvmx_sli_last_win_rdata3 {
1644 uint64_t u64;
1645 struct cvmx_sli_last_win_rdata3_s {
1646#ifdef __BIG_ENDIAN_BITFIELD
1647 uint64_t data:64;
1648#else
1649 uint64_t data:64;
1650#endif
1651 } s;
1652 struct cvmx_sli_last_win_rdata3_s cn61xx;
1653 struct cvmx_sli_last_win_rdata3_s cn66xx;
1654 struct cvmx_sli_last_win_rdata3_s cnf71xx;
1655};
1656
1657union cvmx_sli_mac_credit_cnt {
1658 uint64_t u64;
1659 struct cvmx_sli_mac_credit_cnt_s {
1660#ifdef __BIG_ENDIAN_BITFIELD
1661 uint64_t reserved_54_63:10;
1662 uint64_t p1_c_d:1;
1663 uint64_t p1_n_d:1;
1664 uint64_t p1_p_d:1;
1665 uint64_t p0_c_d:1;
1666 uint64_t p0_n_d:1;
1667 uint64_t p0_p_d:1;
1668 uint64_t p1_ccnt:8;
1669 uint64_t p1_ncnt:8;
1670 uint64_t p1_pcnt:8;
1671 uint64_t p0_ccnt:8;
1672 uint64_t p0_ncnt:8;
1673 uint64_t p0_pcnt:8;
1674#else
1675 uint64_t p0_pcnt:8;
1676 uint64_t p0_ncnt:8;
1677 uint64_t p0_ccnt:8;
1678 uint64_t p1_pcnt:8;
1679 uint64_t p1_ncnt:8;
1680 uint64_t p1_ccnt:8;
1681 uint64_t p0_p_d:1;
1682 uint64_t p0_n_d:1;
1683 uint64_t p0_c_d:1;
1684 uint64_t p1_p_d:1;
1685 uint64_t p1_n_d:1;
1686 uint64_t p1_c_d:1;
1687 uint64_t reserved_54_63:10;
1688#endif
1689 } s;
1690 struct cvmx_sli_mac_credit_cnt_s cn61xx;
1691 struct cvmx_sli_mac_credit_cnt_s cn63xx;
1692 struct cvmx_sli_mac_credit_cnt_cn63xxp1 {
1693#ifdef __BIG_ENDIAN_BITFIELD
1694 uint64_t reserved_48_63:16;
1695 uint64_t p1_ccnt:8;
1696 uint64_t p1_ncnt:8;
1697 uint64_t p1_pcnt:8;
1698 uint64_t p0_ccnt:8;
1699 uint64_t p0_ncnt:8;
1700 uint64_t p0_pcnt:8;
1701#else
1702 uint64_t p0_pcnt:8;
1703 uint64_t p0_ncnt:8;
1704 uint64_t p0_ccnt:8;
1705 uint64_t p1_pcnt:8;
1706 uint64_t p1_ncnt:8;
1707 uint64_t p1_ccnt:8;
1708 uint64_t reserved_48_63:16;
1709#endif
1710 } cn63xxp1;
1711 struct cvmx_sli_mac_credit_cnt_s cn66xx;
1712 struct cvmx_sli_mac_credit_cnt_s cn68xx;
1713 struct cvmx_sli_mac_credit_cnt_s cn68xxp1;
1714 struct cvmx_sli_mac_credit_cnt_s cnf71xx;
1715};
1716
1717union cvmx_sli_mac_credit_cnt2 {
1718 uint64_t u64;
1719 struct cvmx_sli_mac_credit_cnt2_s {
1720#ifdef __BIG_ENDIAN_BITFIELD
1721 uint64_t reserved_54_63:10;
1722 uint64_t p3_c_d:1;
1723 uint64_t p3_n_d:1;
1724 uint64_t p3_p_d:1;
1725 uint64_t p2_c_d:1;
1726 uint64_t p2_n_d:1;
1727 uint64_t p2_p_d:1;
1728 uint64_t p3_ccnt:8;
1729 uint64_t p3_ncnt:8;
1730 uint64_t p3_pcnt:8;
1731 uint64_t p2_ccnt:8;
1732 uint64_t p2_ncnt:8;
1733 uint64_t p2_pcnt:8;
1734#else
1735 uint64_t p2_pcnt:8;
1736 uint64_t p2_ncnt:8;
1737 uint64_t p2_ccnt:8;
1738 uint64_t p3_pcnt:8;
1739 uint64_t p3_ncnt:8;
1740 uint64_t p3_ccnt:8;
1741 uint64_t p2_p_d:1;
1742 uint64_t p2_n_d:1;
1743 uint64_t p2_c_d:1;
1744 uint64_t p3_p_d:1;
1745 uint64_t p3_n_d:1;
1746 uint64_t p3_c_d:1;
1747 uint64_t reserved_54_63:10;
1748#endif
1749 } s;
1750 struct cvmx_sli_mac_credit_cnt2_s cn61xx;
1751 struct cvmx_sli_mac_credit_cnt2_s cn66xx;
1752 struct cvmx_sli_mac_credit_cnt2_s cnf71xx;
1753};
1754
1755union cvmx_sli_mac_number {
1756 uint64_t u64;
1757 struct cvmx_sli_mac_number_s {
1758#ifdef __BIG_ENDIAN_BITFIELD
1759 uint64_t reserved_9_63:55;
1760 uint64_t a_mode:1;
1761 uint64_t num:8;
1762#else
1763 uint64_t num:8;
1764 uint64_t a_mode:1;
1765 uint64_t reserved_9_63:55;
1766#endif
1767 } s;
1768 struct cvmx_sli_mac_number_s cn61xx;
1769 struct cvmx_sli_mac_number_cn63xx {
1770#ifdef __BIG_ENDIAN_BITFIELD
1771 uint64_t reserved_8_63:56;
1772 uint64_t num:8;
1773#else
1774 uint64_t num:8;
1775 uint64_t reserved_8_63:56;
1776#endif
1777 } cn63xx;
1778 struct cvmx_sli_mac_number_s cn66xx;
1779 struct cvmx_sli_mac_number_cn63xx cn68xx;
1780 struct cvmx_sli_mac_number_cn63xx cn68xxp1;
1781 struct cvmx_sli_mac_number_s cnf71xx;
1782}; 76};
1783 77
1784union cvmx_sli_mem_access_ctl { 78union cvmx_sli_mem_access_ctl {
1785 uint64_t u64; 79 uint64_t u64;
1786 struct cvmx_sli_mem_access_ctl_s { 80 struct cvmx_sli_mem_access_ctl_s {
1787#ifdef __BIG_ENDIAN_BITFIELD 81 __BITFIELD_FIELD(uint64_t reserved_14_63:50,
1788 uint64_t reserved_14_63:50; 82 __BITFIELD_FIELD(uint64_t max_word:4,
1789 uint64_t max_word:4; 83 __BITFIELD_FIELD(uint64_t timer:10,
1790 uint64_t timer:10; 84 ;)))
1791#else
1792 uint64_t timer:10;
1793 uint64_t max_word:4;
1794 uint64_t reserved_14_63:50;
1795#endif
1796 } s;
1797 struct cvmx_sli_mem_access_ctl_s cn61xx;
1798 struct cvmx_sli_mem_access_ctl_s cn63xx;
1799 struct cvmx_sli_mem_access_ctl_s cn63xxp1;
1800 struct cvmx_sli_mem_access_ctl_s cn66xx;
1801 struct cvmx_sli_mem_access_ctl_s cn68xx;
1802 struct cvmx_sli_mem_access_ctl_s cn68xxp1;
1803 struct cvmx_sli_mem_access_ctl_s cnf71xx;
1804};
1805
1806union cvmx_sli_mem_access_subidx {
1807 uint64_t u64;
1808 struct cvmx_sli_mem_access_subidx_s {
1809#ifdef __BIG_ENDIAN_BITFIELD
1810 uint64_t reserved_43_63:21;
1811 uint64_t zero:1;
1812 uint64_t port:3;
1813 uint64_t nmerge:1;
1814 uint64_t esr:2;
1815 uint64_t esw:2;
1816 uint64_t wtype:2;
1817 uint64_t rtype:2;
1818 uint64_t reserved_0_29:30;
1819#else
1820 uint64_t reserved_0_29:30;
1821 uint64_t rtype:2;
1822 uint64_t wtype:2;
1823 uint64_t esw:2;
1824 uint64_t esr:2;
1825 uint64_t nmerge:1;
1826 uint64_t port:3;
1827 uint64_t zero:1;
1828 uint64_t reserved_43_63:21;
1829#endif
1830 } s;
1831 struct cvmx_sli_mem_access_subidx_cn61xx {
1832#ifdef __BIG_ENDIAN_BITFIELD
1833 uint64_t reserved_43_63:21;
1834 uint64_t zero:1;
1835 uint64_t port:3;
1836 uint64_t nmerge:1;
1837 uint64_t esr:2;
1838 uint64_t esw:2;
1839 uint64_t wtype:2;
1840 uint64_t rtype:2;
1841 uint64_t ba:30;
1842#else
1843 uint64_t ba:30;
1844 uint64_t rtype:2;
1845 uint64_t wtype:2;
1846 uint64_t esw:2;
1847 uint64_t esr:2;
1848 uint64_t nmerge:1;
1849 uint64_t port:3;
1850 uint64_t zero:1;
1851 uint64_t reserved_43_63:21;
1852#endif
1853 } cn61xx;
1854 struct cvmx_sli_mem_access_subidx_cn61xx cn63xx;
1855 struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1;
1856 struct cvmx_sli_mem_access_subidx_cn61xx cn66xx;
1857 struct cvmx_sli_mem_access_subidx_cn68xx {
1858#ifdef __BIG_ENDIAN_BITFIELD
1859 uint64_t reserved_43_63:21;
1860 uint64_t zero:1;
1861 uint64_t port:3;
1862 uint64_t nmerge:1;
1863 uint64_t esr:2;
1864 uint64_t esw:2;
1865 uint64_t wtype:2;
1866 uint64_t rtype:2;
1867 uint64_t ba:28;
1868 uint64_t reserved_0_1:2;
1869#else
1870 uint64_t reserved_0_1:2;
1871 uint64_t ba:28;
1872 uint64_t rtype:2;
1873 uint64_t wtype:2;
1874 uint64_t esw:2;
1875 uint64_t esr:2;
1876 uint64_t nmerge:1;
1877 uint64_t port:3;
1878 uint64_t zero:1;
1879 uint64_t reserved_43_63:21;
1880#endif
1881 } cn68xx;
1882 struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1;
1883 struct cvmx_sli_mem_access_subidx_cn61xx cnf71xx;
1884};
1885
1886union cvmx_sli_msi_enb0 {
1887 uint64_t u64;
1888 struct cvmx_sli_msi_enb0_s {
1889#ifdef __BIG_ENDIAN_BITFIELD
1890 uint64_t enb:64;
1891#else
1892 uint64_t enb:64;
1893#endif
1894 } s;
1895 struct cvmx_sli_msi_enb0_s cn61xx;
1896 struct cvmx_sli_msi_enb0_s cn63xx;
1897 struct cvmx_sli_msi_enb0_s cn63xxp1;
1898 struct cvmx_sli_msi_enb0_s cn66xx;
1899 struct cvmx_sli_msi_enb0_s cn68xx;
1900 struct cvmx_sli_msi_enb0_s cn68xxp1;
1901 struct cvmx_sli_msi_enb0_s cnf71xx;
1902};
1903
1904union cvmx_sli_msi_enb1 {
1905 uint64_t u64;
1906 struct cvmx_sli_msi_enb1_s {
1907#ifdef __BIG_ENDIAN_BITFIELD
1908 uint64_t enb:64;
1909#else
1910 uint64_t enb:64;
1911#endif
1912 } s;
1913 struct cvmx_sli_msi_enb1_s cn61xx;
1914 struct cvmx_sli_msi_enb1_s cn63xx;
1915 struct cvmx_sli_msi_enb1_s cn63xxp1;
1916 struct cvmx_sli_msi_enb1_s cn66xx;
1917 struct cvmx_sli_msi_enb1_s cn68xx;
1918 struct cvmx_sli_msi_enb1_s cn68xxp1;
1919 struct cvmx_sli_msi_enb1_s cnf71xx;
1920};
1921
1922union cvmx_sli_msi_enb2 {
1923 uint64_t u64;
1924 struct cvmx_sli_msi_enb2_s {
1925#ifdef __BIG_ENDIAN_BITFIELD
1926 uint64_t enb:64;
1927#else
1928 uint64_t enb:64;
1929#endif
1930 } s;
1931 struct cvmx_sli_msi_enb2_s cn61xx;
1932 struct cvmx_sli_msi_enb2_s cn63xx;
1933 struct cvmx_sli_msi_enb2_s cn63xxp1;
1934 struct cvmx_sli_msi_enb2_s cn66xx;
1935 struct cvmx_sli_msi_enb2_s cn68xx;
1936 struct cvmx_sli_msi_enb2_s cn68xxp1;
1937 struct cvmx_sli_msi_enb2_s cnf71xx;
1938};
1939
1940union cvmx_sli_msi_enb3 {
1941 uint64_t u64;
1942 struct cvmx_sli_msi_enb3_s {
1943#ifdef __BIG_ENDIAN_BITFIELD
1944 uint64_t enb:64;
1945#else
1946 uint64_t enb:64;
1947#endif
1948 } s;
1949 struct cvmx_sli_msi_enb3_s cn61xx;
1950 struct cvmx_sli_msi_enb3_s cn63xx;
1951 struct cvmx_sli_msi_enb3_s cn63xxp1;
1952 struct cvmx_sli_msi_enb3_s cn66xx;
1953 struct cvmx_sli_msi_enb3_s cn68xx;
1954 struct cvmx_sli_msi_enb3_s cn68xxp1;
1955 struct cvmx_sli_msi_enb3_s cnf71xx;
1956};
1957
1958union cvmx_sli_msi_rcv0 {
1959 uint64_t u64;
1960 struct cvmx_sli_msi_rcv0_s {
1961#ifdef __BIG_ENDIAN_BITFIELD
1962 uint64_t intr:64;
1963#else
1964 uint64_t intr:64;
1965#endif
1966 } s;
1967 struct cvmx_sli_msi_rcv0_s cn61xx;
1968 struct cvmx_sli_msi_rcv0_s cn63xx;
1969 struct cvmx_sli_msi_rcv0_s cn63xxp1;
1970 struct cvmx_sli_msi_rcv0_s cn66xx;
1971 struct cvmx_sli_msi_rcv0_s cn68xx;
1972 struct cvmx_sli_msi_rcv0_s cn68xxp1;
1973 struct cvmx_sli_msi_rcv0_s cnf71xx;
1974};
1975
1976union cvmx_sli_msi_rcv1 {
1977 uint64_t u64;
1978 struct cvmx_sli_msi_rcv1_s {
1979#ifdef __BIG_ENDIAN_BITFIELD
1980 uint64_t intr:64;
1981#else
1982 uint64_t intr:64;
1983#endif
1984 } s;
1985 struct cvmx_sli_msi_rcv1_s cn61xx;
1986 struct cvmx_sli_msi_rcv1_s cn63xx;
1987 struct cvmx_sli_msi_rcv1_s cn63xxp1;
1988 struct cvmx_sli_msi_rcv1_s cn66xx;
1989 struct cvmx_sli_msi_rcv1_s cn68xx;
1990 struct cvmx_sli_msi_rcv1_s cn68xxp1;
1991 struct cvmx_sli_msi_rcv1_s cnf71xx;
1992};
1993
1994union cvmx_sli_msi_rcv2 {
1995 uint64_t u64;
1996 struct cvmx_sli_msi_rcv2_s {
1997#ifdef __BIG_ENDIAN_BITFIELD
1998 uint64_t intr:64;
1999#else
2000 uint64_t intr:64;
2001#endif
2002 } s;
2003 struct cvmx_sli_msi_rcv2_s cn61xx;
2004 struct cvmx_sli_msi_rcv2_s cn63xx;
2005 struct cvmx_sli_msi_rcv2_s cn63xxp1;
2006 struct cvmx_sli_msi_rcv2_s cn66xx;
2007 struct cvmx_sli_msi_rcv2_s cn68xx;
2008 struct cvmx_sli_msi_rcv2_s cn68xxp1;
2009 struct cvmx_sli_msi_rcv2_s cnf71xx;
2010};
2011
2012union cvmx_sli_msi_rcv3 {
2013 uint64_t u64;
2014 struct cvmx_sli_msi_rcv3_s {
2015#ifdef __BIG_ENDIAN_BITFIELD
2016 uint64_t intr:64;
2017#else
2018 uint64_t intr:64;
2019#endif
2020 } s;
2021 struct cvmx_sli_msi_rcv3_s cn61xx;
2022 struct cvmx_sli_msi_rcv3_s cn63xx;
2023 struct cvmx_sli_msi_rcv3_s cn63xxp1;
2024 struct cvmx_sli_msi_rcv3_s cn66xx;
2025 struct cvmx_sli_msi_rcv3_s cn68xx;
2026 struct cvmx_sli_msi_rcv3_s cn68xxp1;
2027 struct cvmx_sli_msi_rcv3_s cnf71xx;
2028};
2029
2030union cvmx_sli_msi_rd_map {
2031 uint64_t u64;
2032 struct cvmx_sli_msi_rd_map_s {
2033#ifdef __BIG_ENDIAN_BITFIELD
2034 uint64_t reserved_16_63:48;
2035 uint64_t rd_int:8;
2036 uint64_t msi_int:8;
2037#else
2038 uint64_t msi_int:8;
2039 uint64_t rd_int:8;
2040 uint64_t reserved_16_63:48;
2041#endif
2042 } s;
2043 struct cvmx_sli_msi_rd_map_s cn61xx;
2044 struct cvmx_sli_msi_rd_map_s cn63xx;
2045 struct cvmx_sli_msi_rd_map_s cn63xxp1;
2046 struct cvmx_sli_msi_rd_map_s cn66xx;
2047 struct cvmx_sli_msi_rd_map_s cn68xx;
2048 struct cvmx_sli_msi_rd_map_s cn68xxp1;
2049 struct cvmx_sli_msi_rd_map_s cnf71xx;
2050};
2051
2052union cvmx_sli_msi_w1c_enb0 {
2053 uint64_t u64;
2054 struct cvmx_sli_msi_w1c_enb0_s {
2055#ifdef __BIG_ENDIAN_BITFIELD
2056 uint64_t clr:64;
2057#else
2058 uint64_t clr:64;
2059#endif
2060 } s;
2061 struct cvmx_sli_msi_w1c_enb0_s cn61xx;
2062 struct cvmx_sli_msi_w1c_enb0_s cn63xx;
2063 struct cvmx_sli_msi_w1c_enb0_s cn63xxp1;
2064 struct cvmx_sli_msi_w1c_enb0_s cn66xx;
2065 struct cvmx_sli_msi_w1c_enb0_s cn68xx;
2066 struct cvmx_sli_msi_w1c_enb0_s cn68xxp1;
2067 struct cvmx_sli_msi_w1c_enb0_s cnf71xx;
2068};
2069
2070union cvmx_sli_msi_w1c_enb1 {
2071 uint64_t u64;
2072 struct cvmx_sli_msi_w1c_enb1_s {
2073#ifdef __BIG_ENDIAN_BITFIELD
2074 uint64_t clr:64;
2075#else
2076 uint64_t clr:64;
2077#endif
2078 } s;
2079 struct cvmx_sli_msi_w1c_enb1_s cn61xx;
2080 struct cvmx_sli_msi_w1c_enb1_s cn63xx;
2081 struct cvmx_sli_msi_w1c_enb1_s cn63xxp1;
2082 struct cvmx_sli_msi_w1c_enb1_s cn66xx;
2083 struct cvmx_sli_msi_w1c_enb1_s cn68xx;
2084 struct cvmx_sli_msi_w1c_enb1_s cn68xxp1;
2085 struct cvmx_sli_msi_w1c_enb1_s cnf71xx;
2086};
2087
2088union cvmx_sli_msi_w1c_enb2 {
2089 uint64_t u64;
2090 struct cvmx_sli_msi_w1c_enb2_s {
2091#ifdef __BIG_ENDIAN_BITFIELD
2092 uint64_t clr:64;
2093#else
2094 uint64_t clr:64;
2095#endif
2096 } s;
2097 struct cvmx_sli_msi_w1c_enb2_s cn61xx;
2098 struct cvmx_sli_msi_w1c_enb2_s cn63xx;
2099 struct cvmx_sli_msi_w1c_enb2_s cn63xxp1;
2100 struct cvmx_sli_msi_w1c_enb2_s cn66xx;
2101 struct cvmx_sli_msi_w1c_enb2_s cn68xx;
2102 struct cvmx_sli_msi_w1c_enb2_s cn68xxp1;
2103 struct cvmx_sli_msi_w1c_enb2_s cnf71xx;
2104};
2105
2106union cvmx_sli_msi_w1c_enb3 {
2107 uint64_t u64;
2108 struct cvmx_sli_msi_w1c_enb3_s {
2109#ifdef __BIG_ENDIAN_BITFIELD
2110 uint64_t clr:64;
2111#else
2112 uint64_t clr:64;
2113#endif
2114 } s;
2115 struct cvmx_sli_msi_w1c_enb3_s cn61xx;
2116 struct cvmx_sli_msi_w1c_enb3_s cn63xx;
2117 struct cvmx_sli_msi_w1c_enb3_s cn63xxp1;
2118 struct cvmx_sli_msi_w1c_enb3_s cn66xx;
2119 struct cvmx_sli_msi_w1c_enb3_s cn68xx;
2120 struct cvmx_sli_msi_w1c_enb3_s cn68xxp1;
2121 struct cvmx_sli_msi_w1c_enb3_s cnf71xx;
2122};
2123
2124union cvmx_sli_msi_w1s_enb0 {
2125 uint64_t u64;
2126 struct cvmx_sli_msi_w1s_enb0_s {
2127#ifdef __BIG_ENDIAN_BITFIELD
2128 uint64_t set:64;
2129#else
2130 uint64_t set:64;
2131#endif
2132 } s;
2133 struct cvmx_sli_msi_w1s_enb0_s cn61xx;
2134 struct cvmx_sli_msi_w1s_enb0_s cn63xx;
2135 struct cvmx_sli_msi_w1s_enb0_s cn63xxp1;
2136 struct cvmx_sli_msi_w1s_enb0_s cn66xx;
2137 struct cvmx_sli_msi_w1s_enb0_s cn68xx;
2138 struct cvmx_sli_msi_w1s_enb0_s cn68xxp1;
2139 struct cvmx_sli_msi_w1s_enb0_s cnf71xx;
2140};
2141
2142union cvmx_sli_msi_w1s_enb1 {
2143 uint64_t u64;
2144 struct cvmx_sli_msi_w1s_enb1_s {
2145#ifdef __BIG_ENDIAN_BITFIELD
2146 uint64_t set:64;
2147#else
2148 uint64_t set:64;
2149#endif
2150 } s;
2151 struct cvmx_sli_msi_w1s_enb1_s cn61xx;
2152 struct cvmx_sli_msi_w1s_enb1_s cn63xx;
2153 struct cvmx_sli_msi_w1s_enb1_s cn63xxp1;
2154 struct cvmx_sli_msi_w1s_enb1_s cn66xx;
2155 struct cvmx_sli_msi_w1s_enb1_s cn68xx;
2156 struct cvmx_sli_msi_w1s_enb1_s cn68xxp1;
2157 struct cvmx_sli_msi_w1s_enb1_s cnf71xx;
2158};
2159
2160union cvmx_sli_msi_w1s_enb2 {
2161 uint64_t u64;
2162 struct cvmx_sli_msi_w1s_enb2_s {
2163#ifdef __BIG_ENDIAN_BITFIELD
2164 uint64_t set:64;
2165#else
2166 uint64_t set:64;
2167#endif
2168 } s;
2169 struct cvmx_sli_msi_w1s_enb2_s cn61xx;
2170 struct cvmx_sli_msi_w1s_enb2_s cn63xx;
2171 struct cvmx_sli_msi_w1s_enb2_s cn63xxp1;
2172 struct cvmx_sli_msi_w1s_enb2_s cn66xx;
2173 struct cvmx_sli_msi_w1s_enb2_s cn68xx;
2174 struct cvmx_sli_msi_w1s_enb2_s cn68xxp1;
2175 struct cvmx_sli_msi_w1s_enb2_s cnf71xx;
2176};
2177
2178union cvmx_sli_msi_w1s_enb3 {
2179 uint64_t u64;
2180 struct cvmx_sli_msi_w1s_enb3_s {
2181#ifdef __BIG_ENDIAN_BITFIELD
2182 uint64_t set:64;
2183#else
2184 uint64_t set:64;
2185#endif
2186 } s;
2187 struct cvmx_sli_msi_w1s_enb3_s cn61xx;
2188 struct cvmx_sli_msi_w1s_enb3_s cn63xx;
2189 struct cvmx_sli_msi_w1s_enb3_s cn63xxp1;
2190 struct cvmx_sli_msi_w1s_enb3_s cn66xx;
2191 struct cvmx_sli_msi_w1s_enb3_s cn68xx;
2192 struct cvmx_sli_msi_w1s_enb3_s cn68xxp1;
2193 struct cvmx_sli_msi_w1s_enb3_s cnf71xx;
2194};
2195
2196union cvmx_sli_msi_wr_map {
2197 uint64_t u64;
2198 struct cvmx_sli_msi_wr_map_s {
2199#ifdef __BIG_ENDIAN_BITFIELD
2200 uint64_t reserved_16_63:48;
2201 uint64_t ciu_int:8;
2202 uint64_t msi_int:8;
2203#else
2204 uint64_t msi_int:8;
2205 uint64_t ciu_int:8;
2206 uint64_t reserved_16_63:48;
2207#endif
2208 } s;
2209 struct cvmx_sli_msi_wr_map_s cn61xx;
2210 struct cvmx_sli_msi_wr_map_s cn63xx;
2211 struct cvmx_sli_msi_wr_map_s cn63xxp1;
2212 struct cvmx_sli_msi_wr_map_s cn66xx;
2213 struct cvmx_sli_msi_wr_map_s cn68xx;
2214 struct cvmx_sli_msi_wr_map_s cn68xxp1;
2215 struct cvmx_sli_msi_wr_map_s cnf71xx;
2216};
2217
2218union cvmx_sli_pcie_msi_rcv {
2219 uint64_t u64;
2220 struct cvmx_sli_pcie_msi_rcv_s {
2221#ifdef __BIG_ENDIAN_BITFIELD
2222 uint64_t reserved_8_63:56;
2223 uint64_t intr:8;
2224#else
2225 uint64_t intr:8;
2226 uint64_t reserved_8_63:56;
2227#endif
2228 } s;
2229 struct cvmx_sli_pcie_msi_rcv_s cn61xx;
2230 struct cvmx_sli_pcie_msi_rcv_s cn63xx;
2231 struct cvmx_sli_pcie_msi_rcv_s cn63xxp1;
2232 struct cvmx_sli_pcie_msi_rcv_s cn66xx;
2233 struct cvmx_sli_pcie_msi_rcv_s cn68xx;
2234 struct cvmx_sli_pcie_msi_rcv_s cn68xxp1;
2235 struct cvmx_sli_pcie_msi_rcv_s cnf71xx;
2236};
2237
2238union cvmx_sli_pcie_msi_rcv_b1 {
2239 uint64_t u64;
2240 struct cvmx_sli_pcie_msi_rcv_b1_s {
2241#ifdef __BIG_ENDIAN_BITFIELD
2242 uint64_t reserved_16_63:48;
2243 uint64_t intr:8;
2244 uint64_t reserved_0_7:8;
2245#else
2246 uint64_t reserved_0_7:8;
2247 uint64_t intr:8;
2248 uint64_t reserved_16_63:48;
2249#endif
2250 } s;
2251 struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx;
2252 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx;
2253 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1;
2254 struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx;
2255 struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx;
2256 struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1;
2257 struct cvmx_sli_pcie_msi_rcv_b1_s cnf71xx;
2258};
2259
2260union cvmx_sli_pcie_msi_rcv_b2 {
2261 uint64_t u64;
2262 struct cvmx_sli_pcie_msi_rcv_b2_s {
2263#ifdef __BIG_ENDIAN_BITFIELD
2264 uint64_t reserved_24_63:40;
2265 uint64_t intr:8;
2266 uint64_t reserved_0_15:16;
2267#else
2268 uint64_t reserved_0_15:16;
2269 uint64_t intr:8;
2270 uint64_t reserved_24_63:40;
2271#endif
2272 } s;
2273 struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx;
2274 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx;
2275 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1;
2276 struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx;
2277 struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx;
2278 struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1;
2279 struct cvmx_sli_pcie_msi_rcv_b2_s cnf71xx;
2280};
2281
2282union cvmx_sli_pcie_msi_rcv_b3 {
2283 uint64_t u64;
2284 struct cvmx_sli_pcie_msi_rcv_b3_s {
2285#ifdef __BIG_ENDIAN_BITFIELD
2286 uint64_t reserved_32_63:32;
2287 uint64_t intr:8;
2288 uint64_t reserved_0_23:24;
2289#else
2290 uint64_t reserved_0_23:24;
2291 uint64_t intr:8;
2292 uint64_t reserved_32_63:32;
2293#endif
2294 } s;
2295 struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx;
2296 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx;
2297 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1;
2298 struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx;
2299 struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx;
2300 struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1;
2301 struct cvmx_sli_pcie_msi_rcv_b3_s cnf71xx;
2302};
2303
2304union cvmx_sli_pktx_cnts {
2305 uint64_t u64;
2306 struct cvmx_sli_pktx_cnts_s {
2307#ifdef __BIG_ENDIAN_BITFIELD
2308 uint64_t reserved_54_63:10;
2309 uint64_t timer:22;
2310 uint64_t cnt:32;
2311#else
2312 uint64_t cnt:32;
2313 uint64_t timer:22;
2314 uint64_t reserved_54_63:10;
2315#endif
2316 } s;
2317 struct cvmx_sli_pktx_cnts_s cn61xx;
2318 struct cvmx_sli_pktx_cnts_s cn63xx;
2319 struct cvmx_sli_pktx_cnts_s cn63xxp1;
2320 struct cvmx_sli_pktx_cnts_s cn66xx;
2321 struct cvmx_sli_pktx_cnts_s cn68xx;
2322 struct cvmx_sli_pktx_cnts_s cn68xxp1;
2323 struct cvmx_sli_pktx_cnts_s cnf71xx;
2324};
2325
2326union cvmx_sli_pktx_in_bp {
2327 uint64_t u64;
2328 struct cvmx_sli_pktx_in_bp_s {
2329#ifdef __BIG_ENDIAN_BITFIELD
2330 uint64_t wmark:32;
2331 uint64_t cnt:32;
2332#else
2333 uint64_t cnt:32;
2334 uint64_t wmark:32;
2335#endif
2336 } s;
2337 struct cvmx_sli_pktx_in_bp_s cn61xx;
2338 struct cvmx_sli_pktx_in_bp_s cn63xx;
2339 struct cvmx_sli_pktx_in_bp_s cn63xxp1;
2340 struct cvmx_sli_pktx_in_bp_s cn66xx;
2341 struct cvmx_sli_pktx_in_bp_s cnf71xx;
2342};
2343
2344union cvmx_sli_pktx_instr_baddr {
2345 uint64_t u64;
2346 struct cvmx_sli_pktx_instr_baddr_s {
2347#ifdef __BIG_ENDIAN_BITFIELD
2348 uint64_t addr:61;
2349 uint64_t reserved_0_2:3;
2350#else
2351 uint64_t reserved_0_2:3;
2352 uint64_t addr:61;
2353#endif
2354 } s; 85 } s;
2355 struct cvmx_sli_pktx_instr_baddr_s cn61xx;
2356 struct cvmx_sli_pktx_instr_baddr_s cn63xx;
2357 struct cvmx_sli_pktx_instr_baddr_s cn63xxp1;
2358 struct cvmx_sli_pktx_instr_baddr_s cn66xx;
2359 struct cvmx_sli_pktx_instr_baddr_s cn68xx;
2360 struct cvmx_sli_pktx_instr_baddr_s cn68xxp1;
2361 struct cvmx_sli_pktx_instr_baddr_s cnf71xx;
2362};
2363
2364union cvmx_sli_pktx_instr_baoff_dbell {
2365 uint64_t u64;
2366 struct cvmx_sli_pktx_instr_baoff_dbell_s {
2367#ifdef __BIG_ENDIAN_BITFIELD
2368 uint64_t aoff:32;
2369 uint64_t dbell:32;
2370#else
2371 uint64_t dbell:32;
2372 uint64_t aoff:32;
2373#endif
2374 } s;
2375 struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx;
2376 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;
2377 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1;
2378 struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx;
2379 struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx;
2380 struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1;
2381 struct cvmx_sli_pktx_instr_baoff_dbell_s cnf71xx;
2382};
2383
2384union cvmx_sli_pktx_instr_fifo_rsize {
2385 uint64_t u64;
2386 struct cvmx_sli_pktx_instr_fifo_rsize_s {
2387#ifdef __BIG_ENDIAN_BITFIELD
2388 uint64_t max:9;
2389 uint64_t rrp:9;
2390 uint64_t wrp:9;
2391 uint64_t fcnt:5;
2392 uint64_t rsize:32;
2393#else
2394 uint64_t rsize:32;
2395 uint64_t fcnt:5;
2396 uint64_t wrp:9;
2397 uint64_t rrp:9;
2398 uint64_t max:9;
2399#endif
2400 } s;
2401 struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx;
2402 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;
2403 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1;
2404 struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx;
2405 struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx;
2406 struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1;
2407 struct cvmx_sli_pktx_instr_fifo_rsize_s cnf71xx;
2408};
2409
2410union cvmx_sli_pktx_instr_header {
2411 uint64_t u64;
2412 struct cvmx_sli_pktx_instr_header_s {
2413#ifdef __BIG_ENDIAN_BITFIELD
2414 uint64_t reserved_44_63:20;
2415 uint64_t pbp:1;
2416 uint64_t reserved_38_42:5;
2417 uint64_t rparmode:2;
2418 uint64_t reserved_35_35:1;
2419 uint64_t rskp_len:7;
2420 uint64_t rngrpext:2;
2421 uint64_t rnqos:1;
2422 uint64_t rngrp:1;
2423 uint64_t rntt:1;
2424 uint64_t rntag:1;
2425 uint64_t use_ihdr:1;
2426 uint64_t reserved_16_20:5;
2427 uint64_t par_mode:2;
2428 uint64_t reserved_13_13:1;
2429 uint64_t skp_len:7;
2430 uint64_t ngrpext:2;
2431 uint64_t nqos:1;
2432 uint64_t ngrp:1;
2433 uint64_t ntt:1;
2434 uint64_t ntag:1;
2435#else
2436 uint64_t ntag:1;
2437 uint64_t ntt:1;
2438 uint64_t ngrp:1;
2439 uint64_t nqos:1;
2440 uint64_t ngrpext:2;
2441 uint64_t skp_len:7;
2442 uint64_t reserved_13_13:1;
2443 uint64_t par_mode:2;
2444 uint64_t reserved_16_20:5;
2445 uint64_t use_ihdr:1;
2446 uint64_t rntag:1;
2447 uint64_t rntt:1;
2448 uint64_t rngrp:1;
2449 uint64_t rnqos:1;
2450 uint64_t rngrpext:2;
2451 uint64_t rskp_len:7;
2452 uint64_t reserved_35_35:1;
2453 uint64_t rparmode:2;
2454 uint64_t reserved_38_42:5;
2455 uint64_t pbp:1;
2456 uint64_t reserved_44_63:20;
2457#endif
2458 } s;
2459 struct cvmx_sli_pktx_instr_header_cn61xx {
2460#ifdef __BIG_ENDIAN_BITFIELD
2461 uint64_t reserved_44_63:20;
2462 uint64_t pbp:1;
2463 uint64_t reserved_38_42:5;
2464 uint64_t rparmode:2;
2465 uint64_t reserved_35_35:1;
2466 uint64_t rskp_len:7;
2467 uint64_t reserved_26_27:2;
2468 uint64_t rnqos:1;
2469 uint64_t rngrp:1;
2470 uint64_t rntt:1;
2471 uint64_t rntag:1;
2472 uint64_t use_ihdr:1;
2473 uint64_t reserved_16_20:5;
2474 uint64_t par_mode:2;
2475 uint64_t reserved_13_13:1;
2476 uint64_t skp_len:7;
2477 uint64_t reserved_4_5:2;
2478 uint64_t nqos:1;
2479 uint64_t ngrp:1;
2480 uint64_t ntt:1;
2481 uint64_t ntag:1;
2482#else
2483 uint64_t ntag:1;
2484 uint64_t ntt:1;
2485 uint64_t ngrp:1;
2486 uint64_t nqos:1;
2487 uint64_t reserved_4_5:2;
2488 uint64_t skp_len:7;
2489 uint64_t reserved_13_13:1;
2490 uint64_t par_mode:2;
2491 uint64_t reserved_16_20:5;
2492 uint64_t use_ihdr:1;
2493 uint64_t rntag:1;
2494 uint64_t rntt:1;
2495 uint64_t rngrp:1;
2496 uint64_t rnqos:1;
2497 uint64_t reserved_26_27:2;
2498 uint64_t rskp_len:7;
2499 uint64_t reserved_35_35:1;
2500 uint64_t rparmode:2;
2501 uint64_t reserved_38_42:5;
2502 uint64_t pbp:1;
2503 uint64_t reserved_44_63:20;
2504#endif
2505 } cn61xx;
2506 struct cvmx_sli_pktx_instr_header_cn61xx cn63xx;
2507 struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1;
2508 struct cvmx_sli_pktx_instr_header_cn61xx cn66xx;
2509 struct cvmx_sli_pktx_instr_header_s cn68xx;
2510 struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1;
2511 struct cvmx_sli_pktx_instr_header_cn61xx cnf71xx;
2512};
2513
2514union cvmx_sli_pktx_out_size {
2515 uint64_t u64;
2516 struct cvmx_sli_pktx_out_size_s {
2517#ifdef __BIG_ENDIAN_BITFIELD
2518 uint64_t reserved_23_63:41;
2519 uint64_t isize:7;
2520 uint64_t bsize:16;
2521#else
2522 uint64_t bsize:16;
2523 uint64_t isize:7;
2524 uint64_t reserved_23_63:41;
2525#endif
2526 } s;
2527 struct cvmx_sli_pktx_out_size_s cn61xx;
2528 struct cvmx_sli_pktx_out_size_s cn63xx;
2529 struct cvmx_sli_pktx_out_size_s cn63xxp1;
2530 struct cvmx_sli_pktx_out_size_s cn66xx;
2531 struct cvmx_sli_pktx_out_size_s cn68xx;
2532 struct cvmx_sli_pktx_out_size_s cn68xxp1;
2533 struct cvmx_sli_pktx_out_size_s cnf71xx;
2534};
2535
2536union cvmx_sli_pktx_slist_baddr {
2537 uint64_t u64;
2538 struct cvmx_sli_pktx_slist_baddr_s {
2539#ifdef __BIG_ENDIAN_BITFIELD
2540 uint64_t addr:60;
2541 uint64_t reserved_0_3:4;
2542#else
2543 uint64_t reserved_0_3:4;
2544 uint64_t addr:60;
2545#endif
2546 } s;
2547 struct cvmx_sli_pktx_slist_baddr_s cn61xx;
2548 struct cvmx_sli_pktx_slist_baddr_s cn63xx;
2549 struct cvmx_sli_pktx_slist_baddr_s cn63xxp1;
2550 struct cvmx_sli_pktx_slist_baddr_s cn66xx;
2551 struct cvmx_sli_pktx_slist_baddr_s cn68xx;
2552 struct cvmx_sli_pktx_slist_baddr_s cn68xxp1;
2553 struct cvmx_sli_pktx_slist_baddr_s cnf71xx;
2554};
2555
2556union cvmx_sli_pktx_slist_baoff_dbell {
2557 uint64_t u64;
2558 struct cvmx_sli_pktx_slist_baoff_dbell_s {
2559#ifdef __BIG_ENDIAN_BITFIELD
2560 uint64_t aoff:32;
2561 uint64_t dbell:32;
2562#else
2563 uint64_t dbell:32;
2564 uint64_t aoff:32;
2565#endif
2566 } s;
2567 struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx;
2568 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;
2569 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1;
2570 struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx;
2571 struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx;
2572 struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1;
2573 struct cvmx_sli_pktx_slist_baoff_dbell_s cnf71xx;
2574};
2575
2576union cvmx_sli_pktx_slist_fifo_rsize {
2577 uint64_t u64;
2578 struct cvmx_sli_pktx_slist_fifo_rsize_s {
2579#ifdef __BIG_ENDIAN_BITFIELD
2580 uint64_t reserved_32_63:32;
2581 uint64_t rsize:32;
2582#else
2583 uint64_t rsize:32;
2584 uint64_t reserved_32_63:32;
2585#endif
2586 } s;
2587 struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx;
2588 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;
2589 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1;
2590 struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx;
2591 struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx;
2592 struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1;
2593 struct cvmx_sli_pktx_slist_fifo_rsize_s cnf71xx;
2594};
2595
2596union cvmx_sli_pkt_cnt_int {
2597 uint64_t u64;
2598 struct cvmx_sli_pkt_cnt_int_s {
2599#ifdef __BIG_ENDIAN_BITFIELD
2600 uint64_t reserved_32_63:32;
2601 uint64_t port:32;
2602#else
2603 uint64_t port:32;
2604 uint64_t reserved_32_63:32;
2605#endif
2606 } s;
2607 struct cvmx_sli_pkt_cnt_int_s cn61xx;
2608 struct cvmx_sli_pkt_cnt_int_s cn63xx;
2609 struct cvmx_sli_pkt_cnt_int_s cn63xxp1;
2610 struct cvmx_sli_pkt_cnt_int_s cn66xx;
2611 struct cvmx_sli_pkt_cnt_int_s cn68xx;
2612 struct cvmx_sli_pkt_cnt_int_s cn68xxp1;
2613 struct cvmx_sli_pkt_cnt_int_s cnf71xx;
2614};
2615
2616union cvmx_sli_pkt_cnt_int_enb {
2617 uint64_t u64;
2618 struct cvmx_sli_pkt_cnt_int_enb_s {
2619#ifdef __BIG_ENDIAN_BITFIELD
2620 uint64_t reserved_32_63:32;
2621 uint64_t port:32;
2622#else
2623 uint64_t port:32;
2624 uint64_t reserved_32_63:32;
2625#endif
2626 } s;
2627 struct cvmx_sli_pkt_cnt_int_enb_s cn61xx;
2628 struct cvmx_sli_pkt_cnt_int_enb_s cn63xx;
2629 struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1;
2630 struct cvmx_sli_pkt_cnt_int_enb_s cn66xx;
2631 struct cvmx_sli_pkt_cnt_int_enb_s cn68xx;
2632 struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1;
2633 struct cvmx_sli_pkt_cnt_int_enb_s cnf71xx;
2634};
2635
2636union cvmx_sli_pkt_ctl {
2637 uint64_t u64;
2638 struct cvmx_sli_pkt_ctl_s {
2639#ifdef __BIG_ENDIAN_BITFIELD
2640 uint64_t reserved_5_63:59;
2641 uint64_t ring_en:1;
2642 uint64_t pkt_bp:4;
2643#else
2644 uint64_t pkt_bp:4;
2645 uint64_t ring_en:1;
2646 uint64_t reserved_5_63:59;
2647#endif
2648 } s;
2649 struct cvmx_sli_pkt_ctl_s cn61xx;
2650 struct cvmx_sli_pkt_ctl_s cn63xx;
2651 struct cvmx_sli_pkt_ctl_s cn63xxp1;
2652 struct cvmx_sli_pkt_ctl_s cn66xx;
2653 struct cvmx_sli_pkt_ctl_s cn68xx;
2654 struct cvmx_sli_pkt_ctl_s cn68xxp1;
2655 struct cvmx_sli_pkt_ctl_s cnf71xx;
2656};
2657
2658union cvmx_sli_pkt_data_out_es {
2659 uint64_t u64;
2660 struct cvmx_sli_pkt_data_out_es_s {
2661#ifdef __BIG_ENDIAN_BITFIELD
2662 uint64_t es:64;
2663#else
2664 uint64_t es:64;
2665#endif
2666 } s;
2667 struct cvmx_sli_pkt_data_out_es_s cn61xx;
2668 struct cvmx_sli_pkt_data_out_es_s cn63xx;
2669 struct cvmx_sli_pkt_data_out_es_s cn63xxp1;
2670 struct cvmx_sli_pkt_data_out_es_s cn66xx;
2671 struct cvmx_sli_pkt_data_out_es_s cn68xx;
2672 struct cvmx_sli_pkt_data_out_es_s cn68xxp1;
2673 struct cvmx_sli_pkt_data_out_es_s cnf71xx;
2674};
2675
2676union cvmx_sli_pkt_data_out_ns {
2677 uint64_t u64;
2678 struct cvmx_sli_pkt_data_out_ns_s {
2679#ifdef __BIG_ENDIAN_BITFIELD
2680 uint64_t reserved_32_63:32;
2681 uint64_t nsr:32;
2682#else
2683 uint64_t nsr:32;
2684 uint64_t reserved_32_63:32;
2685#endif
2686 } s;
2687 struct cvmx_sli_pkt_data_out_ns_s cn61xx;
2688 struct cvmx_sli_pkt_data_out_ns_s cn63xx;
2689 struct cvmx_sli_pkt_data_out_ns_s cn63xxp1;
2690 struct cvmx_sli_pkt_data_out_ns_s cn66xx;
2691 struct cvmx_sli_pkt_data_out_ns_s cn68xx;
2692 struct cvmx_sli_pkt_data_out_ns_s cn68xxp1;
2693 struct cvmx_sli_pkt_data_out_ns_s cnf71xx;
2694};
2695
2696union cvmx_sli_pkt_data_out_ror {
2697 uint64_t u64;
2698 struct cvmx_sli_pkt_data_out_ror_s {
2699#ifdef __BIG_ENDIAN_BITFIELD
2700 uint64_t reserved_32_63:32;
2701 uint64_t ror:32;
2702#else
2703 uint64_t ror:32;
2704 uint64_t reserved_32_63:32;
2705#endif
2706 } s;
2707 struct cvmx_sli_pkt_data_out_ror_s cn61xx;
2708 struct cvmx_sli_pkt_data_out_ror_s cn63xx;
2709 struct cvmx_sli_pkt_data_out_ror_s cn63xxp1;
2710 struct cvmx_sli_pkt_data_out_ror_s cn66xx;
2711 struct cvmx_sli_pkt_data_out_ror_s cn68xx;
2712 struct cvmx_sli_pkt_data_out_ror_s cn68xxp1;
2713 struct cvmx_sli_pkt_data_out_ror_s cnf71xx;
2714};
2715
2716union cvmx_sli_pkt_dpaddr {
2717 uint64_t u64;
2718 struct cvmx_sli_pkt_dpaddr_s {
2719#ifdef __BIG_ENDIAN_BITFIELD
2720 uint64_t reserved_32_63:32;
2721 uint64_t dptr:32;
2722#else
2723 uint64_t dptr:32;
2724 uint64_t reserved_32_63:32;
2725#endif
2726 } s;
2727 struct cvmx_sli_pkt_dpaddr_s cn61xx;
2728 struct cvmx_sli_pkt_dpaddr_s cn63xx;
2729 struct cvmx_sli_pkt_dpaddr_s cn63xxp1;
2730 struct cvmx_sli_pkt_dpaddr_s cn66xx;
2731 struct cvmx_sli_pkt_dpaddr_s cn68xx;
2732 struct cvmx_sli_pkt_dpaddr_s cn68xxp1;
2733 struct cvmx_sli_pkt_dpaddr_s cnf71xx;
2734};
2735
2736union cvmx_sli_pkt_in_bp {
2737 uint64_t u64;
2738 struct cvmx_sli_pkt_in_bp_s {
2739#ifdef __BIG_ENDIAN_BITFIELD
2740 uint64_t reserved_32_63:32;
2741 uint64_t bp:32;
2742#else
2743 uint64_t bp:32;
2744 uint64_t reserved_32_63:32;
2745#endif
2746 } s;
2747 struct cvmx_sli_pkt_in_bp_s cn61xx;
2748 struct cvmx_sli_pkt_in_bp_s cn63xx;
2749 struct cvmx_sli_pkt_in_bp_s cn63xxp1;
2750 struct cvmx_sli_pkt_in_bp_s cn66xx;
2751 struct cvmx_sli_pkt_in_bp_s cnf71xx;
2752};
2753
2754union cvmx_sli_pkt_in_donex_cnts {
2755 uint64_t u64;
2756 struct cvmx_sli_pkt_in_donex_cnts_s {
2757#ifdef __BIG_ENDIAN_BITFIELD
2758 uint64_t reserved_32_63:32;
2759 uint64_t cnt:32;
2760#else
2761 uint64_t cnt:32;
2762 uint64_t reserved_32_63:32;
2763#endif
2764 } s;
2765 struct cvmx_sli_pkt_in_donex_cnts_s cn61xx;
2766 struct cvmx_sli_pkt_in_donex_cnts_s cn63xx;
2767 struct cvmx_sli_pkt_in_donex_cnts_s cn63xxp1;
2768 struct cvmx_sli_pkt_in_donex_cnts_s cn66xx;
2769 struct cvmx_sli_pkt_in_donex_cnts_s cn68xx;
2770 struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1;
2771 struct cvmx_sli_pkt_in_donex_cnts_s cnf71xx;
2772};
2773
2774union cvmx_sli_pkt_in_instr_counts {
2775 uint64_t u64;
2776 struct cvmx_sli_pkt_in_instr_counts_s {
2777#ifdef __BIG_ENDIAN_BITFIELD
2778 uint64_t wr_cnt:32;
2779 uint64_t rd_cnt:32;
2780#else
2781 uint64_t rd_cnt:32;
2782 uint64_t wr_cnt:32;
2783#endif
2784 } s;
2785 struct cvmx_sli_pkt_in_instr_counts_s cn61xx;
2786 struct cvmx_sli_pkt_in_instr_counts_s cn63xx;
2787 struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1;
2788 struct cvmx_sli_pkt_in_instr_counts_s cn66xx;
2789 struct cvmx_sli_pkt_in_instr_counts_s cn68xx;
2790 struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1;
2791 struct cvmx_sli_pkt_in_instr_counts_s cnf71xx;
2792};
2793
2794union cvmx_sli_pkt_in_pcie_port {
2795 uint64_t u64;
2796 struct cvmx_sli_pkt_in_pcie_port_s {
2797#ifdef __BIG_ENDIAN_BITFIELD
2798 uint64_t pp:64;
2799#else
2800 uint64_t pp:64;
2801#endif
2802 } s;
2803 struct cvmx_sli_pkt_in_pcie_port_s cn61xx;
2804 struct cvmx_sli_pkt_in_pcie_port_s cn63xx;
2805 struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1;
2806 struct cvmx_sli_pkt_in_pcie_port_s cn66xx;
2807 struct cvmx_sli_pkt_in_pcie_port_s cn68xx;
2808 struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1;
2809 struct cvmx_sli_pkt_in_pcie_port_s cnf71xx;
2810};
2811
2812union cvmx_sli_pkt_input_control {
2813 uint64_t u64;
2814 struct cvmx_sli_pkt_input_control_s {
2815#ifdef __BIG_ENDIAN_BITFIELD
2816 uint64_t prd_erst:1;
2817 uint64_t prd_rds:7;
2818 uint64_t gii_erst:1;
2819 uint64_t gii_rds:7;
2820 uint64_t reserved_41_47:7;
2821 uint64_t prc_idle:1;
2822 uint64_t reserved_24_39:16;
2823 uint64_t pin_rst:1;
2824 uint64_t pkt_rr:1;
2825 uint64_t pbp_dhi:13;
2826 uint64_t d_nsr:1;
2827 uint64_t d_esr:2;
2828 uint64_t d_ror:1;
2829 uint64_t use_csr:1;
2830 uint64_t nsr:1;
2831 uint64_t esr:2;
2832 uint64_t ror:1;
2833#else
2834 uint64_t ror:1;
2835 uint64_t esr:2;
2836 uint64_t nsr:1;
2837 uint64_t use_csr:1;
2838 uint64_t d_ror:1;
2839 uint64_t d_esr:2;
2840 uint64_t d_nsr:1;
2841 uint64_t pbp_dhi:13;
2842 uint64_t pkt_rr:1;
2843 uint64_t pin_rst:1;
2844 uint64_t reserved_24_39:16;
2845 uint64_t prc_idle:1;
2846 uint64_t reserved_41_47:7;
2847 uint64_t gii_rds:7;
2848 uint64_t gii_erst:1;
2849 uint64_t prd_rds:7;
2850 uint64_t prd_erst:1;
2851#endif
2852 } s;
2853 struct cvmx_sli_pkt_input_control_s cn61xx;
2854 struct cvmx_sli_pkt_input_control_cn63xx {
2855#ifdef __BIG_ENDIAN_BITFIELD
2856 uint64_t reserved_23_63:41;
2857 uint64_t pkt_rr:1;
2858 uint64_t pbp_dhi:13;
2859 uint64_t d_nsr:1;
2860 uint64_t d_esr:2;
2861 uint64_t d_ror:1;
2862 uint64_t use_csr:1;
2863 uint64_t nsr:1;
2864 uint64_t esr:2;
2865 uint64_t ror:1;
2866#else
2867 uint64_t ror:1;
2868 uint64_t esr:2;
2869 uint64_t nsr:1;
2870 uint64_t use_csr:1;
2871 uint64_t d_ror:1;
2872 uint64_t d_esr:2;
2873 uint64_t d_nsr:1;
2874 uint64_t pbp_dhi:13;
2875 uint64_t pkt_rr:1;
2876 uint64_t reserved_23_63:41;
2877#endif
2878 } cn63xx;
2879 struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1;
2880 struct cvmx_sli_pkt_input_control_s cn66xx;
2881 struct cvmx_sli_pkt_input_control_s cn68xx;
2882 struct cvmx_sli_pkt_input_control_s cn68xxp1;
2883 struct cvmx_sli_pkt_input_control_s cnf71xx;
2884};
2885
2886union cvmx_sli_pkt_instr_enb {
2887 uint64_t u64;
2888 struct cvmx_sli_pkt_instr_enb_s {
2889#ifdef __BIG_ENDIAN_BITFIELD
2890 uint64_t reserved_32_63:32;
2891 uint64_t enb:32;
2892#else
2893 uint64_t enb:32;
2894 uint64_t reserved_32_63:32;
2895#endif
2896 } s;
2897 struct cvmx_sli_pkt_instr_enb_s cn61xx;
2898 struct cvmx_sli_pkt_instr_enb_s cn63xx;
2899 struct cvmx_sli_pkt_instr_enb_s cn63xxp1;
2900 struct cvmx_sli_pkt_instr_enb_s cn66xx;
2901 struct cvmx_sli_pkt_instr_enb_s cn68xx;
2902 struct cvmx_sli_pkt_instr_enb_s cn68xxp1;
2903 struct cvmx_sli_pkt_instr_enb_s cnf71xx;
2904};
2905
2906union cvmx_sli_pkt_instr_rd_size {
2907 uint64_t u64;
2908 struct cvmx_sli_pkt_instr_rd_size_s {
2909#ifdef __BIG_ENDIAN_BITFIELD
2910 uint64_t rdsize:64;
2911#else
2912 uint64_t rdsize:64;
2913#endif
2914 } s;
2915 struct cvmx_sli_pkt_instr_rd_size_s cn61xx;
2916 struct cvmx_sli_pkt_instr_rd_size_s cn63xx;
2917 struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1;
2918 struct cvmx_sli_pkt_instr_rd_size_s cn66xx;
2919 struct cvmx_sli_pkt_instr_rd_size_s cn68xx;
2920 struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1;
2921 struct cvmx_sli_pkt_instr_rd_size_s cnf71xx;
2922};
2923
2924union cvmx_sli_pkt_instr_size {
2925 uint64_t u64;
2926 struct cvmx_sli_pkt_instr_size_s {
2927#ifdef __BIG_ENDIAN_BITFIELD
2928 uint64_t reserved_32_63:32;
2929 uint64_t is_64b:32;
2930#else
2931 uint64_t is_64b:32;
2932 uint64_t reserved_32_63:32;
2933#endif
2934 } s;
2935 struct cvmx_sli_pkt_instr_size_s cn61xx;
2936 struct cvmx_sli_pkt_instr_size_s cn63xx;
2937 struct cvmx_sli_pkt_instr_size_s cn63xxp1;
2938 struct cvmx_sli_pkt_instr_size_s cn66xx;
2939 struct cvmx_sli_pkt_instr_size_s cn68xx;
2940 struct cvmx_sli_pkt_instr_size_s cn68xxp1;
2941 struct cvmx_sli_pkt_instr_size_s cnf71xx;
2942};
2943
2944union cvmx_sli_pkt_int_levels {
2945 uint64_t u64;
2946 struct cvmx_sli_pkt_int_levels_s {
2947#ifdef __BIG_ENDIAN_BITFIELD
2948 uint64_t reserved_54_63:10;
2949 uint64_t time:22;
2950 uint64_t cnt:32;
2951#else
2952 uint64_t cnt:32;
2953 uint64_t time:22;
2954 uint64_t reserved_54_63:10;
2955#endif
2956 } s;
2957 struct cvmx_sli_pkt_int_levels_s cn61xx;
2958 struct cvmx_sli_pkt_int_levels_s cn63xx;
2959 struct cvmx_sli_pkt_int_levels_s cn63xxp1;
2960 struct cvmx_sli_pkt_int_levels_s cn66xx;
2961 struct cvmx_sli_pkt_int_levels_s cn68xx;
2962 struct cvmx_sli_pkt_int_levels_s cn68xxp1;
2963 struct cvmx_sli_pkt_int_levels_s cnf71xx;
2964};
2965
2966union cvmx_sli_pkt_iptr {
2967 uint64_t u64;
2968 struct cvmx_sli_pkt_iptr_s {
2969#ifdef __BIG_ENDIAN_BITFIELD
2970 uint64_t reserved_32_63:32;
2971 uint64_t iptr:32;
2972#else
2973 uint64_t iptr:32;
2974 uint64_t reserved_32_63:32;
2975#endif
2976 } s;
2977 struct cvmx_sli_pkt_iptr_s cn61xx;
2978 struct cvmx_sli_pkt_iptr_s cn63xx;
2979 struct cvmx_sli_pkt_iptr_s cn63xxp1;
2980 struct cvmx_sli_pkt_iptr_s cn66xx;
2981 struct cvmx_sli_pkt_iptr_s cn68xx;
2982 struct cvmx_sli_pkt_iptr_s cn68xxp1;
2983 struct cvmx_sli_pkt_iptr_s cnf71xx;
2984};
2985
2986union cvmx_sli_pkt_out_bmode {
2987 uint64_t u64;
2988 struct cvmx_sli_pkt_out_bmode_s {
2989#ifdef __BIG_ENDIAN_BITFIELD
2990 uint64_t reserved_32_63:32;
2991 uint64_t bmode:32;
2992#else
2993 uint64_t bmode:32;
2994 uint64_t reserved_32_63:32;
2995#endif
2996 } s;
2997 struct cvmx_sli_pkt_out_bmode_s cn61xx;
2998 struct cvmx_sli_pkt_out_bmode_s cn63xx;
2999 struct cvmx_sli_pkt_out_bmode_s cn63xxp1;
3000 struct cvmx_sli_pkt_out_bmode_s cn66xx;
3001 struct cvmx_sli_pkt_out_bmode_s cn68xx;
3002 struct cvmx_sli_pkt_out_bmode_s cn68xxp1;
3003 struct cvmx_sli_pkt_out_bmode_s cnf71xx;
3004};
3005
3006union cvmx_sli_pkt_out_bp_en {
3007 uint64_t u64;
3008 struct cvmx_sli_pkt_out_bp_en_s {
3009#ifdef __BIG_ENDIAN_BITFIELD
3010 uint64_t reserved_32_63:32;
3011 uint64_t bp_en:32;
3012#else
3013 uint64_t bp_en:32;
3014 uint64_t reserved_32_63:32;
3015#endif
3016 } s;
3017 struct cvmx_sli_pkt_out_bp_en_s cn68xx;
3018 struct cvmx_sli_pkt_out_bp_en_s cn68xxp1;
3019};
3020
3021union cvmx_sli_pkt_out_enb {
3022 uint64_t u64;
3023 struct cvmx_sli_pkt_out_enb_s {
3024#ifdef __BIG_ENDIAN_BITFIELD
3025 uint64_t reserved_32_63:32;
3026 uint64_t enb:32;
3027#else
3028 uint64_t enb:32;
3029 uint64_t reserved_32_63:32;
3030#endif
3031 } s;
3032 struct cvmx_sli_pkt_out_enb_s cn61xx;
3033 struct cvmx_sli_pkt_out_enb_s cn63xx;
3034 struct cvmx_sli_pkt_out_enb_s cn63xxp1;
3035 struct cvmx_sli_pkt_out_enb_s cn66xx;
3036 struct cvmx_sli_pkt_out_enb_s cn68xx;
3037 struct cvmx_sli_pkt_out_enb_s cn68xxp1;
3038 struct cvmx_sli_pkt_out_enb_s cnf71xx;
3039};
3040
3041union cvmx_sli_pkt_output_wmark {
3042 uint64_t u64;
3043 struct cvmx_sli_pkt_output_wmark_s {
3044#ifdef __BIG_ENDIAN_BITFIELD
3045 uint64_t reserved_32_63:32;
3046 uint64_t wmark:32;
3047#else
3048 uint64_t wmark:32;
3049 uint64_t reserved_32_63:32;
3050#endif
3051 } s;
3052 struct cvmx_sli_pkt_output_wmark_s cn61xx;
3053 struct cvmx_sli_pkt_output_wmark_s cn63xx;
3054 struct cvmx_sli_pkt_output_wmark_s cn63xxp1;
3055 struct cvmx_sli_pkt_output_wmark_s cn66xx;
3056 struct cvmx_sli_pkt_output_wmark_s cn68xx;
3057 struct cvmx_sli_pkt_output_wmark_s cn68xxp1;
3058 struct cvmx_sli_pkt_output_wmark_s cnf71xx;
3059};
3060
3061union cvmx_sli_pkt_pcie_port {
3062 uint64_t u64;
3063 struct cvmx_sli_pkt_pcie_port_s {
3064#ifdef __BIG_ENDIAN_BITFIELD
3065 uint64_t pp:64;
3066#else
3067 uint64_t pp:64;
3068#endif
3069 } s;
3070 struct cvmx_sli_pkt_pcie_port_s cn61xx;
3071 struct cvmx_sli_pkt_pcie_port_s cn63xx;
3072 struct cvmx_sli_pkt_pcie_port_s cn63xxp1;
3073 struct cvmx_sli_pkt_pcie_port_s cn66xx;
3074 struct cvmx_sli_pkt_pcie_port_s cn68xx;
3075 struct cvmx_sli_pkt_pcie_port_s cn68xxp1;
3076 struct cvmx_sli_pkt_pcie_port_s cnf71xx;
3077};
3078
3079union cvmx_sli_pkt_port_in_rst {
3080 uint64_t u64;
3081 struct cvmx_sli_pkt_port_in_rst_s {
3082#ifdef __BIG_ENDIAN_BITFIELD
3083 uint64_t in_rst:32;
3084 uint64_t out_rst:32;
3085#else
3086 uint64_t out_rst:32;
3087 uint64_t in_rst:32;
3088#endif
3089 } s;
3090 struct cvmx_sli_pkt_port_in_rst_s cn61xx;
3091 struct cvmx_sli_pkt_port_in_rst_s cn63xx;
3092 struct cvmx_sli_pkt_port_in_rst_s cn63xxp1;
3093 struct cvmx_sli_pkt_port_in_rst_s cn66xx;
3094 struct cvmx_sli_pkt_port_in_rst_s cn68xx;
3095 struct cvmx_sli_pkt_port_in_rst_s cn68xxp1;
3096 struct cvmx_sli_pkt_port_in_rst_s cnf71xx;
3097};
3098
3099union cvmx_sli_pkt_slist_es {
3100 uint64_t u64;
3101 struct cvmx_sli_pkt_slist_es_s {
3102#ifdef __BIG_ENDIAN_BITFIELD
3103 uint64_t es:64;
3104#else
3105 uint64_t es:64;
3106#endif
3107 } s;
3108 struct cvmx_sli_pkt_slist_es_s cn61xx;
3109 struct cvmx_sli_pkt_slist_es_s cn63xx;
3110 struct cvmx_sli_pkt_slist_es_s cn63xxp1;
3111 struct cvmx_sli_pkt_slist_es_s cn66xx;
3112 struct cvmx_sli_pkt_slist_es_s cn68xx;
3113 struct cvmx_sli_pkt_slist_es_s cn68xxp1;
3114 struct cvmx_sli_pkt_slist_es_s cnf71xx;
3115};
3116
3117union cvmx_sli_pkt_slist_ns {
3118 uint64_t u64;
3119 struct cvmx_sli_pkt_slist_ns_s {
3120#ifdef __BIG_ENDIAN_BITFIELD
3121 uint64_t reserved_32_63:32;
3122 uint64_t nsr:32;
3123#else
3124 uint64_t nsr:32;
3125 uint64_t reserved_32_63:32;
3126#endif
3127 } s;
3128 struct cvmx_sli_pkt_slist_ns_s cn61xx;
3129 struct cvmx_sli_pkt_slist_ns_s cn63xx;
3130 struct cvmx_sli_pkt_slist_ns_s cn63xxp1;
3131 struct cvmx_sli_pkt_slist_ns_s cn66xx;
3132 struct cvmx_sli_pkt_slist_ns_s cn68xx;
3133 struct cvmx_sli_pkt_slist_ns_s cn68xxp1;
3134 struct cvmx_sli_pkt_slist_ns_s cnf71xx;
3135};
3136
3137union cvmx_sli_pkt_slist_ror {
3138 uint64_t u64;
3139 struct cvmx_sli_pkt_slist_ror_s {
3140#ifdef __BIG_ENDIAN_BITFIELD
3141 uint64_t reserved_32_63:32;
3142 uint64_t ror:32;
3143#else
3144 uint64_t ror:32;
3145 uint64_t reserved_32_63:32;
3146#endif
3147 } s;
3148 struct cvmx_sli_pkt_slist_ror_s cn61xx;
3149 struct cvmx_sli_pkt_slist_ror_s cn63xx;
3150 struct cvmx_sli_pkt_slist_ror_s cn63xxp1;
3151 struct cvmx_sli_pkt_slist_ror_s cn66xx;
3152 struct cvmx_sli_pkt_slist_ror_s cn68xx;
3153 struct cvmx_sli_pkt_slist_ror_s cn68xxp1;
3154 struct cvmx_sli_pkt_slist_ror_s cnf71xx;
3155};
3156
3157union cvmx_sli_pkt_time_int {
3158 uint64_t u64;
3159 struct cvmx_sli_pkt_time_int_s {
3160#ifdef __BIG_ENDIAN_BITFIELD
3161 uint64_t reserved_32_63:32;
3162 uint64_t port:32;
3163#else
3164 uint64_t port:32;
3165 uint64_t reserved_32_63:32;
3166#endif
3167 } s;
3168 struct cvmx_sli_pkt_time_int_s cn61xx;
3169 struct cvmx_sli_pkt_time_int_s cn63xx;
3170 struct cvmx_sli_pkt_time_int_s cn63xxp1;
3171 struct cvmx_sli_pkt_time_int_s cn66xx;
3172 struct cvmx_sli_pkt_time_int_s cn68xx;
3173 struct cvmx_sli_pkt_time_int_s cn68xxp1;
3174 struct cvmx_sli_pkt_time_int_s cnf71xx;
3175};
3176
3177union cvmx_sli_pkt_time_int_enb {
3178 uint64_t u64;
3179 struct cvmx_sli_pkt_time_int_enb_s {
3180#ifdef __BIG_ENDIAN_BITFIELD
3181 uint64_t reserved_32_63:32;
3182 uint64_t port:32;
3183#else
3184 uint64_t port:32;
3185 uint64_t reserved_32_63:32;
3186#endif
3187 } s;
3188 struct cvmx_sli_pkt_time_int_enb_s cn61xx;
3189 struct cvmx_sli_pkt_time_int_enb_s cn63xx;
3190 struct cvmx_sli_pkt_time_int_enb_s cn63xxp1;
3191 struct cvmx_sli_pkt_time_int_enb_s cn66xx;
3192 struct cvmx_sli_pkt_time_int_enb_s cn68xx;
3193 struct cvmx_sli_pkt_time_int_enb_s cn68xxp1;
3194 struct cvmx_sli_pkt_time_int_enb_s cnf71xx;
3195};
3196
3197union cvmx_sli_portx_pkind {
3198 uint64_t u64;
3199 struct cvmx_sli_portx_pkind_s {
3200#ifdef __BIG_ENDIAN_BITFIELD
3201 uint64_t reserved_25_63:39;
3202 uint64_t rpk_enb:1;
3203 uint64_t reserved_22_23:2;
3204 uint64_t pkindr:6;
3205 uint64_t reserved_14_15:2;
3206 uint64_t bpkind:6;
3207 uint64_t reserved_6_7:2;
3208 uint64_t pkind:6;
3209#else
3210 uint64_t pkind:6;
3211 uint64_t reserved_6_7:2;
3212 uint64_t bpkind:6;
3213 uint64_t reserved_14_15:2;
3214 uint64_t pkindr:6;
3215 uint64_t reserved_22_23:2;
3216 uint64_t rpk_enb:1;
3217 uint64_t reserved_25_63:39;
3218#endif
3219 } s;
3220 struct cvmx_sli_portx_pkind_s cn68xx;
3221 struct cvmx_sli_portx_pkind_cn68xxp1 {
3222#ifdef __BIG_ENDIAN_BITFIELD
3223 uint64_t reserved_14_63:50;
3224 uint64_t bpkind:6;
3225 uint64_t reserved_6_7:2;
3226 uint64_t pkind:6;
3227#else
3228 uint64_t pkind:6;
3229 uint64_t reserved_6_7:2;
3230 uint64_t bpkind:6;
3231 uint64_t reserved_14_63:50;
3232#endif
3233 } cn68xxp1;
3234}; 86};
3235 87
3236union cvmx_sli_s2m_portx_ctl { 88union cvmx_sli_s2m_portx_ctl {
3237 uint64_t u64; 89 uint64_t u64;
3238 struct cvmx_sli_s2m_portx_ctl_s { 90 struct cvmx_sli_s2m_portx_ctl_s {
3239#ifdef __BIG_ENDIAN_BITFIELD 91 __BITFIELD_FIELD(uint64_t reserved_5_63:59,
3240 uint64_t reserved_5_63:59; 92 __BITFIELD_FIELD(uint64_t wind_d:1,
3241 uint64_t wind_d:1; 93 __BITFIELD_FIELD(uint64_t bar0_d:1,
3242 uint64_t bar0_d:1; 94 __BITFIELD_FIELD(uint64_t mrrs:3,
3243 uint64_t mrrs:3; 95 ;))))
3244#else
3245 uint64_t mrrs:3;
3246 uint64_t bar0_d:1;
3247 uint64_t wind_d:1;
3248 uint64_t reserved_5_63:59;
3249#endif
3250 } s;
3251 struct cvmx_sli_s2m_portx_ctl_s cn61xx;
3252 struct cvmx_sli_s2m_portx_ctl_s cn63xx;
3253 struct cvmx_sli_s2m_portx_ctl_s cn63xxp1;
3254 struct cvmx_sli_s2m_portx_ctl_s cn66xx;
3255 struct cvmx_sli_s2m_portx_ctl_s cn68xx;
3256 struct cvmx_sli_s2m_portx_ctl_s cn68xxp1;
3257 struct cvmx_sli_s2m_portx_ctl_s cnf71xx;
3258};
3259
3260union cvmx_sli_scratch_1 {
3261 uint64_t u64;
3262 struct cvmx_sli_scratch_1_s {
3263#ifdef __BIG_ENDIAN_BITFIELD
3264 uint64_t data:64;
3265#else
3266 uint64_t data:64;
3267#endif
3268 } s;
3269 struct cvmx_sli_scratch_1_s cn61xx;
3270 struct cvmx_sli_scratch_1_s cn63xx;
3271 struct cvmx_sli_scratch_1_s cn63xxp1;
3272 struct cvmx_sli_scratch_1_s cn66xx;
3273 struct cvmx_sli_scratch_1_s cn68xx;
3274 struct cvmx_sli_scratch_1_s cn68xxp1;
3275 struct cvmx_sli_scratch_1_s cnf71xx;
3276};
3277
3278union cvmx_sli_scratch_2 {
3279 uint64_t u64;
3280 struct cvmx_sli_scratch_2_s {
3281#ifdef __BIG_ENDIAN_BITFIELD
3282 uint64_t data:64;
3283#else
3284 uint64_t data:64;
3285#endif
3286 } s;
3287 struct cvmx_sli_scratch_2_s cn61xx;
3288 struct cvmx_sli_scratch_2_s cn63xx;
3289 struct cvmx_sli_scratch_2_s cn63xxp1;
3290 struct cvmx_sli_scratch_2_s cn66xx;
3291 struct cvmx_sli_scratch_2_s cn68xx;
3292 struct cvmx_sli_scratch_2_s cn68xxp1;
3293 struct cvmx_sli_scratch_2_s cnf71xx;
3294};
3295
3296union cvmx_sli_state1 {
3297 uint64_t u64;
3298 struct cvmx_sli_state1_s {
3299#ifdef __BIG_ENDIAN_BITFIELD
3300 uint64_t cpl1:12;
3301 uint64_t cpl0:12;
3302 uint64_t arb:1;
3303 uint64_t csr:39;
3304#else
3305 uint64_t csr:39;
3306 uint64_t arb:1;
3307 uint64_t cpl0:12;
3308 uint64_t cpl1:12;
3309#endif
3310 } s;
3311 struct cvmx_sli_state1_s cn61xx;
3312 struct cvmx_sli_state1_s cn63xx;
3313 struct cvmx_sli_state1_s cn63xxp1;
3314 struct cvmx_sli_state1_s cn66xx;
3315 struct cvmx_sli_state1_s cn68xx;
3316 struct cvmx_sli_state1_s cn68xxp1;
3317 struct cvmx_sli_state1_s cnf71xx;
3318};
3319
3320union cvmx_sli_state2 {
3321 uint64_t u64;
3322 struct cvmx_sli_state2_s {
3323#ifdef __BIG_ENDIAN_BITFIELD
3324 uint64_t reserved_56_63:8;
3325 uint64_t nnp1:8;
3326 uint64_t reserved_47_47:1;
3327 uint64_t rac:1;
3328 uint64_t csm1:15;
3329 uint64_t csm0:15;
3330 uint64_t nnp0:8;
3331 uint64_t nnd:8;
3332#else
3333 uint64_t nnd:8;
3334 uint64_t nnp0:8;
3335 uint64_t csm0:15;
3336 uint64_t csm1:15;
3337 uint64_t rac:1;
3338 uint64_t reserved_47_47:1;
3339 uint64_t nnp1:8;
3340 uint64_t reserved_56_63:8;
3341#endif
3342 } s;
3343 struct cvmx_sli_state2_s cn61xx;
3344 struct cvmx_sli_state2_s cn63xx;
3345 struct cvmx_sli_state2_s cn63xxp1;
3346 struct cvmx_sli_state2_s cn66xx;
3347 struct cvmx_sli_state2_s cn68xx;
3348 struct cvmx_sli_state2_s cn68xxp1;
3349 struct cvmx_sli_state2_s cnf71xx;
3350};
3351
3352union cvmx_sli_state3 {
3353 uint64_t u64;
3354 struct cvmx_sli_state3_s {
3355#ifdef __BIG_ENDIAN_BITFIELD
3356 uint64_t reserved_56_63:8;
3357 uint64_t psm1:15;
3358 uint64_t psm0:15;
3359 uint64_t nsm1:13;
3360 uint64_t nsm0:13;
3361#else
3362 uint64_t nsm0:13;
3363 uint64_t nsm1:13;
3364 uint64_t psm0:15;
3365 uint64_t psm1:15;
3366 uint64_t reserved_56_63:8;
3367#endif
3368 } s;
3369 struct cvmx_sli_state3_s cn61xx;
3370 struct cvmx_sli_state3_s cn63xx;
3371 struct cvmx_sli_state3_s cn63xxp1;
3372 struct cvmx_sli_state3_s cn66xx;
3373 struct cvmx_sli_state3_s cn68xx;
3374 struct cvmx_sli_state3_s cn68xxp1;
3375 struct cvmx_sli_state3_s cnf71xx;
3376};
3377
3378union cvmx_sli_tx_pipe {
3379 uint64_t u64;
3380 struct cvmx_sli_tx_pipe_s {
3381#ifdef __BIG_ENDIAN_BITFIELD
3382 uint64_t reserved_24_63:40;
3383 uint64_t nump:8;
3384 uint64_t reserved_7_15:9;
3385 uint64_t base:7;
3386#else
3387 uint64_t base:7;
3388 uint64_t reserved_7_15:9;
3389 uint64_t nump:8;
3390 uint64_t reserved_24_63:40;
3391#endif
3392 } s; 96 } s;
3393 struct cvmx_sli_tx_pipe_s cn68xx;
3394 struct cvmx_sli_tx_pipe_s cn68xxp1;
3395}; 97};
3396 98
3397union cvmx_sli_win_rd_addr { 99union cvmx_sli_mem_access_subidx {
3398 uint64_t u64;
3399 struct cvmx_sli_win_rd_addr_s {
3400#ifdef __BIG_ENDIAN_BITFIELD
3401 uint64_t reserved_51_63:13;
3402 uint64_t ld_cmd:2;
3403 uint64_t iobit:1;
3404 uint64_t rd_addr:48;
3405#else
3406 uint64_t rd_addr:48;
3407 uint64_t iobit:1;
3408 uint64_t ld_cmd:2;
3409 uint64_t reserved_51_63:13;
3410#endif
3411 } s;
3412 struct cvmx_sli_win_rd_addr_s cn61xx;
3413 struct cvmx_sli_win_rd_addr_s cn63xx;
3414 struct cvmx_sli_win_rd_addr_s cn63xxp1;
3415 struct cvmx_sli_win_rd_addr_s cn66xx;
3416 struct cvmx_sli_win_rd_addr_s cn68xx;
3417 struct cvmx_sli_win_rd_addr_s cn68xxp1;
3418 struct cvmx_sli_win_rd_addr_s cnf71xx;
3419};
3420
3421union cvmx_sli_win_rd_data {
3422 uint64_t u64;
3423 struct cvmx_sli_win_rd_data_s {
3424#ifdef __BIG_ENDIAN_BITFIELD
3425 uint64_t rd_data:64;
3426#else
3427 uint64_t rd_data:64;
3428#endif
3429 } s;
3430 struct cvmx_sli_win_rd_data_s cn61xx;
3431 struct cvmx_sli_win_rd_data_s cn63xx;
3432 struct cvmx_sli_win_rd_data_s cn63xxp1;
3433 struct cvmx_sli_win_rd_data_s cn66xx;
3434 struct cvmx_sli_win_rd_data_s cn68xx;
3435 struct cvmx_sli_win_rd_data_s cn68xxp1;
3436 struct cvmx_sli_win_rd_data_s cnf71xx;
3437};
3438
3439union cvmx_sli_win_wr_addr {
3440 uint64_t u64;
3441 struct cvmx_sli_win_wr_addr_s {
3442#ifdef __BIG_ENDIAN_BITFIELD
3443 uint64_t reserved_49_63:15;
3444 uint64_t iobit:1;
3445 uint64_t wr_addr:45;
3446 uint64_t reserved_0_2:3;
3447#else
3448 uint64_t reserved_0_2:3;
3449 uint64_t wr_addr:45;
3450 uint64_t iobit:1;
3451 uint64_t reserved_49_63:15;
3452#endif
3453 } s;
3454 struct cvmx_sli_win_wr_addr_s cn61xx;
3455 struct cvmx_sli_win_wr_addr_s cn63xx;
3456 struct cvmx_sli_win_wr_addr_s cn63xxp1;
3457 struct cvmx_sli_win_wr_addr_s cn66xx;
3458 struct cvmx_sli_win_wr_addr_s cn68xx;
3459 struct cvmx_sli_win_wr_addr_s cn68xxp1;
3460 struct cvmx_sli_win_wr_addr_s cnf71xx;
3461};
3462
3463union cvmx_sli_win_wr_data {
3464 uint64_t u64;
3465 struct cvmx_sli_win_wr_data_s {
3466#ifdef __BIG_ENDIAN_BITFIELD
3467 uint64_t wr_data:64;
3468#else
3469 uint64_t wr_data:64;
3470#endif
3471 } s;
3472 struct cvmx_sli_win_wr_data_s cn61xx;
3473 struct cvmx_sli_win_wr_data_s cn63xx;
3474 struct cvmx_sli_win_wr_data_s cn63xxp1;
3475 struct cvmx_sli_win_wr_data_s cn66xx;
3476 struct cvmx_sli_win_wr_data_s cn68xx;
3477 struct cvmx_sli_win_wr_data_s cn68xxp1;
3478 struct cvmx_sli_win_wr_data_s cnf71xx;
3479};
3480
3481union cvmx_sli_win_wr_mask {
3482 uint64_t u64;
3483 struct cvmx_sli_win_wr_mask_s {
3484#ifdef __BIG_ENDIAN_BITFIELD
3485 uint64_t reserved_8_63:56;
3486 uint64_t wr_mask:8;
3487#else
3488 uint64_t wr_mask:8;
3489 uint64_t reserved_8_63:56;
3490#endif
3491 } s;
3492 struct cvmx_sli_win_wr_mask_s cn61xx;
3493 struct cvmx_sli_win_wr_mask_s cn63xx;
3494 struct cvmx_sli_win_wr_mask_s cn63xxp1;
3495 struct cvmx_sli_win_wr_mask_s cn66xx;
3496 struct cvmx_sli_win_wr_mask_s cn68xx;
3497 struct cvmx_sli_win_wr_mask_s cn68xxp1;
3498 struct cvmx_sli_win_wr_mask_s cnf71xx;
3499};
3500
3501union cvmx_sli_window_ctl {
3502 uint64_t u64; 100 uint64_t u64;
3503 struct cvmx_sli_window_ctl_s { 101 struct cvmx_sli_mem_access_subidx_s {
3504#ifdef __BIG_ENDIAN_BITFIELD 102 __BITFIELD_FIELD(uint64_t reserved_43_63:21,
3505 uint64_t reserved_32_63:32; 103 __BITFIELD_FIELD(uint64_t zero:1,
3506 uint64_t time:32; 104 __BITFIELD_FIELD(uint64_t port:3,
3507#else 105 __BITFIELD_FIELD(uint64_t nmerge:1,
3508 uint64_t time:32; 106 __BITFIELD_FIELD(uint64_t esr:2,
3509 uint64_t reserved_32_63:32; 107 __BITFIELD_FIELD(uint64_t esw:2,
3510#endif 108 __BITFIELD_FIELD(uint64_t wtype:2,
109 __BITFIELD_FIELD(uint64_t rtype:2,
110 __BITFIELD_FIELD(uint64_t ba:30,
111 ;)))))))))
3511 } s; 112 } s;
3512 struct cvmx_sli_window_ctl_s cn61xx; 113 struct cvmx_sli_mem_access_subidx_cn68xx {
3513 struct cvmx_sli_window_ctl_s cn63xx; 114 __BITFIELD_FIELD(uint64_t reserved_43_63:21,
3514 struct cvmx_sli_window_ctl_s cn63xxp1; 115 __BITFIELD_FIELD(uint64_t zero:1,
3515 struct cvmx_sli_window_ctl_s cn66xx; 116 __BITFIELD_FIELD(uint64_t port:3,
3516 struct cvmx_sli_window_ctl_s cn68xx; 117 __BITFIELD_FIELD(uint64_t nmerge:1,
3517 struct cvmx_sli_window_ctl_s cn68xxp1; 118 __BITFIELD_FIELD(uint64_t esr:2,
3518 struct cvmx_sli_window_ctl_s cnf71xx; 119 __BITFIELD_FIELD(uint64_t esw:2,
120 __BITFIELD_FIELD(uint64_t wtype:2,
121 __BITFIELD_FIELD(uint64_t rtype:2,
122 __BITFIELD_FIELD(uint64_t ba:28,
123 __BITFIELD_FIELD(uint64_t reserved_0_1:2,
124 ;))))))))))
125 } cn68xx;
3519}; 126};
3520 127
3521#endif 128#endif
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 2530e8731c8a..9742202f2a32 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2017 Cavium, Inc.
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -62,7 +62,6 @@ enum cvmx_mips_space {
62#include <asm/octeon/cvmx-iob-defs.h> 62#include <asm/octeon/cvmx-iob-defs.h>
63#include <asm/octeon/cvmx-ipd-defs.h> 63#include <asm/octeon/cvmx-ipd-defs.h>
64#include <asm/octeon/cvmx-l2c-defs.h> 64#include <asm/octeon/cvmx-l2c-defs.h>
65#include <asm/octeon/cvmx-l2d-defs.h>
66#include <asm/octeon/cvmx-l2t-defs.h> 65#include <asm/octeon/cvmx-l2t-defs.h>
67#include <asm/octeon/cvmx-led-defs.h> 66#include <asm/octeon/cvmx-led-defs.h>
68#include <asm/octeon/cvmx-mio-defs.h> 67#include <asm/octeon/cvmx-mio-defs.h>
diff --git a/arch/mips/include/asm/pgalloc.h b/arch/mips/include/asm/pgalloc.h
index a8705f6c8180..a1bdb1ea5234 100644
--- a/arch/mips/include/asm/pgalloc.h
+++ b/arch/mips/include/asm/pgalloc.h
@@ -110,6 +110,32 @@ static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
110 110
111#endif 111#endif
112 112
113#ifndef __PAGETABLE_PUD_FOLDED
114
115static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long address)
116{
117 pud_t *pud;
118
119 pud = (pud_t *) __get_free_pages(GFP_KERNEL|__GFP_REPEAT, PUD_ORDER);
120 if (pud)
121 pud_init((unsigned long)pud, (unsigned long)invalid_pmd_table);
122 return pud;
123}
124
125static inline void pud_free(struct mm_struct *mm, pud_t *pud)
126{
127 free_pages((unsigned long)pud, PUD_ORDER);
128}
129
130static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
131{
132 set_pgd(pgd, __pgd((unsigned long)pud));
133}
134
135#define __pud_free_tlb(tlb, x, addr) pud_free((tlb)->mm, x)
136
137#endif /* __PAGETABLE_PUD_FOLDED */
138
113#define check_pgt_cache() do { } while (0) 139#define check_pgt_cache() do { } while (0)
114 140
115extern void pagetable_init(void); 141extern void pagetable_init(void);
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index 130a2a6c1531..67fe6dc5211c 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -20,7 +20,7 @@
20#define __ARCH_USE_5LEVEL_HACK 20#define __ARCH_USE_5LEVEL_HACK
21#if defined(CONFIG_PAGE_SIZE_64KB) && !defined(CONFIG_MIPS_VA_BITS_48) 21#if defined(CONFIG_PAGE_SIZE_64KB) && !defined(CONFIG_MIPS_VA_BITS_48)
22#include <asm-generic/pgtable-nopmd.h> 22#include <asm-generic/pgtable-nopmd.h>
23#else 23#elif !(defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_MIPS_VA_BITS_48))
24#include <asm-generic/pgtable-nopud.h> 24#include <asm-generic/pgtable-nopud.h>
25#endif 25#endif
26 26
@@ -54,9 +54,18 @@
54#define PMD_SIZE (1UL << PMD_SHIFT) 54#define PMD_SIZE (1UL << PMD_SHIFT)
55#define PMD_MASK (~(PMD_SIZE-1)) 55#define PMD_MASK (~(PMD_SIZE-1))
56 56
57# ifdef __PAGETABLE_PUD_FOLDED
58# define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
59# endif
60#endif
57 61
58#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3)) 62#ifndef __PAGETABLE_PUD_FOLDED
63#define PUD_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
64#define PUD_SIZE (1UL << PUD_SHIFT)
65#define PUD_MASK (~(PUD_SIZE-1))
66#define PGDIR_SHIFT (PUD_SHIFT + (PAGE_SHIFT + PUD_ORDER - 3))
59#endif 67#endif
68
60#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 69#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
61#define PGDIR_MASK (~(PGDIR_SIZE-1)) 70#define PGDIR_MASK (~(PGDIR_SIZE-1))
62 71
@@ -79,8 +88,13 @@
79 * of virtual address space. 88 * of virtual address space.
80 */ 89 */
81#ifdef CONFIG_PAGE_SIZE_4KB 90#ifdef CONFIG_PAGE_SIZE_4KB
82#define PGD_ORDER 1 91# ifdef CONFIG_MIPS_VA_BITS_48
83#define PUD_ORDER aieeee_attempt_to_allocate_pud 92# define PGD_ORDER 0
93# define PUD_ORDER 0
94# else
95# define PGD_ORDER 1
96# define PUD_ORDER aieeee_attempt_to_allocate_pud
97# endif
84#define PMD_ORDER 0 98#define PMD_ORDER 0
85#define PTE_ORDER 0 99#define PTE_ORDER 0
86#endif 100#endif
@@ -118,6 +132,9 @@
118#endif 132#endif
119 133
120#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) 134#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
135#ifndef __PAGETABLE_PUD_FOLDED
136#define PTRS_PER_PUD ((PAGE_SIZE << PUD_ORDER) / sizeof(pud_t))
137#endif
121#ifndef __PAGETABLE_PMD_FOLDED 138#ifndef __PAGETABLE_PMD_FOLDED
122#define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t)) 139#define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t))
123#endif 140#endif
@@ -134,7 +151,7 @@
134#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE)) 151#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE))
135#define VMALLOC_END \ 152#define VMALLOC_END \
136 (MAP_BASE + \ 153 (MAP_BASE + \
137 min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \ 154 min(PTRS_PER_PGD * PTRS_PER_PUD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \
138 (1UL << cpu_vmbits)) - (1UL << 32)) 155 (1UL << cpu_vmbits)) - (1UL << 32))
139 156
140#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ 157#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \
@@ -150,12 +167,72 @@
150#define pmd_ERROR(e) \ 167#define pmd_ERROR(e) \
151 printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 168 printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
152#endif 169#endif
170#ifndef __PAGETABLE_PUD_FOLDED
171#define pud_ERROR(e) \
172 printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e))
173#endif
153#define pgd_ERROR(e) \ 174#define pgd_ERROR(e) \
154 printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 175 printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
155 176
156extern pte_t invalid_pte_table[PTRS_PER_PTE]; 177extern pte_t invalid_pte_table[PTRS_PER_PTE];
157extern pte_t empty_bad_page_table[PTRS_PER_PTE]; 178extern pte_t empty_bad_page_table[PTRS_PER_PTE];
158 179
180#ifndef __PAGETABLE_PUD_FOLDED
181/*
182 * For 4-level pagetables we defines these ourselves, for 3-level the
183 * definitions are below, for 2-level the
184 * definitions are supplied by <asm-generic/pgtable-nopmd.h>.
185 */
186typedef struct { unsigned long pud; } pud_t;
187#define pud_val(x) ((x).pud)
188#define __pud(x) ((pud_t) { (x) })
189
190extern pud_t invalid_pud_table[PTRS_PER_PUD];
191
192/*
193 * Empty pgd entries point to the invalid_pud_table.
194 */
195static inline int pgd_none(pgd_t pgd)
196{
197 return pgd_val(pgd) == (unsigned long)invalid_pud_table;
198}
199
200static inline int pgd_bad(pgd_t pgd)
201{
202 if (unlikely(pgd_val(pgd) & ~PAGE_MASK))
203 return 1;
204
205 return 0;
206}
207
208static inline int pgd_present(pgd_t pgd)
209{
210 return pgd_val(pgd) != (unsigned long)invalid_pud_table;
211}
212
213static inline void pgd_clear(pgd_t *pgdp)
214{
215 pgd_val(*pgdp) = (unsigned long)invalid_pud_table;
216}
217
218#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
219
220static inline unsigned long pgd_page_vaddr(pgd_t pgd)
221{
222 return pgd_val(pgd);
223}
224
225static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
226{
227 return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(address);
228}
229
230static inline void set_pgd(pgd_t *pgd, pgd_t pgdval)
231{
232 *pgd = pgdval;
233}
234
235#endif
159 236
160#ifndef __PAGETABLE_PMD_FOLDED 237#ifndef __PAGETABLE_PMD_FOLDED
161/* 238/*
@@ -281,6 +358,7 @@ static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
281 * Initialize a new pgd / pmd table with invalid pointers. 358 * Initialize a new pgd / pmd table with invalid pointers.
282 */ 359 */
283extern void pgd_init(unsigned long page); 360extern void pgd_init(unsigned long page);
361extern void pud_init(unsigned long page, unsigned long pagetable);
284extern void pmd_init(unsigned long page, unsigned long pagetable); 362extern void pmd_init(unsigned long page, unsigned long pagetable);
285 363
286/* 364/*
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index e9a9e2ade1d2..3748f4d120a5 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -21,77 +21,46 @@
21#define UASM_EXPORT_SYMBOL(sym) 21#define UASM_EXPORT_SYMBOL(sym)
22#endif 22#endif
23 23
24#define _UASM_ISA_CLASSIC 0
25#define _UASM_ISA_MICROMIPS 1
26
27#ifndef UASM_ISA
28#ifdef CONFIG_CPU_MICROMIPS
29#define UASM_ISA _UASM_ISA_MICROMIPS
30#else
31#define UASM_ISA _UASM_ISA_CLASSIC
32#endif
33#endif
34
35#if (UASM_ISA == _UASM_ISA_CLASSIC)
36#ifdef CONFIG_CPU_MICROMIPS
37#define ISAOPC(op) CL_uasm_i##op
38#define ISAFUNC(x) CL_##x
39#else
40#define ISAOPC(op) uasm_i##op
41#define ISAFUNC(x) x
42#endif
43#elif (UASM_ISA == _UASM_ISA_MICROMIPS)
44#ifdef CONFIG_CPU_MICROMIPS
45#define ISAOPC(op) uasm_i##op
46#define ISAFUNC(x) x
47#else
48#define ISAOPC(op) MM_uasm_i##op
49#define ISAFUNC(x) MM_##x
50#endif
51#else
52#error Unsupported micro-assembler ISA!!!
53#endif
54
55#define Ip_u1u2u3(op) \ 24#define Ip_u1u2u3(op) \
56void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 25void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
57 26
58#define Ip_u2u1u3(op) \ 27#define Ip_u2u1u3(op) \
59void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 28void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
60 29
61#define Ip_u3u2u1(op) \ 30#define Ip_u3u2u1(op) \
62void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 31void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
63 32
64#define Ip_u3u1u2(op) \ 33#define Ip_u3u1u2(op) \
65void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 34void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
66 35
67#define Ip_u1u2s3(op) \ 36#define Ip_u1u2s3(op) \
68void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c) 37void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
69 38
70#define Ip_u2s3u1(op) \ 39#define Ip_u2s3u1(op) \
71void ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c) 40void uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
72 41
73#define Ip_s3s1s2(op) \ 42#define Ip_s3s1s2(op) \
74void ISAOPC(op)(u32 **buf, int a, int b, int c) 43void uasm_i##op(u32 **buf, int a, int b, int c)
75 44
76#define Ip_u2u1s3(op) \ 45#define Ip_u2u1s3(op) \
77void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c) 46void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
78 47
79#define Ip_u2u1msbu3(op) \ 48#define Ip_u2u1msbu3(op) \
80void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \ 49void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
81 unsigned int d) 50 unsigned int d)
82 51
83#define Ip_u1u2(op) \ 52#define Ip_u1u2(op) \
84void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b) 53void uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
85 54
86#define Ip_u2u1(op) \ 55#define Ip_u2u1(op) \
87void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b) 56void uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
88 57
89#define Ip_u1s2(op) \ 58#define Ip_u1s2(op) \
90void ISAOPC(op)(u32 **buf, unsigned int a, signed int b) 59void uasm_i##op(u32 **buf, unsigned int a, signed int b)
91 60
92#define Ip_u1(op) void ISAOPC(op)(u32 **buf, unsigned int a) 61#define Ip_u1(op) void uasm_i##op(u32 **buf, unsigned int a)
93 62
94#define Ip_0(op) void ISAOPC(op)(u32 **buf) 63#define Ip_0(op) void uasm_i##op(u32 **buf)
95 64
96Ip_u2u1s3(_addiu); 65Ip_u2u1s3(_addiu);
97Ip_u3u1u2(_addu); 66Ip_u3u1u2(_addu);
@@ -138,6 +107,7 @@ Ip_u2s3u1(_lb);
138Ip_u2s3u1(_ld); 107Ip_u2s3u1(_ld);
139Ip_u3u1u2(_ldx); 108Ip_u3u1u2(_ldx);
140Ip_u2s3u1(_lh); 109Ip_u2s3u1(_lh);
110Ip_u2s3u1(_lhu);
141Ip_u2s3u1(_ll); 111Ip_u2s3u1(_ll);
142Ip_u2s3u1(_lld); 112Ip_u2s3u1(_lld);
143Ip_u1s2(_lui); 113Ip_u1s2(_lui);
@@ -190,20 +160,20 @@ struct uasm_label {
190 int lab; 160 int lab;
191}; 161};
192 162
193void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, 163void uasm_build_label(struct uasm_label **lab, u32 *addr,
194 int lid); 164 int lid);
195#ifdef CONFIG_64BIT 165#ifdef CONFIG_64BIT
196int ISAFUNC(uasm_in_compat_space_p)(long addr); 166int uasm_in_compat_space_p(long addr);
197#endif 167#endif
198int ISAFUNC(uasm_rel_hi)(long val); 168int uasm_rel_hi(long val);
199int ISAFUNC(uasm_rel_lo)(long val); 169int uasm_rel_lo(long val);
200void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr); 170void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr);
201void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr); 171void UASM_i_LA(u32 **buf, unsigned int rs, long addr);
202 172
203#define UASM_L_LA(lb) \ 173#define UASM_L_LA(lb) \
204static inline void ISAFUNC(uasm_l##lb)(struct uasm_label **lab, u32 *addr) \ 174static inline void uasm_l##lb(struct uasm_label **lab, u32 *addr) \
205{ \ 175{ \
206 ISAFUNC(uasm_build_label)(lab, addr, label##lb); \ 176 uasm_build_label(lab, addr, label##lb); \
207} 177}
208 178
209/* convenience macros for instructions */ 179/* convenience macros for instructions */
@@ -255,27 +225,27 @@ static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,
255 unsigned int a2, unsigned int a3) 225 unsigned int a2, unsigned int a3)
256{ 226{
257 if (a3 < 32) 227 if (a3 < 32)
258 ISAOPC(_drotr)(p, a1, a2, a3); 228 uasm_i_drotr(p, a1, a2, a3);
259 else 229 else
260 ISAOPC(_drotr32)(p, a1, a2, a3 - 32); 230 uasm_i_drotr32(p, a1, a2, a3 - 32);
261} 231}
262 232
263static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1, 233static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1,
264 unsigned int a2, unsigned int a3) 234 unsigned int a2, unsigned int a3)
265{ 235{
266 if (a3 < 32) 236 if (a3 < 32)
267 ISAOPC(_dsll)(p, a1, a2, a3); 237 uasm_i_dsll(p, a1, a2, a3);
268 else 238 else
269 ISAOPC(_dsll32)(p, a1, a2, a3 - 32); 239 uasm_i_dsll32(p, a1, a2, a3 - 32);
270} 240}
271 241
272static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1, 242static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
273 unsigned int a2, unsigned int a3) 243 unsigned int a2, unsigned int a3)
274{ 244{
275 if (a3 < 32) 245 if (a3 < 32)
276 ISAOPC(_dsrl)(p, a1, a2, a3); 246 uasm_i_dsrl(p, a1, a2, a3);
277 else 247 else
278 ISAOPC(_dsrl32)(p, a1, a2, a3 - 32); 248 uasm_i_dsrl32(p, a1, a2, a3 - 32);
279} 249}
280 250
281/* Handle relocations. */ 251/* Handle relocations. */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 3382892544f0..1aba27786bd5 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -34,6 +34,7 @@
34 34
35/* Hardware capabilities */ 35/* Hardware capabilities */
36unsigned int elf_hwcap __read_mostly; 36unsigned int elf_hwcap __read_mostly;
37EXPORT_SYMBOL_GPL(elf_hwcap);
37 38
38/* 39/*
39 * Get the FPU Implementation/Revision. 40 * Get the FPU Implementation/Revision.
@@ -1955,6 +1956,12 @@ void cpu_probe(void)
1955 struct cpuinfo_mips *c = &current_cpu_data; 1956 struct cpuinfo_mips *c = &current_cpu_data;
1956 unsigned int cpu = smp_processor_id(); 1957 unsigned int cpu = smp_processor_id();
1957 1958
1959 /*
1960 * Set a default elf platform, cpu probe may later
1961 * overwrite it with a more precise value
1962 */
1963 set_elf_platform(cpu, "mips");
1964
1958 c->processor_id = PRID_IMP_UNKNOWN; 1965 c->processor_id = PRID_IMP_UNKNOWN;
1959 c->fpu_id = FPIR_IMP_NONE; 1966 c->fpu_id = FPIR_IMP_NONE;
1960 c->cputype = CPU_UNKNOWN; 1967 c->cputype = CPU_UNKNOWN;
diff --git a/arch/mips/kernel/mips-r2-to-r6-emul.c b/arch/mips/kernel/mips-r2-to-r6-emul.c
index 550e7d03090a..ae64c8f56a8c 100644
--- a/arch/mips/kernel/mips-r2-to-r6-emul.c
+++ b/arch/mips/kernel/mips-r2-to-r6-emul.c
@@ -1096,10 +1096,20 @@ repeat:
1096 } 1096 }
1097 break; 1097 break;
1098 1098
1099 case beql_op:
1100 case bnel_op:
1101 case blezl_op: 1099 case blezl_op:
1102 case bgtzl_op: 1100 case bgtzl_op:
1101 /*
1102 * For BLEZL and BGTZL, rt field must be set to 0. If this
1103 * is not the case, this may be an encoding of a MIPS R6
1104 * instruction, so return to CPU execution if this occurs
1105 */
1106 if (MIPSInst_RT(inst)) {
1107 err = SIGILL;
1108 break;
1109 }
1110 /* fall through */
1111 case beql_op:
1112 case bnel_op:
1103 if (delay_slot(regs)) { 1113 if (delay_slot(regs)) {
1104 err = SIGILL; 1114 err = SIGILL;
1105 break; 1115 break;
@@ -2329,6 +2339,8 @@ static int mipsr2_stats_clear_show(struct seq_file *s, void *unused)
2329 __this_cpu_write((mipsr2bremustats).bgezl, 0); 2339 __this_cpu_write((mipsr2bremustats).bgezl, 0);
2330 __this_cpu_write((mipsr2bremustats).bltzll, 0); 2340 __this_cpu_write((mipsr2bremustats).bltzll, 0);
2331 __this_cpu_write((mipsr2bremustats).bgezll, 0); 2341 __this_cpu_write((mipsr2bremustats).bgezll, 0);
2342 __this_cpu_write((mipsr2bremustats).bltzall, 0);
2343 __this_cpu_write((mipsr2bremustats).bgezall, 0);
2332 __this_cpu_write((mipsr2bremustats).bltzal, 0); 2344 __this_cpu_write((mipsr2bremustats).bltzal, 0);
2333 __this_cpu_write((mipsr2bremustats).bgezal, 0); 2345 __this_cpu_write((mipsr2bremustats).bgezal, 0);
2334 __this_cpu_write((mipsr2bremustats).beql, 0); 2346 __this_cpu_write((mipsr2bremustats).beql, 0);
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index b68e10fc453d..918d4c73e951 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -114,8 +114,8 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
114/* 114/*
115 * Copy architecture-specific thread state 115 * Copy architecture-specific thread state
116 */ 116 */
117int copy_thread(unsigned long clone_flags, unsigned long usp, 117int copy_thread_tls(unsigned long clone_flags, unsigned long usp,
118 unsigned long kthread_arg, struct task_struct *p) 118 unsigned long kthread_arg, struct task_struct *p, unsigned long tls)
119{ 119{
120 struct thread_info *ti = task_thread_info(p); 120 struct thread_info *ti = task_thread_info(p);
121 struct pt_regs *childregs, *regs = current_pt_regs(); 121 struct pt_regs *childregs, *regs = current_pt_regs();
@@ -176,7 +176,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
176 atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE); 176 atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE);
177 177
178 if (clone_flags & CLONE_SETTLS) 178 if (clone_flags & CLONE_SETTLS)
179 ti->tp_value = regs->regs[7]; 179 ti->tp_value = tls;
180 180
181 return 0; 181 return 0;
182} 182}
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 758577861523..7b386d54fd65 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -25,12 +25,6 @@
25/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */ 25/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
26#undef fp 26#undef fp
27 27
28/*
29 * Offset to the current process status flags, the first 32 bytes of the
30 * stack are not used.
31 */
32#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
33
34#ifndef USE_ALTERNATE_RESUME_IMPL 28#ifndef USE_ALTERNATE_RESUME_IMPL
35/* 29/*
36 * task_struct *resume(task_struct *prev, task_struct *next, 30 * task_struct *resume(task_struct *prev, task_struct *next,
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index 795b4aaf8927..36954ddd0b9f 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -8,6 +8,7 @@
8 * option) any later version. 8 * option) any later version.
9 */ 9 */
10 10
11#include <linux/cpu.h>
11#include <linux/delay.h> 12#include <linux/delay.h>
12#include <linux/io.h> 13#include <linux/io.h>
13#include <linux/irqchip/mips-gic.h> 14#include <linux/irqchip/mips-gic.h>
@@ -408,7 +409,6 @@ static int cps_cpu_disable(void)
408 return 0; 409 return 0;
409} 410}
410 411
411static DECLARE_COMPLETION(cpu_death_chosen);
412static unsigned cpu_death_sibling; 412static unsigned cpu_death_sibling;
413static enum { 413static enum {
414 CPU_DEATH_HALT, 414 CPU_DEATH_HALT,
@@ -443,7 +443,7 @@ void play_dead(void)
443 } 443 }
444 444
445 /* This CPU has chosen its way out */ 445 /* This CPU has chosen its way out */
446 complete(&cpu_death_chosen); 446 (void)cpu_report_death();
447 447
448 if (cpu_death == CPU_DEATH_HALT) { 448 if (cpu_death == CPU_DEATH_HALT) {
449 vpe_id = cpu_vpe_id(&cpu_data[cpu]); 449 vpe_id = cpu_vpe_id(&cpu_data[cpu]);
@@ -492,8 +492,7 @@ static void cps_cpu_die(unsigned int cpu)
492 int err; 492 int err;
493 493
494 /* Wait for the cpu to choose its way out */ 494 /* Wait for the cpu to choose its way out */
495 if (!wait_for_completion_timeout(&cpu_death_chosen, 495 if (!cpu_wait_death(cpu, 5)) {
496 msecs_to_jiffies(5000))) {
497 pr_err("CPU%u: didn't offline\n", cpu); 496 pr_err("CPU%u: didn't offline\n", cpu);
498 return; 497 return;
499 } 498 }
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index e398cbc3d776..ed6b4df583ea 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -83,6 +83,8 @@ static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
83 if (tc != 0) 83 if (tc != 0)
84 smvp_copy_vpe_config(); 84 smvp_copy_vpe_config();
85 85
86 cpu_data[ncpu].vpe_id = tc;
87
86 return ncpu; 88 return ncpu;
87} 89}
88 90
@@ -114,49 +116,6 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
114 write_tc_c0_tchalt(TCHALT_H); 116 write_tc_c0_tchalt(TCHALT_H);
115} 117}
116 118
117static void vsmp_send_ipi_single(int cpu, unsigned int action)
118{
119 int i;
120 unsigned long flags;
121 int vpflags;
122
123#ifdef CONFIG_MIPS_GIC
124 if (gic_present) {
125 mips_smp_send_ipi_single(cpu, action);
126 return;
127 }
128#endif
129 local_irq_save(flags);
130
131 vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */
132
133 switch (action) {
134 case SMP_CALL_FUNCTION:
135 i = C_SW1;
136 break;
137
138 case SMP_RESCHEDULE_YOURSELF:
139 default:
140 i = C_SW0;
141 break;
142 }
143
144 /* 1:1 mapping of vpe and tc... */
145 settc(cpu);
146 write_vpe_c0_cause(read_vpe_c0_cause() | i);
147 evpe(vpflags);
148
149 local_irq_restore(flags);
150}
151
152static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
153{
154 unsigned int i;
155
156 for_each_cpu(i, mask)
157 vsmp_send_ipi_single(i, action);
158}
159
160static void vsmp_init_secondary(void) 119static void vsmp_init_secondary(void)
161{ 120{
162#ifdef CONFIG_MIPS_GIC 121#ifdef CONFIG_MIPS_GIC
@@ -281,8 +240,8 @@ static void __init vsmp_prepare_cpus(unsigned int max_cpus)
281} 240}
282 241
283struct plat_smp_ops vsmp_smp_ops = { 242struct plat_smp_ops vsmp_smp_ops = {
284 .send_ipi_single = vsmp_send_ipi_single, 243 .send_ipi_single = mips_smp_send_ipi_single,
285 .send_ipi_mask = vsmp_send_ipi_mask, 244 .send_ipi_mask = mips_smp_send_ipi_mask,
286 .init_secondary = vsmp_init_secondary, 245 .init_secondary = vsmp_init_secondary,
287 .smp_finish = vsmp_smp_finish, 246 .smp_finish = vsmp_smp_finish,
288 .boot_secondary = vsmp_boot_secondary, 247 .boot_secondary = vsmp_boot_secondary,
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 6e71130549ea..aba1afb64b62 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -261,16 +261,20 @@ int mips_smp_ipi_allocate(const struct cpumask *mask)
261 ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI); 261 ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI);
262 262
263 /* 263 /*
264 * There are systems which only use IPI domains some of the time, 264 * There are systems which use IPI IRQ domains, but only have one
265 * depending upon configuration we don't know until runtime. An 265 * registered when some runtime condition is met. For example a Malta
266 * example is Malta where we may compile in support for GIC & the 266 * kernel may include support for GIC & CPU interrupt controller IPI
267 * MT ASE, but run on a system which has multiple VPEs in a single 267 * IRQ domains, but if run on a system with no GIC & no MT ASE then
268 * core and doesn't include a GIC. Until all IPI implementations 268 * neither will be supported or registered.
269 * have been converted to use IPI domains the best we can do here 269 *
270 * is to return & hope some other code sets up the IPIs. 270 * We only have a problem if we're actually using multiple CPUs so fail
271 * loudly if that is the case. Otherwise simply return, skipping IPI
272 * setup, if we're running with only a single CPU.
271 */ 273 */
272 if (!ipidomain) 274 if (!ipidomain) {
275 BUG_ON(num_present_cpus() > 1);
273 return 0; 276 return 0;
277 }
274 278
275 virq = irq_reserve_ipi(ipidomain, mask); 279 virq = irq_reserve_ipi(ipidomain, mask);
276 BUG_ON(!virq); 280 BUG_ON(!virq);
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index 0ddf3698b85d..33728b7af426 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -274,47 +274,6 @@ static void ltq_hw_irq_handler(struct irq_desc *desc)
274 ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2); 274 ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
275} 275}
276 276
277#ifdef CONFIG_MIPS_MT_SMP
278void __init arch_init_ipiirq(int irq, struct irqaction *action)
279{
280 setup_irq(irq, action);
281 irq_set_handler(irq, handle_percpu_irq);
282}
283
284static void ltq_sw0_irqdispatch(void)
285{
286 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
287}
288
289static void ltq_sw1_irqdispatch(void)
290{
291 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
292}
293static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
294{
295 scheduler_ipi();
296 return IRQ_HANDLED;
297}
298
299static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
300{
301 generic_smp_call_function_interrupt();
302 return IRQ_HANDLED;
303}
304
305static struct irqaction irq_resched = {
306 .handler = ipi_resched_interrupt,
307 .flags = IRQF_PERCPU,
308 .name = "IPI_resched"
309};
310
311static struct irqaction irq_call = {
312 .handler = ipi_call_interrupt,
313 .flags = IRQF_PERCPU,
314 .name = "IPI_call"
315};
316#endif
317
318asmlinkage void plat_irq_dispatch(void) 277asmlinkage void plat_irq_dispatch(void)
319{ 278{
320 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 279 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
@@ -402,17 +361,6 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
402 (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE, 361 (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
403 &irq_domain_ops, 0); 362 &irq_domain_ops, 0);
404 363
405#if defined(CONFIG_MIPS_MT_SMP)
406 if (cpu_has_vint) {
407 pr_info("Setting up IPI vectored interrupts\n");
408 set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
409 set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
410 }
411 arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
412 &irq_resched);
413 arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
414#endif
415
416#ifndef CONFIG_MIPS_MT_SMP 364#ifndef CONFIG_MIPS_MT_SMP
417 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | 365 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
418 IE_IRQ3 | IE_IRQ4 | IE_IRQ5); 366 IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index a298ac93edcc..f12fde10c8ad 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -439,6 +439,8 @@ int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
439 union mips_instruction insn = (union mips_instruction)dec_insn.insn; 439 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
440 unsigned int fcr31; 440 unsigned int fcr31;
441 unsigned int bit = 0; 441 unsigned int bit = 0;
442 unsigned int bit0;
443 union fpureg *fpr;
442 444
443 switch (insn.i_format.opcode) { 445 switch (insn.i_format.opcode) {
444 case spec_op: 446 case spec_op:
@@ -706,14 +708,14 @@ int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
706 ((insn.i_format.rs == bc1eqz_op) || 708 ((insn.i_format.rs == bc1eqz_op) ||
707 (insn.i_format.rs == bc1nez_op))) { 709 (insn.i_format.rs == bc1nez_op))) {
708 bit = 0; 710 bit = 0;
711 fpr = &current->thread.fpu.fpr[insn.i_format.rt];
712 bit0 = get_fpr32(fpr, 0) & 0x1;
709 switch (insn.i_format.rs) { 713 switch (insn.i_format.rs) {
710 case bc1eqz_op: 714 case bc1eqz_op:
711 if (get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1) 715 bit = bit0 == 0;
712 bit = 1;
713 break; 716 break;
714 case bc1nez_op: 717 case bc1nez_op:
715 if (!(get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)) 718 bit = bit0 != 0;
716 bit = 1;
717 break; 719 break;
718 } 720 }
719 if (bit) 721 if (bit)
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index 3bef306cdfdb..4f8f5bf46977 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -267,19 +267,19 @@ do_sigbus:
267 /* Kernel mode? Handle exceptions or die */ 267 /* Kernel mode? Handle exceptions or die */
268 if (!user_mode(regs)) 268 if (!user_mode(regs))
269 goto no_context; 269 goto no_context;
270 else 270
271 /* 271 /*
272 * Send a sigbus, regardless of whether we were in kernel 272 * Send a sigbus, regardless of whether we were in kernel
273 * or user mode. 273 * or user mode.
274 */ 274 */
275#if 0 275#if 0
276 printk("do_page_fault() #3: sending SIGBUS to %s for " 276 printk("do_page_fault() #3: sending SIGBUS to %s for "
277 "invalid %s\n%0*lx (epc == %0*lx, ra == %0*lx)\n", 277 "invalid %s\n%0*lx (epc == %0*lx, ra == %0*lx)\n",
278 tsk->comm, 278 tsk->comm,
279 write ? "write access to" : "read access from", 279 write ? "write access to" : "read access from",
280 field, address, 280 field, address,
281 field, (unsigned long) regs->cp0_epc, 281 field, (unsigned long) regs->cp0_epc,
282 field, (unsigned long) regs->regs[31]); 282 field, (unsigned long) regs->regs[31]);
283#endif 283#endif
284 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 284 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
285 tsk->thread.cp0_badvaddr = address; 285 tsk->thread.cp0_badvaddr = address;
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 3ca20283b31e..8ce2983a7015 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -537,6 +537,9 @@ unsigned long pgd_current[NR_CPUS];
537 * it in the linker script. 537 * it in the linker script.
538 */ 538 */
539pgd_t swapper_pg_dir[_PTRS_PER_PGD] __section(.bss..swapper_pg_dir); 539pgd_t swapper_pg_dir[_PTRS_PER_PGD] __section(.bss..swapper_pg_dir);
540#ifndef __PAGETABLE_PUD_FOLDED
541pud_t invalid_pud_table[PTRS_PER_PUD] __page_aligned_bss;
542#endif
540#ifndef __PAGETABLE_PMD_FOLDED 543#ifndef __PAGETABLE_PMD_FOLDED
541pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss; 544pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss;
542EXPORT_SYMBOL_GPL(invalid_pmd_table); 545EXPORT_SYMBOL_GPL(invalid_pmd_table);
diff --git a/arch/mips/mm/pgtable-64.c b/arch/mips/mm/pgtable-64.c
index 0ae7b28b4db5..6fd6e96fdebb 100644
--- a/arch/mips/mm/pgtable-64.c
+++ b/arch/mips/mm/pgtable-64.c
@@ -19,10 +19,12 @@ void pgd_init(unsigned long page)
19 unsigned long *p, *end; 19 unsigned long *p, *end;
20 unsigned long entry; 20 unsigned long entry;
21 21
22#ifdef __PAGETABLE_PMD_FOLDED 22#if !defined(__PAGETABLE_PUD_FOLDED)
23 entry = (unsigned long)invalid_pte_table; 23 entry = (unsigned long)invalid_pud_table;
24#else 24#elif !defined(__PAGETABLE_PMD_FOLDED)
25 entry = (unsigned long)invalid_pmd_table; 25 entry = (unsigned long)invalid_pmd_table;
26#else
27 entry = (unsigned long)invalid_pte_table;
26#endif 28#endif
27 29
28 p = (unsigned long *) page; 30 p = (unsigned long *) page;
@@ -64,6 +66,28 @@ void pmd_init(unsigned long addr, unsigned long pagetable)
64EXPORT_SYMBOL_GPL(pmd_init); 66EXPORT_SYMBOL_GPL(pmd_init);
65#endif 67#endif
66 68
69#ifndef __PAGETABLE_PUD_FOLDED
70void pud_init(unsigned long addr, unsigned long pagetable)
71{
72 unsigned long *p, *end;
73
74 p = (unsigned long *)addr;
75 end = p + PTRS_PER_PUD;
76
77 do {
78 p[0] = pagetable;
79 p[1] = pagetable;
80 p[2] = pagetable;
81 p[3] = pagetable;
82 p[4] = pagetable;
83 p += 8;
84 p[-3] = pagetable;
85 p[-2] = pagetable;
86 p[-1] = pagetable;
87 } while (p != end);
88}
89#endif
90
67pmd_t mk_pmd(struct page *page, pgprot_t prot) 91pmd_t mk_pmd(struct page *page, pgprot_t prot)
68{ 92{
69 pmd_t pmd; 93 pmd_t pmd;
@@ -87,6 +111,9 @@ void __init pagetable_init(void)
87 111
88 /* Initialize the entire pgd. */ 112 /* Initialize the entire pgd. */
89 pgd_init((unsigned long)swapper_pg_dir); 113 pgd_init((unsigned long)swapper_pg_dir);
114#ifndef __PAGETABLE_PUD_FOLDED
115 pud_init((unsigned long)invalid_pud_table, (unsigned long)invalid_pmd_table);
116#endif
90#ifndef __PAGETABLE_PMD_FOLDED 117#ifndef __PAGETABLE_PMD_FOLDED
91 pmd_init((unsigned long)invalid_pmd_table, (unsigned long)invalid_pte_table); 118 pmd_init((unsigned long)invalid_pmd_table, (unsigned long)invalid_pte_table);
92#endif 119#endif
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 4f642e07c2b1..ed1c5297547a 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -865,6 +865,13 @@ void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
865 865
866 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 866 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
867 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 867 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
868#ifndef __PAGETABLE_PUD_FOLDED
869 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
870 uasm_i_ld(p, ptr, 0, ptr); /* get pud pointer */
871 uasm_i_dsrl_safe(p, tmp, tmp, PUD_SHIFT - 3); /* get pud offset in bytes */
872 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PUD - 1) << 3);
873 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pud offset */
874#endif
868#ifndef __PAGETABLE_PMD_FOLDED 875#ifndef __PAGETABLE_PMD_FOLDED
869 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 876 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
870 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 877 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
@@ -1184,6 +1191,21 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1184 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ 1191 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
1185 } 1192 }
1186 1193
1194#ifndef __PAGETABLE_PUD_FOLDED
1195 /* get pud offset in bytes */
1196 uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3);
1197 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3);
1198
1199 if (use_lwx_insns()) {
1200 UASM_i_LWX(p, ptr, scratch, ptr);
1201 } else {
1202 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1203 UASM_i_LW(p, ptr, 0, ptr);
1204 }
1205 /* ptr contains a pointer to PMD entry */
1206 /* tmp contains the address */
1207#endif
1208
1187#ifndef __PAGETABLE_PMD_FOLDED 1209#ifndef __PAGETABLE_PMD_FOLDED
1188 /* get pmd offset in bytes */ 1210 /* get pmd offset in bytes */
1189 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); 1211 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c
index 763d3f1edb8a..2277499fe6ae 100644
--- a/arch/mips/mm/uasm-mips.c
+++ b/arch/mips/mm/uasm-mips.c
@@ -103,6 +103,7 @@ static struct insn insn_table[] = {
103 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 103 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
104 { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD }, 104 { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
105 { insn_lh, M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 105 { insn_lh, M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
106 { insn_lhu, M(lhu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
106#ifndef CONFIG_CPU_MIPSR6 107#ifndef CONFIG_CPU_MIPSR6
107 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 108 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
108 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 109 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index a82970442b8a..730363b59bac 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -61,7 +61,7 @@ enum opcode {
61 insn_sllv, insn_slt, insn_sltiu, insn_sltu, insn_sra, insn_srl, 61 insn_sllv, insn_slt, insn_sltiu, insn_sltu, insn_sra, insn_srl,
62 insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp, 62 insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp,
63 insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor, 63 insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor,
64 insn_xori, insn_yield, insn_lddir, insn_ldpte, 64 insn_xori, insn_yield, insn_lddir, insn_ldpte, insn_lhu,
65}; 65};
66 66
67struct insn { 67struct insn {
@@ -297,6 +297,7 @@ I_u1(_jr)
297I_u2s3u1(_lb) 297I_u2s3u1(_lb)
298I_u2s3u1(_ld) 298I_u2s3u1(_ld)
299I_u2s3u1(_lh) 299I_u2s3u1(_lh)
300I_u2s3u1(_lhu)
300I_u2s3u1(_ll) 301I_u2s3u1(_ll)
301I_u2s3u1(_lld) 302I_u2s3u1(_lld)
302I_u1s2(_lui) 303I_u1s2(_lui)
@@ -349,7 +350,7 @@ I_u2u1u3(_lddir)
349 350
350#ifdef CONFIG_CPU_CAVIUM_OCTEON 351#ifdef CONFIG_CPU_CAVIUM_OCTEON
351#include <asm/octeon/octeon.h> 352#include <asm/octeon/octeon.h>
352void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b, 353void uasm_i_pref(u32 **buf, unsigned int a, signed int b,
353 unsigned int c) 354 unsigned int c)
354{ 355{
355 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5) 356 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5)
@@ -361,26 +362,26 @@ void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
361 else 362 else
362 build_insn(buf, insn_pref, c, a, b); 363 build_insn(buf, insn_pref, c, a, b);
363} 364}
364UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref)); 365UASM_EXPORT_SYMBOL(uasm_i_pref);
365#else 366#else
366I_u2s3u1(_pref) 367I_u2s3u1(_pref)
367#endif 368#endif
368 369
369/* Handle labels. */ 370/* Handle labels. */
370void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid) 371void uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
371{ 372{
372 (*lab)->addr = addr; 373 (*lab)->addr = addr;
373 (*lab)->lab = lid; 374 (*lab)->lab = lid;
374 (*lab)++; 375 (*lab)++;
375} 376}
376UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label)); 377UASM_EXPORT_SYMBOL(uasm_build_label);
377 378
378int ISAFUNC(uasm_in_compat_space_p)(long addr) 379int uasm_in_compat_space_p(long addr)
379{ 380{
380 /* Is this address in 32bit compat space? */ 381 /* Is this address in 32bit compat space? */
381 return addr == (int)addr; 382 return addr == (int)addr;
382} 383}
383UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p)); 384UASM_EXPORT_SYMBOL(uasm_in_compat_space_p);
384 385
385static int uasm_rel_highest(long val) 386static int uasm_rel_highest(long val)
386{ 387{
@@ -400,64 +401,64 @@ static int uasm_rel_higher(long val)
400#endif 401#endif
401} 402}
402 403
403int ISAFUNC(uasm_rel_hi)(long val) 404int uasm_rel_hi(long val)
404{ 405{
405 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 406 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
406} 407}
407UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi)); 408UASM_EXPORT_SYMBOL(uasm_rel_hi);
408 409
409int ISAFUNC(uasm_rel_lo)(long val) 410int uasm_rel_lo(long val)
410{ 411{
411 return ((val & 0xffff) ^ 0x8000) - 0x8000; 412 return ((val & 0xffff) ^ 0x8000) - 0x8000;
412} 413}
413UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo)); 414UASM_EXPORT_SYMBOL(uasm_rel_lo);
414 415
415void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr) 416void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
416{ 417{
417 if (!ISAFUNC(uasm_in_compat_space_p)(addr)) { 418 if (!uasm_in_compat_space_p(addr)) {
418 ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr)); 419 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
419 if (uasm_rel_higher(addr)) 420 if (uasm_rel_higher(addr))
420 ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr)); 421 uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
421 if (ISAFUNC(uasm_rel_hi(addr))) { 422 if (uasm_rel_hi(addr)) {
422 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16); 423 uasm_i_dsll(buf, rs, rs, 16);
423 ISAFUNC(uasm_i_daddiu)(buf, rs, rs, 424 uasm_i_daddiu(buf, rs, rs,
424 ISAFUNC(uasm_rel_hi)(addr)); 425 uasm_rel_hi(addr));
425 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16); 426 uasm_i_dsll(buf, rs, rs, 16);
426 } else 427 } else
427 ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0); 428 uasm_i_dsll32(buf, rs, rs, 0);
428 } else 429 } else
429 ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr))); 430 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
430} 431}
431UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly)); 432UASM_EXPORT_SYMBOL(UASM_i_LA_mostly);
432 433
433void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr) 434void UASM_i_LA(u32 **buf, unsigned int rs, long addr)
434{ 435{
435 ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr); 436 UASM_i_LA_mostly(buf, rs, addr);
436 if (ISAFUNC(uasm_rel_lo(addr))) { 437 if (uasm_rel_lo(addr)) {
437 if (!ISAFUNC(uasm_in_compat_space_p)(addr)) 438 if (!uasm_in_compat_space_p(addr))
438 ISAFUNC(uasm_i_daddiu)(buf, rs, rs, 439 uasm_i_daddiu(buf, rs, rs,
439 ISAFUNC(uasm_rel_lo(addr))); 440 uasm_rel_lo(addr));
440 else 441 else
441 ISAFUNC(uasm_i_addiu)(buf, rs, rs, 442 uasm_i_addiu(buf, rs, rs,
442 ISAFUNC(uasm_rel_lo(addr))); 443 uasm_rel_lo(addr));
443 } 444 }
444} 445}
445UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA)); 446UASM_EXPORT_SYMBOL(UASM_i_LA);
446 447
447/* Handle relocations. */ 448/* Handle relocations. */
448void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid) 449void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
449{ 450{
450 (*rel)->addr = addr; 451 (*rel)->addr = addr;
451 (*rel)->type = R_MIPS_PC16; 452 (*rel)->type = R_MIPS_PC16;
452 (*rel)->lab = lid; 453 (*rel)->lab = lid;
453 (*rel)++; 454 (*rel)++;
454} 455}
455UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16)); 456UASM_EXPORT_SYMBOL(uasm_r_mips_pc16);
456 457
457static inline void __resolve_relocs(struct uasm_reloc *rel, 458static inline void __resolve_relocs(struct uasm_reloc *rel,
458 struct uasm_label *lab); 459 struct uasm_label *lab);
459 460
460void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel, 461void uasm_resolve_relocs(struct uasm_reloc *rel,
461 struct uasm_label *lab) 462 struct uasm_label *lab)
462{ 463{
463 struct uasm_label *l; 464 struct uasm_label *l;
@@ -467,39 +468,39 @@ void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
467 if (rel->lab == l->lab) 468 if (rel->lab == l->lab)
468 __resolve_relocs(rel, l); 469 __resolve_relocs(rel, l);
469} 470}
470UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs)); 471UASM_EXPORT_SYMBOL(uasm_resolve_relocs);
471 472
472void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end, 473void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end,
473 long off) 474 long off)
474{ 475{
475 for (; rel->lab != UASM_LABEL_INVALID; rel++) 476 for (; rel->lab != UASM_LABEL_INVALID; rel++)
476 if (rel->addr >= first && rel->addr < end) 477 if (rel->addr >= first && rel->addr < end)
477 rel->addr += off; 478 rel->addr += off;
478} 479}
479UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs)); 480UASM_EXPORT_SYMBOL(uasm_move_relocs);
480 481
481void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end, 482void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end,
482 long off) 483 long off)
483{ 484{
484 for (; lab->lab != UASM_LABEL_INVALID; lab++) 485 for (; lab->lab != UASM_LABEL_INVALID; lab++)
485 if (lab->addr >= first && lab->addr < end) 486 if (lab->addr >= first && lab->addr < end)
486 lab->addr += off; 487 lab->addr += off;
487} 488}
488UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels)); 489UASM_EXPORT_SYMBOL(uasm_move_labels);
489 490
490void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab, 491void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab,
491 u32 *first, u32 *end, u32 *target) 492 u32 *first, u32 *end, u32 *target)
492{ 493{
493 long off = (long)(target - first); 494 long off = (long)(target - first);
494 495
495 memcpy(target, first, (end - first) * sizeof(u32)); 496 memcpy(target, first, (end - first) * sizeof(u32));
496 497
497 ISAFUNC(uasm_move_relocs(rel, first, end, off)); 498 uasm_move_relocs(rel, first, end, off);
498 ISAFUNC(uasm_move_labels(lab, first, end, off)); 499 uasm_move_labels(lab, first, end, off);
499} 500}
500UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler)); 501UASM_EXPORT_SYMBOL(uasm_copy_handler);
501 502
502int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr) 503int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
503{ 504{
504 for (; rel->lab != UASM_LABEL_INVALID; rel++) { 505 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
505 if (rel->addr == addr 506 if (rel->addr == addr
@@ -510,92 +511,92 @@ int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr)
510 511
511 return 0; 512 return 0;
512} 513}
513UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay)); 514UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay);
514 515
515/* Convenience functions for labeled branches. */ 516/* Convenience functions for labeled branches. */
516void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg, 517void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg,
517 int lid) 518 int lid)
518{ 519{
519 uasm_r_mips_pc16(r, *p, lid); 520 uasm_r_mips_pc16(r, *p, lid);
520 ISAFUNC(uasm_i_bltz)(p, reg, 0); 521 uasm_i_bltz(p, reg, 0);
521} 522}
522UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz)); 523UASM_EXPORT_SYMBOL(uasm_il_bltz);
523 524
524void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid) 525void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
525{ 526{
526 uasm_r_mips_pc16(r, *p, lid); 527 uasm_r_mips_pc16(r, *p, lid);
527 ISAFUNC(uasm_i_b)(p, 0); 528 uasm_i_b(p, 0);
528} 529}
529UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b)); 530UASM_EXPORT_SYMBOL(uasm_il_b);
530 531
531void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1, 532void uasm_il_beq(u32 **p, struct uasm_reloc **r, unsigned int r1,
532 unsigned int r2, int lid) 533 unsigned int r2, int lid)
533{ 534{
534 uasm_r_mips_pc16(r, *p, lid); 535 uasm_r_mips_pc16(r, *p, lid);
535 ISAFUNC(uasm_i_beq)(p, r1, r2, 0); 536 uasm_i_beq(p, r1, r2, 0);
536} 537}
537UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq)); 538UASM_EXPORT_SYMBOL(uasm_il_beq);
538 539
539void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg, 540void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg,
540 int lid) 541 int lid)
541{ 542{
542 uasm_r_mips_pc16(r, *p, lid); 543 uasm_r_mips_pc16(r, *p, lid);
543 ISAFUNC(uasm_i_beqz)(p, reg, 0); 544 uasm_i_beqz(p, reg, 0);
544} 545}
545UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz)); 546UASM_EXPORT_SYMBOL(uasm_il_beqz);
546 547
547void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg, 548void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg,
548 int lid) 549 int lid)
549{ 550{
550 uasm_r_mips_pc16(r, *p, lid); 551 uasm_r_mips_pc16(r, *p, lid);
551 ISAFUNC(uasm_i_beqzl)(p, reg, 0); 552 uasm_i_beqzl(p, reg, 0);
552} 553}
553UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl)); 554UASM_EXPORT_SYMBOL(uasm_il_beqzl);
554 555
555void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1, 556void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
556 unsigned int reg2, int lid) 557 unsigned int reg2, int lid)
557{ 558{
558 uasm_r_mips_pc16(r, *p, lid); 559 uasm_r_mips_pc16(r, *p, lid);
559 ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0); 560 uasm_i_bne(p, reg1, reg2, 0);
560} 561}
561UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne)); 562UASM_EXPORT_SYMBOL(uasm_il_bne);
562 563
563void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg, 564void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg,
564 int lid) 565 int lid)
565{ 566{
566 uasm_r_mips_pc16(r, *p, lid); 567 uasm_r_mips_pc16(r, *p, lid);
567 ISAFUNC(uasm_i_bnez)(p, reg, 0); 568 uasm_i_bnez(p, reg, 0);
568} 569}
569UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez)); 570UASM_EXPORT_SYMBOL(uasm_il_bnez);
570 571
571void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg, 572void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg,
572 int lid) 573 int lid)
573{ 574{
574 uasm_r_mips_pc16(r, *p, lid); 575 uasm_r_mips_pc16(r, *p, lid);
575 ISAFUNC(uasm_i_bgezl)(p, reg, 0); 576 uasm_i_bgezl(p, reg, 0);
576} 577}
577UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl)); 578UASM_EXPORT_SYMBOL(uasm_il_bgezl);
578 579
579void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg, 580void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg,
580 int lid) 581 int lid)
581{ 582{
582 uasm_r_mips_pc16(r, *p, lid); 583 uasm_r_mips_pc16(r, *p, lid);
583 ISAFUNC(uasm_i_bgez)(p, reg, 0); 584 uasm_i_bgez(p, reg, 0);
584} 585}
585UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez)); 586UASM_EXPORT_SYMBOL(uasm_il_bgez);
586 587
587void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg, 588void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
588 unsigned int bit, int lid) 589 unsigned int bit, int lid)
589{ 590{
590 uasm_r_mips_pc16(r, *p, lid); 591 uasm_r_mips_pc16(r, *p, lid);
591 ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0); 592 uasm_i_bbit0(p, reg, bit, 0);
592} 593}
593UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0)); 594UASM_EXPORT_SYMBOL(uasm_il_bbit0);
594 595
595void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg, 596void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
596 unsigned int bit, int lid) 597 unsigned int bit, int lid)
597{ 598{
598 uasm_r_mips_pc16(r, *p, lid); 599 uasm_r_mips_pc16(r, *p, lid);
599 ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0); 600 uasm_i_bbit1(p, reg, bit, 0);
600} 601}
601UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1)); 602UASM_EXPORT_SYMBOL(uasm_il_bbit1);
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 54f56d5a96c4..b0f9b188e833 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -145,56 +145,6 @@ static irqreturn_t corehi_handler(int irq, void *dev_id)
145 return IRQ_HANDLED; 145 return IRQ_HANDLED;
146} 146}
147 147
148#ifdef CONFIG_MIPS_MT_SMP
149
150#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
151#define C_RESCHED C_SW0
152#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */
153#define C_CALL C_SW1
154static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
155
156static void ipi_resched_dispatch(void)
157{
158 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
159}
160
161static void ipi_call_dispatch(void)
162{
163 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
164}
165
166static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
167{
168#ifdef CONFIG_MIPS_VPE_APSP_API_CMP
169 if (aprp_hook)
170 aprp_hook();
171#endif
172
173 scheduler_ipi();
174
175 return IRQ_HANDLED;
176}
177
178static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
179{
180 generic_smp_call_function_interrupt();
181
182 return IRQ_HANDLED;
183}
184
185static struct irqaction irq_resched = {
186 .handler = ipi_resched_interrupt,
187 .flags = IRQF_PERCPU,
188 .name = "IPI_resched"
189};
190
191static struct irqaction irq_call = {
192 .handler = ipi_call_interrupt,
193 .flags = IRQF_PERCPU,
194 .name = "IPI_call"
195};
196#endif /* CONFIG_MIPS_MT_SMP */
197
198static struct irqaction corehi_irqaction = { 148static struct irqaction corehi_irqaction = {
199 .handler = corehi_handler, 149 .handler = corehi_handler,
200 .name = "CoreHi", 150 .name = "CoreHi",
@@ -222,12 +172,6 @@ static msc_irqmap_t msc_eicirqmap[] __initdata = {
222 172
223static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap); 173static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap);
224 174
225void __init arch_init_ipiirq(int irq, struct irqaction *action)
226{
227 setup_irq(irq, action);
228 irq_set_handler(irq, handle_percpu_irq);
229}
230
231void __init arch_init_irq(void) 175void __init arch_init_irq(void)
232{ 176{
233 int corehi_irq; 177 int corehi_irq;
@@ -273,30 +217,11 @@ void __init arch_init_irq(void)
273 217
274 if (gic_present) { 218 if (gic_present) {
275 corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; 219 corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
220 } else if (cpu_has_veic) {
221 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
222 corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
276 } else { 223 } else {
277#if defined(CONFIG_MIPS_MT_SMP) 224 corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
278 /* set up ipi interrupts */
279 if (cpu_has_veic) {
280 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
281 set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
282 cpu_ipi_resched_irq = MSC01E_INT_SW0;
283 cpu_ipi_call_irq = MSC01E_INT_SW1;
284 } else {
285 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE +
286 MIPS_CPU_IPI_RESCHED_IRQ;
287 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE +
288 MIPS_CPU_IPI_CALL_IRQ;
289 }
290 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
291 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
292#endif
293 if (cpu_has_veic) {
294 set_vi_handler(MSC01E_INT_COREHI,
295 corehi_irqdispatch);
296 corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
297 } else {
298 corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
299 }
300 } 225 }
301 226
302 setup_irq(corehi_irq, &corehi_irqaction); 227 setup_irq(corehi_irq, &corehi_irqaction);
diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c
index 49a2e2226fee..44b925005dd3 100644
--- a/arch/mips/net/bpf_jit.c
+++ b/arch/mips/net/bpf_jit.c
@@ -365,6 +365,12 @@ static inline void emit_half_load(unsigned int reg, unsigned int base,
365 emit_instr(ctx, lh, reg, offset, base); 365 emit_instr(ctx, lh, reg, offset, base);
366} 366}
367 367
368static inline void emit_half_load_unsigned(unsigned int reg, unsigned int base,
369 unsigned int offset, struct jit_ctx *ctx)
370{
371 emit_instr(ctx, lhu, reg, offset, base);
372}
373
368static inline void emit_mul(unsigned int dst, unsigned int src1, 374static inline void emit_mul(unsigned int dst, unsigned int src1,
369 unsigned int src2, struct jit_ctx *ctx) 375 unsigned int src2, struct jit_ctx *ctx)
370{ 376{
@@ -526,7 +532,8 @@ static void save_bpf_jit_regs(struct jit_ctx *ctx, unsigned offset)
526 u32 sflags, tmp_flags; 532 u32 sflags, tmp_flags;
527 533
528 /* Adjust the stack pointer */ 534 /* Adjust the stack pointer */
529 emit_stack_offset(-align_sp(offset), ctx); 535 if (offset)
536 emit_stack_offset(-align_sp(offset), ctx);
530 537
531 tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT; 538 tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT;
532 /* sflags is essentially a bitmap */ 539 /* sflags is essentially a bitmap */
@@ -578,7 +585,8 @@ static void restore_bpf_jit_regs(struct jit_ctx *ctx,
578 emit_load_stack_reg(r_ra, r_sp, real_off, ctx); 585 emit_load_stack_reg(r_ra, r_sp, real_off, ctx);
579 586
580 /* Restore the sp and discard the scrach memory */ 587 /* Restore the sp and discard the scrach memory */
581 emit_stack_offset(align_sp(offset), ctx); 588 if (offset)
589 emit_stack_offset(align_sp(offset), ctx);
582} 590}
583 591
584static unsigned int get_stack_depth(struct jit_ctx *ctx) 592static unsigned int get_stack_depth(struct jit_ctx *ctx)
@@ -625,8 +633,14 @@ static void build_prologue(struct jit_ctx *ctx)
625 if (ctx->flags & SEEN_X) 633 if (ctx->flags & SEEN_X)
626 emit_jit_reg_move(r_X, r_zero, ctx); 634 emit_jit_reg_move(r_X, r_zero, ctx);
627 635
628 /* Do not leak kernel data to userspace */ 636 /*
629 if (bpf_needs_clear_a(&ctx->skf->insns[0])) 637 * Do not leak kernel data to userspace, we only need to clear
638 * r_A if it is ever used. In fact if it is never used, we
639 * will not save/restore it, so clearing it in this case would
640 * corrupt the state of the caller.
641 */
642 if (bpf_needs_clear_a(&ctx->skf->insns[0]) &&
643 (ctx->flags & SEEN_A))
630 emit_jit_reg_move(r_A, r_zero, ctx); 644 emit_jit_reg_move(r_A, r_zero, ctx);
631} 645}
632 646
@@ -1112,6 +1126,8 @@ jmp_cmp:
1112 break; 1126 break;
1113 case BPF_ANC | SKF_AD_IFINDEX: 1127 case BPF_ANC | SKF_AD_IFINDEX:
1114 /* A = skb->dev->ifindex */ 1128 /* A = skb->dev->ifindex */
1129 case BPF_ANC | SKF_AD_HATYPE:
1130 /* A = skb->dev->type */
1115 ctx->flags |= SEEN_SKB | SEEN_A; 1131 ctx->flags |= SEEN_SKB | SEEN_A;
1116 off = offsetof(struct sk_buff, dev); 1132 off = offsetof(struct sk_buff, dev);
1117 /* Load *dev pointer */ 1133 /* Load *dev pointer */
@@ -1120,10 +1136,15 @@ jmp_cmp:
1120 emit_bcond(MIPS_COND_EQ, r_s0, r_zero, 1136 emit_bcond(MIPS_COND_EQ, r_s0, r_zero,
1121 b_imm(prog->len, ctx), ctx); 1137 b_imm(prog->len, ctx), ctx);
1122 emit_reg_move(r_ret, r_zero, ctx); 1138 emit_reg_move(r_ret, r_zero, ctx);
1123 BUILD_BUG_ON(FIELD_SIZEOF(struct net_device, 1139 if (code == (BPF_ANC | SKF_AD_IFINDEX)) {
1124 ifindex) != 4); 1140 BUILD_BUG_ON(FIELD_SIZEOF(struct net_device, ifindex) != 4);
1125 off = offsetof(struct net_device, ifindex); 1141 off = offsetof(struct net_device, ifindex);
1126 emit_load(r_A, r_s0, off, ctx); 1142 emit_load(r_A, r_s0, off, ctx);
1143 } else { /* (code == (BPF_ANC | SKF_AD_HATYPE) */
1144 BUILD_BUG_ON(FIELD_SIZEOF(struct net_device, type) != 2);
1145 off = offsetof(struct net_device, type);
1146 emit_half_load_unsigned(r_A, r_s0, off, ctx);
1147 }
1127 break; 1148 break;
1128 case BPF_ANC | SKF_AD_MARK: 1149 case BPF_ANC | SKF_AD_MARK:
1129 ctx->flags |= SEEN_SKB | SEEN_A; 1150 ctx->flags |= SEEN_SKB | SEEN_A;
@@ -1143,7 +1164,7 @@ jmp_cmp:
1143 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, 1164 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
1144 vlan_tci) != 2); 1165 vlan_tci) != 2);
1145 off = offsetof(struct sk_buff, vlan_tci); 1166 off = offsetof(struct sk_buff, vlan_tci);
1146 emit_half_load(r_s0, r_skb, off, ctx); 1167 emit_half_load_unsigned(r_s0, r_skb, off, ctx);
1147 if (code == (BPF_ANC | SKF_AD_VLAN_TAG)) { 1168 if (code == (BPF_ANC | SKF_AD_VLAN_TAG)) {
1148 emit_andi(r_A, r_s0, (u16)~VLAN_TAG_PRESENT, ctx); 1169 emit_andi(r_A, r_s0, (u16)~VLAN_TAG_PRESENT, ctx);
1149 } else { 1170 } else {
@@ -1170,7 +1191,7 @@ jmp_cmp:
1170 BUILD_BUG_ON(offsetof(struct sk_buff, 1191 BUILD_BUG_ON(offsetof(struct sk_buff,
1171 queue_mapping) > 0xff); 1192 queue_mapping) > 0xff);
1172 off = offsetof(struct sk_buff, queue_mapping); 1193 off = offsetof(struct sk_buff, queue_mapping);
1173 emit_half_load(r_A, r_skb, off, ctx); 1194 emit_half_load_unsigned(r_A, r_skb, off, ctx);
1174 break; 1195 break;
1175 default: 1196 default:
1176 pr_debug("%s: Unhandled opcode: 0x%02x\n", __FILE__, 1197 pr_debug("%s: Unhandled opcode: 0x%02x\n", __FILE__,
diff --git a/arch/mips/net/bpf_jit_asm.S b/arch/mips/net/bpf_jit_asm.S
index 5d2e0c8d29c0..88a2075305d1 100644
--- a/arch/mips/net/bpf_jit_asm.S
+++ b/arch/mips/net/bpf_jit_asm.S
@@ -90,18 +90,14 @@ FEXPORT(sk_load_half_positive)
90 is_offset_in_header(2, half) 90 is_offset_in_header(2, half)
91 /* Offset within header boundaries */ 91 /* Offset within header boundaries */
92 PTR_ADDU t1, $r_skb_data, offset 92 PTR_ADDU t1, $r_skb_data, offset
93 .set reorder 93 lhu $r_A, 0(t1)
94 lh $r_A, 0(t1)
95 .set noreorder
96#ifdef CONFIG_CPU_LITTLE_ENDIAN 94#ifdef CONFIG_CPU_LITTLE_ENDIAN
97# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) 95# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
98 wsbh t0, $r_A 96 wsbh $r_A, $r_A
99 seh $r_A, t0
100# else 97# else
101 sll t0, $r_A, 24 98 sll t0, $r_A, 8
102 andi t1, $r_A, 0xff00 99 srl t1, $r_A, 8
103 sra t0, t0, 16 100 andi t0, t0, 0xff00
104 srl t1, t1, 8
105 or $r_A, t0, t1 101 or $r_A, t0, t1
106# endif 102# endif
107#endif 103#endif
@@ -115,7 +111,7 @@ FEXPORT(sk_load_byte_positive)
115 is_offset_in_header(1, byte) 111 is_offset_in_header(1, byte)
116 /* Offset within header boundaries */ 112 /* Offset within header boundaries */
117 PTR_ADDU t1, $r_skb_data, offset 113 PTR_ADDU t1, $r_skb_data, offset
118 lb $r_A, 0(t1) 114 lbu $r_A, 0(t1)
119 jr $r_ra 115 jr $r_ra
120 move $r_ret, zero 116 move $r_ret, zero
121 END(sk_load_byte) 117 END(sk_load_byte)
@@ -139,6 +135,11 @@ FEXPORT(sk_load_byte_positive)
139 * (void *to) is returned in r_s0 135 * (void *to) is returned in r_s0
140 * 136 *
141 */ 137 */
138#ifdef CONFIG_CPU_LITTLE_ENDIAN
139#define DS_OFFSET(SIZE) (4 * SZREG)
140#else
141#define DS_OFFSET(SIZE) ((4 * SZREG) + (4 - SIZE))
142#endif
142#define bpf_slow_path_common(SIZE) \ 143#define bpf_slow_path_common(SIZE) \
143 /* Quick check. Are we within reasonable boundaries? */ \ 144 /* Quick check. Are we within reasonable boundaries? */ \
144 LONG_ADDIU $r_s1, $r_skb_len, -SIZE; \ 145 LONG_ADDIU $r_s1, $r_skb_len, -SIZE; \
@@ -150,7 +151,7 @@ FEXPORT(sk_load_byte_positive)
150 PTR_LA t0, skb_copy_bits; \ 151 PTR_LA t0, skb_copy_bits; \
151 PTR_S $r_ra, (5 * SZREG)($r_sp); \ 152 PTR_S $r_ra, (5 * SZREG)($r_sp); \
152 /* Assign low slot to a2 */ \ 153 /* Assign low slot to a2 */ \
153 move a2, $r_sp; \ 154 PTR_ADDIU a2, $r_sp, DS_OFFSET(SIZE); \
154 jalr t0; \ 155 jalr t0; \
155 /* Reset our destination slot (DS but it's ok) */ \ 156 /* Reset our destination slot (DS but it's ok) */ \
156 INT_S zero, (4 * SZREG)($r_sp); \ 157 INT_S zero, (4 * SZREG)($r_sp); \
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index 9f672ceb089b..ad3584dbc9d7 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -679,7 +679,7 @@ static void __cvmx_increment_ba(union cvmx_sli_mem_access_subidx *pmas)
679 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 679 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
680 pmas->cn68xx.ba++; 680 pmas->cn68xx.ba++;
681 else 681 else
682 pmas->cn63xx.ba++; 682 pmas->s.ba++;
683} 683}
684 684
685/** 685/**
@@ -1351,7 +1351,7 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
1351 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 1351 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
1352 mem_access_subid.cn68xx.ba = 0; 1352 mem_access_subid.cn68xx.ba = 0;
1353 else 1353 else
1354 mem_access_subid.cn63xx.ba = 0; 1354 mem_access_subid.s.ba = 0;
1355 1355
1356 /* 1356 /*
1357 * Setup mem access 12-15 for port 0, 16-19 for port 1, 1357 * Setup mem access 12-15 for port 0, 16-19 for port 1,
diff --git a/arch/mips/sibyte/bcm1480/setup.c b/arch/mips/sibyte/bcm1480/setup.c
index a05246cbf54c..2035aaec8514 100644
--- a/arch/mips/sibyte/bcm1480/setup.c
+++ b/arch/mips/sibyte/bcm1480/setup.c
@@ -36,6 +36,7 @@ unsigned int soc_pass;
36unsigned int soc_type; 36unsigned int soc_type;
37EXPORT_SYMBOL(soc_type); 37EXPORT_SYMBOL(soc_type);
38unsigned int periph_rev; 38unsigned int periph_rev;
39EXPORT_SYMBOL_GPL(periph_rev);
39unsigned int zbbus_mhz; 40unsigned int zbbus_mhz;
40EXPORT_SYMBOL(zbbus_mhz); 41EXPORT_SYMBOL(zbbus_mhz);
41 42
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
index 90e43782342b..aa7713adfa58 100644
--- a/arch/mips/sibyte/sb1250/setup.c
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -34,6 +34,7 @@ unsigned int soc_pass;
34unsigned int soc_type; 34unsigned int soc_type;
35EXPORT_SYMBOL(soc_type); 35EXPORT_SYMBOL(soc_type);
36unsigned int periph_rev; 36unsigned int periph_rev;
37EXPORT_SYMBOL_GPL(periph_rev);
37unsigned int zbbus_mhz; 38unsigned int zbbus_mhz;
38EXPORT_SYMBOL(zbbus_mhz); 39EXPORT_SYMBOL(zbbus_mhz);
39 40
diff --git a/drivers/cpufreq/loongson2_cpufreq.c b/drivers/cpufreq/loongson2_cpufreq.c
index 6bbdac1065ff..9ac27b22476c 100644
--- a/drivers/cpufreq/loongson2_cpufreq.c
+++ b/drivers/cpufreq/loongson2_cpufreq.c
@@ -51,19 +51,12 @@ static int loongson2_cpu_freq_notifier(struct notifier_block *nb,
51static int loongson2_cpufreq_target(struct cpufreq_policy *policy, 51static int loongson2_cpufreq_target(struct cpufreq_policy *policy,
52 unsigned int index) 52 unsigned int index)
53{ 53{
54 unsigned int cpu = policy->cpu;
55 cpumask_t cpus_allowed;
56 unsigned int freq; 54 unsigned int freq;
57 55
58 cpus_allowed = current->cpus_allowed;
59 set_cpus_allowed_ptr(current, cpumask_of(cpu));
60
61 freq = 56 freq =
62 ((cpu_clock_freq / 1000) * 57 ((cpu_clock_freq / 1000) *
63 loongson2_clockmod_table[index].driver_data) / 8; 58 loongson2_clockmod_table[index].driver_data) / 8;
64 59
65 set_cpus_allowed_ptr(current, &cpus_allowed);
66
67 /* setting the cpu frequency */ 60 /* setting the cpu frequency */
68 clk_set_rate(policy->clk, freq * 1000); 61 clk_set_rate(policy->clk, freq * 1000);
69 62
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 595d0c95563b..478f8ace2664 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -134,7 +134,9 @@ config IMGPDC_IRQ
134config IRQ_MIPS_CPU 134config IRQ_MIPS_CPU
135 bool 135 bool
136 select GENERIC_IRQ_CHIP 136 select GENERIC_IRQ_CHIP
137 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
137 select IRQ_DOMAIN 138 select IRQ_DOMAIN
139 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
138 140
139config CLPS711X_IRQCHIP 141config CLPS711X_IRQCHIP
140 bool 142 bool
diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 8c504f562e9d..b247f3c743ac 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -17,15 +17,14 @@
17/* 17/*
18 * Almost all MIPS CPUs define 8 interrupt sources. They are typically 18 * Almost all MIPS CPUs define 8 interrupt sources. They are typically
19 * level triggered (i.e., cannot be cleared from CPU; must be cleared from 19 * level triggered (i.e., cannot be cleared from CPU; must be cleared from
20 * device). The first two are software interrupts which we don't really 20 * device).
21 * use or support. The last one is usually the CPU timer interrupt if
22 * counter register is present or, for CPUs with an external FPU, by
23 * convention it's the FPU exception interrupt.
24 * 21 *
25 * Don't even think about using this on SMP. You have been warned. 22 * The first two are software interrupts (i.e. not exposed as pins) which
23 * may be used for IPIs in multi-threaded single-core systems.
26 * 24 *
27 * This file exports one global function: 25 * The last one is usually the CPU timer interrupt if the counter register
28 * void mips_cpu_irq_init(void); 26 * is present, or for old CPUs with an external FPU by convention it's the
27 * FPU exception interrupt.
29 */ 28 */
30#include <linux/init.h> 29#include <linux/init.h>
31#include <linux/interrupt.h> 30#include <linux/interrupt.h>
@@ -39,15 +38,18 @@
39#include <asm/mipsmtregs.h> 38#include <asm/mipsmtregs.h>
40#include <asm/setup.h> 39#include <asm/setup.h>
41 40
41static struct irq_domain *irq_domain;
42static struct irq_domain *ipi_domain;
43
42static inline void unmask_mips_irq(struct irq_data *d) 44static inline void unmask_mips_irq(struct irq_data *d)
43{ 45{
44 set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 46 set_c0_status(IE_SW0 << d->hwirq);
45 irq_enable_hazard(); 47 irq_enable_hazard();
46} 48}
47 49
48static inline void mask_mips_irq(struct irq_data *d) 50static inline void mask_mips_irq(struct irq_data *d)
49{ 51{
50 clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 52 clear_c0_status(IE_SW0 << d->hwirq);
51 irq_disable_hazard(); 53 irq_disable_hazard();
52} 54}
53 55
@@ -70,7 +72,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
70{ 72{
71 unsigned int vpflags = dvpe(); 73 unsigned int vpflags = dvpe();
72 74
73 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 75 clear_c0_cause(C_SW0 << d->hwirq);
74 evpe(vpflags); 76 evpe(vpflags);
75 unmask_mips_irq(d); 77 unmask_mips_irq(d);
76 return 0; 78 return 0;
@@ -83,11 +85,34 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
83static void mips_mt_cpu_irq_ack(struct irq_data *d) 85static void mips_mt_cpu_irq_ack(struct irq_data *d)
84{ 86{
85 unsigned int vpflags = dvpe(); 87 unsigned int vpflags = dvpe();
86 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 88 clear_c0_cause(C_SW0 << d->hwirq);
87 evpe(vpflags); 89 evpe(vpflags);
88 mask_mips_irq(d); 90 mask_mips_irq(d);
89} 91}
90 92
93#ifdef CONFIG_GENERIC_IRQ_IPI
94
95static void mips_mt_send_ipi(struct irq_data *d, unsigned int cpu)
96{
97 irq_hw_number_t hwirq = irqd_to_hwirq(d);
98 unsigned long flags;
99 int vpflags;
100
101 local_irq_save(flags);
102
103 /* We can only send IPIs to VPEs within the local core */
104 WARN_ON(cpu_data[cpu].core != current_cpu_data.core);
105
106 vpflags = dvpe();
107 settc(cpu_vpe_id(&cpu_data[cpu]));
108 write_vpe_c0_cause(read_vpe_c0_cause() | (C_SW0 << hwirq));
109 evpe(vpflags);
110
111 local_irq_restore(flags);
112}
113
114#endif /* CONFIG_GENERIC_IRQ_IPI */
115
91static struct irq_chip mips_mt_cpu_irq_controller = { 116static struct irq_chip mips_mt_cpu_irq_controller = {
92 .name = "MIPS", 117 .name = "MIPS",
93 .irq_startup = mips_mt_cpu_irq_startup, 118 .irq_startup = mips_mt_cpu_irq_startup,
@@ -98,11 +123,15 @@ static struct irq_chip mips_mt_cpu_irq_controller = {
98 .irq_eoi = unmask_mips_irq, 123 .irq_eoi = unmask_mips_irq,
99 .irq_disable = mask_mips_irq, 124 .irq_disable = mask_mips_irq,
100 .irq_enable = unmask_mips_irq, 125 .irq_enable = unmask_mips_irq,
126#ifdef CONFIG_GENERIC_IRQ_IPI
127 .ipi_send_single = mips_mt_send_ipi,
128#endif
101}; 129};
102 130
103asmlinkage void __weak plat_irq_dispatch(void) 131asmlinkage void __weak plat_irq_dispatch(void)
104{ 132{
105 unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM; 133 unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM;
134 unsigned int virq;
106 int irq; 135 int irq;
107 136
108 if (!pending) { 137 if (!pending) {
@@ -113,7 +142,11 @@ asmlinkage void __weak plat_irq_dispatch(void)
113 pending >>= CAUSEB_IP; 142 pending >>= CAUSEB_IP;
114 while (pending) { 143 while (pending) {
115 irq = fls(pending) - 1; 144 irq = fls(pending) - 1;
116 do_IRQ(MIPS_CPU_IRQ_BASE + irq); 145 if (IS_ENABLED(CONFIG_GENERIC_IRQ_IPI) && irq < 2)
146 virq = irq_linear_revmap(ipi_domain, irq);
147 else
148 virq = irq_linear_revmap(irq_domain, irq);
149 do_IRQ(virq);
117 pending &= ~BIT(irq); 150 pending &= ~BIT(irq);
118 } 151 }
119} 152}
@@ -143,18 +176,97 @@ static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
143 .xlate = irq_domain_xlate_onecell, 176 .xlate = irq_domain_xlate_onecell,
144}; 177};
145 178
146static void __init __mips_cpu_irq_init(struct device_node *of_node) 179#ifdef CONFIG_GENERIC_IRQ_IPI
180
181struct cpu_ipi_domain_state {
182 DECLARE_BITMAP(allocated, 2);
183};
184
185static int mips_cpu_ipi_alloc(struct irq_domain *domain, unsigned int virq,
186 unsigned int nr_irqs, void *arg)
147{ 187{
148 struct irq_domain *domain; 188 struct cpu_ipi_domain_state *state = domain->host_data;
189 unsigned int i, hwirq;
190 int ret;
149 191
192 for (i = 0; i < nr_irqs; i++) {
193 hwirq = find_first_zero_bit(state->allocated, 2);
194 if (hwirq == 2)
195 return -EBUSY;
196 bitmap_set(state->allocated, hwirq, 1);
197
198 ret = irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq,
199 &mips_mt_cpu_irq_controller,
200 NULL);
201 if (ret)
202 return ret;
203
204 ret = irq_set_irq_type(virq + i, IRQ_TYPE_LEVEL_HIGH);
205 if (ret)
206 return ret;
207 }
208
209 return 0;
210}
211
212static int mips_cpu_ipi_match(struct irq_domain *d, struct device_node *node,
213 enum irq_domain_bus_token bus_token)
214{
215 bool is_ipi;
216
217 switch (bus_token) {
218 case DOMAIN_BUS_IPI:
219 is_ipi = d->bus_token == bus_token;
220 return (!node || (to_of_node(d->fwnode) == node)) && is_ipi;
221 default:
222 return 0;
223 }
224}
225
226static const struct irq_domain_ops mips_cpu_ipi_chip_ops = {
227 .alloc = mips_cpu_ipi_alloc,
228 .match = mips_cpu_ipi_match,
229};
230
231static void mips_cpu_register_ipi_domain(struct device_node *of_node)
232{
233 struct cpu_ipi_domain_state *ipi_domain_state;
234
235 ipi_domain_state = kzalloc(sizeof(*ipi_domain_state), GFP_KERNEL);
236 ipi_domain = irq_domain_add_hierarchy(irq_domain,
237 IRQ_DOMAIN_FLAG_IPI_SINGLE,
238 2, of_node,
239 &mips_cpu_ipi_chip_ops,
240 ipi_domain_state);
241 if (!ipi_domain)
242 panic("Failed to add MIPS CPU IPI domain");
243 ipi_domain->bus_token = DOMAIN_BUS_IPI;
244}
245
246#else /* !CONFIG_GENERIC_IRQ_IPI */
247
248static inline void mips_cpu_register_ipi_domain(struct device_node *of_node) {}
249
250#endif /* !CONFIG_GENERIC_IRQ_IPI */
251
252static void __init __mips_cpu_irq_init(struct device_node *of_node)
253{
150 /* Mask interrupts. */ 254 /* Mask interrupts. */
151 clear_c0_status(ST0_IM); 255 clear_c0_status(ST0_IM);
152 clear_c0_cause(CAUSEF_IP); 256 clear_c0_cause(CAUSEF_IP);
153 257
154 domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, 258 irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
155 &mips_cpu_intc_irq_domain_ops, NULL); 259 &mips_cpu_intc_irq_domain_ops,
156 if (!domain) 260 NULL);
261 if (!irq_domain)
157 panic("Failed to add irqdomain for MIPS CPU"); 262 panic("Failed to add irqdomain for MIPS CPU");
263
264 /*
265 * Only proceed to register the software interrupt IPI implementation
266 * for CPUs which implement the MIPS MT (multi-threading) ASE.
267 */
268 if (cpu_has_mipsmt)
269 mips_cpu_register_ipi_domain(of_node);
158} 270}
159 271
160void __init mips_cpu_irq_init(void) 272void __init mips_cpu_irq_init(void)
diff --git a/drivers/net/ethernet/broadcom/sb1250-mac.c b/drivers/net/ethernet/broadcom/sb1250-mac.c
index 55c8e25b43d9..16a0f192daec 100644
--- a/drivers/net/ethernet/broadcom/sb1250-mac.c
+++ b/drivers/net/ethernet/broadcom/sb1250-mac.c
@@ -2641,3 +2641,4 @@ static struct platform_driver sbmac_driver = {
2641}; 2641};
2642 2642
2643module_platform_driver(sbmac_driver); 2643module_platform_driver(sbmac_driver);
2644MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-03 19:30:19 -0400