2 files changed, 24 insertions, 5 deletions

diff --git a/arch/nds32/include/asm/bitfield.h b/arch/nds32/include/asm/bitfield.h
index 28b7d797fd59..8e84fc385b94 100644
--- a/arch/nds32/include/asm/bitfield.h
+++ b/arch/nds32/include/asm/bitfield.h
@@ -396,6 +396,7 @@
 #define MMU_CTL_D8KB            1
 #define MMU_CTL_UNA             ( 0x1  << MMU_CTL_offUNA )
 
+#define MMU_CTL_CACHEABLE_NON   0
 #define MMU_CTL_CACHEABLE_WB    2
 #define MMU_CTL_CACHEABLE_WT    3
 
diff --git a/arch/nds32/kernel/head.S b/arch/nds32/kernel/head.S
index 71f57bd70f3b..c5fdae174ced 100644
--- a/arch/nds32/kernel/head.S
+++ b/arch/nds32/kernel/head.S
@@ -57,14 +57,32 @@ _nodtb:
         isb
         mtsr    $r4, $L1_PPTB       ! load page table pointer\n"
 
-/* set NTC0 cacheable/writeback, mutliple page size in use */
+#ifdef CONFIG_CPU_DCACHE_DISABLE
+        #define MMU_CTL_NTCC MMU_CTL_CACHEABLE_NON
+#else
+        #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+                #define MMU_CTL_NTCC MMU_CTL_CACHEABLE_WT
+        #else
+                #define MMU_CTL_NTCC MMU_CTL_CACHEABLE_WB
+        #endif
+#endif
+
+/* set NTC cacheability, mutliple page size in use */
         mfsr    $r3, $MMU_CTL
-        li      $r0, #~MMU_CTL_mskNTC0
-        and     $r3, $r3, $r0
+#if CONFIG_MEMORY_START >= 0xc0000000
+        ori     $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC3)
+#elif CONFIG_MEMORY_START >= 0x80000000
+        ori     $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC2)
+#elif CONFIG_MEMORY_START >= 0x40000000
+        ori     $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC1)
+#else
+        ori     $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC0)
+#endif
+
 #ifdef CONFIG_ANDES_PAGE_SIZE_4KB
-        ori     $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << MMU_CTL_offNTC0))
+        ori     $r3, $r3, #(MMU_CTL_mskMPZIU)
 #else
-        ori     $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << MMU_CTL_offNTC0)|MMU_CTL_D8KB)
+        ori     $r3, $r3, #(MMU_CTL_mskMPZIU|MMU_CTL_D8KB)
 #endif
 #ifdef CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS
         li      $r0, #MMU_CTL_UNA