aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--Documentation/devicetree/bindings/regmap/regmap.txt11
-rw-r--r--Documentation/devicetree/bindings/sound/max9867.txt17
-rw-r--r--Documentation/devicetree/bindings/sound/max98926.txt32
-rw-r--r--arch/mips/boot/dts/brcm/bcm6328.dtsi2
-rw-r--r--arch/mips/boot/dts/brcm/bcm6368.dtsi2
-rw-r--r--arch/mips/boot/dts/brcm/bcm7125.dtsi2
-rw-r--r--arch/mips/boot/dts/brcm/bcm7346.dtsi2
-rw-r--r--arch/mips/boot/dts/brcm/bcm7358.dtsi2
-rw-r--r--arch/mips/boot/dts/brcm/bcm7360.dtsi2
-rw-r--r--arch/mips/boot/dts/brcm/bcm7362.dtsi2
-rw-r--r--arch/mips/boot/dts/brcm/bcm7420.dtsi2
-rw-r--r--arch/mips/boot/dts/brcm/bcm7425.dtsi2
-rw-r--r--arch/mips/boot/dts/brcm/bcm7435.dtsi2
-rw-r--r--drivers/base/regmap/regcache.c41
-rw-r--r--drivers/base/regmap/regmap-mmio.c259
-rw-r--r--drivers/base/regmap/regmap.c5
-rw-r--r--sound/soc/codecs/Kconfig8
-rw-r--r--sound/soc/codecs/Makefile4
-rw-r--r--sound/soc/codecs/hdac_hdmi.c5
-rwxr-xr-xsound/soc/codecs/max9867.c546
-rwxr-xr-xsound/soc/codecs/max9867.h83
-rw-r--r--sound/soc/codecs/max98926.c606
-rw-r--r--sound/soc/codecs/max98926.h848
-rw-r--r--sound/soc/fsl/fsl_sai.c3
-rw-r--r--sound/soc/fsl/fsl_ssi.c42
25 files changed, 2361 insertions, 169 deletions
diff --git a/Documentation/devicetree/bindings/regmap/regmap.txt b/Documentation/devicetree/bindings/regmap/regmap.txt
index b494f8b8ef72..e98a9652ccc8 100644
--- a/Documentation/devicetree/bindings/regmap/regmap.txt
+++ b/Documentation/devicetree/bindings/regmap/regmap.txt
@@ -5,15 +5,18 @@ Index Device Endianness properties
5--------------------------------------------------- 5---------------------------------------------------
61 BE 'big-endian' 61 BE 'big-endian'
72 LE 'little-endian' 72 LE 'little-endian'
83 Native 'native-endian'
8 9
9For one device driver, which will run in different scenarios above 10For one device driver, which will run in different scenarios above
10on different SoCs using the devicetree, we need one way to simplify 11on different SoCs using the devicetree, we need one way to simplify
11this. 12this.
12 13
13Required properties: 14Optional properties:
14- {big,little}-endian: these are boolean properties, if absent 15- {big,little,native}-endian: these are boolean properties, if absent
15 meaning that the CPU and the Device are in the same endianness mode, 16 then the implementation will choose a default based on the device
16 these properties are for register values and all the buffers only. 17 being controlled. These properties are for register values and all
18 the buffers only. Native endian means that the CPU and device have
19 the same endianness.
17 20
18Examples: 21Examples:
19Scenario 1 : CPU in LE mode & device in LE mode. 22Scenario 1 : CPU in LE mode & device in LE mode.
diff --git a/Documentation/devicetree/bindings/sound/max9867.txt b/Documentation/devicetree/bindings/sound/max9867.txt
new file mode 100644
index 000000000000..394cd4eb17ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/max9867.txt
@@ -0,0 +1,17 @@
1max9867 codec
2
3This device supports I2C mode only.
4
5Required properties:
6
7- compatible : "maxim,max9867"
8- reg : The chip select number on the I2C bus
9
10Example:
11
12&i2c {
13 max9867: max9867@0x18 {
14 compatible = "maxim,max9867";
15 reg = <0x18>;
16 };
17};
diff --git a/Documentation/devicetree/bindings/sound/max98926.txt b/Documentation/devicetree/bindings/sound/max98926.txt
new file mode 100644
index 000000000000..0b7f4e4d5f9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/max98926.txt
@@ -0,0 +1,32 @@
1max98926 audio CODEC
2
3This device supports I2C.
4
5Required properties:
6
7 - compatible : "maxim,max98926"
8
9 - vmon-slot-no : slot number used to send voltage information
10 or in inteleave mode this will be used as
11 interleave slot.
12
13 - imon-slot-no : slot number used to send current information
14
15 - interleave-mode : When using two MAX98926 in a system it is
16 possible to create ADC data that that will
17 overflow the frame size. Digital Audio Interleave
18 mode provides a means to output VMON and IMON data
19 from two devices on a single DOUT line when running
20 smaller frames sizes such as 32 BCLKS per LRCLK or
21 48 BCLKS per LRCLK.
22
23 - reg : the I2C address of the device for I2C
24
25Example:
26
27codec: max98926@1a {
28 compatible = "maxim,max98926";
29 vmon-slot-no = <0>;
30 imon-slot-no = <2>;
31 reg = <0x1a>;
32};
diff --git a/arch/mips/boot/dts/brcm/bcm6328.dtsi b/arch/mips/boot/dts/brcm/bcm6328.dtsi
index d61b1616b604..9d19236f53e7 100644
--- a/arch/mips/boot/dts/brcm/bcm6328.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm6328.dtsi
@@ -74,7 +74,7 @@
74 timer: timer@10000040 { 74 timer: timer@10000040 {
75 compatible = "syscon"; 75 compatible = "syscon";
76 reg = <0x10000040 0x2c>; 76 reg = <0x10000040 0x2c>;
77 little-endian; 77 native-endian;
78 }; 78 };
79 79
80 reboot { 80 reboot {
diff --git a/arch/mips/boot/dts/brcm/bcm6368.dtsi b/arch/mips/boot/dts/brcm/bcm6368.dtsi
index 9c8d3fe28b31..1f6b9b5cddb4 100644
--- a/arch/mips/boot/dts/brcm/bcm6368.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm6368.dtsi
@@ -54,7 +54,7 @@
54 periph_cntl: syscon@10000000 { 54 periph_cntl: syscon@10000000 {
55 compatible = "syscon"; 55 compatible = "syscon";
56 reg = <0x10000000 0x14>; 56 reg = <0x10000000 0x14>;
57 little-endian; 57 native-endian;
58 }; 58 };
59 59
60 reboot: syscon-reboot@10000008 { 60 reboot: syscon-reboot@10000008 {
diff --git a/arch/mips/boot/dts/brcm/bcm7125.dtsi b/arch/mips/boot/dts/brcm/bcm7125.dtsi
index 1a7efa883c5e..3ae16053a0c9 100644
--- a/arch/mips/boot/dts/brcm/bcm7125.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7125.dtsi
@@ -98,7 +98,7 @@
98 sun_top_ctrl: syscon@404000 { 98 sun_top_ctrl: syscon@404000 {
99 compatible = "brcm,bcm7125-sun-top-ctrl", "syscon"; 99 compatible = "brcm,bcm7125-sun-top-ctrl", "syscon";
100 reg = <0x404000 0x60c>; 100 reg = <0x404000 0x60c>;
101 little-endian; 101 native-endian;
102 }; 102 };
103 103
104 reboot { 104 reboot {
diff --git a/arch/mips/boot/dts/brcm/bcm7346.dtsi b/arch/mips/boot/dts/brcm/bcm7346.dtsi
index d4bf52cfcf17..be7991917d29 100644
--- a/arch/mips/boot/dts/brcm/bcm7346.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7346.dtsi
@@ -118,7 +118,7 @@
118 sun_top_ctrl: syscon@404000 { 118 sun_top_ctrl: syscon@404000 {
119 compatible = "brcm,bcm7346-sun-top-ctrl", "syscon"; 119 compatible = "brcm,bcm7346-sun-top-ctrl", "syscon";
120 reg = <0x404000 0x51c>; 120 reg = <0x404000 0x51c>;
121 little-endian; 121 native-endian;
122 }; 122 };
123 123
124 reboot { 124 reboot {
diff --git a/arch/mips/boot/dts/brcm/bcm7358.dtsi b/arch/mips/boot/dts/brcm/bcm7358.dtsi
index 8e2501694d03..060805be619a 100644
--- a/arch/mips/boot/dts/brcm/bcm7358.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7358.dtsi
@@ -112,7 +112,7 @@
112 sun_top_ctrl: syscon@404000 { 112 sun_top_ctrl: syscon@404000 {
113 compatible = "brcm,bcm7358-sun-top-ctrl", "syscon"; 113 compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
114 reg = <0x404000 0x51c>; 114 reg = <0x404000 0x51c>;
115 little-endian; 115 native-endian;
116 }; 116 };
117 117
118 reboot { 118 reboot {
diff --git a/arch/mips/boot/dts/brcm/bcm7360.dtsi b/arch/mips/boot/dts/brcm/bcm7360.dtsi
index 7e5f76040fb8..bcdb09bfe07b 100644
--- a/arch/mips/boot/dts/brcm/bcm7360.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7360.dtsi
@@ -112,7 +112,7 @@
112 sun_top_ctrl: syscon@404000 { 112 sun_top_ctrl: syscon@404000 {
113 compatible = "brcm,bcm7360-sun-top-ctrl", "syscon"; 113 compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
114 reg = <0x404000 0x51c>; 114 reg = <0x404000 0x51c>;
115 little-endian; 115 native-endian;
116 }; 116 };
117 117
118 reboot { 118 reboot {
diff --git a/arch/mips/boot/dts/brcm/bcm7362.dtsi b/arch/mips/boot/dts/brcm/bcm7362.dtsi
index c739ea77acb0..d3b1b762e6c3 100644
--- a/arch/mips/boot/dts/brcm/bcm7362.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7362.dtsi
@@ -118,7 +118,7 @@
118 sun_top_ctrl: syscon@404000 { 118 sun_top_ctrl: syscon@404000 {
119 compatible = "brcm,bcm7362-sun-top-ctrl", "syscon"; 119 compatible = "brcm,bcm7362-sun-top-ctrl", "syscon";
120 reg = <0x404000 0x51c>; 120 reg = <0x404000 0x51c>;
121 little-endian; 121 native-endian;
122 }; 122 };
123 123
124 reboot { 124 reboot {
diff --git a/arch/mips/boot/dts/brcm/bcm7420.dtsi b/arch/mips/boot/dts/brcm/bcm7420.dtsi
index 5f55d0a50a28..3302a1b8a5c9 100644
--- a/arch/mips/boot/dts/brcm/bcm7420.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7420.dtsi
@@ -99,7 +99,7 @@
99 sun_top_ctrl: syscon@404000 { 99 sun_top_ctrl: syscon@404000 {
100 compatible = "brcm,bcm7420-sun-top-ctrl", "syscon"; 100 compatible = "brcm,bcm7420-sun-top-ctrl", "syscon";
101 reg = <0x404000 0x60c>; 101 reg = <0x404000 0x60c>;
102 little-endian; 102 native-endian;
103 }; 103 };
104 104
105 reboot { 105 reboot {
diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi
index e24d41ab4e30..15b27aae15a9 100644
--- a/arch/mips/boot/dts/brcm/bcm7425.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
@@ -100,7 +100,7 @@
100 sun_top_ctrl: syscon@404000 { 100 sun_top_ctrl: syscon@404000 {
101 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon"; 101 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
102 reg = <0x404000 0x51c>; 102 reg = <0x404000 0x51c>;
103 little-endian; 103 native-endian;
104 }; 104 };
105 105
106 reboot { 106 reboot {
diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi
index 8b9432cc062b..adb33e355043 100644
--- a/arch/mips/boot/dts/brcm/bcm7435.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi
@@ -114,7 +114,7 @@
114 sun_top_ctrl: syscon@404000 { 114 sun_top_ctrl: syscon@404000 {
115 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon"; 115 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
116 reg = <0x404000 0x51c>; 116 reg = <0x404000 0x51c>;
117 little-endian; 117 native-endian;
118 }; 118 };
119 119
120 reboot { 120 reboot {
diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c
index 348be3a35410..cccceb599b02 100644
--- a/drivers/base/regmap/regcache.c
+++ b/drivers/base/regmap/regcache.c
@@ -30,7 +30,7 @@ static int regcache_hw_init(struct regmap *map)
30 int i, j; 30 int i, j;
31 int ret; 31 int ret;
32 int count; 32 int count;
33 unsigned int val; 33 unsigned int reg, val;
34 void *tmp_buf; 34 void *tmp_buf;
35 35
36 if (!map->num_reg_defaults_raw) 36 if (!map->num_reg_defaults_raw)
@@ -67,27 +67,46 @@ static int regcache_hw_init(struct regmap *map)
67 ret = regmap_raw_read(map, 0, tmp_buf, 67 ret = regmap_raw_read(map, 0, tmp_buf,
68 map->num_reg_defaults_raw); 68 map->num_reg_defaults_raw);
69 map->cache_bypass = cache_bypass; 69 map->cache_bypass = cache_bypass;
70 if (ret < 0) 70 if (ret == 0) {
71 goto err_cache_free; 71 map->reg_defaults_raw = tmp_buf;
72 72 map->cache_free = 1;
73 map->reg_defaults_raw = tmp_buf; 73 } else {
74 map->cache_free = 1; 74 kfree(tmp_buf);
75 }
75 } 76 }
76 77
77 /* fill the reg_defaults */ 78 /* fill the reg_defaults */
78 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) { 79 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
79 if (regmap_volatile(map, i * map->reg_stride)) 80 reg = i * map->reg_stride;
81
82 if (!regmap_readable(map, reg))
80 continue; 83 continue;
81 val = regcache_get_val(map, map->reg_defaults_raw, i); 84
82 map->reg_defaults[j].reg = i * map->reg_stride; 85 if (regmap_volatile(map, reg))
86 continue;
87
88 if (map->reg_defaults_raw) {
89 val = regcache_get_val(map, map->reg_defaults_raw, i);
90 } else {
91 bool cache_bypass = map->cache_bypass;
92
93 map->cache_bypass = true;
94 ret = regmap_read(map, reg, &val);
95 map->cache_bypass = cache_bypass;
96 if (ret != 0) {
97 dev_err(map->dev, "Failed to read %d: %d\n",
98 reg, ret);
99 goto err_free;
100 }
101 }
102
103 map->reg_defaults[j].reg = reg;
83 map->reg_defaults[j].def = val; 104 map->reg_defaults[j].def = val;
84 j++; 105 j++;
85 } 106 }
86 107
87 return 0; 108 return 0;
88 109
89err_cache_free:
90 kfree(tmp_buf);
91err_free: 110err_free:
92 kfree(map->reg_defaults); 111 kfree(map->reg_defaults);
93 112
diff --git a/drivers/base/regmap/regmap-mmio.c b/drivers/base/regmap/regmap-mmio.c
index eea51569f0eb..7526906ca080 100644
--- a/drivers/base/regmap/regmap-mmio.c
+++ b/drivers/base/regmap/regmap-mmio.c
@@ -25,26 +25,14 @@
25 25
26struct regmap_mmio_context { 26struct regmap_mmio_context {
27 void __iomem *regs; 27 void __iomem *regs;
28 unsigned reg_bytes;
29 unsigned val_bytes; 28 unsigned val_bytes;
30 unsigned pad_bytes;
31 struct clk *clk; 29 struct clk *clk;
32};
33 30
34static inline void regmap_mmio_regsize_check(size_t reg_size) 31 void (*reg_write)(struct regmap_mmio_context *ctx,
35{ 32 unsigned int reg, unsigned int val);
36 switch (reg_size) { 33 unsigned int (*reg_read)(struct regmap_mmio_context *ctx,
37 case 1: 34 unsigned int reg);
38 case 2: 35};
39 case 4:
40#ifdef CONFIG_64BIT
41 case 8:
42#endif
43 break;
44 default:
45 BUG();
46 }
47}
48 36
49static int regmap_mmio_regbits_check(size_t reg_bits) 37static int regmap_mmio_regbits_check(size_t reg_bits)
50{ 38{
@@ -88,72 +76,62 @@ static int regmap_mmio_get_min_stride(size_t val_bits)
88 return min_stride; 76 return min_stride;
89} 77}
90 78
91static inline void regmap_mmio_count_check(size_t count, u32 offset) 79static void regmap_mmio_write8(struct regmap_mmio_context *ctx,
80 unsigned int reg,
81 unsigned int val)
82{
83 writeb(val, ctx->regs + reg);
84}
85
86static void regmap_mmio_write16le(struct regmap_mmio_context *ctx,
87 unsigned int reg,
88 unsigned int val)
92{ 89{
93 BUG_ON(count <= offset); 90 writew(val, ctx->regs + reg);
94} 91}
95 92
96static inline unsigned int 93static void regmap_mmio_write16be(struct regmap_mmio_context *ctx,
97regmap_mmio_get_offset(const void *reg, size_t reg_size) 94 unsigned int reg,
95 unsigned int val)
98{ 96{
99 switch (reg_size) { 97 iowrite16be(val, ctx->regs + reg);
100 case 1: 98}
101 return *(u8 *)reg; 99
102 case 2: 100static void regmap_mmio_write32le(struct regmap_mmio_context *ctx,
103 return *(u16 *)reg; 101 unsigned int reg,
104 case 4: 102 unsigned int val)
105 return *(u32 *)reg; 103{
104 writel(val, ctx->regs + reg);
105}
106
107static void regmap_mmio_write32be(struct regmap_mmio_context *ctx,
108 unsigned int reg,
109 unsigned int val)
110{
111 iowrite32be(val, ctx->regs + reg);
112}
113
106#ifdef CONFIG_64BIT 114#ifdef CONFIG_64BIT
107 case 8: 115static void regmap_mmio_write64le(struct regmap_mmio_context *ctx,
108 return *(u64 *)reg; 116 unsigned int reg,
109#endif 117 unsigned int val)
110 default: 118{
111 BUG(); 119 writeq(val, ctx->regs + reg);
112 }
113} 120}
121#endif
114 122
115static int regmap_mmio_gather_write(void *context, 123static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val)
116 const void *reg, size_t reg_size,
117 const void *val, size_t val_size)
118{ 124{
119 struct regmap_mmio_context *ctx = context; 125 struct regmap_mmio_context *ctx = context;
120 unsigned int offset;
121 int ret; 126 int ret;
122 127
123 regmap_mmio_regsize_check(reg_size);
124
125 if (!IS_ERR(ctx->clk)) { 128 if (!IS_ERR(ctx->clk)) {
126 ret = clk_enable(ctx->clk); 129 ret = clk_enable(ctx->clk);
127 if (ret < 0) 130 if (ret < 0)
128 return ret; 131 return ret;
129 } 132 }
130 133
131 offset = regmap_mmio_get_offset(reg, reg_size); 134 ctx->reg_write(ctx, reg, val);
132
133 while (val_size) {
134 switch (ctx->val_bytes) {
135 case 1:
136 writeb(*(u8 *)val, ctx->regs + offset);
137 break;
138 case 2:
139 writew(*(u16 *)val, ctx->regs + offset);
140 break;
141 case 4:
142 writel(*(u32 *)val, ctx->regs + offset);
143 break;
144#ifdef CONFIG_64BIT
145 case 8:
146 writeq(*(u64 *)val, ctx->regs + offset);
147 break;
148#endif
149 default:
150 /* Should be caught by regmap_mmio_check_config */
151 BUG();
152 }
153 val_size -= ctx->val_bytes;
154 val += ctx->val_bytes;
155 offset += ctx->val_bytes;
156 }
157 135
158 if (!IS_ERR(ctx->clk)) 136 if (!IS_ERR(ctx->clk))
159 clk_disable(ctx->clk); 137 clk_disable(ctx->clk);
@@ -161,59 +139,56 @@ static int regmap_mmio_gather_write(void *context,
161 return 0; 139 return 0;
162} 140}
163 141
164static int regmap_mmio_write(void *context, const void *data, size_t count) 142static unsigned int regmap_mmio_read8(struct regmap_mmio_context *ctx,
143 unsigned int reg)
165{ 144{
166 struct regmap_mmio_context *ctx = context; 145 return readb(ctx->regs + reg);
167 unsigned int offset = ctx->reg_bytes + ctx->pad_bytes; 146}
147
148static unsigned int regmap_mmio_read16le(struct regmap_mmio_context *ctx,
149 unsigned int reg)
150{
151 return readw(ctx->regs + reg);
152}
153
154static unsigned int regmap_mmio_read16be(struct regmap_mmio_context *ctx,
155 unsigned int reg)
156{
157 return ioread16be(ctx->regs + reg);
158}
159
160static unsigned int regmap_mmio_read32le(struct regmap_mmio_context *ctx,
161 unsigned int reg)
162{
163 return readl(ctx->regs + reg);
164}
168 165
169 regmap_mmio_count_check(count, offset); 166static unsigned int regmap_mmio_read32be(struct regmap_mmio_context *ctx,
167 unsigned int reg)
168{
169 return ioread32be(ctx->regs + reg);
170}
170 171
171 return regmap_mmio_gather_write(context, data, ctx->reg_bytes, 172#ifdef CONFIG_64BIT
172 data + offset, count - offset); 173static unsigned int regmap_mmio_read64le(struct regmap_mmio_context *ctx,
174 unsigned int reg)
175{
176 return readq(ctx->regs + reg);
173} 177}
178#endif
174 179
175static int regmap_mmio_read(void *context, 180static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val)
176 const void *reg, size_t reg_size,
177 void *val, size_t val_size)
178{ 181{
179 struct regmap_mmio_context *ctx = context; 182 struct regmap_mmio_context *ctx = context;
180 unsigned int offset;
181 int ret; 183 int ret;
182 184
183 regmap_mmio_regsize_check(reg_size);
184
185 if (!IS_ERR(ctx->clk)) { 185 if (!IS_ERR(ctx->clk)) {
186 ret = clk_enable(ctx->clk); 186 ret = clk_enable(ctx->clk);
187 if (ret < 0) 187 if (ret < 0)
188 return ret; 188 return ret;
189 } 189 }
190 190
191 offset = regmap_mmio_get_offset(reg, reg_size); 191 *val = ctx->reg_read(ctx, reg);
192
193 while (val_size) {
194 switch (ctx->val_bytes) {
195 case 1:
196 *(u8 *)val = readb(ctx->regs + offset);
197 break;
198 case 2:
199 *(u16 *)val = readw(ctx->regs + offset);
200 break;
201 case 4:
202 *(u32 *)val = readl(ctx->regs + offset);
203 break;
204#ifdef CONFIG_64BIT
205 case 8:
206 *(u64 *)val = readq(ctx->regs + offset);
207 break;
208#endif
209 default:
210 /* Should be caught by regmap_mmio_check_config */
211 BUG();
212 }
213 val_size -= ctx->val_bytes;
214 val += ctx->val_bytes;
215 offset += ctx->val_bytes;
216 }
217 192
218 if (!IS_ERR(ctx->clk)) 193 if (!IS_ERR(ctx->clk))
219 clk_disable(ctx->clk); 194 clk_disable(ctx->clk);
@@ -232,14 +207,11 @@ static void regmap_mmio_free_context(void *context)
232 kfree(context); 207 kfree(context);
233} 208}
234 209
235static struct regmap_bus regmap_mmio = { 210static const struct regmap_bus regmap_mmio = {
236 .fast_io = true, 211 .fast_io = true,
237 .write = regmap_mmio_write, 212 .reg_write = regmap_mmio_write,
238 .gather_write = regmap_mmio_gather_write, 213 .reg_read = regmap_mmio_read,
239 .read = regmap_mmio_read,
240 .free_context = regmap_mmio_free_context, 214 .free_context = regmap_mmio_free_context,
241 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
242 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
243}; 215};
244 216
245static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev, 217static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
@@ -265,24 +237,71 @@ static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
265 if (config->reg_stride < min_stride) 237 if (config->reg_stride < min_stride)
266 return ERR_PTR(-EINVAL); 238 return ERR_PTR(-EINVAL);
267 239
268 switch (config->reg_format_endian) {
269 case REGMAP_ENDIAN_DEFAULT:
270 case REGMAP_ENDIAN_NATIVE:
271 break;
272 default:
273 return ERR_PTR(-EINVAL);
274 }
275
276 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 240 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
277 if (!ctx) 241 if (!ctx)
278 return ERR_PTR(-ENOMEM); 242 return ERR_PTR(-ENOMEM);
279 243
280 ctx->regs = regs; 244 ctx->regs = regs;
281 ctx->val_bytes = config->val_bits / 8; 245 ctx->val_bytes = config->val_bits / 8;
282 ctx->reg_bytes = config->reg_bits / 8;
283 ctx->pad_bytes = config->pad_bits / 8;
284 ctx->clk = ERR_PTR(-ENODEV); 246 ctx->clk = ERR_PTR(-ENODEV);
285 247
248 switch (config->reg_format_endian) {
249 case REGMAP_ENDIAN_DEFAULT:
250 case REGMAP_ENDIAN_LITTLE:
251#ifdef __LITTLE_ENDIAN
252 case REGMAP_ENDIAN_NATIVE:
253#endif
254 switch (config->val_bits) {
255 case 8:
256 ctx->reg_read = regmap_mmio_read8;
257 ctx->reg_write = regmap_mmio_write8;
258 break;
259 case 16:
260 ctx->reg_read = regmap_mmio_read16le;
261 ctx->reg_write = regmap_mmio_write16le;
262 break;
263 case 32:
264 ctx->reg_read = regmap_mmio_read32le;
265 ctx->reg_write = regmap_mmio_write32le;
266 break;
267#ifdef CONFIG_64BIT
268 case 64:
269 ctx->reg_read = regmap_mmio_read64le;
270 ctx->reg_write = regmap_mmio_write64le;
271 break;
272#endif
273 default:
274 ret = -EINVAL;
275 goto err_free;
276 }
277 break;
278 case REGMAP_ENDIAN_BIG:
279#ifdef __BIG_ENDIAN
280 case REGMAP_ENDIAN_NATIVE:
281#endif
282 switch (config->val_bits) {
283 case 8:
284 ctx->reg_read = regmap_mmio_read8;
285 ctx->reg_write = regmap_mmio_write8;
286 break;
287 case 16:
288 ctx->reg_read = regmap_mmio_read16be;
289 ctx->reg_write = regmap_mmio_write16be;
290 break;
291 case 32:
292 ctx->reg_read = regmap_mmio_read32be;
293 ctx->reg_write = regmap_mmio_write32be;
294 break;
295 default:
296 ret = -EINVAL;
297 goto err_free;
298 }
299 break;
300 default:
301 ret = -EINVAL;
302 goto err_free;
303 }
304
286 if (clk_id == NULL) 305 if (clk_id == NULL)
287 return ctx; 306 return ctx;
288 307
diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index ee54e841de4a..e2f68807d970 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -557,6 +557,8 @@ enum regmap_endian regmap_get_val_endian(struct device *dev,
557 endian = REGMAP_ENDIAN_BIG; 557 endian = REGMAP_ENDIAN_BIG;
558 else if (of_property_read_bool(np, "little-endian")) 558 else if (of_property_read_bool(np, "little-endian"))
559 endian = REGMAP_ENDIAN_LITTLE; 559 endian = REGMAP_ENDIAN_LITTLE;
560 else if (of_property_read_bool(np, "native-endian"))
561 endian = REGMAP_ENDIAN_NATIVE;
560 562
561 /* If the endianness was specified in DT, use that */ 563 /* If the endianness was specified in DT, use that */
562 if (endian != REGMAP_ENDIAN_DEFAULT) 564 if (endian != REGMAP_ENDIAN_DEFAULT)
@@ -2253,6 +2255,9 @@ static int _regmap_raw_read(struct regmap *map, unsigned int reg, void *val,
2253 2255
2254 WARN_ON(!map->bus); 2256 WARN_ON(!map->bus);
2255 2257
2258 if (!map->bus || !map->bus->read)
2259 return -EINVAL;
2260
2256 range = _regmap_range_lookup(map, reg); 2261 range = _regmap_range_lookup(map, reg);
2257 if (range) { 2262 if (range) {
2258 ret = _regmap_select_page(map, &reg, range, 2263 ret = _regmap_select_page(map, &reg, range,
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index bfbb6deb1be6..b414a92b677a 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -79,7 +79,9 @@ config SND_SOC_ALL_CODECS
79 select SND_SOC_MAX98090 if I2C 79 select SND_SOC_MAX98090 if I2C
80 select SND_SOC_MAX98095 if I2C 80 select SND_SOC_MAX98095 if I2C
81 select SND_SOC_MAX98357A if GPIOLIB 81 select SND_SOC_MAX98357A if GPIOLIB
82 select SND_SOC_MAX9867 if I2C
82 select SND_SOC_MAX98925 if I2C 83 select SND_SOC_MAX98925 if I2C
84 select SND_SOC_MAX98926 if I2C
83 select SND_SOC_MAX9850 if I2C 85 select SND_SOC_MAX9850 if I2C
84 select SND_SOC_MAX9768 if I2C 86 select SND_SOC_MAX9768 if I2C
85 select SND_SOC_MAX9877 if I2C 87 select SND_SOC_MAX9877 if I2C
@@ -518,9 +520,15 @@ config SND_SOC_MAX98095
518config SND_SOC_MAX98357A 520config SND_SOC_MAX98357A
519 tristate 521 tristate
520 522
523config SND_SOC_MAX9867
524 tristate
525
521config SND_SOC_MAX98925 526config SND_SOC_MAX98925
522 tristate 527 tristate
523 528
529config SND_SOC_MAX98926
530 tristate
531
524config SND_SOC_MAX9850 532config SND_SOC_MAX9850
525 tristate 533 tristate
526 534
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 9acd777a7a98..d10418ccd181 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -74,7 +74,9 @@ snd-soc-max98088-objs := max98088.o
74snd-soc-max98090-objs := max98090.o 74snd-soc-max98090-objs := max98090.o
75snd-soc-max98095-objs := max98095.o 75snd-soc-max98095-objs := max98095.o
76snd-soc-max98357a-objs := max98357a.o 76snd-soc-max98357a-objs := max98357a.o
77snd-soc-max9867-objs := max9867.o
77snd-soc-max98925-objs := max98925.o 78snd-soc-max98925-objs := max98925.o
79snd-soc-max98926-objs := max98926.o
78snd-soc-max9850-objs := max9850.o 80snd-soc-max9850-objs := max9850.o
79snd-soc-mc13783-objs := mc13783.o 81snd-soc-mc13783-objs := mc13783.o
80snd-soc-ml26124-objs := ml26124.o 82snd-soc-ml26124-objs := ml26124.o
@@ -280,7 +282,9 @@ obj-$(CONFIG_SND_SOC_MAX98088) += snd-soc-max98088.o
280obj-$(CONFIG_SND_SOC_MAX98090) += snd-soc-max98090.o 282obj-$(CONFIG_SND_SOC_MAX98090) += snd-soc-max98090.o
281obj-$(CONFIG_SND_SOC_MAX98095) += snd-soc-max98095.o 283obj-$(CONFIG_SND_SOC_MAX98095) += snd-soc-max98095.o
282obj-$(CONFIG_SND_SOC_MAX98357A) += snd-soc-max98357a.o 284obj-$(CONFIG_SND_SOC_MAX98357A) += snd-soc-max98357a.o
285obj-$(CONFIG_SND_SOC_MAX9867) += snd-soc-max9867.o
283obj-$(CONFIG_SND_SOC_MAX98925) += snd-soc-max98925.o 286obj-$(CONFIG_SND_SOC_MAX98925) += snd-soc-max98925.o
287obj-$(CONFIG_SND_SOC_MAX98926) += snd-soc-max98926.o
284obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o 288obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o
285obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o 289obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o
286obj-$(CONFIG_SND_SOC_ML26124) += snd-soc-ml26124.o 290obj-$(CONFIG_SND_SOC_ML26124) += snd-soc-ml26124.o
diff --git a/sound/soc/codecs/hdac_hdmi.c b/sound/soc/codecs/hdac_hdmi.c
index cb0b036a1139..26f9459cb3bc 100644
--- a/sound/soc/codecs/hdac_hdmi.c
+++ b/sound/soc/codecs/hdac_hdmi.c
@@ -303,7 +303,6 @@ static int hdac_hdmi_setup_audio_infoframe(struct hdac_ext_device *hdac,
303 if (ret < 0) 303 if (ret < 0)
304 return ret; 304 return ret;
305 305
306 dip = (u8 *)&frame;
307 break; 306 break;
308 307
309 case DRM_ELD_CONN_TYPE_DP: 308 case DRM_ELD_CONN_TYPE_DP:
@@ -332,9 +331,9 @@ static int hdac_hdmi_setup_audio_infoframe(struct hdac_ext_device *hdac,
332 /* Fill infoframe. Index auto-incremented */ 331 /* Fill infoframe. Index auto-incremented */
333 hdac_hdmi_set_dip_index(hdac, pin_nid, 0x0, 0x0); 332 hdac_hdmi_set_dip_index(hdac, pin_nid, 0x0, 0x0);
334 if (conn_type == DRM_ELD_CONN_TYPE_HDMI) { 333 if (conn_type == DRM_ELD_CONN_TYPE_HDMI) {
335 for (i = 0; i < sizeof(frame); i++) 334 for (i = 0; i < sizeof(buffer); i++)
336 snd_hdac_codec_write(&hdac->hdac, pin_nid, 0, 335 snd_hdac_codec_write(&hdac->hdac, pin_nid, 0,
337 AC_VERB_SET_HDMI_DIP_DATA, dip[i]); 336 AC_VERB_SET_HDMI_DIP_DATA, buffer[i]);
338 } else { 337 } else {
339 for (i = 0; i < sizeof(dp_ai); i++) 338 for (i = 0; i < sizeof(dp_ai); i++)
340 snd_hdac_codec_write(&hdac->hdac, pin_nid, 0, 339 snd_hdac_codec_write(&hdac->hdac, pin_nid, 0,
diff --git a/sound/soc/codecs/max9867.c b/sound/soc/codecs/max9867.c
new file mode 100755
index 000000000000..2a22fddeb6af
--- /dev/null
+++ b/sound/soc/codecs/max9867.c
@@ -0,0 +1,546 @@
1/*
2 * max9867.c -- max9867 ALSA SoC Audio driver
3 *
4 * Copyright 2013-15 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/delay.h>
12#include <linux/i2c.h>
13#include <linux/module.h>
14#include <linux/regmap.h>
15#include <sound/pcm_params.h>
16#include <sound/soc.h>
17#include <sound/tlv.h>
18#include "max9867.h"
19
20static const char *const max9867_spmode[] = {
21 "Stereo Diff", "Mono Diff",
22 "Stereo Cap", "Mono Cap",
23 "Stereo Single", "Mono Single",
24 "Stereo Single Fast", "Mono Single Fast"
25};
26static const char *const max9867_sidetone_text[] = {
27 "None", "Left", "Right", "LeftRight", "LeftRightDiv2",
28};
29static const char *const max9867_filter_text[] = {"IIR", "FIR"};
30
31static SOC_ENUM_SINGLE_DECL(max9867_filter, MAX9867_CODECFLTR, 7,
32 max9867_filter_text);
33static SOC_ENUM_SINGLE_DECL(max9867_spkmode, MAX9867_MODECONFIG, 0,
34 max9867_spmode);
35static SOC_ENUM_SINGLE_DECL(max9867_sidetone, MAX9867_DACGAIN, 6,
36 max9867_sidetone_text);
37static DECLARE_TLV_DB_SCALE(max9860_capture_tlv, -600, 200, 0);
38static DECLARE_TLV_DB_SCALE(max9860_mic_tlv, 2000, 100, 1);
39static DECLARE_TLV_DB_SCALE(max9860_adc_left_tlv, -1200, 100, 1);
40static DECLARE_TLV_DB_SCALE(max9860_adc_right_tlv, -1200, 100, 1);
41static const unsigned int max98088_micboost_tlv[] = {
42 TLV_DB_RANGE_HEAD(2),
43 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
44 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
45};
46
47static const struct snd_kcontrol_new max9867_snd_controls[] = {
48 SOC_DOUBLE_R("Master Playback Volume", MAX9867_LEFTVOL,
49 MAX9867_RIGHTVOL, 0, 63, 1),
50 SOC_DOUBLE_R_TLV("Capture Volume", MAX9867_LEFTMICGAIN,
51 MAX9867_RIGHTMICGAIN,
52 0, 15, 1, max9860_capture_tlv),
53 SOC_DOUBLE_R_TLV("Mic Volume", MAX9867_LEFTMICGAIN,
54 MAX9867_RIGHTMICGAIN, 0, 31, 1, max9860_mic_tlv),
55 SOC_DOUBLE_R_TLV("Mic Boost Volume", MAX9867_LEFTMICGAIN,
56 MAX9867_RIGHTMICGAIN, 5, 3, 0, max98088_micboost_tlv),
57 SOC_ENUM("Digital Sidetone Src", max9867_sidetone),
58 SOC_SINGLE("Sidetone Volume", MAX9867_DACGAIN, 0, 31, 1),
59 SOC_SINGLE("DAC Volume", MAX9867_DACLEVEL, 4, 3, 0),
60 SOC_SINGLE("DAC Attenuation", MAX9867_DACLEVEL, 0, 15, 1),
61 SOC_SINGLE_TLV("ADC Left Volume", MAX9867_ADCLEVEL,
62 4, 15, 1, max9860_adc_left_tlv),
63 SOC_SINGLE_TLV("ADC Right Volume", MAX9867_ADCLEVEL,
64 0, 15, 1, max9860_adc_right_tlv),
65 SOC_ENUM("Speaker Mode", max9867_spkmode),
66 SOC_SINGLE("Volume Smoothing Switch", MAX9867_MODECONFIG, 6, 1, 0),
67 SOC_SINGLE("ZCD Switch", MAX9867_MODECONFIG, 5, 1, 0),
68 SOC_ENUM("DSP Filter", max9867_filter),
69};
70
71static const char *const max9867_mux[] = {"None", "Mic", "Line", "Mic_Line"};
72
73static SOC_ENUM_SINGLE_DECL(max9867_mux_enum,
74 MAX9867_INPUTCONFIG, MAX9867_INPUT_SHIFT,
75 max9867_mux);
76
77static const struct snd_kcontrol_new max9867_dapm_mux_controls =
78 SOC_DAPM_ENUM("Route", max9867_mux_enum);
79
80static const struct snd_kcontrol_new max9867_left_dapm_control =
81 SOC_DAPM_SINGLE("Switch", MAX9867_PWRMAN, 6, 1, 0);
82static const struct snd_kcontrol_new max9867_right_dapm_control =
83 SOC_DAPM_SINGLE("Switch", MAX9867_PWRMAN, 5, 1, 0);
84static const struct snd_kcontrol_new max9867_line_dapm_control =
85 SOC_DAPM_SINGLE("Switch", MAX9867_LEFTLINELVL, 6, 1, 1);
86
87static const struct snd_soc_dapm_widget max9867_dapm_widgets[] = {
88 SND_SOC_DAPM_AIF_IN("DAI_OUT", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
89 SND_SOC_DAPM_DAC("Left DAC", NULL, MAX9867_PWRMAN, 3, 0),
90 SND_SOC_DAPM_DAC("Right DAC", NULL, MAX9867_PWRMAN, 2, 0),
91 SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
92 SND_SOC_DAPM_OUTPUT("HPOUT"),
93
94 SND_SOC_DAPM_AIF_IN("DAI_IN", "HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
95 SND_SOC_DAPM_ADC("Left ADC", "HiFi Capture", MAX9867_PWRMAN, 1, 0),
96 SND_SOC_DAPM_ADC("Right ADC", "HiFi Capture", MAX9867_PWRMAN, 0, 0),
97 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
98 &max9867_dapm_mux_controls),
99
100 SND_SOC_DAPM_MIXER("Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
101 SND_SOC_DAPM_SWITCH("Left Line", MAX9867_LEFTLINELVL, 6, 1,
102 &max9867_left_dapm_control),
103 SND_SOC_DAPM_SWITCH("Right Line", MAX9867_RIGTHLINELVL, 6, 1,
104 &max9867_right_dapm_control),
105 SND_SOC_DAPM_SWITCH("Line Mixer", SND_SOC_NOPM, 0, 0,
106 &max9867_line_dapm_control),
107 SND_SOC_DAPM_INPUT("LINE_IN"),
108};
109
110static const struct snd_soc_dapm_route max9867_audio_map[] = {
111 {"Left DAC", NULL, "DAI_OUT"},
112 {"Right DAC", NULL, "DAI_OUT"},
113 {"Output Mixer", NULL, "Left DAC"},
114 {"Output Mixer", NULL, "Right DAC"},
115 {"HPOUT", NULL, "Output Mixer"},
116
117 {"Left ADC", NULL, "DAI_IN"},
118 {"Right ADC", NULL, "DAI_IN"},
119 {"Input Mixer", NULL, "Left ADC"},
120 {"Input Mixer", NULL, "Right ADC"},
121 {"Input Mux", "Line", "Input Mixer"},
122 {"Input Mux", "Mic", "Input Mixer"},
123 {"Input Mux", "Mic_Line", "Input Mixer"},
124 {"Right Line", "Switch", "Input Mux"},
125 {"Left Line", "Switch", "Input Mux"},
126 {"LINE_IN", NULL, "Left Line"},
127 {"LINE_IN", NULL, "Right Line"},
128};
129
130enum rates {
131 pcm_rate_8, pcm_rate_16, pcm_rate_24,
132 pcm_rate_32, pcm_rate_44,
133 pcm_rate_48, max_pcm_rate,
134};
135
136struct ni_div_rates {
137 u32 mclk;
138 u16 ni[max_pcm_rate];
139} ni_div[] = {
140 {11289600, {0x116A, 0x22D4, 0x343F, 0x45A9, 0x6000, 0x687D} },
141 {12000000, {0x1062, 0x20C5, 0x3127, 0x4189, 0x5A51, 0x624E} },
142 {12288000, {0x1000, 0x2000, 0x3000, 0x4000, 0x5833, 0x6000} },
143 {13000000, {0x0F20, 0x1E3F, 0x2D5F, 0x3C7F, 0x535F, 0x5ABE} },
144 {19200000, {0x0A3D, 0x147B, 0x1EB8, 0x28F6, 0x3873, 0x3D71} },
145 {24000000, {0x1062, 0x20C5, 0x1893, 0x4189, 0x5A51, 0x624E} },
146 {26000000, {0x0F20, 0x1E3F, 0x16AF, 0x3C7F, 0x535F, 0x5ABE} },
147 {27000000, {0x0E90, 0x1D21, 0x15D8, 0x3A41, 0x5048, 0x5762} },
148};
149
150static inline int get_ni_value(int mclk, int rate)
151{
152 int i, ret = 0;
153
154 /* find the closest rate index*/
155 for (i = 0; i < ARRAY_SIZE(ni_div); i++) {
156 if (ni_div[i].mclk >= mclk)
157 break;
158 }
159 if (i == ARRAY_SIZE(ni_div))
160 return -EINVAL;
161
162 switch (rate) {
163 case 8000:
164 return ni_div[i].ni[pcm_rate_8];
165 case 16000:
166 return ni_div[i].ni[pcm_rate_16];
167 case 32000:
168 return ni_div[i].ni[pcm_rate_32];
169 case 44100:
170 return ni_div[i].ni[pcm_rate_44];
171 case 48000:
172 return ni_div[i].ni[pcm_rate_48];
173 default:
174 pr_err("%s wrong rate %d\n", __func__, rate);
175 ret = -EINVAL;
176 }
177 return ret;
178}
179
180static int max9867_dai_hw_params(struct snd_pcm_substream *substream,
181 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
182{
183 struct snd_soc_codec *codec = dai->codec;
184 struct max9867_priv *max9867 = snd_soc_codec_get_drvdata(codec);
185 unsigned int ni_h, ni_l;
186 int value;
187
188 value = get_ni_value(max9867->sysclk, params_rate(params));
189 if (value < 0)
190 return value;
191
192 ni_h = (0xFF00 & value) >> 8;
193 ni_l = 0x00FF & value;
194 /* set up the ni value */
195 regmap_update_bits(max9867->regmap, MAX9867_AUDIOCLKHIGH,
196 MAX9867_NI_HIGH_MASK, ni_h);
197 regmap_update_bits(max9867->regmap, MAX9867_AUDIOCLKLOW,
198 MAX9867_NI_LOW_MASK, ni_l);
199 if (!max9867->master) {
200 /*
201 * digital pll locks on to any externally supplied LRCLK signal
202 * and also enable rapid lock mode.
203 */
204 regmap_update_bits(max9867->regmap, MAX9867_AUDIOCLKLOW,
205 MAX9867_RAPID_LOCK, MAX9867_RAPID_LOCK);
206 regmap_update_bits(max9867->regmap, MAX9867_AUDIOCLKHIGH,
207 MAX9867_PLL, MAX9867_PLL);
208 } else {
209 unsigned long int bclk_rate, pclk_bclk_ratio;
210 int bclk_value;
211
212 bclk_rate = params_rate(params) * 2 * params_width(params);
213 pclk_bclk_ratio = max9867->pclk/bclk_rate;
214 switch (params_width(params)) {
215 case 8:
216 case 16:
217 switch (pclk_bclk_ratio) {
218 case 2:
219 bclk_value = MAX9867_IFC1B_PCLK_2;
220 break;
221 case 4:
222 bclk_value = MAX9867_IFC1B_PCLK_4;
223 break;
224 case 8:
225 bclk_value = MAX9867_IFC1B_PCLK_8;
226 break;
227 case 16:
228 bclk_value = MAX9867_IFC1B_PCLK_16;
229 break;
230 default:
231 dev_err(codec->dev,
232 "unsupported sampling rate\n");
233 return -EINVAL;
234 }
235 break;
236 case 24:
237 bclk_value = MAX9867_IFC1B_24BIT;
238 break;
239 case 32:
240 bclk_value = MAX9867_IFC1B_32BIT;
241 break;
242 default:
243 dev_err(codec->dev, "unsupported sampling rate\n");
244 return -EINVAL;
245 }
246 regmap_update_bits(max9867->regmap, MAX9867_IFC1B,
247 MAX9867_IFC1B_BCLK_MASK, bclk_value);
248 }
249 return 0;
250}
251
252static int max9867_prepare(struct snd_pcm_substream *substream,
253 struct snd_soc_dai *dai)
254{
255 struct snd_soc_codec *codec = dai->codec;
256 struct max9867_priv *max9867 = snd_soc_codec_get_drvdata(codec);
257
258 regmap_update_bits(max9867->regmap, MAX9867_PWRMAN,
259 MAX9867_SHTDOWN_MASK, MAX9867_SHTDOWN_MASK);
260 return 0;
261}
262
263static int max9867_mute(struct snd_soc_dai *dai, int mute)
264{
265 struct snd_soc_codec *codec = dai->codec;
266 struct max9867_priv *max9867 = snd_soc_codec_get_drvdata(codec);
267
268 if (mute)
269 regmap_update_bits(max9867->regmap, MAX9867_DACLEVEL,
270 MAX9867_DAC_MUTE_MASK, MAX9867_DAC_MUTE_MASK);
271 else
272 regmap_update_bits(max9867->regmap, MAX9867_DACLEVEL,
273 MAX9867_DAC_MUTE_MASK, 0);
274 return 0;
275}
276
277static int max9867_set_dai_sysclk(struct snd_soc_dai *codec_dai,
278 int clk_id, unsigned int freq, int dir)
279{
280 struct snd_soc_codec *codec = codec_dai->codec;
281 struct max9867_priv *max9867 = snd_soc_codec_get_drvdata(codec);
282 int value = 0;
283
284 /* Set the prescaler based on the master clock frequency*/
285 if (freq >= 10000000 && freq <= 20000000) {
286 value |= MAX9867_PSCLK_10_20;
287 max9867->pclk = freq;
288 } else if (freq >= 20000000 && freq <= 40000000) {
289 value |= MAX9867_PSCLK_20_40;
290 max9867->pclk = freq/2;
291 } else if (freq >= 40000000 && freq <= 60000000) {
292 value |= MAX9867_PSCLK_40_60;
293 max9867->pclk = freq/4;
294 } else {
295 pr_err("bad clock frequency %d", freq);
296 return -EINVAL;
297 }
298 value = value << MAX9867_PSCLK_SHIFT;
299 max9867->sysclk = freq;
300 /* exact integer mode is not supported */
301 value &= ~MAX9867_FREQ_MASK;
302 regmap_update_bits(max9867->regmap, MAX9867_SYSCLK,
303 MAX9867_PSCLK_MASK, value);
304 return 0;
305}
306
307static int max9867_dai_set_fmt(struct snd_soc_dai *codec_dai,
308 unsigned int fmt)
309{
310 struct snd_soc_codec *codec = codec_dai->codec;
311 struct max9867_priv *max9867 = snd_soc_codec_get_drvdata(codec);
312 u8 iface1A = 0, iface1B = 0;
313 int ret;
314
315 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
316 case SND_SOC_DAIFMT_CBM_CFM:
317 max9867->master = 1;
318 iface1A |= MAX9867_MASTER;
319 break;
320 case SND_SOC_DAIFMT_CBS_CFS:
321 max9867->master = 0;
322 iface1A &= ~MAX9867_MASTER;
323 break;
324 default:
325 return -EINVAL;
326 }
327
328 /* for i2s compatible mode */
329 iface1A |= MAX9867_I2S_DLY;
330 /* SDOUT goes to hiz state after all data is transferred */
331 iface1A |= MAX9867_SDOUT_HIZ;
332
333 /* Clock inversion bits, BCI and WCI */
334 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
335 case SND_SOC_DAIFMT_NB_NF:
336 break;
337 case SND_SOC_DAIFMT_IB_IF:
338 iface1A |= MAX9867_WCI_MODE | MAX9867_BCI_MODE;
339 break;
340 case SND_SOC_DAIFMT_IB_NF:
341 iface1A |= MAX9867_BCI_MODE;
342 break;
343 case SND_SOC_DAIFMT_NB_IF:
344 iface1A |= MAX9867_WCI_MODE;
345 break;
346 default:
347 return -EINVAL;
348 }
349
350 ret = regmap_write(max9867->regmap, MAX9867_IFC1A, iface1A);
351 ret = regmap_write(max9867->regmap, MAX9867_IFC1B, iface1B);
352 return 0;
353}
354
355static struct snd_soc_dai_ops max9867_dai_ops = {
356 .set_fmt = max9867_dai_set_fmt,
357 .set_sysclk = max9867_set_dai_sysclk,
358 .prepare = max9867_prepare,
359 .digital_mute = max9867_mute,
360 .hw_params = max9867_dai_hw_params,
361};
362
363#define MAX9867_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
364 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
365#define MAX9867_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
366
367static struct snd_soc_dai_driver max9867_dai[] = {
368 {
369 .name = "max9867-aif1",
370 .playback = {
371 .stream_name = "HiFi Playback",
372 .channels_min = 1,
373 .channels_max = 2,
374 .rates = MAX9867_RATES,
375 .formats = MAX9867_FORMATS,
376 },
377 .capture = {
378 .stream_name = "HiFi Capture",
379 .channels_min = 1,
380 .channels_max = 2,
381 .rates = MAX9867_RATES,
382 .formats = MAX9867_FORMATS,
383 },
384 .ops = &max9867_dai_ops,
385 }
386};
387
388#ifdef CONFIG_PM_SLEEP
389static int max9867_suspend(struct device *dev)
390{
391 struct max9867_priv *max9867 = dev_get_drvdata(dev);
392
393 /* Drop down to power saving mode when system is suspended */
394 regmap_update_bits(max9867->regmap, MAX9867_PWRMAN,
395 MAX9867_SHTDOWN_MASK, ~MAX9867_SHTDOWN_MASK);
396 return 0;
397}
398
399static int max9867_resume(struct device *dev)
400{
401 struct max9867_priv *max9867 = dev_get_drvdata(dev);
402
403 regmap_update_bits(max9867->regmap, MAX9867_PWRMAN,
404 MAX9867_SHTDOWN_MASK, MAX9867_SHTDOWN_MASK);
405 return 0;
406}
407#endif
408
409static int max9867_probe(struct snd_soc_codec *codec)
410{
411 struct max9867_priv *max9867 = snd_soc_codec_get_drvdata(codec);
412
413 dev_dbg(codec->dev, "max98090_probe\n");
414 max9867->codec = codec;
415 return 0;
416}
417
418static struct snd_soc_codec_driver max9867_codec = {
419 .probe = max9867_probe,
420 .controls = max9867_snd_controls,
421 .num_controls = ARRAY_SIZE(max9867_snd_controls),
422 .dapm_routes = max9867_audio_map,
423 .num_dapm_routes = ARRAY_SIZE(max9867_audio_map),
424 .dapm_widgets = max9867_dapm_widgets,
425 .num_dapm_widgets = ARRAY_SIZE(max9867_dapm_widgets),
426};
427
428static bool max9867_volatile_register(struct device *dev, unsigned int reg)
429{
430 switch (reg) {
431 case MAX9867_STATUS:
432 case MAX9867_JACKSTATUS:
433 case MAX9867_AUXHIGH:
434 case MAX9867_AUXLOW:
435 return true;
436 default:
437 return false;
438 }
439}
440
441static const struct reg_default max9867_reg[] = {
442 { 0x04, 0x00 },
443 { 0x05, 0x00 },
444 { 0x06, 0x00 },
445 { 0x07, 0x00 },
446 { 0x08, 0x00 },
447 { 0x09, 0x00 },
448 { 0x0A, 0x00 },
449 { 0x0B, 0x00 },
450 { 0x0C, 0x00 },
451 { 0x0D, 0x00 },
452 { 0x0E, 0x00 },
453 { 0x0F, 0x00 },
454 { 0x10, 0x00 },
455 { 0x11, 0x00 },
456 { 0x12, 0x00 },
457 { 0x13, 0x00 },
458 { 0x14, 0x00 },
459 { 0x15, 0x00 },
460 { 0x16, 0x00 },
461 { 0x17, 0x00 },
462};
463
464static const struct regmap_config max9867_regmap = {
465 .reg_bits = 8,
466 .val_bits = 8,
467 .max_register = MAX9867_REVISION,
468 .reg_defaults = max9867_reg,
469 .num_reg_defaults = ARRAY_SIZE(max9867_reg),
470 .volatile_reg = max9867_volatile_register,
471 .cache_type = REGCACHE_RBTREE,
472};
473
474static int max9867_i2c_probe(struct i2c_client *i2c,
475 const struct i2c_device_id *id)
476{
477 struct max9867_priv *max9867;
478 int ret = 0, reg;
479
480 max9867 = devm_kzalloc(&i2c->dev,
481 sizeof(*max9867), GFP_KERNEL);
482 if (!max9867)
483 return -ENOMEM;
484
485 i2c_set_clientdata(i2c, max9867);
486 max9867->regmap = devm_regmap_init_i2c(i2c, &max9867_regmap);
487 if (IS_ERR(max9867->regmap)) {
488 ret = PTR_ERR(max9867->regmap);
489 dev_err(&i2c->dev,
490 "Failed to allocate regmap: %d\n", ret);
491 return ret;
492 }
493 ret = regmap_read(max9867->regmap,
494 MAX9867_REVISION, &reg);
495 if (ret < 0) {
496 dev_err(&i2c->dev, "Failed to read: %d\n", ret);
497 return ret;
498 }
499 dev_info(&i2c->dev, "device revision: %x\n", reg);
500 ret = snd_soc_register_codec(&i2c->dev, &max9867_codec,
501 max9867_dai, ARRAY_SIZE(max9867_dai));
502 if (ret < 0) {
503 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
504 return ret;
505 }
506 return ret;
507}
508
509static int max9867_i2c_remove(struct i2c_client *client)
510{
511 snd_soc_unregister_codec(&client->dev);
512 return 0;
513}
514
515static const struct i2c_device_id max9867_i2c_id[] = {
516 { "max9867", 0 },
517 { }
518};
519
520static const struct of_device_id max9867_of_match[] = {
521 { .compatible = "maxim,max9867", },
522 { }
523};
524
525MODULE_DEVICE_TABLE(i2c, max9867_i2c_id);
526
527static const struct dev_pm_ops max9867_pm_ops = {
528 SET_SYSTEM_SLEEP_PM_OPS(max9867_suspend, max9867_resume)
529};
530
531static struct i2c_driver max9867_i2c_driver = {
532 .driver = {
533 .name = "max9867",
534 .of_match_table = of_match_ptr(max9867_of_match),
535 .pm = &max9867_pm_ops,
536 },
537 .probe = max9867_i2c_probe,
538 .remove = max9867_i2c_remove,
539 .id_table = max9867_i2c_id,
540};
541
542module_i2c_driver(max9867_i2c_driver);
543
544MODULE_AUTHOR("anish kumar <yesanishhere@gmail.com>");
545MODULE_DESCRIPTION("ALSA SoC MAX9867 driver");
546MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/max9867.h b/sound/soc/codecs/max9867.h
new file mode 100755
index 000000000000..65590b4ad62a
--- /dev/null
+++ b/sound/soc/codecs/max9867.h
@@ -0,0 +1,83 @@
1/*
2 * max9867.h -- MAX9867 ALSA SoC Audio driver
3 *
4 * Copyright 2013-2015 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef _MAX9867_H
12#define _MAX9867_H
13
14/* MAX9867 register space */
15
16#define MAX9867_STATUS 0x00
17#define MAX9867_JACKSTATUS 0x01
18#define MAX9867_AUXHIGH 0x02
19#define MAX9867_AUXLOW 0x03
20#define MAX9867_INTEN 0x04
21#define MAX9867_SYSCLK 0x05
22#define MAX9867_FREQ_MASK 0xF
23#define MAX9867_PSCLK_SHIFT 0x4
24#define MAX9867_PSCLK_WIDTH 0x2
25#define MAX9867_PSCLK_MASK (0x03<<MAX9867_PSCLK_SHIFT)
26#define MAX9867_PSCLK_10_20 0x1
27#define MAX9867_PSCLK_20_40 0x2
28#define MAX9867_PSCLK_40_60 0x3
29#define MAX9867_AUDIOCLKHIGH 0x06
30#define MAX9867_NI_HIGH_WIDTH 0x7
31#define MAX9867_NI_HIGH_MASK 0x7F
32#define MAX9867_NI_LOW_MASK 0x7F
33#define MAX9867_NI_LOW_SHIFT 0x1
34#define MAX9867_PLL (1<<7)
35#define MAX9867_AUDIOCLKLOW 0x07
36#define MAX9867_RAPID_LOCK 0x01
37#define MAX9867_IFC1A 0x08
38#define MAX9867_MASTER (1<<7)
39#define MAX9867_I2S_DLY (1<<4)
40#define MAX9867_SDOUT_HIZ (1<<3)
41#define MAX9867_TDM_MODE (1<<2)
42#define MAX9867_WCI_MODE (1<<6)
43#define MAX9867_BCI_MODE (1<<5)
44#define MAX9867_IFC1B 0x09
45#define MAX9867_IFC1B_BCLK_MASK 7
46#define MAX9867_IFC1B_32BIT 0x01
47#define MAX9867_IFC1B_24BIT 0x02
48#define MAX9867_IFC1B_PCLK_2 4
49#define MAX9867_IFC1B_PCLK_4 5
50#define MAX9867_IFC1B_PCLK_8 6
51#define MAX9867_IFC1B_PCLK_16 7
52#define MAX9867_CODECFLTR 0x0a
53#define MAX9867_DACGAIN 0x0b
54#define MAX9867_DACLEVEL 0x0c
55#define MAX9867_DAC_MUTE_SHIFT 0x6
56#define MAX9867_DAC_MUTE_WIDTH 0x1
57#define MAX9867_DAC_MUTE_MASK (0x1<<MAX9867_DAC_MUTE_SHIFT)
58#define MAX9867_ADCLEVEL 0x0d
59#define MAX9867_LEFTLINELVL 0x0e
60#define MAX9867_RIGTHLINELVL 0x0f
61#define MAX9867_LEFTVOL 0x10
62#define MAX9867_RIGHTVOL 0x11
63#define MAX9867_LEFTMICGAIN 0x12
64#define MAX9867_RIGHTMICGAIN 0x13
65#define MAX9867_INPUTCONFIG 0x14
66#define MAX9867_INPUT_SHIFT 0x6
67#define MAX9867_MICCONFIG 0x15
68#define MAX9867_MODECONFIG 0x16
69#define MAX9867_PWRMAN 0x17
70#define MAX9867_SHTDOWN_MASK (1<<7)
71#define MAX9867_REVISION 0xff
72
73#define MAX9867_CACHEREGNUM 10
74
75/* codec private data */
76struct max9867_priv {
77 struct regmap *regmap;
78 struct snd_soc_codec *codec;
79 unsigned int sysclk;
80 unsigned int pclk;
81 unsigned int master;
82};
83#endif
diff --git a/sound/soc/codecs/max98926.c b/sound/soc/codecs/max98926.c
new file mode 100644
index 000000000000..5245e107de30
--- /dev/null
+++ b/sound/soc/codecs/max98926.c
@@ -0,0 +1,606 @@
1/*
2 * max98926.c -- ALSA SoC MAX98926 driver
3 * Copyright 2013-15 Maxim Integrated Products
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include <linux/delay.h>
9#include <linux/i2c.h>
10#include <linux/module.h>
11#include <linux/regmap.h>
12#include <linux/slab.h>
13#include <linux/cdev.h>
14#include <sound/pcm.h>
15#include <sound/pcm_params.h>
16#include <sound/soc.h>
17#include <sound/tlv.h>
18#include "max98926.h"
19
20static const char * const max98926_boost_voltage_txt[] = {
21 "8.5V", "8.25V", "8.0V", "7.75V", "7.5V", "7.25V", "7.0V", "6.75V",
22 "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V"
23};
24
25static const char * const max98926_boost_current_txt[] = {
26 "0.6", "0.8", "1.0", "1.2", "1.4", "1.6", "1.8", "2.0",
27 "2.2", "2.4", "2.6", "2.8", "3.2", "3.6", "4.0", "4.4"
28};
29
30static const char *const max98926_dai_txt[] = {
31 "Left", "Right", "LeftRight", "LeftRightDiv2",
32};
33
34static const char *const max98926_pdm_ch_text[] = {
35 "Current", "Voltage",
36};
37
38static const char *const max98926_hpf_cutoff_txt[] = {
39 "Disable", "DC Block", "100Hz",
40 "200Hz", "400Hz", "800Hz",
41};
42
43static struct reg_default max98926_reg[] = {
44 { 0x0B, 0x00 }, /* IRQ Enable0 */
45 { 0x0C, 0x00 }, /* IRQ Enable1 */
46 { 0x0D, 0x00 }, /* IRQ Enable2 */
47 { 0x0E, 0x00 }, /* IRQ Clear0 */
48 { 0x0F, 0x00 }, /* IRQ Clear1 */
49 { 0x10, 0x00 }, /* IRQ Clear2 */
50 { 0x11, 0xC0 }, /* Map0 */
51 { 0x12, 0x00 }, /* Map1 */
52 { 0x13, 0x00 }, /* Map2 */
53 { 0x14, 0xF0 }, /* Map3 */
54 { 0x15, 0x00 }, /* Map4 */
55 { 0x16, 0xAB }, /* Map5 */
56 { 0x17, 0x89 }, /* Map6 */
57 { 0x18, 0x00 }, /* Map7 */
58 { 0x19, 0x00 }, /* Map8 */
59 { 0x1A, 0x04 }, /* DAI Clock Mode 1 */
60 { 0x1B, 0x00 }, /* DAI Clock Mode 2 */
61 { 0x1C, 0x00 }, /* DAI Clock Divider Denominator MSBs */
62 { 0x1D, 0x00 }, /* DAI Clock Divider Denominator LSBs */
63 { 0x1E, 0xF0 }, /* DAI Clock Divider Numerator MSBs */
64 { 0x1F, 0x00 }, /* DAI Clock Divider Numerator LSBs */
65 { 0x20, 0x50 }, /* Format */
66 { 0x21, 0x00 }, /* TDM Slot Select */
67 { 0x22, 0x00 }, /* DOUT Configuration VMON */
68 { 0x23, 0x00 }, /* DOUT Configuration IMON */
69 { 0x24, 0x00 }, /* DOUT Configuration VBAT */
70 { 0x25, 0x00 }, /* DOUT Configuration VBST */
71 { 0x26, 0x00 }, /* DOUT Configuration FLAG */
72 { 0x27, 0xFF }, /* DOUT HiZ Configuration 1 */
73 { 0x28, 0xFF }, /* DOUT HiZ Configuration 2 */
74 { 0x29, 0xFF }, /* DOUT HiZ Configuration 3 */
75 { 0x2A, 0xFF }, /* DOUT HiZ Configuration 4 */
76 { 0x2B, 0x02 }, /* DOUT Drive Strength */
77 { 0x2C, 0x90 }, /* Filters */
78 { 0x2D, 0x00 }, /* Gain */
79 { 0x2E, 0x02 }, /* Gain Ramping */
80 { 0x2F, 0x00 }, /* Speaker Amplifier */
81 { 0x30, 0x0A }, /* Threshold */
82 { 0x31, 0x00 }, /* ALC Attack */
83 { 0x32, 0x80 }, /* ALC Atten and Release */
84 { 0x33, 0x00 }, /* ALC Infinite Hold Release */
85 { 0x34, 0x92 }, /* ALC Configuration */
86 { 0x35, 0x01 }, /* Boost Converter */
87 { 0x36, 0x00 }, /* Block Enable */
88 { 0x37, 0x00 }, /* Configuration */
89 { 0x38, 0x00 }, /* Global Enable */
90 { 0x3A, 0x00 }, /* Boost Limiter */
91};
92
93static const struct soc_enum max98926_voltage_enum[] = {
94 SOC_ENUM_SINGLE(MAX98926_DAI_CLK_DIV_N_LSBS, 0,
95 ARRAY_SIZE(max98926_pdm_ch_text),
96 max98926_pdm_ch_text),
97};
98
99static const struct snd_kcontrol_new max98926_voltage_control =
100 SOC_DAPM_ENUM("Route", max98926_voltage_enum);
101
102static const struct soc_enum max98926_current_enum[] = {
103 SOC_ENUM_SINGLE(MAX98926_DAI_CLK_DIV_N_LSBS,
104 MAX98926_PDM_SOURCE_1_SHIFT,
105 ARRAY_SIZE(max98926_pdm_ch_text),
106 max98926_pdm_ch_text),
107};
108
109static const struct snd_kcontrol_new max98926_current_control =
110 SOC_DAPM_ENUM("Route", max98926_current_enum);
111
112static const struct snd_kcontrol_new max98926_mixer_controls[] = {
113 SOC_DAPM_SINGLE("PCM Single Switch", MAX98926_SPK_AMP,
114 MAX98926_INSELECT_MODE_SHIFT, 0, 0),
115 SOC_DAPM_SINGLE("PDM Single Switch", MAX98926_SPK_AMP,
116 MAX98926_INSELECT_MODE_SHIFT, 1, 0),
117};
118
119static const struct snd_kcontrol_new max98926_dai_controls[] = {
120 SOC_DAPM_SINGLE("Left", MAX98926_GAIN,
121 MAX98926_DAC_IN_SEL_SHIFT, 0, 0),
122 SOC_DAPM_SINGLE("Right", MAX98926_GAIN,
123 MAX98926_DAC_IN_SEL_SHIFT, 1, 0),
124 SOC_DAPM_SINGLE("LeftRight", MAX98926_GAIN,
125 MAX98926_DAC_IN_SEL_SHIFT, 2, 0),
126 SOC_DAPM_SINGLE("(Left+Right)/2 Switch", MAX98926_GAIN,
127 MAX98926_DAC_IN_SEL_SHIFT, 3, 0),
128};
129
130static const struct snd_soc_dapm_widget max98926_dapm_widgets[] = {
131 SND_SOC_DAPM_AIF_IN("DAI_OUT", "HiFi Playback", 0,
132 SND_SOC_NOPM, 0, 0),
133 SND_SOC_DAPM_DAC("Amp Enable", NULL, MAX98926_BLOCK_ENABLE,
134 MAX98926_SPK_EN_SHIFT, 0),
135 SND_SOC_DAPM_SUPPLY("Global Enable", MAX98926_GLOBAL_ENABLE,
136 MAX98926_EN_SHIFT, 0, NULL, 0),
137 SND_SOC_DAPM_SUPPLY("VI Enable", MAX98926_BLOCK_ENABLE,
138 MAX98926_ADC_IMON_EN_WIDTH |
139 MAX98926_ADC_VMON_EN_SHIFT,
140 0, NULL, 0),
141 SND_SOC_DAPM_PGA("BST Enable", MAX98926_BLOCK_ENABLE,
142 MAX98926_BST_EN_SHIFT, 0, NULL, 0),
143 SND_SOC_DAPM_OUTPUT("BE_OUT"),
144 SND_SOC_DAPM_MIXER("PCM Sel", MAX98926_SPK_AMP,
145 MAX98926_INSELECT_MODE_SHIFT, 0,
146 &max98926_mixer_controls[0],
147 ARRAY_SIZE(max98926_mixer_controls)),
148 SND_SOC_DAPM_MIXER("DAI Sel",
149 MAX98926_GAIN, MAX98926_DAC_IN_SEL_SHIFT, 0,
150 &max98926_dai_controls[0],
151 ARRAY_SIZE(max98926_dai_controls)),
152 SND_SOC_DAPM_MUX("PDM CH1 Source",
153 MAX98926_DAI_CLK_DIV_N_LSBS,
154 MAX98926_PDM_CURRENT_SHIFT,
155 0, &max98926_current_control),
156 SND_SOC_DAPM_MUX("PDM CH0 Source",
157 MAX98926_DAI_CLK_DIV_N_LSBS,
158 MAX98926_PDM_VOLTAGE_SHIFT,
159 0, &max98926_voltage_control),
160};
161
162static const struct snd_soc_dapm_route max98926_audio_map[] = {
163 {"VI Enable", NULL, "DAI_OUT"},
164 {"DAI Sel", "Left", "VI Enable"},
165 {"DAI Sel", "Right", "VI Enable"},
166 {"DAI Sel", "LeftRight", "VI Enable"},
167 {"DAI Sel", "LeftRightDiv2", "VI Enable"},
168 {"PCM Sel", "PCM", "DAI Sel"},
169
170 {"PDM CH1 Source", "Current", "DAI_OUT"},
171 {"PDM CH1 Source", "Voltage", "DAI_OUT"},
172 {"PDM CH0 Source", "Current", "DAI_OUT"},
173 {"PDM CH0 Source", "Voltage", "DAI_OUT"},
174 {"PCM Sel", "Analog", "PDM CH1 Source"},
175 {"PCM Sel", "Analog", "PDM CH0 Source"},
176 {"Amp Enable", NULL, "PCM Sel"},
177
178 {"BST Enable", NULL, "Amp Enable"},
179 {"BE_OUT", NULL, "BST Enable"},
180};
181
182static bool max98926_volatile_register(struct device *dev, unsigned int reg)
183{
184 switch (reg) {
185 case MAX98926_VBAT_DATA:
186 case MAX98926_VBST_DATA:
187 case MAX98926_LIVE_STATUS0:
188 case MAX98926_LIVE_STATUS1:
189 case MAX98926_LIVE_STATUS2:
190 case MAX98926_STATE0:
191 case MAX98926_STATE1:
192 case MAX98926_STATE2:
193 case MAX98926_FLAG0:
194 case MAX98926_FLAG1:
195 case MAX98926_FLAG2:
196 case MAX98926_VERSION:
197 return true;
198 default:
199 return false;
200 }
201}
202
203static bool max98926_readable_register(struct device *dev, unsigned int reg)
204{
205 switch (reg) {
206 case MAX98926_IRQ_CLEAR0:
207 case MAX98926_IRQ_CLEAR1:
208 case MAX98926_IRQ_CLEAR2:
209 case MAX98926_ALC_HOLD_RLS:
210 return false;
211 default:
212 return true;
213 }
214};
215
216DECLARE_TLV_DB_SCALE(max98926_spk_tlv, -600, 100, 0);
217DECLARE_TLV_DB_RANGE(max98926_current_tlv,
218 0, 11, TLV_DB_SCALE_ITEM(20, 20, 0),
219 12, 15, TLV_DB_SCALE_ITEM(320, 40, 0),
220);
221
222static SOC_ENUM_SINGLE_DECL(max98926_dac_hpf_cutoff,
223 MAX98926_FILTERS, MAX98926_DAC_HPF_SHIFT,
224 max98926_hpf_cutoff_txt);
225
226static SOC_ENUM_SINGLE_DECL(max98926_boost_voltage,
227 MAX98926_CONFIGURATION, MAX98926_BST_VOUT_SHIFT,
228 max98926_boost_voltage_txt);
229
230static const struct snd_kcontrol_new max98926_snd_controls[] = {
231 SOC_SINGLE_TLV("Speaker Volume", MAX98926_GAIN,
232 MAX98926_SPK_GAIN_SHIFT,
233 (1<<MAX98926_SPK_GAIN_WIDTH)-1, 0,
234 max98926_spk_tlv),
235 SOC_SINGLE("Ramp Switch", MAX98926_GAIN_RAMPING,
236 MAX98926_SPK_RMP_EN_SHIFT, 1, 0),
237 SOC_SINGLE("ZCD Switch", MAX98926_GAIN_RAMPING,
238 MAX98926_SPK_ZCD_EN_SHIFT, 1, 0),
239 SOC_SINGLE("ALC Switch", MAX98926_THRESHOLD,
240 MAX98926_ALC_EN_SHIFT, 1, 0),
241 SOC_SINGLE("ALC Threshold", MAX98926_THRESHOLD,
242 MAX98926_ALC_TH_SHIFT,
243 (1<<MAX98926_ALC_TH_WIDTH)-1, 0),
244 SOC_ENUM("Boost Output Voltage", max98926_boost_voltage),
245 SOC_SINGLE_TLV("Boost Current Limit", MAX98926_BOOST_LIMITER,
246 MAX98926_BST_ILIM_SHIFT,
247 (1<<MAX98926_BST_ILIM_SHIFT)-1, 0,
248 max98926_current_tlv),
249 SOC_ENUM("DAC HPF Cutoff", max98926_dac_hpf_cutoff),
250 SOC_DOUBLE("PDM Channel One", MAX98926_DAI_CLK_DIV_N_LSBS,
251 MAX98926_PDM_CHANNEL_1_SHIFT,
252 MAX98926_PDM_CHANNEL_1_HIZ, 1, 0),
253 SOC_DOUBLE("PDM Channel Zero", MAX98926_DAI_CLK_DIV_N_LSBS,
254 MAX98926_PDM_CHANNEL_0_SHIFT,
255 MAX98926_PDM_CHANNEL_0_HIZ, 1, 0),
256};
257
258static const struct {
259 int rate;
260 int sr;
261} rate_table[] = {
262 {
263 .rate = 8000,
264 .sr = 0,
265 },
266 {
267 .rate = 11025,
268 .sr = 1,
269 },
270 {
271 .rate = 12000,
272 .sr = 2,
273 },
274 {
275 .rate = 16000,
276 .sr = 3,
277 },
278 {
279 .rate = 22050,
280 .sr = 4,
281 },
282 {
283 .rate = 24000,
284 .sr = 5,
285 },
286 {
287 .rate = 32000,
288 .sr = 6,
289 },
290 {
291 .rate = 44100,
292 .sr = 7,
293 },
294 {
295 .rate = 48000,
296 .sr = 8,
297 },
298};
299
300static void max98926_set_sense_data(struct max98926_priv *max98926)
301{
302 regmap_update_bits(max98926->regmap,
303 MAX98926_DOUT_CFG_VMON,
304 MAX98926_DAI_VMON_EN_MASK,
305 MAX98926_DAI_VMON_EN_MASK);
306 regmap_update_bits(max98926->regmap,
307 MAX98926_DOUT_CFG_IMON,
308 MAX98926_DAI_IMON_EN_MASK,
309 MAX98926_DAI_IMON_EN_MASK);
310
311 if (!max98926->interleave_mode) {
312 /* set VMON slots */
313 regmap_update_bits(max98926->regmap,
314 MAX98926_DOUT_CFG_VMON,
315 MAX98926_DAI_VMON_SLOT_MASK,
316 max98926->v_slot);
317 /* set IMON slots */
318 regmap_update_bits(max98926->regmap,
319 MAX98926_DOUT_CFG_IMON,
320 MAX98926_DAI_IMON_SLOT_MASK,
321 max98926->i_slot);
322 } else {
323 /* enable interleave mode */
324 regmap_update_bits(max98926->regmap,
325 MAX98926_FORMAT,
326 MAX98926_DAI_INTERLEAVE_MASK,
327 MAX98926_DAI_INTERLEAVE_MASK);
328 /* set interleave slots */
329 regmap_update_bits(max98926->regmap,
330 MAX98926_DOUT_CFG_VBAT,
331 MAX98926_DAI_INTERLEAVE_SLOT_MASK,
332 max98926->v_slot);
333 }
334}
335
336static int max98926_dai_set_fmt(struct snd_soc_dai *codec_dai,
337 unsigned int fmt)
338{
339 struct snd_soc_codec *codec = codec_dai->codec;
340 struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
341 unsigned int invert = 0;
342
343 dev_dbg(codec->dev, "%s: fmt 0x%08X\n", __func__, fmt);
344
345 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
346 case SND_SOC_DAIFMT_CBS_CFS:
347 max98926_set_sense_data(max98926);
348 break;
349 default:
350 dev_err(codec->dev, "DAI clock mode unsupported");
351 return -EINVAL;
352 }
353
354 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
355 case SND_SOC_DAIFMT_NB_NF:
356 break;
357 case SND_SOC_DAIFMT_NB_IF:
358 invert = MAX98926_DAI_WCI_MASK;
359 break;
360 case SND_SOC_DAIFMT_IB_NF:
361 invert = MAX98926_DAI_BCI_MASK;
362 break;
363 case SND_SOC_DAIFMT_IB_IF:
364 invert = MAX98926_DAI_BCI_MASK | MAX98926_DAI_WCI_MASK;
365 break;
366 default:
367 dev_err(codec->dev, "DAI invert mode unsupported");
368 return -EINVAL;
369 }
370
371 regmap_write(max98926->regmap,
372 MAX98926_FORMAT, MAX98926_DAI_DLY_MASK);
373 regmap_update_bits(max98926->regmap, MAX98926_FORMAT,
374 MAX98926_DAI_BCI_MASK, invert);
375 return 0;
376}
377
378static int max98926_dai_hw_params(struct snd_pcm_substream *substream,
379 struct snd_pcm_hw_params *params,
380 struct snd_soc_dai *dai)
381{
382 int dai_sr = -EINVAL;
383 int rate = params_rate(params), i;
384 struct snd_soc_codec *codec = dai->codec;
385 struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
386 int blr_clk_ratio;
387
388 switch (params_format(params)) {
389 case SNDRV_PCM_FORMAT_S16_LE:
390 regmap_update_bits(max98926->regmap,
391 MAX98926_FORMAT,
392 MAX98926_DAI_CHANSZ_MASK,
393 MAX98926_DAI_CHANSZ_16);
394 max98926->ch_size = 16;
395 break;
396 case SNDRV_PCM_FORMAT_S24_LE:
397 regmap_update_bits(max98926->regmap,
398 MAX98926_FORMAT,
399 MAX98926_DAI_CHANSZ_MASK,
400 MAX98926_DAI_CHANSZ_24);
401 max98926->ch_size = 24;
402 break;
403 case SNDRV_PCM_FORMAT_S32_LE:
404 regmap_update_bits(max98926->regmap,
405 MAX98926_FORMAT,
406 MAX98926_DAI_CHANSZ_MASK,
407 MAX98926_DAI_CHANSZ_32);
408 max98926->ch_size = 32;
409 break;
410 default:
411 dev_dbg(codec->dev, "format unsupported %d",
412 params_format(params));
413 return -EINVAL;
414 }
415
416 /* BCLK/LRCLK ratio calculation */
417 blr_clk_ratio = params_channels(params) * max98926->ch_size;
418
419 switch (blr_clk_ratio) {
420 case 32:
421 regmap_update_bits(max98926->regmap,
422 MAX98926_DAI_CLK_MODE2,
423 MAX98926_DAI_BSEL_MASK,
424 MAX98926_DAI_BSEL_32);
425 break;
426 case 48:
427 regmap_update_bits(max98926->regmap,
428 MAX98926_DAI_CLK_MODE2,
429 MAX98926_DAI_BSEL_MASK,
430 MAX98926_DAI_BSEL_48);
431 break;
432 case 64:
433 regmap_update_bits(max98926->regmap,
434 MAX98926_DAI_CLK_MODE2,
435 MAX98926_DAI_BSEL_MASK,
436 MAX98926_DAI_BSEL_64);
437 break;
438 default:
439 return -EINVAL;
440 }
441
442 /* find the closest rate */
443 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
444 if (rate_table[i].rate >= rate) {
445 dai_sr = rate_table[i].sr;
446 break;
447 }
448 }
449 if (dai_sr < 0)
450 return -EINVAL;
451
452 /* set DAI_SR to correct LRCLK frequency */
453 regmap_update_bits(max98926->regmap,
454 MAX98926_DAI_CLK_MODE2,
455 MAX98926_DAI_SR_MASK, dai_sr << MAX98926_DAI_SR_SHIFT);
456 return 0;
457}
458
459#define MAX98926_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
460 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
461
462static struct snd_soc_dai_ops max98926_dai_ops = {
463 .set_fmt = max98926_dai_set_fmt,
464 .hw_params = max98926_dai_hw_params,
465};
466
467static struct snd_soc_dai_driver max98926_dai[] = {
468{
469 .name = "max98926-aif1",
470 .playback = {
471 .stream_name = "HiFi Playback",
472 .channels_min = 1,
473 .channels_max = 2,
474 .rates = SNDRV_PCM_RATE_8000_48000,
475 .formats = MAX98926_FORMATS,
476 },
477 .capture = {
478 .stream_name = "HiFi Capture",
479 .channels_min = 1,
480 .channels_max = 2,
481 .rates = SNDRV_PCM_RATE_8000_48000,
482 .formats = MAX98926_FORMATS,
483 },
484 .ops = &max98926_dai_ops,
485}
486};
487
488static int max98926_probe(struct snd_soc_codec *codec)
489{
490 struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
491
492 max98926->codec = codec;
493 codec->control_data = max98926->regmap;
494 /* Hi-Z all the slots */
495 regmap_write(max98926->regmap, MAX98926_DOUT_HIZ_CFG4, 0xF0);
496 return 0;
497}
498
499static struct snd_soc_codec_driver soc_codec_dev_max98926 = {
500 .probe = max98926_probe,
501 .controls = max98926_snd_controls,
502 .num_controls = ARRAY_SIZE(max98926_snd_controls),
503 .dapm_routes = max98926_audio_map,
504 .num_dapm_routes = ARRAY_SIZE(max98926_audio_map),
505 .dapm_widgets = max98926_dapm_widgets,
506 .num_dapm_widgets = ARRAY_SIZE(max98926_dapm_widgets),
507};
508
509static struct regmap_config max98926_regmap = {
510 .reg_bits = 8,
511 .val_bits = 8,
512 .max_register = MAX98926_VERSION,
513 .reg_defaults = max98926_reg,
514 .num_reg_defaults = ARRAY_SIZE(max98926_reg),
515 .volatile_reg = max98926_volatile_register,
516 .readable_reg = max98926_readable_register,
517 .cache_type = REGCACHE_RBTREE,
518};
519
520static int max98926_i2c_probe(struct i2c_client *i2c,
521 const struct i2c_device_id *id)
522{
523 int ret, reg;
524 u32 value;
525 struct max98926_priv *max98926;
526
527 max98926 = devm_kzalloc(&i2c->dev,
528 sizeof(*max98926), GFP_KERNEL);
529 if (!max98926)
530 return -ENOMEM;
531
532 i2c_set_clientdata(i2c, max98926);
533 max98926->regmap = devm_regmap_init_i2c(i2c, &max98926_regmap);
534 if (IS_ERR(max98926->regmap)) {
535 ret = PTR_ERR(max98926->regmap);
536 dev_err(&i2c->dev,
537 "Failed to allocate regmap: %d\n", ret);
538 goto err_out;
539 }
540 if (of_property_read_bool(i2c->dev.of_node, "interleave-mode"))
541 max98926->interleave_mode = true;
542
543 if (!of_property_read_u32(i2c->dev.of_node, "vmon-slot-no", &value)) {
544 if (value > MAX98926_DAI_VMON_SLOT_1E_1F) {
545 dev_err(&i2c->dev, "vmon slot number is wrong:\n");
546 return -EINVAL;
547 }
548 max98926->v_slot = value;
549 }
550 if (!of_property_read_u32(i2c->dev.of_node, "imon-slot-no", &value)) {
551 if (value > MAX98926_DAI_IMON_SLOT_1E_1F) {
552 dev_err(&i2c->dev, "imon slot number is wrong:\n");
553 return -EINVAL;
554 }
555 max98926->i_slot = value;
556 }
557 ret = regmap_read(max98926->regmap,
558 MAX98926_VERSION, &reg);
559 if (ret < 0) {
560 dev_err(&i2c->dev, "Failed to read: %x\n", reg);
561 return ret;
562 }
563
564 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98926,
565 max98926_dai, ARRAY_SIZE(max98926_dai));
566 if (ret < 0)
567 dev_err(&i2c->dev,
568 "Failed to register codec: %d\n", ret);
569 dev_info(&i2c->dev, "device version: %x\n", reg);
570err_out:
571 return ret;
572}
573
574static int max98926_i2c_remove(struct i2c_client *client)
575{
576 snd_soc_unregister_codec(&client->dev);
577 return 0;
578}
579
580static const struct i2c_device_id max98926_i2c_id[] = {
581 { "max98926", 0 },
582 { }
583};
584MODULE_DEVICE_TABLE(i2c, max98926_i2c_id);
585
586static const struct of_device_id max98926_of_match[] = {
587 { .compatible = "maxim,max98926", },
588 { }
589};
590MODULE_DEVICE_TABLE(of, max98926_of_match);
591
592static struct i2c_driver max98926_i2c_driver = {
593 .driver = {
594 .name = "max98926",
595 .of_match_table = of_match_ptr(max98926_of_match),
596 .pm = NULL,
597 },
598 .probe = max98926_i2c_probe,
599 .remove = max98926_i2c_remove,
600 .id_table = max98926_i2c_id,
601};
602
603module_i2c_driver(max98926_i2c_driver)
604MODULE_DESCRIPTION("ALSA SoC MAX98926 driver");
605MODULE_AUTHOR("Anish kumar <anish.kumar@maximintegrated.com>");
606MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/max98926.h b/sound/soc/codecs/max98926.h
new file mode 100644
index 000000000000..9d7ab6df79ca
--- /dev/null
+++ b/sound/soc/codecs/max98926.h
@@ -0,0 +1,848 @@
1/*
2 * max98926.h -- MAX98926 ALSA SoC Audio driver
3 * Copyright 2013-2015 Maxim Integrated Products
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef _MAX98926_H
10#define _MAX98926_H
11
12#define MAX98926_CHIP_VERSION 0x40
13#define MAX98926_CHIP_VERSION1 0x50
14
15#define MAX98926_VBAT_DATA 0x00
16#define MAX98926_VBST_DATA 0x01
17#define MAX98926_LIVE_STATUS0 0x02
18#define MAX98926_LIVE_STATUS1 0x03
19#define MAX98926_LIVE_STATUS2 0x04
20#define MAX98926_STATE0 0x05
21#define MAX98926_STATE1 0x06
22#define MAX98926_STATE2 0x07
23#define MAX98926_FLAG0 0x08
24#define MAX98926_FLAG1 0x09
25#define MAX98926_FLAG2 0x0A
26#define MAX98926_IRQ_ENABLE0 0x0B
27#define MAX98926_IRQ_ENABLE1 0x0C
28#define MAX98926_IRQ_ENABLE2 0x0D
29#define MAX98926_IRQ_CLEAR0 0x0E
30#define MAX98926_IRQ_CLEAR1 0x0F
31#define MAX98926_IRQ_CLEAR2 0x10
32#define MAX98926_MAP0 0x11
33#define MAX98926_MAP1 0x12
34#define MAX98926_MAP2 0x13
35#define MAX98926_MAP3 0x14
36#define MAX98926_MAP4 0x15
37#define MAX98926_MAP5 0x16
38#define MAX98926_MAP6 0x17
39#define MAX98926_MAP7 0x18
40#define MAX98926_MAP8 0x19
41#define MAX98926_DAI_CLK_MODE1 0x1A
42#define MAX98926_DAI_CLK_MODE2 0x1B
43#define MAX98926_DAI_CLK_DIV_M_MSBS 0x1C
44#define MAX98926_DAI_CLK_DIV_M_LSBS 0x1D
45#define MAX98926_DAI_CLK_DIV_N_MSBS 0x1E
46#define MAX98926_DAI_CLK_DIV_N_LSBS 0x1F
47#define MAX98926_FORMAT 0x20
48#define MAX98926_TDM_SLOT_SELECT 0x21
49#define MAX98926_DOUT_CFG_VMON 0x22
50#define MAX98926_DOUT_CFG_IMON 0x23
51#define MAX98926_DOUT_CFG_VBAT 0x24
52#define MAX98926_DOUT_CFG_VBST 0x25
53#define MAX98926_DOUT_CFG_FLAG 0x26
54#define MAX98926_DOUT_HIZ_CFG1 0x27
55#define MAX98926_DOUT_HIZ_CFG2 0x28
56#define MAX98926_DOUT_HIZ_CFG3 0x29
57#define MAX98926_DOUT_HIZ_CFG4 0x2A
58#define MAX98926_DOUT_DRV_STRENGTH 0x2B
59#define MAX98926_FILTERS 0x2C
60#define MAX98926_GAIN 0x2D
61#define MAX98926_GAIN_RAMPING 0x2E
62#define MAX98926_SPK_AMP 0x2F
63#define MAX98926_THRESHOLD 0x30
64#define MAX98926_ALC_ATTACK 0x31
65#define MAX98926_ALC_ATTEN_RLS 0x32
66#define MAX98926_ALC_HOLD_RLS 0x33
67#define MAX98926_ALC_CONFIGURATION 0x34
68#define MAX98926_BOOST_CONVERTER 0x35
69#define MAX98926_BLOCK_ENABLE 0x36
70#define MAX98926_CONFIGURATION 0x37
71#define MAX98926_GLOBAL_ENABLE 0x38
72#define MAX98926_BOOST_LIMITER 0x3A
73#define MAX98926_VERSION 0xFF
74
75#define MAX98926_REG_CNT (MAX98926_R03A_BOOST_LIMITER+1)
76
77#define MAX98926_PDM_CURRENT_MASK (1<<7)
78#define MAX98926_PDM_CURRENT_SHIFT 7
79#define MAX98926_PDM_VOLTAGE_MASK (1<<3)
80#define MAX98926_PDM_VOLTAGE_SHIFT 3
81#define MAX98926_PDM_CHANNEL_0_MASK (1<<2)
82#define MAX98926_PDM_CHANNEL_0_SHIFT 2
83#define MAX98926_PDM_CHANNEL_1_MASK (1<<6)
84#define MAX98926_PDM_CHANNEL_1_SHIFT 6
85#define MAX98926_PDM_CHANNEL_1_HIZ 5
86#define MAX98926_PDM_CHANNEL_0_HIZ 1
87#define MAX98926_PDM_SOURCE_0_SHIFT 0
88#define MAX98926_PDM_SOURCE_0_MASK (1<<0)
89#define MAX98926_PDM_SOURCE_1_MASK (1<<4)
90#define MAX98926_PDM_SOURCE_1_SHIFT 4
91
92/* MAX98926 Register Bit Fields */
93
94/* MAX98926_R002_LIVE_STATUS0 */
95#define MAX98926_THERMWARN_STATUS_MASK (1<<3)
96#define MAX98926_THERMWARN_STATUS_SHIFT 3
97#define MAX98926_THERMWARN_STATUS_WIDTH 1
98#define MAX98926_THERMSHDN_STATUS_MASK (1<<1)
99#define MAX98926_THERMSHDN_STATUS_SHIFT 1
100#define MAX98926_THERMSHDN_STATUS_WIDTH 1
101
102/* MAX98926_R003_LIVE_STATUS1 */
103#define MAX98926_SPKCURNT_STATUS_MASK (1<<5)
104#define MAX98926_SPKCURNT_STATUS_SHIFT 5
105#define MAX98926_SPKCURNT_STATUS_WIDTH 1
106#define MAX98926_WATCHFAIL_STATUS_MASK (1<<4)
107#define MAX98926_WATCHFAIL_STATUS_SHIFT 4
108#define MAX98926_WATCHFAIL_STATUS_WIDTH 1
109#define MAX98926_ALCINFH_STATUS_MASK (1<<3)
110#define MAX98926_ALCINFH_STATUS_SHIFT 3
111#define MAX98926_ALCINFH_STATUS_WIDTH 1
112#define MAX98926_ALCACT_STATUS_MASK (1<<2)
113#define MAX98926_ALCACT_STATUS_SHIFT 2
114#define MAX98926_ALCACT_STATUS_WIDTH 1
115#define MAX98926_ALCMUT_STATUS_MASK (1<<1)
116#define MAX98926_ALCMUT_STATUS_SHIFT 1
117#define MAX98926_ALCMUT_STATUS_WIDTH 1
118#define MAX98926_ACLP_STATUS_MASK (1<<0)
119#define MAX98926_ACLP_STATUS_SHIFT 0
120#define MAX98926_ACLP_STATUS_WIDTH 1
121
122/* MAX98926_R004_LIVE_STATUS2 */
123#define MAX98926_SLOTOVRN_STATUS_MASK (1<<6)
124#define MAX98926_SLOTOVRN_STATUS_SHIFT 6
125#define MAX98926_SLOTOVRN_STATUS_WIDTH 1
126#define MAX98926_INVALSLOT_STATUS_MASK (1<<5)
127#define MAX98926_INVALSLOT_STATUS_SHIFT 5
128#define MAX98926_INVALSLOT_STATUS_WIDTH 1
129#define MAX98926_SLOTCNFLT_STATUS_MASK (1<<4)
130#define MAX98926_SLOTCNFLT_STATUS_SHIFT 4
131#define MAX98926_SLOTCNFLT_STATUS_WIDTH 1
132#define MAX98926_VBSTOVFL_STATUS_MASK (1<<3)
133#define MAX98926_VBSTOVFL_STATUS_SHIFT 3
134#define MAX98926_VBSTOVFL_STATUS_WIDTH 1
135#define MAX98926_VBATOVFL_STATUS_MASK (1<<2)
136#define MAX98926_VBATOVFL_STATUS_SHIFT 2
137#define MAX98926_VBATOVFL_STATUS_WIDTH 1
138#define MAX98926_IMONOVFL_STATUS_MASK (1<<1)
139#define MAX98926_IMONOVFL_STATUS_SHIFT 1
140#define MAX98926_IMONOVFL_STATUS_WIDTH 1
141#define MAX98926_VMONOVFL_STATUS_MASK (1<<0)
142#define MAX98926_VMONOVFL_STATUS_SHIFT 0
143#define MAX98926_VMONOVFL_STATUS_WIDTH 1
144
145/* MAX98926_R005_STATE0 */
146#define MAX98926_THERMWARN_END_STATE_MASK (1<<3)
147#define MAX98926_THERMWARN_END_STATE_SHIFT 3
148#define MAX98926_THERMWARN_END_STATE_WIDTH 1
149#define MAX98926_THERMWARN_BGN_STATE_MASK (1<<2)
150#define MAX98926_THERMWARN_BGN_STATE_SHIFT 1
151#define MAX98926_THERMWARN_BGN_STATE_WIDTH 1
152#define MAX98926_THERMSHDN_END_STATE_MASK (1<<1)
153#define MAX98926_THERMSHDN_END_STATE_SHIFT 1
154#define MAX98926_THERMSHDN_END_STATE_WIDTH 1
155#define MAX98926_THERMSHDN_BGN_STATE_MASK (1<<0)
156#define MAX98926_THERMSHDN_BGN_STATE_SHIFT 0
157#define MAX98926_THERMSHDN_BGN_STATE_WIDTH 1
158
159/* MAX98926_R006_STATE1 */
160#define MAX98926_SPRCURNT_STATE_MASK (1<<5)
161#define MAX98926_SPRCURNT_STATE_SHIFT 5
162#define MAX98926_SPRCURNT_STATE_WIDTH 1
163#define MAX98926_WATCHFAIL_STATE_MASK (1<<4)
164#define MAX98926_WATCHFAIL_STATE_SHIFT 4
165#define MAX98926_WATCHFAIL_STATE_WIDTH 1
166#define MAX98926_ALCINFH_STATE_MASK (1<<3)
167#define MAX98926_ALCINFH_STATE_SHIFT 3
168#define MAX98926_ALCINFH_STATE_WIDTH 1
169#define MAX98926_ALCACT_STATE_MASK (1<<2)
170#define MAX98926_ALCACT_STATE_SHIFT 2
171#define MAX98926_ALCACT_STATE_WIDTH 1
172#define MAX98926_ALCMUT_STATE_MASK (1<<1)
173#define MAX98926_ALCMUT_STATE_SHIFT 1
174#define MAX98926_ALCMUT_STATE_WIDTH 1
175#define MAX98926_ALCP_STATE_MASK (1<<0)
176#define MAX98926_ALCP_STATE_SHIFT 0
177#define MAX98926_ALCP_STATE_WIDTH 1
178
179/* MAX98926_R007_STATE2 */
180#define MAX98926_SLOTOVRN_STATE_MASK (1<<6)
181#define MAX98926_SLOTOVRN_STATE_SHIFT 6
182#define MAX98926_SLOTOVRN_STATE_WIDTH 1
183#define MAX98926_INVALSLOT_STATE_MASK (1<<5)
184#define MAX98926_INVALSLOT_STATE_SHIFT 5
185#define MAX98926_INVALSLOT_STATE_WIDTH 1
186#define MAX98926_SLOTCNFLT_STATE_MASK (1<<4)
187#define MAX98926_SLOTCNFLT_STATE_SHIFT 4
188#define MAX98926_SLOTCNFLT_STATE_WIDTH 1
189#define MAX98926_VBSTOVFL_STATE_MASK (1<<3)
190#define MAX98926_VBSTOVFL_STATE_SHIFT 3
191#define MAX98926_VBSTOVFL_STATE_WIDTH 1
192#define MAX98926_VBATOVFL_STATE_MASK (1<<2)
193#define MAX98926_VBATOVFL_STATE_SHIFT 2
194#define MAX98926_VBATOVFL_STATE_WIDTH 1
195#define MAX98926_IMONOVFL_STATE_MASK (1<<1)
196#define MAX98926_IMONOVFL_STATE_SHIFT 1
197#define MAX98926_IMONOVFL_STATE_WIDTH 1
198#define MAX98926_VMONOVFL_STATE_MASK (1<<0)
199#define MAX98926_VMONOVFL_STATE_SHIFT 0
200#define MAX98926_VMONOVFL_STATE_WIDTH 1
201
202/* MAX98926_R008_FLAG0 */
203#define MAX98926_THERMWARN_END_FLAG_MASK (1<<3)
204#define MAX98926_THERMWARN_END_FLAG_SHIFT 3
205#define MAX98926_THERMWARN_END_FLAG_WIDTH 1
206#define MAX98926_THERMWARN_BGN_FLAG_MASK (1<<2)
207#define MAX98926_THERMWARN_BGN_FLAG_SHIFT 2
208#define MAX98926_THERMWARN_BGN_FLAG_WIDTH 1
209#define MAX98926_THERMSHDN_END_FLAG_MASK (1<<1)
210#define MAX98926_THERMSHDN_END_FLAG_SHIFT 1
211#define MAX98926_THERMSHDN_END_FLAG_WIDTH 1
212#define MAX98926_THERMSHDN_BGN_FLAG_MASK (1<<0)
213#define MAX98926_THERMSHDN_BGN_FLAG_SHIFT 0
214#define MAX98926_THERMSHDN_BGN_FLAG_WIDTH 1
215
216/* MAX98926_R009_FLAG1 */
217#define MAX98926_SPKCURNT_FLAG_MASK (1<<5)
218#define MAX98926_SPKCURNT_FLAG_SHIFT 5
219#define MAX98926_SPKCURNT_FLAG_WIDTH 1
220#define MAX98926_WATCHFAIL_FLAG_MASK (1<<4)
221#define MAX98926_WATCHFAIL_FLAG_SHIFT 4
222#define MAX98926_WATCHFAIL_FLAG_WIDTH 1
223#define MAX98926_ALCINFH_FLAG_MASK (1<<3)
224#define MAX98926_ALCINFH_FLAG_SHIFT 3
225#define MAX98926_ALCINFH_FLAG_WIDTH 1
226#define MAX98926_ALCACT_FLAG_MASK (1<<2)
227#define MAX98926_ALCACT_FLAG_SHIFT 2
228#define MAX98926_ALCACT_FLAG_WIDTH 1
229#define MAX98926_ALCMUT_FLAG_MASK (1<<1)
230#define MAX98926_ALCMUT_FLAG_SHIFT 1
231#define MAX98926_ALCMUT_FLAG_WIDTH 1
232#define MAX98926_ALCP_FLAG_MASK (1<<0)
233#define MAX98926_ALCP_FLAG_SHIFT 0
234#define MAX98926_ALCP_FLAG_WIDTH 1
235
236/* MAX98926_R00A_FLAG2 */
237#define MAX98926_SLOTOVRN_FLAG_MASK (1<<6)
238#define MAX98926_SLOTOVRN_FLAG_SHIFT 6
239#define MAX98926_SLOTOVRN_FLAG_WIDTH 1
240#define MAX98926_INVALSLOT_FLAG_MASK (1<<5)
241#define MAX98926_INVALSLOT_FLAG_SHIFT 5
242#define MAX98926_INVALSLOT_FLAG_WIDTH 1
243#define MAX98926_SLOTCNFLT_FLAG_MASK (1<<4)
244#define MAX98926_SLOTCNFLT_FLAG_SHIFT 4
245#define MAX98926_SLOTCNFLT_FLAG_WIDTH 1
246#define MAX98926_VBSTOVFL_FLAG_MASK (1<<3)
247#define MAX98926_VBSTOVFL_FLAG_SHIFT 3
248#define MAX98926_VBSTOVFL_FLAG_WIDTH 1
249#define MAX98926_VBATOVFL_FLAG_MASK (1<<2)
250#define MAX98926_VBATOVFL_FLAG_SHIFT 2
251#define MAX98926_VBATOVFL_FLAG_WIDTH 1
252#define MAX98926_IMONOVFL_FLAG_MASK (1<<1)
253#define MAX98926_IMONOVFL_FLAG_SHIFT 1
254#define MAX98926_IMONOVFL_FLAG_WIDTH 1
255#define MAX98926_VMONOVFL_FLAG_MASK (1<<0)
256#define MAX98926_VMONOVFL_FLAG_SHIFT 0
257#define MAX98926_VMONOVFL_FLAG_WIDTH 1
258
259/* MAX98926_R00B_IRQ_ENABLE0 */
260#define MAX98926_THERMWARN_END_EN_MASK (1<<3)
261#define MAX98926_THERMWARN_END_EN_SHIFT 3
262#define MAX98926_THERMWARN_END_EN_WIDTH 1
263#define MAX98926_THERMWARN_BGN_EN_MASK (1<<2)
264#define MAX98926_THERMWARN_BGN_EN_SHIFT 2
265#define MAX98926_THERMWARN_BGN_EN_WIDTH 1
266#define MAX98926_THERMSHDN_END_EN_MASK (1<<1)
267#define MAX98926_THERMSHDN_END_EN_SHIFT 1
268#define MAX98926_THERMSHDN_END_EN_WIDTH 1
269#define MAX98926_THERMSHDN_BGN_EN_MASK (1<<0)
270#define MAX98926_THERMSHDN_BGN_EN_SHIFT 0
271#define MAX98926_THERMSHDN_BGN_EN_WIDTH 1
272
273/* MAX98926_R00C_IRQ_ENABLE1 */
274#define MAX98926_SPKCURNT_EN_MASK (1<<5)
275#define MAX98926_SPKCURNT_EN_SHIFT 5
276#define MAX98926_SPKCURNT_EN_WIDTH 1
277#define MAX98926_WATCHFAIL_EN_MASK (1<<4)
278#define MAX98926_WATCHFAIL_EN_SHIFT 4
279#define MAX98926_WATCHFAIL_EN_WIDTH 1
280#define MAX98926_ALCINFH_EN_MASK (1<<3)
281#define MAX98926_ALCINFH_EN_SHIFT 3
282#define MAX98926_ALCINFH_EN_WIDTH 1
283#define MAX98926_ALCACT_EN_MASK (1<<2)
284#define MAX98926_ALCACT_EN_SHIFT 2
285#define MAX98926_ALCACT_EN_WIDTH 1
286#define MAX98926_ALCMUT_EN_MASK (1<<1)
287#define MAX98926_ALCMUT_EN_SHIFT 1
288#define MAX98926_ALCMUT_EN_WIDTH 1
289#define MAX98926_ALCP_EN_MASK (1<<0)
290#define MAX98926_ALCP_EN_SHIFT 0
291#define MAX98926_ALCP_EN_WIDTH 1
292
293/* MAX98926_R00D_IRQ_ENABLE2 */
294#define MAX98926_SLOTOVRN_EN_MASK (1<<6)
295#define MAX98926_SLOTOVRN_EN_SHIFT 6
296#define MAX98926_SLOTOVRN_EN_WIDTH 1
297#define MAX98926_INVALSLOT_EN_MASK (1<<5)
298#define MAX98926_INVALSLOT_EN_SHIFT 5
299#define MAX98926_INVALSLOT_EN_WIDTH 1
300#define MAX98926_SLOTCNFLT_EN_MASK (1<<4)
301#define MAX98926_SLOTCNFLT_EN_SHIFT 4
302#define MAX98926_SLOTCNFLT_EN_WIDTH 1
303#define MAX98926_VBSTOVFL_EN_MASK (1<<3)
304#define MAX98926_VBSTOVFL_EN_SHIFT 3
305#define MAX98926_VBSTOVFL_EN_WIDTH 1
306#define MAX98926_VBATOVFL_EN_MASK (1<<2)
307#define MAX98926_VBATOVFL_EN_SHIFT 2
308#define MAX98926_VBATOVFL_EN_WIDTH 1
309#define MAX98926_IMONOVFL_EN_MASK (1<<1)
310#define MAX98926_IMONOVFL_EN_SHIFT 1
311#define MAX98926_IMONOVFL_EN_WIDTH 1
312#define MAX98926_VMONOVFL_EN_MASK (1<<0)
313#define MAX98926_VMONOVFL_EN_SHIFT 0
314#define MAX98926_VMONOVFL_EN_WIDTH 1
315
316/* MAX98926_R00E_IRQ_CLEAR0 */
317#define MAX98926_THERMWARN_END_CLR_MASK (1<<3)
318#define MAX98926_THERMWARN_END_CLR_SHIFT 3
319#define MAX98926_THERMWARN_END_CLR_WIDTH 1
320#define MAX98926_THERMWARN_BGN_CLR_MASK (1<<2)
321#define MAX98926_THERMWARN_BGN_CLR_SHIFT 2
322#define MAX98926_THERMWARN_BGN_CLR_WIDTH 1
323#define MAX98926_THERMSHDN_END_CLR_MASK (1<<1)
324#define MAX98926_THERMSHDN_END_CLR_SHIFT 1
325#define MAX98926_THERMSHDN_END_CLR_WIDTH 1
326#define MAX98926_THERMSHDN_BGN_CLR_MASK (1<<0)
327#define MAX98926_THERMSHDN_BGN_CLR_SHIFT 0
328#define MAX98926_THERMSHDN_BGN_CLR_WIDTH 1
329
330/* MAX98926_R00F_IRQ_CLEAR1 */
331#define MAX98926_SPKCURNT_CLR_MASK (1<<5)
332#define MAX98926_SPKCURNT_CLR_SHIFT 5
333#define MAX98926_SPKCURNT_CLR_WIDTH 1
334#define MAX98926_WATCHFAIL_CLR_MASK (1<<4)
335#define MAX98926_WATCHFAIL_CLR_SHIFT 4
336#define MAX98926_WATCHFAIL_CLR_WIDTH 1
337#define MAX98926_ALCINFH_CLR_MASK (1<<3)
338#define MAX98926_ALCINFH_CLR_SHIFT 3
339#define MAX98926_ALCINFH_CLR_WIDTH 1
340#define MAX98926_ALCACT_CLR_MASK (1<<2)
341#define MAX98926_ALCACT_CLR_SHIFT 2
342#define MAX98926_ALCACT_CLR_WIDTH 1
343#define MAX98926_ALCMUT_CLR_MASK (1<<1)
344#define MAX98926_ALCMUT_CLR_SHIFT 1
345#define MAX98926_ALCMUT_CLR_WIDTH 1
346#define MAX98926_ALCP_CLR_MASK (1<<0)
347#define MAX98926_ALCP_CLR_SHIFT 0
348#define MAX98926_ALCP_CLR_WIDTH 1
349
350/* MAX98926_R010_IRQ_CLEAR2 */
351#define MAX98926_SLOTOVRN_CLR_MASK (1<<6)
352#define MAX98926_SLOTOVRN_CLR_SHIFT 6
353#define MAX98926_SLOTOVRN_CLR_WIDTH 1
354#define MAX98926_INVALSLOT_CLR_MASK (1<<5)
355#define MAX98926_INVALSLOT_CLR_SHIFT 5
356#define MAX98926_INVALSLOT_CLR_WIDTH 1
357#define MAX98926_SLOTCNFLT_CLR_MASK (1<<4)
358#define MAX98926_SLOTCNFLT_CLR_SHIFT 4
359#define MAX98926_SLOTCNFLT_CLR_WIDTH 1
360#define MAX98926_VBSTOVFL_CLR_MASK (1<<3)
361#define MAX98926_VBSTOVFL_CLR_SHIFT 3
362#define MAX98926_VBSTOVFL_CLR_WIDTH 1
363#define MAX98926_VBATOVFL_CLR_MASK (1<<2)
364#define MAX98926_VBATOVFL_CLR_SHIFT 2
365#define MAX98926_VBATOVFL_CLR_WIDTH 1
366#define MAX98926_IMONOVFL_CLR_MASK (1<<1)
367#define MAX98926_IMONOVFL_CLR_SHIFT 1
368#define MAX98926_IMONOVFL_CLR_WIDTH 1
369#define MAX98926_VMONOVFL_CLR_MASK (1<<0)
370#define MAX98926_VMONOVFL_CLR_SHIFT 0
371#define MAX98926_VMONOVFL_CLR_WIDTH 1
372
373/* MAX98926_R011_MAP0 */
374#define MAX98926_ER_THERMWARN_EN_MASK (1<<7)
375#define MAX98926_ER_THERMWARN_EN_SHIFT 7
376#define MAX98926_ER_THERMWARN_EN_WIDTH 1
377#define MAX98926_ER_THERMWARN_MAP_MASK (0x07<<4)
378#define MAX98926_ER_THERMWARN_MAP_SHIFT 4
379#define MAX98926_ER_THERMWARN_MAP_WIDTH 3
380
381/* MAX98926_R012_MAP1 */
382#define MAX98926_ER_ALCMUT_EN_MASK (1<<7)
383#define MAX98926_ER_ALCMUT_EN_SHIFT 7
384#define MAX98926_ER_ALCMUT_EN_WIDTH 1
385#define MAX98926_ER_ALCMUT_MAP_MASK (0x07<<4)
386#define MAX98926_ER_ALCMUT_MAP_SHIFT 4
387#define MAX98926_ER_ALCMUT_MAP_WIDTH 3
388#define MAX98926_ER_ALCP_EN_MASK (1<<3)
389#define MAX98926_ER_ALCP_EN_SHIFT 3
390#define MAX98926_ER_ALCP_EN_WIDTH 1
391#define MAX98926_ER_ALCP_MAP_MASK (0x07<<0)
392#define MAX98926_ER_ALCP_MAP_SHIFT 0
393#define MAX98926_ER_ALCP_MAP_WIDTH 3
394
395/* MAX98926_R013_MAP2 */
396#define MAX98926_ER_ALCINFH_EN_MASK (1<<7)
397#define MAX98926_ER_ALCINFH_EN_SHIFT 7
398#define MAX98926_ER_ALCINFH_EN_WIDTH 1
399#define MAX98926_ER_ALCINFH_MAP_MASK (0x07<<4)
400#define MAX98926_ER_ALCINFH_MAP_SHIFT 4
401#define MAX98926_ER_ALCINFH_MAP_WIDTH 3
402#define MAX98926_ER_ALCACT_EN_MASK (1<<3)
403#define MAX98926_ER_ALCACT_EN_SHIFT 3
404#define MAX98926_ER_ALCACT_EN_WIDTH 1
405#define MAX98926_ER_ALCACT_MAP_MASK (0x07<<0)
406#define MAX98926_ER_ALCACT_MAP_SHIFT 0
407#define MAX98926_ER_ALCACT_MAP_WIDTH 3
408
409/* MAX98926_R014_MAP3 */
410#define MAX98926_ER_SPKCURNT_EN_MASK (1<<7)
411#define MAX98926_ER_SPKCURNT_EN_SHIFT 7
412#define MAX98926_ER_SPKCURNT_EN_WIDTH 1
413#define MAX98926_ER_SPKCURNT_MAP_MASK (0x07<<4)
414#define MAX98926_ER_SPKCURNT_MAP_SHIFT 4
415#define MAX98926_ER_SPKCURNT_MAP_WIDTH 3
416
417/* MAX98926_R015_MAP4 */
418/* RESERVED */
419
420/* MAX98926_R016_MAP5 */
421#define MAX98926_ER_IMONOVFL_EN_MASK (1<<7)
422#define MAX98926_ER_IMONOVFL_EN_SHIFT 7
423#define MAX98926_ER_IMONOVFL_EN_WIDTH 1
424#define MAX98926_ER_IMONOVFL_MAP_MASK (0x07<<4)
425#define MAX98926_ER_IMONOVFL_MAP_SHIFT 4
426#define MAX98926_ER_IMONOVFL_MAP_WIDTH 3
427#define MAX98926_ER_VMONOVFL_EN_MASK (1<<3)
428#define MAX98926_ER_VMONOVFL_EN_SHIFT 3
429#define MAX98926_ER_VMONOVFL_EN_WIDTH 1
430#define MAX98926_ER_VMONOVFL_MAP_MASK (0x07<<0)
431#define MAX98926_ER_VMONOVFL_MAP_SHIFT 0
432#define MAX98926_ER_VMONOVFL_MAP_WIDTH 3
433
434/* MAX98926_R017_MAP6 */
435#define MAX98926_ER_VBSTOVFL_EN_MASK (1<<7)
436#define MAX98926_ER_VBSTOVFL_EN_SHIFT 7
437#define MAX98926_ER_VBSTOVFL_EN_WIDTH 1
438#define MAX98926_ER_VBSTOVFL_MAP_MASK (0x07<<4)
439#define MAX98926_ER_VBSTOVFL_MAP_SHIFT 4
440#define MAX98926_ER_VBSTOVFL_MAP_WIDTH 3
441#define MAX98926_ER_VBATOVFL_EN_MASK (1<<3)
442#define MAX98926_ER_VBATOVFL_EN_SHIFT 3
443#define MAX98926_ER_VBATOVFL_EN_WIDTH 1
444#define MAX98926_ER_VBATOVFL_MAP_MASK (0x07<<0)
445#define MAX98926_ER_VBATOVFL_MAP_SHIFT 0
446#define MAX98926_ER_VBATOVFL_MAP_WIDTH 3
447
448/* MAX98926_R018_MAP7 */
449#define MAX98926_ER_INVALSLOT_EN_MASK (1<<7)
450#define MAX98926_ER_INVALSLOT_EN_SHIFT 7
451#define MAX98926_ER_INVALSLOT_EN_WIDTH 1
452#define MAX98926_ER_INVALSLOT_MAP_MASK (0x07<<4)
453#define MAX98926_ER_INVALSLOT_MAP_SHIFT 4
454#define MAX98926_ER_INVALSLOT_MAP_WIDTH 3
455#define MAX98926_ER_SLOTCNFLT_EN_MASK (1<<3)
456#define MAX98926_ER_SLOTCNFLT_EN_SHIFT 3
457#define MAX98926_ER_SLOTCNFLT_EN_WIDTH 1
458#define MAX98926_ER_SLOTCNFLT_MAP_MASK (0x07<<0)
459#define MAX98926_ER_SLOTCNFLT_MAP_SHIFT 0
460#define MAX98926_ER_SLOTCNFLT_MAP_WIDTH 3
461
462/* MAX98926_R019_MAP8 */
463#define MAX98926_ER_SLOTOVRN_EN_MASK (1<<3)
464#define MAX98926_ER_SLOTOVRN_EN_SHIFT 3
465#define MAX98926_ER_SLOTOVRN_EN_WIDTH 1
466#define MAX98926_ER_SLOTOVRN_MAP_MASK (0x07<<0)
467#define MAX98926_ER_SLOTOVRN_MAP_SHIFT 0
468#define MAX98926_ER_SLOTOVRN_MAP_WIDTH 3
469
470/* MAX98926_R01A_DAI_CLK_MODE1 */
471#define MAX98926_DAI_CLK_SOURCE_MASK (1<<6)
472#define MAX98926_DAI_CLK_SOURCE_SHIFT 6
473#define MAX98926_DAI_CLK_SOURCE_WIDTH 1
474#define MAX98926_MDLL_MULT_MASK (0x0F<<0)
475#define MAX98926_MDLL_MULT_SHIFT 0
476#define MAX98926_MDLL_MULT_WIDTH 4
477
478#define MAX98926_MDLL_MULT_MCLKx8 6
479#define MAX98926_MDLL_MULT_MCLKx16 8
480
481/* MAX98926_R01B_DAI_CLK_MODE2 */
482#define MAX98926_DAI_SR_MASK (0x0F<<4)
483#define MAX98926_DAI_SR_SHIFT 4
484#define MAX98926_DAI_SR_WIDTH 4
485#define MAX98926_DAI_MAS_MASK (1<<3)
486#define MAX98926_DAI_MAS_SHIFT 3
487#define MAX98926_DAI_MAS_WIDTH 1
488#define MAX98926_DAI_BSEL_MASK (0x07<<0)
489#define MAX98926_DAI_BSEL_SHIFT 0
490#define MAX98926_DAI_BSEL_WIDTH 3
491
492#define MAX98926_DAI_BSEL_32 (0 << MAX98926_DAI_BSEL_SHIFT)
493#define MAX98926_DAI_BSEL_48 (1 << MAX98926_DAI_BSEL_SHIFT)
494#define MAX98926_DAI_BSEL_64 (2 << MAX98926_DAI_BSEL_SHIFT)
495#define MAX98926_DAI_BSEL_256 (6 << MAX98926_DAI_BSEL_SHIFT)
496
497/* MAX98926_R01C_DAI_CLK_DIV_M_MSBS */
498#define MAX98926_DAI_M_MSBS_MASK (0xFF<<0)
499#define MAX98926_DAI_M_MSBS_SHIFT 0
500#define MAX98926_DAI_M_MSBS_WIDTH 8
501
502/* MAX98926_R01D_DAI_CLK_DIV_M_LSBS */
503#define MAX98926_DAI_M_LSBS_MASK (0xFF<<0)
504#define MAX98926_DAI_M_LSBS_SHIFT 0
505#define MAX98926_DAI_M_LSBS_WIDTH 8
506
507/* MAX98926_R01E_DAI_CLK_DIV_N_MSBS */
508#define MAX98926_DAI_N_MSBS_MASK (0x7F<<0)
509#define MAX98926_DAI_N_MSBS_SHIFT 0
510#define MAX98926_DAI_N_MSBS_WIDTH 7
511
512/* MAX98926_R01F_DAI_CLK_DIV_N_LSBS */
513#define MAX98926_DAI_N_LSBS_MASK (0xFF<<0)
514#define MAX98926_DAI_N_LSBS_SHIFT 0
515#define MAX98926_DAI_N_LSBS_WIDTH 8
516
517/* MAX98926_R020_FORMAT */
518#define MAX98926_DAI_CHANSZ_MASK (0x03<<6)
519#define MAX98926_DAI_CHANSZ_SHIFT 6
520#define MAX98926_DAI_CHANSZ_WIDTH 2
521#define MAX98926_DAI_INTERLEAVE_MASK (1<<5)
522#define MAX98926_DAI_INTERLEAVE_SHIFT 5
523#define MAX98926_DAI_INTERLEAVE_WIDTH 1
524#define MAX98926_DAI_EXTBCLK_HIZ_MASK (1<<4)
525#define MAX98926_DAI_EXTBCLK_HIZ_SHIFT 4
526#define MAX98926_DAI_EXTBCLK_HIZ_WIDTH 1
527#define MAX98926_DAI_WCI_MASK (1<<3)
528#define MAX98926_DAI_WCI_SHIFT 3
529#define MAX98926_DAI_WCI_WIDTH 1
530#define MAX98926_DAI_BCI_MASK (1<<2)
531#define MAX98926_DAI_BCI_SHIFT 2
532#define MAX98926_DAI_BCI_WIDTH 1
533#define MAX98926_DAI_DLY_MASK (1<<1)
534#define MAX98926_DAI_DLY_SHIFT 1
535#define MAX98926_DAI_DLY_WIDTH 1
536#define MAX98926_DAI_TDM_MASK (1<<0)
537#define MAX98926_DAI_TDM_SHIFT 0
538#define MAX98926_DAI_TDM_WIDTH 1
539
540#define MAX98926_DAI_CHANSZ_16 (1 << MAX98926_DAI_CHANSZ_SHIFT)
541#define MAX98926_DAI_CHANSZ_24 (2 << MAX98926_DAI_CHANSZ_SHIFT)
542#define MAX98926_DAI_CHANSZ_32 (3 << MAX98926_DAI_CHANSZ_SHIFT)
543
544/* MAX98926_R021_TDM_SLOT_SELECT */
545#define MAX98926_DAI_DO_EN_MASK (1<<7)
546#define MAX98926_DAI_DO_EN_SHIFT 7
547#define MAX98926_DAI_DO_EN_WIDTH 1
548#define MAX98926_DAI_DIN_EN_MASK (1<<6)
549#define MAX98926_DAI_DIN_EN_SHIFT 6
550#define MAX98926_DAI_DIN_EN_WIDTH 1
551#define MAX98926_DAI_INR_SOURCE_MASK (0x07<<3)
552#define MAX98926_DAI_INR_SOURCE_SHIFT 3
553#define MAX98926_DAI_INR_SOURCE_WIDTH 3
554#define MAX98926_DAI_INL_SOURCE_MASK (0x07<<0)
555#define MAX98926_DAI_INL_SOURCE_SHIFT 0
556#define MAX98926_DAI_INL_SOURCE_WIDTH 3
557
558/* MAX98926_R022_DOUT_CFG_VMON */
559#define MAX98926_DAI_VMON_EN_MASK (1<<5)
560#define MAX98926_DAI_VMON_EN_SHIFT 5
561#define MAX98926_DAI_VMON_EN_WIDTH 1
562#define MAX98926_DAI_VMON_SLOT_MASK (0x1F<<0)
563#define MAX98926_DAI_VMON_SLOT_SHIFT 0
564#define MAX98926_DAI_VMON_SLOT_WIDTH 5
565
566#define MAX98926_DAI_VMON_SLOT_00_01 (0 << MAX98926_DAI_VMON_SLOT_SHIFT)
567#define MAX98926_DAI_VMON_SLOT_01_02 (1 << MAX98926_DAI_VMON_SLOT_SHIFT)
568#define MAX98926_DAI_VMON_SLOT_02_03 (2 << MAX98926_DAI_VMON_SLOT_SHIFT)
569#define MAX98926_DAI_VMON_SLOT_03_04 (3 << MAX98926_DAI_VMON_SLOT_SHIFT)
570#define MAX98926_DAI_VMON_SLOT_04_05 (4 << MAX98926_DAI_VMON_SLOT_SHIFT)
571#define MAX98926_DAI_VMON_SLOT_05_06 (5 << MAX98926_DAI_VMON_SLOT_SHIFT)
572#define MAX98926_DAI_VMON_SLOT_06_07 (6 << MAX98926_DAI_VMON_SLOT_SHIFT)
573#define MAX98926_DAI_VMON_SLOT_07_08 (7 << MAX98926_DAI_VMON_SLOT_SHIFT)
574#define MAX98926_DAI_VMON_SLOT_08_09 (8 << MAX98926_DAI_VMON_SLOT_SHIFT)
575#define MAX98926_DAI_VMON_SLOT_09_0A (9 << MAX98926_DAI_VMON_SLOT_SHIFT)
576#define MAX98926_DAI_VMON_SLOT_0A_0B (10 << MAX98926_DAI_VMON_SLOT_SHIFT)
577#define MAX98926_DAI_VMON_SLOT_0B_0C (11 << MAX98926_DAI_VMON_SLOT_SHIFT)
578#define MAX98926_DAI_VMON_SLOT_0C_0D (12 << MAX98926_DAI_VMON_SLOT_SHIFT)
579#define MAX98926_DAI_VMON_SLOT_0D_0E (13 << MAX98926_DAI_VMON_SLOT_SHIFT)
580#define MAX98926_DAI_VMON_SLOT_0E_0F (14 << MAX98926_DAI_VMON_SLOT_SHIFT)
581#define MAX98926_DAI_VMON_SLOT_0F_10 (15 << MAX98926_DAI_VMON_SLOT_SHIFT)
582#define MAX98926_DAI_VMON_SLOT_10_11 (16 << MAX98926_DAI_VMON_SLOT_SHIFT)
583#define MAX98926_DAI_VMON_SLOT_11_12 (17 << MAX98926_DAI_VMON_SLOT_SHIFT)
584#define MAX98926_DAI_VMON_SLOT_12_13 (18 << MAX98926_DAI_VMON_SLOT_SHIFT)
585#define MAX98926_DAI_VMON_SLOT_13_14 (19 << MAX98926_DAI_VMON_SLOT_SHIFT)
586#define MAX98926_DAI_VMON_SLOT_14_15 (20 << MAX98926_DAI_VMON_SLOT_SHIFT)
587#define MAX98926_DAI_VMON_SLOT_15_16 (21 << MAX98926_DAI_VMON_SLOT_SHIFT)
588#define MAX98926_DAI_VMON_SLOT_16_17 (22 << MAX98926_DAI_VMON_SLOT_SHIFT)
589#define MAX98926_DAI_VMON_SLOT_17_18 (23 << MAX98926_DAI_VMON_SLOT_SHIFT)
590#define MAX98926_DAI_VMON_SLOT_18_19 (24 << MAX98926_DAI_VMON_SLOT_SHIFT)
591#define MAX98926_DAI_VMON_SLOT_19_1A (25 << MAX98926_DAI_VMON_SLOT_SHIFT)
592#define MAX98926_DAI_VMON_SLOT_1A_1B (26 << MAX98926_DAI_VMON_SLOT_SHIFT)
593#define MAX98926_DAI_VMON_SLOT_1B_1C (27 << MAX98926_DAI_VMON_SLOT_SHIFT)
594#define MAX98926_DAI_VMON_SLOT_1C_1D (28 << MAX98926_DAI_VMON_SLOT_SHIFT)
595#define MAX98926_DAI_VMON_SLOT_1D_1E (29 << MAX98926_DAI_VMON_SLOT_SHIFT)
596#define MAX98926_DAI_VMON_SLOT_1E_1F (30 << MAX98926_DAI_VMON_SLOT_SHIFT)
597
598/* MAX98926_R023_DOUT_CFG_IMON */
599#define MAX98926_DAI_IMON_EN_MASK (1<<5)
600#define MAX98926_DAI_IMON_EN_SHIFT 5
601#define MAX98926_DAI_IMON_EN_WIDTH 1
602#define MAX98926_DAI_IMON_SLOT_MASK (0x1F<<0)
603#define MAX98926_DAI_IMON_SLOT_SHIFT 0
604#define MAX98926_DAI_IMON_SLOT_WIDTH 5
605
606#define MAX98926_DAI_IMON_SLOT_00_01 (0 << MAX98926_DAI_IMON_SLOT_SHIFT)
607#define MAX98926_DAI_IMON_SLOT_01_02 (1 << MAX98926_DAI_IMON_SLOT_SHIFT)
608#define MAX98926_DAI_IMON_SLOT_02_03 (2 << MAX98926_DAI_IMON_SLOT_SHIFT)
609#define MAX98926_DAI_IMON_SLOT_03_04 (3 << MAX98926_DAI_IMON_SLOT_SHIFT)
610#define MAX98926_DAI_IMON_SLOT_04_05 (4 << MAX98926_DAI_IMON_SLOT_SHIFT)
611#define MAX98926_DAI_IMON_SLOT_05_06 (5 << MAX98926_DAI_IMON_SLOT_SHIFT)
612#define MAX98926_DAI_IMON_SLOT_06_07 (6 << MAX98926_DAI_IMON_SLOT_SHIFT)
613#define MAX98926_DAI_IMON_SLOT_07_08 (7 << MAX98926_DAI_IMON_SLOT_SHIFT)
614#define MAX98926_DAI_IMON_SLOT_08_09 (8 << MAX98926_DAI_IMON_SLOT_SHIFT)
615#define MAX98926_DAI_IMON_SLOT_09_0A (9 << MAX98926_DAI_IMON_SLOT_SHIFT)
616#define MAX98926_DAI_IMON_SLOT_0A_0B (10 << MAX98926_DAI_IMON_SLOT_SHIFT)
617#define MAX98926_DAI_IMON_SLOT_0B_0C (11 << MAX98926_DAI_IMON_SLOT_SHIFT)
618#define MAX98926_DAI_IMON_SLOT_0C_0D (12 << MAX98926_DAI_IMON_SLOT_SHIFT)
619#define MAX98926_DAI_IMON_SLOT_0D_0E (13 << MAX98926_DAI_IMON_SLOT_SHIFT)
620#define MAX98926_DAI_IMON_SLOT_0E_0F (14 << MAX98926_DAI_IMON_SLOT_SHIFT)
621#define MAX98926_DAI_IMON_SLOT_0F_10 (15 << MAX98926_DAI_IMON_SLOT_SHIFT)
622#define MAX98926_DAI_IMON_SLOT_10_11 (16 << MAX98926_DAI_IMON_SLOT_SHIFT)
623#define MAX98926_DAI_IMON_SLOT_11_12 (17 << MAX98926_DAI_IMON_SLOT_SHIFT)
624#define MAX98926_DAI_IMON_SLOT_12_13 (18 << MAX98926_DAI_IMON_SLOT_SHIFT)
625#define MAX98926_DAI_IMON_SLOT_13_14 (19 << MAX98926_DAI_IMON_SLOT_SHIFT)
626#define MAX98926_DAI_IMON_SLOT_14_15 (20 << MAX98926_DAI_IMON_SLOT_SHIFT)
627#define MAX98926_DAI_IMON_SLOT_15_16 (21 << MAX98926_DAI_IMON_SLOT_SHIFT)
628#define MAX98926_DAI_IMON_SLOT_16_17 (22 << MAX98926_DAI_IMON_SLOT_SHIFT)
629#define MAX98926_DAI_IMON_SLOT_17_18 (23 << MAX98926_DAI_IMON_SLOT_SHIFT)
630#define MAX98926_DAI_IMON_SLOT_18_19 (24 << MAX98926_DAI_IMON_SLOT_SHIFT)
631#define MAX98926_DAI_IMON_SLOT_19_1A (25 << MAX98926_DAI_IMON_SLOT_SHIFT)
632#define MAX98926_DAI_IMON_SLOT_1A_1B (26 << MAX98926_DAI_IMON_SLOT_SHIFT)
633#define MAX98926_DAI_IMON_SLOT_1B_1C (27 << MAX98926_DAI_IMON_SLOT_SHIFT)
634#define MAX98926_DAI_IMON_SLOT_1C_1D (28 << MAX98926_DAI_IMON_SLOT_SHIFT)
635#define MAX98926_DAI_IMON_SLOT_1D_1E (29 << MAX98926_DAI_IMON_SLOT_SHIFT)
636#define MAX98926_DAI_IMON_SLOT_1E_1F (30 << MAX98926_DAI_IMON_SLOT_SHIFT)
637
638/* MAX98926_R024_DOUT_CFG_VBAT */
639#define MAX98926_DAI_INTERLEAVE_SLOT_MASK (0x1F<<0)
640#define MAX98926_DAI_INTERLEAVE_SLOT_SHIFT 0
641#define MAX98926_DAI_INTERLEAVE_SLOT_WIDTH 5
642
643/* MAX98926_R025_DOUT_CFG_VBST */
644#define MAX98926_DAI_VBST_EN_MASK (1<<5)
645#define MAX98926_DAI_VBST_EN_SHIFT 5
646#define MAX98926_DAI_VBST_EN_WIDTH 1
647#define MAX98926_DAI_VBST_SLOT_MASK (0x1F<<0)
648#define MAX98926_DAI_VBST_SLOT_SHIFT 0
649#define MAX98926_DAI_VBST_SLOT_WIDTH 5
650
651/* MAX98926_R026_DOUT_CFG_FLAG */
652#define MAX98926_DAI_FLAG_EN_MASK (1<<5)
653#define MAX98926_DAI_FLAG_EN_SHIFT 5
654#define MAX98926_DAI_FLAG_EN_WIDTH 1
655#define MAX98926_DAI_FLAG_SLOT_MASK (0x1F<<0)
656#define MAX98926_DAI_FLAG_SLOT_SHIFT 0
657#define MAX98926_DAI_FLAG_SLOT_WIDTH 5
658
659/* MAX98926_R027_DOUT_HIZ_CFG1 */
660#define MAX98926_DAI_SLOT_HIZ_CFG1_MASK (0xFF<<0)
661#define MAX98926_DAI_SLOT_HIZ_CFG1_SHIFT 0
662#define MAX98926_DAI_SLOT_HIZ_CFG1_WIDTH 8
663
664/* MAX98926_R028_DOUT_HIZ_CFG2 */
665#define MAX98926_DAI_SLOT_HIZ_CFG2_MASK (0xFF<<0)
666#define MAX98926_DAI_SLOT_HIZ_CFG2_SHIFT 0
667#define MAX98926_DAI_SLOT_HIZ_CFG2_WIDTH 8
668
669/* MAX98926_R029_DOUT_HIZ_CFG3 */
670#define MAX98926_DAI_SLOT_HIZ_CFG3_MASK (0xFF<<0)
671#define MAX98926_DAI_SLOT_HIZ_CFG3_SHIFT 0
672#define MAX98926_DAI_SLOT_HIZ_CFG3_WIDTH 8
673
674/* MAX98926_R02A_DOUT_HIZ_CFG4 */
675#define MAX98926_DAI_SLOT_HIZ_CFG4_MASK (0xFF<<0)
676#define MAX98926_DAI_SLOT_HIZ_CFG4_SHIFT 0
677#define MAX98926_DAI_SLOT_HIZ_CFG4_WIDTH 8
678
679/* MAX98926_R02B_DOUT_DRV_STRENGTH */
680#define MAX98926_DAI_OUT_DRIVE_MASK (0x03<<0)
681#define MAX98926_DAI_OUT_DRIVE_SHIFT 0
682#define MAX98926_DAI_OUT_DRIVE_WIDTH 2
683
684/* MAX98926_R02C_FILTERS */
685#define MAX98926_ADC_DITHER_EN_MASK (1<<7)
686#define MAX98926_ADC_DITHER_EN_SHIFT 7
687#define MAX98926_ADC_DITHER_EN_WIDTH 1
688#define MAX98926_IV_DCB_EN_MASK (1<<6)
689#define MAX98926_IV_DCB_EN_SHIFT 6
690#define MAX98926_IV_DCB_EN_WIDTH 1
691#define MAX98926_DAC_DITHER_EN_MASK (1<<4)
692#define MAX98926_DAC_DITHER_EN_SHIFT 4
693#define MAX98926_DAC_DITHER_EN_WIDTH 1
694#define MAX98926_DAC_FILTER_MODE_MASK (1<<3)
695#define MAX98926_DAC_FILTER_MODE_SHIFT 3
696#define MAX98926_DAC_FILTER_MODE_WIDTH 1
697#define MAX98926_DAC_HPF_MASK (0x07<<0)
698#define MAX98926_DAC_HPF_SHIFT 0
699#define MAX98926_DAC_HPF_WIDTH 3
700#define MAX98926_DAC_HPF_DISABLE (0 << MAX98926_DAC_HPF_SHIFT)
701#define MAX98926_DAC_HPF_DC_BLOCK (1 << MAX98926_DAC_HPF_SHIFT)
702#define MAX98926_DAC_HPF_EN_100 (2 << MAX98926_DAC_HPF_SHIFT)
703#define MAX98926_DAC_HPF_EN_200 (3 << MAX98926_DAC_HPF_SHIFT)
704#define MAX98926_DAC_HPF_EN_400 (4 << MAX98926_DAC_HPF_SHIFT)
705#define MAX98926_DAC_HPF_EN_800 (5 << MAX98926_DAC_HPF_SHIFT)
706
707/* MAX98926_R02D_GAIN */
708#define MAX98926_DAC_IN_SEL_MASK (0x03<<5)
709#define MAX98926_DAC_IN_SEL_SHIFT 5
710#define MAX98926_DAC_IN_SEL_WIDTH 2
711#define MAX98926_SPK_GAIN_MASK (0x1F<<0)
712#define MAX98926_SPK_GAIN_SHIFT 0
713#define MAX98926_SPK_GAIN_WIDTH 5
714
715#define MAX98926_DAC_IN_SEL_LEFT_DAI (0 << MAX98926_DAC_IN_SEL_SHIFT)
716#define MAX98926_DAC_IN_SEL_RIGHT_DAI (1 << MAX98926_DAC_IN_SEL_SHIFT)
717#define MAX98926_DAC_IN_SEL_SUMMED_DAI (2 << MAX98926_DAC_IN_SEL_SHIFT)
718#define MAX98926_DAC_IN_SEL_DIV2_SUMMED_DAI (3 << MAX98926_DAC_IN_SEL_SHIFT)
719
720/* MAX98926_R02E_GAIN_RAMPING */
721#define MAX98926_SPK_RMP_EN_MASK (1<<1)
722#define MAX98926_SPK_RMP_EN_SHIFT 1
723#define MAX98926_SPK_RMP_EN_WIDTH 1
724#define MAX98926_SPK_ZCD_EN_MASK (1<<0)
725#define MAX98926_SPK_ZCD_EN_SHIFT 0
726#define MAX98926_SPK_ZCD_EN_WIDTH 1
727
728/* MAX98926_R02F_SPK_AMP */
729#define MAX98926_SPK_MODE_MASK (1<<0)
730#define MAX98926_SPK_MODE_SHIFT 0
731#define MAX98926_SPK_MODE_WIDTH 1
732#define MAX98926_INSELECT_MODE_MASK (1<<1)
733#define MAX98926_INSELECT_MODE_SHIFT 1
734#define MAX98926_INSELECT_MODE_WIDTH 1
735
736/* MAX98926_R030_THRESHOLD */
737#define MAX98926_ALC_EN_MASK (1<<5)
738#define MAX98926_ALC_EN_SHIFT 5
739#define MAX98926_ALC_EN_WIDTH 1
740#define MAX98926_ALC_TH_MASK (0x1F<<0)
741#define MAX98926_ALC_TH_SHIFT 0
742#define MAX98926_ALC_TH_WIDTH 5
743
744/* MAX98926_R031_ALC_ATTACK */
745#define MAX98926_ALC_ATK_STEP_MASK (0x0F<<4)
746#define MAX98926_ALC_ATK_STEP_SHIFT 4
747#define MAX98926_ALC_ATK_STEP_WIDTH 4
748#define MAX98926_ALC_ATK_RATE_MASK (0x7<<0)
749#define MAX98926_ALC_ATK_RATE_SHIFT 0
750#define MAX98926_ALC_ATK_RATE_WIDTH 3
751
752/* MAX98926_R032_ALC_ATTEN_RLS */
753#define MAX98926_ALC_MAX_ATTEN_MASK (0x0F<<4)
754#define MAX98926_ALC_MAX_ATTEN_SHIFT 4
755#define MAX98926_ALC_MAX_ATTEN_WIDTH 4
756#define MAX98926_ALC_RLS_RATE_MASK (0x7<<0)
757#define MAX98926_ALC_RLS_RATE_SHIFT 0
758#define MAX98926_ALC_RLS_RATE_WIDTH 3
759
760/* MAX98926_R033_ALC_HOLD_RLS */
761#define MAX98926_ALC_RLS_TGR_MASK (1<<0)
762#define MAX98926_ALC_RLS_TGR_SHIFT 0
763#define MAX98926_ALC_RLS_TGR_WIDTH 1
764
765/* MAX98926_R034_ALC_CONFIGURATION */
766#define MAX98926_ALC_MUTE_EN_MASK (1<<7)
767#define MAX98926_ALC_MUTE_EN_SHIFT 7
768#define MAX98926_ALC_MUTE_EN_WIDTH 1
769#define MAX98926_ALC_MUTE_DLY_MASK (0x07<<4)
770#define MAX98926_ALC_MUTE_DLY_SHIFT 4
771#define MAX98926_ALC_MUTE_DLY_WIDTH 3
772#define MAX98926_ALC_RLS_DBT_MASK (0x07<<0)
773#define MAX98926_ALC_RLS_DBT_SHIFT 0
774#define MAX98926_ALC_RLS_DBT_WIDTH 3
775
776/* MAX98926_R035_BOOST_CONVERTER */
777#define MAX98926_BST_SYNC_MASK (1<<7)
778#define MAX98926_BST_SYNC_SHIFT 7
779#define MAX98926_BST_SYNC_WIDTH 1
780#define MAX98926_BST_PHASE_MASK (0x03<<4)
781#define MAX98926_BST_PHASE_SHIFT 4
782#define MAX98926_BST_PHASE_WIDTH 2
783#define MAX98926_BST_SKIP_MODE_MASK (0x03<<0)
784#define MAX98926_BST_SKIP_MODE_SHIFT 0
785#define MAX98926_BST_SKIP_MODE_WIDTH 2
786
787/* MAX98926_R036_BLOCK_ENABLE */
788#define MAX98926_BST_EN_MASK (1<<7)
789#define MAX98926_BST_EN_SHIFT 7
790#define MAX98926_BST_EN_WIDTH 1
791#define MAX98926_WATCH_EN_MASK (1<<6)
792#define MAX98926_WATCH_EN_SHIFT 6
793#define MAX98926_WATCH_EN_WIDTH 1
794#define MAX98926_CLKMON_EN_MASK (1<<5)
795#define MAX98926_CLKMON_EN_SHIFT 5
796#define MAX98926_CLKMON_EN_WIDTH 1
797#define MAX98926_SPK_EN_MASK (1<<4)
798#define MAX98926_SPK_EN_SHIFT 4
799#define MAX98926_SPK_EN_WIDTH 1
800#define MAX98926_ADC_VBST_EN_MASK (1<<3)
801#define MAX98926_ADC_VBST_EN_SHIFT 3
802#define MAX98926_ADC_VBST_EN_WIDTH 1
803#define MAX98926_ADC_VBAT_EN_MASK (1<<2)
804#define MAX98926_ADC_VBAT_EN_SHIFT 2
805#define MAX98926_ADC_VBAT_EN_WIDTH 1
806#define MAX98926_ADC_IMON_EN_MASK (1<<1)
807#define MAX98926_ADC_IMON_EN_SHIFT 1
808#define MAX98926_ADC_IMON_EN_WIDTH 1
809#define MAX98926_ADC_VMON_EN_MASK (1<<0)
810#define MAX98926_ADC_VMON_EN_SHIFT 0
811#define MAX98926_ADC_VMON_EN_WIDTH 1
812
813/* MAX98926_R037_CONFIGURATION */
814#define MAX98926_BST_VOUT_MASK (0x0F<<4)
815#define MAX98926_BST_VOUT_SHIFT 4
816#define MAX98926_BST_VOUT_WIDTH 4
817#define MAX98926_THERMWARN_LEVEL_MASK (0x03<<2)
818#define MAX98926_THERMWARN_LEVEL_SHIFT 2
819#define MAX98926_THERMWARN_LEVEL_WIDTH 2
820#define MAX98926_WATCH_TIME_MASK (0x03<<0)
821#define MAX98926_WATCH_TIME_SHIFT 0
822#define MAX98926_WATCH_TIME_WIDTH 2
823
824/* MAX98926_R038_GLOBAL_ENABLE */
825#define MAX98926_EN_MASK (1<<7)
826#define MAX98926_EN_SHIFT 7
827#define MAX98926_EN_WIDTH 1
828
829/* MAX98926_R03A_BOOST_LIMITER */
830#define MAX98926_BST_ILIM_MASK (0xF<<4)
831#define MAX98926_BST_ILIM_SHIFT 4
832#define MAX98926_BST_ILIM_WIDTH 4
833
834/* MAX98926_R0FF_VERSION */
835#define MAX98926_REV_ID_MASK (0xFF<<0)
836#define MAX98926_REV_ID_SHIFT 0
837#define MAX98926_REV_ID_WIDTH 8
838
839struct max98926_priv {
840 struct regmap *regmap;
841 struct snd_soc_codec *codec;
842 unsigned int sysclk;
843 unsigned int v_slot;
844 unsigned int i_slot;
845 unsigned int ch_size;
846 unsigned int interleave_mode;
847};
848#endif
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index fef264d27fd3..0754df771e3b 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -17,6 +17,7 @@
17#include <linux/of_address.h> 17#include <linux/of_address.h>
18#include <linux/regmap.h> 18#include <linux/regmap.h>
19#include <linux/slab.h> 19#include <linux/slab.h>
20#include <linux/time.h>
20#include <sound/core.h> 21#include <sound/core.h>
21#include <sound/dmaengine_pcm.h> 22#include <sound/dmaengine_pcm.h>
22#include <sound/pcm_params.h> 23#include <sound/pcm_params.h>
@@ -919,7 +920,7 @@ static int fsl_sai_resume(struct device *dev)
919 regcache_cache_only(sai->regmap, false); 920 regcache_cache_only(sai->regmap, false);
920 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR); 921 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
921 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR); 922 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
922 msleep(1); 923 usleep_range(1000, 2000);
923 regmap_write(sai->regmap, FSL_SAI_TCSR, 0); 924 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
924 regmap_write(sai->regmap, FSL_SAI_RCSR, 0); 925 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
925 return regcache_sync(sai->regmap); 926 return regcache_sync(sai->regmap);
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 40dfd8a36484..ed8de1035cda 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -112,20 +112,6 @@ struct fsl_ssi_rxtx_reg_val {
112 struct fsl_ssi_reg_val tx; 112 struct fsl_ssi_reg_val tx;
113}; 113};
114 114
115static const struct reg_default fsl_ssi_reg_defaults[] = {
116 {CCSR_SSI_SCR, 0x00000000},
117 {CCSR_SSI_SIER, 0x00003003},
118 {CCSR_SSI_STCR, 0x00000200},
119 {CCSR_SSI_SRCR, 0x00000200},
120 {CCSR_SSI_STCCR, 0x00040000},
121 {CCSR_SSI_SRCCR, 0x00040000},
122 {CCSR_SSI_SACNT, 0x00000000},
123 {CCSR_SSI_STMSK, 0x00000000},
124 {CCSR_SSI_SRMSK, 0x00000000},
125 {CCSR_SSI_SACCEN, 0x00000000},
126 {CCSR_SSI_SACCDIS, 0x00000000},
127};
128
129static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg) 115static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
130{ 116{
131 switch (reg) { 117 switch (reg) {
@@ -190,8 +176,7 @@ static const struct regmap_config fsl_ssi_regconfig = {
190 .val_bits = 32, 176 .val_bits = 32,
191 .reg_stride = 4, 177 .reg_stride = 4,
192 .val_format_endian = REGMAP_ENDIAN_NATIVE, 178 .val_format_endian = REGMAP_ENDIAN_NATIVE,
193 .reg_defaults = fsl_ssi_reg_defaults, 179 .num_reg_defaults_raw = CCSR_SSI_SACCDIS / sizeof(uint32_t) + 1,
194 .num_reg_defaults = ARRAY_SIZE(fsl_ssi_reg_defaults),
195 .readable_reg = fsl_ssi_readable_reg, 180 .readable_reg = fsl_ssi_readable_reg,
196 .volatile_reg = fsl_ssi_volatile_reg, 181 .volatile_reg = fsl_ssi_volatile_reg,
197 .precious_reg = fsl_ssi_precious_reg, 182 .precious_reg = fsl_ssi_precious_reg,
@@ -201,6 +186,7 @@ static const struct regmap_config fsl_ssi_regconfig = {
201 186
202struct fsl_ssi_soc_data { 187struct fsl_ssi_soc_data {
203 bool imx; 188 bool imx;
189 bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */
204 bool offline_config; 190 bool offline_config;
205 u32 sisr_write_mask; 191 u32 sisr_write_mask;
206}; 192};
@@ -303,6 +289,7 @@ static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
303 289
304static struct fsl_ssi_soc_data fsl_ssi_imx21 = { 290static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
305 .imx = true, 291 .imx = true,
292 .imx21regs = true,
306 .offline_config = true, 293 .offline_config = true,
307 .sisr_write_mask = 0, 294 .sisr_write_mask = 0,
308}; 295};
@@ -586,8 +573,12 @@ static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
586 */ 573 */
587 regmap_write(regs, CCSR_SSI_SACNT, 574 regmap_write(regs, CCSR_SSI_SACNT,
588 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV); 575 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
589 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff); 576
590 regmap_write(regs, CCSR_SSI_SACCEN, 0x300); 577 /* no SACC{ST,EN,DIS} regs on imx21-class SSI */
578 if (!ssi_private->soc->imx21regs) {
579 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
580 regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
581 }
591 582
592 /* 583 /*
593 * Enable SSI, Transmit and Receive. AC97 has to communicate with the 584 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
@@ -1397,6 +1388,7 @@ static int fsl_ssi_probe(struct platform_device *pdev)
1397 struct resource *res; 1388 struct resource *res;
1398 void __iomem *iomem; 1389 void __iomem *iomem;
1399 char name[64]; 1390 char name[64];
1391 struct regmap_config regconfig = fsl_ssi_regconfig;
1400 1392
1401 of_id = of_match_device(fsl_ssi_ids, &pdev->dev); 1393 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1402 if (!of_id || !of_id->data) 1394 if (!of_id || !of_id->data)
@@ -1444,15 +1436,25 @@ static int fsl_ssi_probe(struct platform_device *pdev)
1444 return PTR_ERR(iomem); 1436 return PTR_ERR(iomem);
1445 ssi_private->ssi_phys = res->start; 1437 ssi_private->ssi_phys = res->start;
1446 1438
1439 if (ssi_private->soc->imx21regs) {
1440 /*
1441 * According to datasheet imx21-class SSI
1442 * don't have SACC{ST,EN,DIS} regs.
1443 */
1444 regconfig.max_register = CCSR_SSI_SRMSK;
1445 regconfig.num_reg_defaults_raw =
1446 CCSR_SSI_SRMSK / sizeof(uint32_t) + 1;
1447 }
1448
1447 ret = of_property_match_string(np, "clock-names", "ipg"); 1449 ret = of_property_match_string(np, "clock-names", "ipg");
1448 if (ret < 0) { 1450 if (ret < 0) {
1449 ssi_private->has_ipg_clk_name = false; 1451 ssi_private->has_ipg_clk_name = false;
1450 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem, 1452 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
1451 &fsl_ssi_regconfig); 1453 &regconfig);
1452 } else { 1454 } else {
1453 ssi_private->has_ipg_clk_name = true; 1455 ssi_private->has_ipg_clk_name = true;
1454 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev, 1456 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev,
1455 "ipg", iomem, &fsl_ssi_regconfig); 1457 "ipg", iomem, &regconfig);
1456 } 1458 }
1457 if (IS_ERR(ssi_private->regs)) { 1459 if (IS_ERR(ssi_private->regs)) {
1458 dev_err(&pdev->dev, "Failed to init register map\n"); 1460 dev_err(&pdev->dev, "Failed to init register map\n");
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-31 22:02:26 -0500