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-rw-r--r--arch/arm64/boot/dts/hisilicon/Makefile4
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip06-d03.dts34
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip06.dtsi307
3 files changed, 344 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile
index cd158b80e29b..d5f43a06b1c1 100644
--- a/arch/arm64/boot/dts/hisilicon/Makefile
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -1,4 +1,6 @@
1dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb 1dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
2dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
3dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
2 4
3always := $(dtb-y) 5always := $(dtb-y)
4subdir-y := $(dts-dirs) 6subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
new file mode 100644
index 000000000000..f3e5323e430b
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
@@ -0,0 +1,34 @@
1/**
2 * dts file for Hisilicon D03 Development Board
3 *
4 * Copyright (C) 2016 Hisilicon Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 *
10 */
11
12/dts-v1/;
13
14#include "hip06.dtsi"
15
16/ {
17 model = "Hisilicon Hip06 D03 Development Board";
18 compatible = "hisilicon,hip06-d03";
19
20 memory@00000000 {
21 device_type = "memory";
22 reg = <0x0 0x00000000 0x0 0x40000000>;
23 };
24
25 chosen { };
26};
27
28&usb_ohci {
29 status = "ok";
30};
31
32&usb_ehci {
33 status = "ok";
34};
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
new file mode 100644
index 000000000000..5927bc472f1b
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -0,0 +1,307 @@
1/**
2 * dts file for Hisilicon D03 Development Board
3 *
4 * Copyright (C) 2016 Hisilicon Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 *
10 */
11
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14/ {
15 compatible = "hisilicon,hip06-d03";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 psci {
21 compatible = "arm,psci-0.2";
22 method = "smc";
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu-map {
30 cluster0 {
31 core0 {
32 cpu = <&cpu0>;
33 };
34 core1 {
35 cpu = <&cpu1>;
36 };
37 core2 {
38 cpu = <&cpu2>;
39 };
40 core3 {
41 cpu = <&cpu3>;
42 };
43 };
44 cluster1 {
45 core0 {
46 cpu = <&cpu4>;
47 };
48 core1 {
49 cpu = <&cpu5>;
50 };
51 core2 {
52 cpu = <&cpu6>;
53 };
54 core3 {
55 cpu = <&cpu7>;
56 };
57 };
58 cluster2 {
59 core0 {
60 cpu = <&cpu8>;
61 };
62 core1 {
63 cpu = <&cpu9>;
64 };
65 core2 {
66 cpu = <&cpu10>;
67 };
68 core3 {
69 cpu = <&cpu11>;
70 };
71 };
72 cluster3 {
73 core0 {
74 cpu = <&cpu12>;
75 };
76 core1 {
77 cpu = <&cpu13>;
78 };
79 core2 {
80 cpu = <&cpu14>;
81 };
82 core3 {
83 cpu = <&cpu15>;
84 };
85 };
86 };
87
88 cpu0: cpu@10000 {
89 device_type = "cpu";
90 compatible = "arm,cortex-a57", "arm,armv8";
91 reg = <0x10000>;
92 enable-method = "psci";
93 next-level-cache = <&cluster0_l2>;
94 };
95
96 cpu1: cpu@10001 {
97 device_type = "cpu";
98 compatible = "arm,cortex-a57", "arm,armv8";
99 reg = <0x10001>;
100 enable-method = "psci";
101 next-level-cache = <&cluster0_l2>;
102 };
103
104 cpu2: cpu@10002 {
105 device_type = "cpu";
106 compatible = "arm,cortex-a57", "arm,armv8";
107 reg = <0x10002>;
108 enable-method = "psci";
109 next-level-cache = <&cluster0_l2>;
110 };
111
112 cpu3: cpu@10003 {
113 device_type = "cpu";
114 compatible = "arm,cortex-a57", "arm,armv8";
115 reg = <0x10003>;
116 enable-method = "psci";
117 next-level-cache = <&cluster0_l2>;
118 };
119
120 cpu4: cpu@10100 {
121 device_type = "cpu";
122 compatible = "arm,cortex-a57", "arm,armv8";
123 reg = <0x10100>;
124 enable-method = "psci";
125 next-level-cache = <&cluster1_l2>;
126 };
127
128 cpu5: cpu@10101 {
129 device_type = "cpu";
130 compatible = "arm,cortex-a57", "arm,armv8";
131 reg = <0x10101>;
132 enable-method = "psci";
133 next-level-cache = <&cluster1_l2>;
134 };
135
136 cpu6: cpu@10102 {
137 device_type = "cpu";
138 compatible = "arm,cortex-a57", "arm,armv8";
139 reg = <0x10102>;
140 enable-method = "psci";
141 next-level-cache = <&cluster1_l2>;
142 };
143
144 cpu7: cpu@10103 {
145 device_type = "cpu";
146 compatible = "arm,cortex-a57", "arm,armv8";
147 reg = <0x10103>;
148 enable-method = "psci";
149 next-level-cache = <&cluster1_l2>;
150 };
151
152 cpu8: cpu@10200 {
153 device_type = "cpu";
154 compatible = "arm,cortex-a57", "arm,armv8";
155 reg = <0x10200>;
156 enable-method = "psci";
157 next-level-cache = <&cluster2_l2>;
158 };
159
160 cpu9: cpu@10201 {
161 device_type = "cpu";
162 compatible = "arm,cortex-a57", "arm,armv8";
163 reg = <0x10201>;
164 enable-method = "psci";
165 next-level-cache = <&cluster2_l2>;
166 };
167
168 cpu10: cpu@10202 {
169 device_type = "cpu";
170 compatible = "arm,cortex-a57", "arm,armv8";
171 reg = <0x10202>;
172 enable-method = "psci";
173 next-level-cache = <&cluster2_l2>;
174 };
175
176 cpu11: cpu@10203 {
177 device_type = "cpu";
178 compatible = "arm,cortex-a57", "arm,armv8";
179 reg = <0x10203>;
180 enable-method = "psci";
181 next-level-cache = <&cluster2_l2>;
182 };
183
184 cpu12: cpu@10300 {
185 device_type = "cpu";
186 compatible = "arm,cortex-a57", "arm,armv8";
187 reg = <0x10300>;
188 enable-method = "psci";
189 next-level-cache = <&cluster3_l2>;
190 };
191
192 cpu13: cpu@10301 {
193 device_type = "cpu";
194 compatible = "arm,cortex-a57", "arm,armv8";
195 reg = <0x10301>;
196 enable-method = "psci";
197 next-level-cache = <&cluster3_l2>;
198 };
199
200 cpu14: cpu@10302 {
201 device_type = "cpu";
202 compatible = "arm,cortex-a57", "arm,armv8";
203 reg = <0x10302>;
204 enable-method = "psci";
205 next-level-cache = <&cluster3_l2>;
206 };
207
208 cpu15: cpu@10303 {
209 device_type = "cpu";
210 compatible = "arm,cortex-a57", "arm,armv8";
211 reg = <0x10303>;
212 enable-method = "psci";
213 next-level-cache = <&cluster3_l2>;
214 };
215
216 cluster0_l2: l2-cache0 {
217 compatible = "cache";
218 };
219
220 cluster1_l2: l2-cache1 {
221 compatible = "cache";
222 };
223
224 cluster2_l2: l2-cache2 {
225 compatible = "cache";
226 };
227
228 cluster3_l2: l2-cache3 {
229 compatible = "cache";
230 };
231 };
232
233 gic: interrupt-controller@4d000000 {
234 compatible = "arm,gic-v3";
235 #interrupt-cells = <3>;
236 #address-cells = <2>;
237 #size-cells = <2>;
238 ranges;
239 interrupt-controller;
240 #redistributor-regions = <1>;
241 redistributor-stride = <0x0 0x30000>;
242 reg = <0x0 0x4d000000 0 0x10000>, /* GICD */
243 <0x0 0x4d100000 0 0x300000>, /* GICR */
244 <0x0 0xfe000000 0 0x10000>, /* GICC */
245 <0x0 0xfe010000 0 0x10000>, /* GICH */
246 <0x0 0xfe020000 0 0x10000>; /* GICV */
247 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
248
249 its_dsa: interrupt-controller@c6000000 {
250 compatible = "arm,gic-v3-its";
251 msi-controller;
252 #msi-cells = <1>;
253 reg = <0x0 0xc6000000 0x0 0x40000>;
254 };
255 };
256
257 timer {
258 compatible = "arm,armv8-timer";
259 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
260 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
261 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
262 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
263 };
264
265 pmu {
266 compatible = "arm,cortex-a57-pmu";
267 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
268 };
269
270 mbigen_pcie@a0080000 {
271 compatible = "hisilicon,mbigen-v2";
272 reg = <0x0 0xa0080000 0x0 0x10000>;
273
274 mbigen_usb: intc_usb {
275 msi-parent = <&its_dsa 0x40080>;
276 interrupt-controller;
277 #interrupt-cells = <2>;
278 num-pins = <2>;
279 };
280 };
281
282 soc {
283 compatible = "simple-bus";
284 #address-cells = <2>;
285 #size-cells = <2>;
286 ranges;
287
288 usb_ohci: ohci@a7030000 {
289 compatible = "generic-ohci";
290 reg = <0x0 0xa7030000 0x0 0x10000>;
291 interrupt-parent = <&mbigen_usb>;
292 interrupts = <64 4>;
293 dma-coherent;
294 status = "disabled";
295 };
296
297 usb_ehci: ehci@a7020000 {
298 compatible = "generic-ehci";
299 reg = <0x0 0xa7020000 0x0 0x10000>;
300 interrupt-parent = <&mbigen_usb>;
301 interrupts = <65 4>;
302 dma-coherent;
303 status = "disabled";
304 };
305 };
306
307};
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-02 15:37:16 -0400