aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/mach-exynos/common.c218
-rw-r--r--arch/arm/mach-exynos/common.h3
-rw-r--r--drivers/irqchip/Makefile1
-rw-r--r--drivers/irqchip/exynos-combiner.c230
4 files changed, 236 insertions, 216 deletions
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 9ce3e54a77c4..4bf62c97849f 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -12,6 +12,7 @@
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14#include <linux/irq.h> 14#include <linux/irq.h>
15#include <linux/irqchip.h>
15#include <linux/io.h> 16#include <linux/io.h>
16#include <linux/device.h> 17#include <linux/device.h>
17#include <linux/gpio.h> 18#include <linux/gpio.h>
@@ -438,218 +439,6 @@ static void __init exynos5_init_clocks(int xtal)
438#endif 439#endif
439} 440}
440 441
441#define COMBINER_ENABLE_SET 0x0
442#define COMBINER_ENABLE_CLEAR 0x4
443#define COMBINER_INT_STATUS 0xC
444
445static DEFINE_SPINLOCK(irq_controller_lock);
446
447struct combiner_chip_data {
448 unsigned int irq_offset;
449 unsigned int irq_mask;
450 void __iomem *base;
451};
452
453static struct irq_domain *combiner_irq_domain;
454static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
455
456static inline void __iomem *combiner_base(struct irq_data *data)
457{
458 struct combiner_chip_data *combiner_data =
459 irq_data_get_irq_chip_data(data);
460
461 return combiner_data->base;
462}
463
464static void combiner_mask_irq(struct irq_data *data)
465{
466 u32 mask = 1 << (data->hwirq % 32);
467
468 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
469}
470
471static void combiner_unmask_irq(struct irq_data *data)
472{
473 u32 mask = 1 << (data->hwirq % 32);
474
475 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
476}
477
478static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
479{
480 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
481 struct irq_chip *chip = irq_get_chip(irq);
482 unsigned int cascade_irq, combiner_irq;
483 unsigned long status;
484
485 chained_irq_enter(chip, desc);
486
487 spin_lock(&irq_controller_lock);
488 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
489 spin_unlock(&irq_controller_lock);
490 status &= chip_data->irq_mask;
491
492 if (status == 0)
493 goto out;
494
495 combiner_irq = __ffs(status);
496
497 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
498 if (unlikely(cascade_irq >= NR_IRQS))
499 do_bad_IRQ(cascade_irq, desc);
500 else
501 generic_handle_irq(cascade_irq);
502
503 out:
504 chained_irq_exit(chip, desc);
505}
506
507static struct irq_chip combiner_chip = {
508 .name = "COMBINER",
509 .irq_mask = combiner_mask_irq,
510 .irq_unmask = combiner_unmask_irq,
511};
512
513static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
514{
515 unsigned int max_nr;
516
517 if (soc_is_exynos5250())
518 max_nr = EXYNOS5_MAX_COMBINER_NR;
519 else
520 max_nr = EXYNOS4_MAX_COMBINER_NR;
521
522 if (combiner_nr >= max_nr)
523 BUG();
524 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
525 BUG();
526 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
527}
528
529static void __init combiner_init_one(unsigned int combiner_nr,
530 void __iomem *base)
531{
532 combiner_data[combiner_nr].base = base;
533 combiner_data[combiner_nr].irq_offset = irq_find_mapping(
534 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
535 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
536
537 /* Disable all interrupts */
538 __raw_writel(combiner_data[combiner_nr].irq_mask,
539 base + COMBINER_ENABLE_CLEAR);
540}
541
542#ifdef CONFIG_OF
543static int combiner_irq_domain_xlate(struct irq_domain *d,
544 struct device_node *controller,
545 const u32 *intspec, unsigned int intsize,
546 unsigned long *out_hwirq,
547 unsigned int *out_type)
548{
549 if (d->of_node != controller)
550 return -EINVAL;
551
552 if (intsize < 2)
553 return -EINVAL;
554
555 *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
556 *out_type = 0;
557
558 return 0;
559}
560#else
561static int combiner_irq_domain_xlate(struct irq_domain *d,
562 struct device_node *controller,
563 const u32 *intspec, unsigned int intsize,
564 unsigned long *out_hwirq,
565 unsigned int *out_type)
566{
567 return -EINVAL;
568}
569#endif
570
571static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
572 irq_hw_number_t hw)
573{
574 irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
575 irq_set_chip_data(irq, &combiner_data[hw >> 3]);
576 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
577
578 return 0;
579}
580
581static struct irq_domain_ops combiner_irq_domain_ops = {
582 .xlate = combiner_irq_domain_xlate,
583 .map = combiner_irq_domain_map,
584};
585
586static void __init combiner_init(void __iomem *combiner_base,
587 struct device_node *np)
588{
589 int i, irq, irq_base;
590 unsigned int max_nr, nr_irq;
591
592 if (np) {
593 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
594 pr_warning("%s: number of combiners not specified, "
595 "setting default as %d.\n",
596 __func__, EXYNOS4_MAX_COMBINER_NR);
597 max_nr = EXYNOS4_MAX_COMBINER_NR;
598 }
599 } else {
600 max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
601 EXYNOS4_MAX_COMBINER_NR;
602 }
603 nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
604
605 irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
606 if (IS_ERR_VALUE(irq_base)) {
607 irq_base = COMBINER_IRQ(0, 0);
608 pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
609 }
610
611 combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
612 &combiner_irq_domain_ops, &combiner_data);
613 if (WARN_ON(!combiner_irq_domain)) {
614 pr_warning("%s: irq domain init failed\n", __func__);
615 return;
616 }
617
618 for (i = 0; i < max_nr; i++) {
619 combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
620 irq = IRQ_SPI(i);
621#ifdef CONFIG_OF
622 if (np)
623 irq = irq_of_parse_and_map(np, i);
624#endif
625 combiner_cascade_irq(i, irq);
626 }
627}
628
629#ifdef CONFIG_OF
630static int __init combiner_of_init(struct device_node *np,
631 struct device_node *parent)
632{
633 void __iomem *combiner_base;
634
635 combiner_base = of_iomap(np, 0);
636 if (!combiner_base) {
637 pr_err("%s: failed to map combiner registers\n", __func__);
638 return -ENXIO;
639 }
640
641 combiner_init(combiner_base, np);
642
643 return 0;
644}
645
646static const struct of_device_id exynos_dt_irq_match[] = {
647 { .compatible = "samsung,exynos4210-combiner",
648 .data = combiner_of_init, },
649 {},
650};
651#endif
652
653void __init exynos4_init_irq(void) 442void __init exynos4_init_irq(void)
654{ 443{
655 unsigned int gic_bank_offset; 444 unsigned int gic_bank_offset;
@@ -659,10 +448,8 @@ void __init exynos4_init_irq(void)
659 if (!of_have_populated_dt()) 448 if (!of_have_populated_dt())
660 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL); 449 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
661#ifdef CONFIG_OF 450#ifdef CONFIG_OF
662 else { 451 else
663 irqchip_init(); 452 irqchip_init();
664 of_irq_init(exynos_dt_irq_match);
665 }
666#endif 453#endif
667 454
668 if (!of_have_populated_dt()) 455 if (!of_have_populated_dt())
@@ -680,7 +467,6 @@ void __init exynos5_init_irq(void)
680{ 467{
681#ifdef CONFIG_OF 468#ifdef CONFIG_OF
682 irqchip_init(); 469 irqchip_init();
683 of_irq_init(exynos_dt_irq_match);
684#endif 470#endif
685 /* 471 /*
686 * The parameters of s5p_init_irq() are for VIC init. 472 * The parameters of s5p_init_irq() are for VIC init.
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index feefc86293c2..9339bb8954be 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -60,6 +60,9 @@ void exynos4212_register_clocks(void);
60#define exynos4212_register_clocks() 60#define exynos4212_register_clocks()
61#endif 61#endif
62 62
63struct device_node;
64void combiner_init(void __iomem *combiner_base, struct device_node *np);
65
63extern struct smp_operations exynos_smp_ops; 66extern struct smp_operations exynos_smp_ops;
64 67
65extern void exynos_cpu_die(unsigned int cpu); 68extern void exynos_cpu_die(unsigned int cpu);
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 0fb865574390..e65fbf2cdf71 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -1,6 +1,7 @@
1obj-$(CONFIG_IRQCHIP) += irqchip.o 1obj-$(CONFIG_IRQCHIP) += irqchip.o
2 2
3obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o 3obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
4obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
4obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o 5obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o
5obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o 6obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
6obj-$(CONFIG_ARM_GIC) += irq-gic.o 7obj-$(CONFIG_ARM_GIC) += irq-gic.o
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
new file mode 100644
index 000000000000..04d86a9803f4
--- /dev/null
+++ b/drivers/irqchip/exynos-combiner.c
@@ -0,0 +1,230 @@
1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Combiner irqchip for EXYNOS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/err.h>
12#include <linux/export.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/irqdomain.h>
16#include <linux/of_address.h>
17#include <linux/of_irq.h>
18#include <asm/mach/irq.h>
19
20#include <plat/cpu.h>
21
22#include "irqchip.h"
23
24#define COMBINER_ENABLE_SET 0x0
25#define COMBINER_ENABLE_CLEAR 0x4
26#define COMBINER_INT_STATUS 0xC
27
28static DEFINE_SPINLOCK(irq_controller_lock);
29
30struct combiner_chip_data {
31 unsigned int irq_offset;
32 unsigned int irq_mask;
33 void __iomem *base;
34};
35
36static struct irq_domain *combiner_irq_domain;
37static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
38
39static inline void __iomem *combiner_base(struct irq_data *data)
40{
41 struct combiner_chip_data *combiner_data =
42 irq_data_get_irq_chip_data(data);
43
44 return combiner_data->base;
45}
46
47static void combiner_mask_irq(struct irq_data *data)
48{
49 u32 mask = 1 << (data->hwirq % 32);
50
51 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
52}
53
54static void combiner_unmask_irq(struct irq_data *data)
55{
56 u32 mask = 1 << (data->hwirq % 32);
57
58 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
59}
60
61static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
62{
63 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
64 struct irq_chip *chip = irq_get_chip(irq);
65 unsigned int cascade_irq, combiner_irq;
66 unsigned long status;
67
68 chained_irq_enter(chip, desc);
69
70 spin_lock(&irq_controller_lock);
71 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
72 spin_unlock(&irq_controller_lock);
73 status &= chip_data->irq_mask;
74
75 if (status == 0)
76 goto out;
77
78 combiner_irq = __ffs(status);
79
80 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
81 if (unlikely(cascade_irq >= NR_IRQS))
82 do_bad_IRQ(cascade_irq, desc);
83 else
84 generic_handle_irq(cascade_irq);
85
86 out:
87 chained_irq_exit(chip, desc);
88}
89
90static struct irq_chip combiner_chip = {
91 .name = "COMBINER",
92 .irq_mask = combiner_mask_irq,
93 .irq_unmask = combiner_unmask_irq,
94};
95
96static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
97{
98 unsigned int max_nr;
99
100 if (soc_is_exynos5250())
101 max_nr = EXYNOS5_MAX_COMBINER_NR;
102 else
103 max_nr = EXYNOS4_MAX_COMBINER_NR;
104
105 if (combiner_nr >= max_nr)
106 BUG();
107 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
108 BUG();
109 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
110}
111
112static void __init combiner_init_one(unsigned int combiner_nr,
113 void __iomem *base)
114{
115 combiner_data[combiner_nr].base = base;
116 combiner_data[combiner_nr].irq_offset = irq_find_mapping(
117 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
118 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
119
120 /* Disable all interrupts */
121 __raw_writel(combiner_data[combiner_nr].irq_mask,
122 base + COMBINER_ENABLE_CLEAR);
123}
124
125#ifdef CONFIG_OF
126static int combiner_irq_domain_xlate(struct irq_domain *d,
127 struct device_node *controller,
128 const u32 *intspec, unsigned int intsize,
129 unsigned long *out_hwirq,
130 unsigned int *out_type)
131{
132 if (d->of_node != controller)
133 return -EINVAL;
134
135 if (intsize < 2)
136 return -EINVAL;
137
138 *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
139 *out_type = 0;
140
141 return 0;
142}
143#else
144static int combiner_irq_domain_xlate(struct irq_domain *d,
145 struct device_node *controller,
146 const u32 *intspec, unsigned int intsize,
147 unsigned long *out_hwirq,
148 unsigned int *out_type)
149{
150 return -EINVAL;
151}
152#endif
153
154static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
155 irq_hw_number_t hw)
156{
157 irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
158 irq_set_chip_data(irq, &combiner_data[hw >> 3]);
159 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
160
161 return 0;
162}
163
164static struct irq_domain_ops combiner_irq_domain_ops = {
165 .xlate = combiner_irq_domain_xlate,
166 .map = combiner_irq_domain_map,
167};
168
169void __init combiner_init(void __iomem *combiner_base,
170 struct device_node *np)
171{
172 int i, irq, irq_base;
173 unsigned int max_nr, nr_irq;
174
175 if (np) {
176 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
177 pr_warning("%s: number of combiners not specified, "
178 "setting default as %d.\n",
179 __func__, EXYNOS4_MAX_COMBINER_NR);
180 max_nr = EXYNOS4_MAX_COMBINER_NR;
181 }
182 } else {
183 max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
184 EXYNOS4_MAX_COMBINER_NR;
185 }
186 nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
187
188 irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
189 if (IS_ERR_VALUE(irq_base)) {
190 irq_base = COMBINER_IRQ(0, 0);
191 pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
192 }
193
194 combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
195 &combiner_irq_domain_ops, &combiner_data);
196 if (WARN_ON(!combiner_irq_domain)) {
197 pr_warning("%s: irq domain init failed\n", __func__);
198 return;
199 }
200
201 for (i = 0; i < max_nr; i++) {
202 combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
203 irq = IRQ_SPI(i);
204#ifdef CONFIG_OF
205 if (np)
206 irq = irq_of_parse_and_map(np, i);
207#endif
208 combiner_cascade_irq(i, irq);
209 }
210}
211
212#ifdef CONFIG_OF
213static int __init combiner_of_init(struct device_node *np,
214 struct device_node *parent)
215{
216 void __iomem *combiner_base;
217
218 combiner_base = of_iomap(np, 0);
219 if (!combiner_base) {
220 pr_err("%s: failed to map combiner registers\n", __func__);
221 return -ENXIO;
222 }
223
224 combiner_init(combiner_base, np);
225
226 return 0;
227}
228IRQCHIP_DECLARE(exynos4210_combiner, "samsung,exynos4210-combiner",
229 combiner_of_init);
230#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-31 19:19:01 -0500