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-rw-r--r--crypto/testmgr.c43
-rw-r--r--drivers/crypto/ccree/cc_cipher.c350
-rw-r--r--drivers/crypto/ccree/cc_cipher.h30
3 files changed, 361 insertions, 62 deletions
diff --git a/crypto/testmgr.c b/crypto/testmgr.c
index 397b117309f1..c31da0f3f680 100644
--- a/crypto/testmgr.c
+++ b/crypto/testmgr.c
@@ -2582,6 +2582,13 @@ static const struct alg_test_desc alg_test_descs[] = {
2582 } 2582 }
2583 } 2583 }
2584 }, { 2584 }, {
2585 /* Same as cbc(aes) except the key is stored in
2586 * hardware secure memory which we reference by index
2587 */
2588 .alg = "cbc(paes)",
2589 .test = alg_test_null,
2590 .fips_allowed = 1,
2591 }, {
2585 .alg = "cbc(serpent)", 2592 .alg = "cbc(serpent)",
2586 .test = alg_test_skcipher, 2593 .test = alg_test_skcipher,
2587 .suite = { 2594 .suite = {
@@ -2728,6 +2735,13 @@ static const struct alg_test_desc alg_test_descs[] = {
2728 } 2735 }
2729 } 2736 }
2730 }, { 2737 }, {
2738 /* Same as ctr(aes) except the key is stored in
2739 * hardware secure memory which we reference by index
2740 */
2741 .alg = "ctr(paes)",
2742 .test = alg_test_null,
2743 .fips_allowed = 1,
2744 }, {
2731 .alg = "ctr(serpent)", 2745 .alg = "ctr(serpent)",
2732 .test = alg_test_skcipher, 2746 .test = alg_test_skcipher,
2733 .suite = { 2747 .suite = {
@@ -2998,6 +3012,13 @@ static const struct alg_test_desc alg_test_descs[] = {
2998 } 3012 }
2999 } 3013 }
3000 }, { 3014 }, {
3015 /* Same as ecb(aes) except the key is stored in
3016 * hardware secure memory which we reference by index
3017 */
3018 .alg = "ecb(paes)",
3019 .test = alg_test_null,
3020 .fips_allowed = 1,
3021 }, {
3001 .alg = "ecb(khazad)", 3022 .alg = "ecb(khazad)",
3002 .test = alg_test_skcipher, 3023 .test = alg_test_skcipher,
3003 .suite = { 3024 .suite = {
@@ -3325,6 +3346,13 @@ static const struct alg_test_desc alg_test_descs[] = {
3325 } 3346 }
3326 } 3347 }
3327 }, { 3348 }, {
3349 /* Same as ofb(aes) except the key is stored in
3350 * hardware secure memory which we reference by index
3351 */
3352 .alg = "ofb(paes)",
3353 .test = alg_test_null,
3354 .fips_allowed = 1,
3355 }, {
3328 .alg = "pcbc(fcrypt)", 3356 .alg = "pcbc(fcrypt)",
3329 .test = alg_test_skcipher, 3357 .test = alg_test_skcipher,
3330 .suite = { 3358 .suite = {
@@ -3582,6 +3610,21 @@ static const struct alg_test_desc alg_test_descs[] = {
3582 } 3610 }
3583 } 3611 }
3584 }, { 3612 }, {
3613 /* Same as xts(aes) except the key is stored in
3614 * hardware secure memory which we reference by index
3615 */
3616 .alg = "xts(paes)",
3617 .test = alg_test_null,
3618 .fips_allowed = 1,
3619 }, {
3620 .alg = "xts4096(paes)",
3621 .test = alg_test_null,
3622 .fips_allowed = 1,
3623 }, {
3624 .alg = "xts512(paes)",
3625 .test = alg_test_null,
3626 .fips_allowed = 1,
3627 }, {
3585 .alg = "xts(camellia)", 3628 .alg = "xts(camellia)",
3586 .test = alg_test_skcipher, 3629 .test = alg_test_skcipher,
3587 .suite = { 3630 .suite = {
diff --git a/drivers/crypto/ccree/cc_cipher.c b/drivers/crypto/ccree/cc_cipher.c
index df98f7afe645..d2810c183b73 100644
--- a/drivers/crypto/ccree/cc_cipher.c
+++ b/drivers/crypto/ccree/cc_cipher.c
@@ -42,6 +42,7 @@ struct cc_cipher_ctx {
42 int cipher_mode; 42 int cipher_mode;
43 int flow_mode; 43 int flow_mode;
44 unsigned int flags; 44 unsigned int flags;
45 bool hw_key;
45 struct cc_user_key_info user; 46 struct cc_user_key_info user;
46 struct cc_hw_key_info hw; 47 struct cc_hw_key_info hw;
47 struct crypto_shash *shash_tfm; 48 struct crypto_shash *shash_tfm;
@@ -49,6 +50,13 @@ struct cc_cipher_ctx {
49 50
50static void cc_cipher_complete(struct device *dev, void *cc_req, int err); 51static void cc_cipher_complete(struct device *dev, void *cc_req, int err);
51 52
53static inline bool cc_is_hw_key(struct crypto_tfm *tfm)
54{
55 struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
56
57 return ctx_p->hw_key;
58}
59
52static int validate_keys_sizes(struct cc_cipher_ctx *ctx_p, u32 size) 60static int validate_keys_sizes(struct cc_cipher_ctx *ctx_p, u32 size)
53{ 61{
54 switch (ctx_p->flow_mode) { 62 switch (ctx_p->flow_mode) {
@@ -211,7 +219,7 @@ struct tdes_keys {
211 u8 key3[DES_KEY_SIZE]; 219 u8 key3[DES_KEY_SIZE];
212}; 220};
213 221
214static enum cc_hw_crypto_key hw_key_to_cc_hw_key(int slot_num) 222static enum cc_hw_crypto_key cc_slot_to_hw_key(int slot_num)
215{ 223{
216 switch (slot_num) { 224 switch (slot_num) {
217 case 0: 225 case 0:
@@ -226,69 +234,100 @@ static enum cc_hw_crypto_key hw_key_to_cc_hw_key(int slot_num)
226 return END_OF_KEYS; 234 return END_OF_KEYS;
227} 235}
228 236
229static int cc_cipher_setkey(struct crypto_skcipher *sktfm, const u8 *key, 237static int cc_cipher_sethkey(struct crypto_skcipher *sktfm, const u8 *key,
230 unsigned int keylen) 238 unsigned int keylen)
231{ 239{
232 struct crypto_tfm *tfm = crypto_skcipher_tfm(sktfm); 240 struct crypto_tfm *tfm = crypto_skcipher_tfm(sktfm);
233 struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); 241 struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
234 struct device *dev = drvdata_to_dev(ctx_p->drvdata); 242 struct device *dev = drvdata_to_dev(ctx_p->drvdata);
235 u32 tmp[DES3_EDE_EXPKEY_WORDS]; 243 struct cc_hkey_info hki;
236 struct cc_crypto_alg *cc_alg =
237 container_of(tfm->__crt_alg, struct cc_crypto_alg,
238 skcipher_alg.base);
239 unsigned int max_key_buf_size = cc_alg->skcipher_alg.max_keysize;
240 244
241 dev_dbg(dev, "Setting key in context @%p for %s. keylen=%u\n", 245 dev_dbg(dev, "Setting HW key in context @%p for %s. keylen=%u\n",
242 ctx_p, crypto_tfm_alg_name(tfm), keylen); 246 ctx_p, crypto_tfm_alg_name(tfm), keylen);
243 dump_byte_array("key", (u8 *)key, keylen); 247 dump_byte_array("key", (u8 *)key, keylen);
244 248
245 /* STAT_PHASE_0: Init and sanity checks */ 249 /* STAT_PHASE_0: Init and sanity checks */
246 250
251 /* This check the size of the hardware key token */
252 if (keylen != sizeof(hki)) {
253 dev_err(dev, "Unsupported HW key size %d.\n", keylen);
254 crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
255 return -EINVAL;
256 }
257
258 if (ctx_p->flow_mode != S_DIN_to_AES) {
259 dev_err(dev, "HW key not supported for non-AES flows\n");
260 return -EINVAL;
261 }
262
263 memcpy(&hki, key, keylen);
264
265 /* The real key len for crypto op is the size of the HW key
266 * referenced by the HW key slot, not the hardware key token
267 */
268 keylen = hki.keylen;
269
247 if (validate_keys_sizes(ctx_p, keylen)) { 270 if (validate_keys_sizes(ctx_p, keylen)) {
248 dev_err(dev, "Unsupported key size %d.\n", keylen); 271 dev_err(dev, "Unsupported key size %d.\n", keylen);
249 crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); 272 crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
250 return -EINVAL; 273 return -EINVAL;
251 } 274 }
252 275
253 if (cc_is_hw_key(tfm)) { 276 ctx_p->hw.key1_slot = cc_slot_to_hw_key(hki.hw_key1);
254 /* setting HW key slots */ 277 if (ctx_p->hw.key1_slot == END_OF_KEYS) {
255 struct arm_hw_key_info *hki = (struct arm_hw_key_info *)key; 278 dev_err(dev, "Unsupported hw key1 number (%d)\n", hki.hw_key1);
279 return -EINVAL;
280 }
256 281
257 if (ctx_p->flow_mode != S_DIN_to_AES) { 282 if (ctx_p->cipher_mode == DRV_CIPHER_XTS ||
258 dev_err(dev, "HW key not supported for non-AES flows\n"); 283 ctx_p->cipher_mode == DRV_CIPHER_ESSIV ||
284 ctx_p->cipher_mode == DRV_CIPHER_BITLOCKER) {
285 if (hki.hw_key1 == hki.hw_key2) {
286 dev_err(dev, "Illegal hw key numbers (%d,%d)\n",
287 hki.hw_key1, hki.hw_key2);
259 return -EINVAL; 288 return -EINVAL;
260 } 289 }
261 290 ctx_p->hw.key2_slot = cc_slot_to_hw_key(hki.hw_key2);
262 ctx_p->hw.key1_slot = hw_key_to_cc_hw_key(hki->hw_key1); 291 if (ctx_p->hw.key2_slot == END_OF_KEYS) {
263 if (ctx_p->hw.key1_slot == END_OF_KEYS) { 292 dev_err(dev, "Unsupported hw key2 number (%d)\n",
264 dev_err(dev, "Unsupported hw key1 number (%d)\n", 293 hki.hw_key2);
265 hki->hw_key1);
266 return -EINVAL; 294 return -EINVAL;
267 } 295 }
296 }
268 297
269 if (ctx_p->cipher_mode == DRV_CIPHER_XTS || 298 ctx_p->keylen = keylen;
270 ctx_p->cipher_mode == DRV_CIPHER_ESSIV || 299 ctx_p->hw_key = true;
271 ctx_p->cipher_mode == DRV_CIPHER_BITLOCKER) { 300 dev_dbg(dev, "cc_is_hw_key ret 0");
272 if (hki->hw_key1 == hki->hw_key2) { 301
273 dev_err(dev, "Illegal hw key numbers (%d,%d)\n", 302 return 0;
274 hki->hw_key1, hki->hw_key2); 303}
275 return -EINVAL; 304
276 } 305static int cc_cipher_setkey(struct crypto_skcipher *sktfm, const u8 *key,
277 ctx_p->hw.key2_slot = 306 unsigned int keylen)
278 hw_key_to_cc_hw_key(hki->hw_key2); 307{
279 if (ctx_p->hw.key2_slot == END_OF_KEYS) { 308 struct crypto_tfm *tfm = crypto_skcipher_tfm(sktfm);
280 dev_err(dev, "Unsupported hw key2 number (%d)\n", 309 struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
281 hki->hw_key2); 310 struct device *dev = drvdata_to_dev(ctx_p->drvdata);
282 return -EINVAL; 311 u32 tmp[DES3_EDE_EXPKEY_WORDS];
283 } 312 struct cc_crypto_alg *cc_alg =
284 } 313 container_of(tfm->__crt_alg, struct cc_crypto_alg,
314 skcipher_alg.base);
315 unsigned int max_key_buf_size = cc_alg->skcipher_alg.max_keysize;
316
317 dev_dbg(dev, "Setting key in context @%p for %s. keylen=%u\n",
318 ctx_p, crypto_tfm_alg_name(tfm), keylen);
319 dump_byte_array("key", (u8 *)key, keylen);
285 320
286 ctx_p->keylen = keylen; 321 /* STAT_PHASE_0: Init and sanity checks */
287 dev_dbg(dev, "cc_is_hw_key ret 0");
288 322
289 return 0; 323 if (validate_keys_sizes(ctx_p, keylen)) {
324 dev_err(dev, "Unsupported key size %d.\n", keylen);
325 crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
326 return -EINVAL;
290 } 327 }
291 328
329 ctx_p->hw_key = false;
330
292 /* 331 /*
293 * Verify DES weak keys 332 * Verify DES weak keys
294 * Note that we're dropping the expanded key since the 333 * Note that we're dropping the expanded key since the
@@ -735,6 +774,241 @@ static int cc_cipher_decrypt(struct skcipher_request *req)
735/* Block cipher alg */ 774/* Block cipher alg */
736static const struct cc_alg_template skcipher_algs[] = { 775static const struct cc_alg_template skcipher_algs[] = {
737 { 776 {
777 .name = "xts(paes)",
778 .driver_name = "xts-paes-ccree",
779 .blocksize = AES_BLOCK_SIZE,
780 .template_skcipher = {
781 .setkey = cc_cipher_sethkey,
782 .encrypt = cc_cipher_encrypt,
783 .decrypt = cc_cipher_decrypt,
784 .min_keysize = CC_HW_KEY_SIZE,
785 .max_keysize = CC_HW_KEY_SIZE,
786 .ivsize = AES_BLOCK_SIZE,
787 },
788 .cipher_mode = DRV_CIPHER_XTS,
789 .flow_mode = S_DIN_to_AES,
790 .min_hw_rev = CC_HW_REV_630,
791 },
792 {
793 .name = "xts512(paes)",
794 .driver_name = "xts-paes-du512-ccree",
795 .blocksize = AES_BLOCK_SIZE,
796 .template_skcipher = {
797 .setkey = cc_cipher_sethkey,
798 .encrypt = cc_cipher_encrypt,
799 .decrypt = cc_cipher_decrypt,
800 .min_keysize = CC_HW_KEY_SIZE,
801 .max_keysize = CC_HW_KEY_SIZE,
802 .ivsize = AES_BLOCK_SIZE,
803 },
804 .cipher_mode = DRV_CIPHER_XTS,
805 .flow_mode = S_DIN_to_AES,
806 .data_unit = 512,
807 .min_hw_rev = CC_HW_REV_712,
808 },
809 {
810 .name = "xts4096(paes)",
811 .driver_name = "xts-paes-du4096-ccree",
812 .blocksize = AES_BLOCK_SIZE,
813 .template_skcipher = {
814 .setkey = cc_cipher_sethkey,
815 .encrypt = cc_cipher_encrypt,
816 .decrypt = cc_cipher_decrypt,
817 .min_keysize = CC_HW_KEY_SIZE,
818 .max_keysize = CC_HW_KEY_SIZE,
819 .ivsize = AES_BLOCK_SIZE,
820 },
821 .cipher_mode = DRV_CIPHER_XTS,
822 .flow_mode = S_DIN_to_AES,
823 .data_unit = 4096,
824 .min_hw_rev = CC_HW_REV_712,
825 },
826 {
827 .name = "essiv(paes)",
828 .driver_name = "essiv-paes-ccree",
829 .blocksize = AES_BLOCK_SIZE,
830 .template_skcipher = {
831 .setkey = cc_cipher_sethkey,
832 .encrypt = cc_cipher_encrypt,
833 .decrypt = cc_cipher_decrypt,
834 .min_keysize = CC_HW_KEY_SIZE,
835 .max_keysize = CC_HW_KEY_SIZE,
836 .ivsize = AES_BLOCK_SIZE,
837 },
838 .cipher_mode = DRV_CIPHER_ESSIV,
839 .flow_mode = S_DIN_to_AES,
840 .min_hw_rev = CC_HW_REV_712,
841 },
842 {
843 .name = "essiv512(paes)",
844 .driver_name = "essiv-paes-du512-ccree",
845 .blocksize = AES_BLOCK_SIZE,
846 .template_skcipher = {
847 .setkey = cc_cipher_sethkey,
848 .encrypt = cc_cipher_encrypt,
849 .decrypt = cc_cipher_decrypt,
850 .min_keysize = CC_HW_KEY_SIZE,
851 .max_keysize = CC_HW_KEY_SIZE,
852 .ivsize = AES_BLOCK_SIZE,
853 },
854 .cipher_mode = DRV_CIPHER_ESSIV,
855 .flow_mode = S_DIN_to_AES,
856 .data_unit = 512,
857 .min_hw_rev = CC_HW_REV_712,
858 },
859 {
860 .name = "essiv4096(paes)",
861 .driver_name = "essiv-paes-du4096-ccree",
862 .blocksize = AES_BLOCK_SIZE,
863 .template_skcipher = {
864 .setkey = cc_cipher_sethkey,
865 .encrypt = cc_cipher_encrypt,
866 .decrypt = cc_cipher_decrypt,
867 .min_keysize = CC_HW_KEY_SIZE,
868 .max_keysize = CC_HW_KEY_SIZE,
869 .ivsize = AES_BLOCK_SIZE,
870 },
871 .cipher_mode = DRV_CIPHER_ESSIV,
872 .flow_mode = S_DIN_to_AES,
873 .data_unit = 4096,
874 .min_hw_rev = CC_HW_REV_712,
875 },
876 {
877 .name = "bitlocker(paes)",
878 .driver_name = "bitlocker-paes-ccree",
879 .blocksize = AES_BLOCK_SIZE,
880 .template_skcipher = {
881 .setkey = cc_cipher_sethkey,
882 .encrypt = cc_cipher_encrypt,
883 .decrypt = cc_cipher_decrypt,
884 .min_keysize = CC_HW_KEY_SIZE,
885 .max_keysize = CC_HW_KEY_SIZE,
886 .ivsize = AES_BLOCK_SIZE,
887 },
888 .cipher_mode = DRV_CIPHER_BITLOCKER,
889 .flow_mode = S_DIN_to_AES,
890 .min_hw_rev = CC_HW_REV_712,
891 },
892 {
893 .name = "bitlocker512(paes)",
894 .driver_name = "bitlocker-paes-du512-ccree",
895 .blocksize = AES_BLOCK_SIZE,
896 .template_skcipher = {
897 .setkey = cc_cipher_sethkey,
898 .encrypt = cc_cipher_encrypt,
899 .decrypt = cc_cipher_decrypt,
900 .min_keysize = CC_HW_KEY_SIZE,
901 .max_keysize = CC_HW_KEY_SIZE,
902 .ivsize = AES_BLOCK_SIZE,
903 },
904 .cipher_mode = DRV_CIPHER_BITLOCKER,
905 .flow_mode = S_DIN_to_AES,
906 .data_unit = 512,
907 .min_hw_rev = CC_HW_REV_712,
908 },
909 {
910 .name = "bitlocker4096(paes)",
911 .driver_name = "bitlocker-paes-du4096-ccree",
912 .blocksize = AES_BLOCK_SIZE,
913 .template_skcipher = {
914 .setkey = cc_cipher_sethkey,
915 .encrypt = cc_cipher_encrypt,
916 .decrypt = cc_cipher_decrypt,
917 .min_keysize = CC_HW_KEY_SIZE,
918 .max_keysize = CC_HW_KEY_SIZE,
919 .ivsize = AES_BLOCK_SIZE,
920 },
921 .cipher_mode = DRV_CIPHER_BITLOCKER,
922 .flow_mode = S_DIN_to_AES,
923 .data_unit = 4096,
924 .min_hw_rev = CC_HW_REV_712,
925 },
926 {
927 .name = "ecb(paes)",
928 .driver_name = "ecb-paes-ccree",
929 .blocksize = AES_BLOCK_SIZE,
930 .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
931 .template_skcipher = {
932 .setkey = cc_cipher_sethkey,
933 .encrypt = cc_cipher_encrypt,
934 .decrypt = cc_cipher_decrypt,
935 .min_keysize = CC_HW_KEY_SIZE,
936 .max_keysize = CC_HW_KEY_SIZE,
937 .ivsize = 0,
938 },
939 .cipher_mode = DRV_CIPHER_ECB,
940 .flow_mode = S_DIN_to_AES,
941 .min_hw_rev = CC_HW_REV_712,
942 },
943 {
944 .name = "cbc(paes)",
945 .driver_name = "cbc-paes-ccree",
946 .blocksize = AES_BLOCK_SIZE,
947 .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
948 .template_skcipher = {
949 .setkey = cc_cipher_sethkey,
950 .encrypt = cc_cipher_encrypt,
951 .decrypt = cc_cipher_decrypt,
952 .min_keysize = CC_HW_KEY_SIZE,
953 .max_keysize = CC_HW_KEY_SIZE,
954 .ivsize = AES_BLOCK_SIZE,
955 },
956 .cipher_mode = DRV_CIPHER_CBC,
957 .flow_mode = S_DIN_to_AES,
958 .min_hw_rev = CC_HW_REV_712,
959 },
960 {
961 .name = "ofb(paes)",
962 .driver_name = "ofb-paes-ccree",
963 .blocksize = AES_BLOCK_SIZE,
964 .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
965 .template_skcipher = {
966 .setkey = cc_cipher_sethkey,
967 .encrypt = cc_cipher_encrypt,
968 .decrypt = cc_cipher_decrypt,
969 .min_keysize = CC_HW_KEY_SIZE,
970 .max_keysize = CC_HW_KEY_SIZE,
971 .ivsize = AES_BLOCK_SIZE,
972 },
973 .cipher_mode = DRV_CIPHER_OFB,
974 .flow_mode = S_DIN_to_AES,
975 .min_hw_rev = CC_HW_REV_712,
976 },
977 {
978 .name = "cts1(cbc(paes))",
979 .driver_name = "cts1-cbc-paes-ccree",
980 .blocksize = AES_BLOCK_SIZE,
981 .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
982 .template_skcipher = {
983 .setkey = cc_cipher_sethkey,
984 .encrypt = cc_cipher_encrypt,
985 .decrypt = cc_cipher_decrypt,
986 .min_keysize = CC_HW_KEY_SIZE,
987 .max_keysize = CC_HW_KEY_SIZE,
988 .ivsize = AES_BLOCK_SIZE,
989 },
990 .cipher_mode = DRV_CIPHER_CBC_CTS,
991 .flow_mode = S_DIN_to_AES,
992 .min_hw_rev = CC_HW_REV_712,
993 },
994 {
995 .name = "ctr(paes)",
996 .driver_name = "ctr-paes-ccree",
997 .blocksize = 1,
998 .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
999 .template_skcipher = {
1000 .setkey = cc_cipher_sethkey,
1001 .encrypt = cc_cipher_encrypt,
1002 .decrypt = cc_cipher_decrypt,
1003 .min_keysize = CC_HW_KEY_SIZE,
1004 .max_keysize = CC_HW_KEY_SIZE,
1005 .ivsize = AES_BLOCK_SIZE,
1006 },
1007 .cipher_mode = DRV_CIPHER_CTR,
1008 .flow_mode = S_DIN_to_AES,
1009 .min_hw_rev = CC_HW_REV_712,
1010 },
1011 {
738 .name = "xts(aes)", 1012 .name = "xts(aes)",
739 .driver_name = "xts-aes-ccree", 1013 .driver_name = "xts-aes-ccree",
740 .blocksize = AES_BLOCK_SIZE, 1014 .blocksize = AES_BLOCK_SIZE,
diff --git a/drivers/crypto/ccree/cc_cipher.h b/drivers/crypto/ccree/cc_cipher.h
index 2a2a6f46c515..68444cfa936b 100644
--- a/drivers/crypto/ccree/cc_cipher.h
+++ b/drivers/crypto/ccree/cc_cipher.h
@@ -13,18 +13,6 @@
13#include "cc_driver.h" 13#include "cc_driver.h"
14#include "cc_buffer_mgr.h" 14#include "cc_buffer_mgr.h"
15 15
16/* Crypto cipher flags */
17#define CC_CRYPTO_CIPHER_KEY_KFDE0 BIT(0)
18#define CC_CRYPTO_CIPHER_KEY_KFDE1 BIT(1)
19#define CC_CRYPTO_CIPHER_KEY_KFDE2 BIT(2)
20#define CC_CRYPTO_CIPHER_KEY_KFDE3 BIT(3)
21#define CC_CRYPTO_CIPHER_DU_SIZE_512B BIT(4)
22
23#define CC_CRYPTO_CIPHER_KEY_KFDE_MASK (CC_CRYPTO_CIPHER_KEY_KFDE0 | \
24 CC_CRYPTO_CIPHER_KEY_KFDE1 | \
25 CC_CRYPTO_CIPHER_KEY_KFDE2 | \
26 CC_CRYPTO_CIPHER_KEY_KFDE3)
27
28struct cipher_req_ctx { 16struct cipher_req_ctx {
29 struct async_gen_req_ctx gen_ctx; 17 struct async_gen_req_ctx gen_ctx;
30 enum cc_req_dma_buf_type dma_buf_type; 18 enum cc_req_dma_buf_type dma_buf_type;
@@ -42,18 +30,12 @@ int cc_cipher_alloc(struct cc_drvdata *drvdata);
42 30
43int cc_cipher_free(struct cc_drvdata *drvdata); 31int cc_cipher_free(struct cc_drvdata *drvdata);
44 32
45struct arm_hw_key_info { 33struct cc_hkey_info {
46 int hw_key1; 34 u16 keylen;
47 int hw_key2; 35 u8 hw_key1;
48}; 36 u8 hw_key2;
37} __packed;
49 38
50/* 39#define CC_HW_KEY_SIZE sizeof(struct cc_hkey_info)
51 * This is a stub function that will replaced when we
52 * implement secure keys
53 */
54static inline bool cc_is_hw_key(struct crypto_tfm *tfm)
55{
56 return false;
57}
58 40
59#endif /*__CC_CIPHER_H__*/ 41#endif /*__CC_CIPHER_H__*/
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-17 15:13:46 -0400