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-rw-r--r--drivers/clk/ingenic/jz4770-cgu.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c
index a5ad69464e57..314f3143ca61 100644
--- a/drivers/clk/ingenic/jz4770-cgu.c
+++ b/drivers/clk/ingenic/jz4770-cgu.c
@@ -154,7 +154,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
154 "h1clk", CGU_CLK_DIV | CGU_CLK_GATE, 154 "h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
155 .parents = { JZ4770_CLK_PLL0, }, 155 .parents = { JZ4770_CLK_PLL0, },
156 .div = { CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1 }, 156 .div = { CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1 },
157 .gate = { CGU_REG_LCR, 30 }, 157 .gate = { CGU_REG_CLKGR1, 7 },
158 }, 158 },
159 [JZ4770_CLK_H2CLK] = { 159 [JZ4770_CLK_H2CLK] = {
160 "h2clk", CGU_CLK_DIV, 160 "h2clk", CGU_CLK_DIV,
@@ -362,7 +362,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
362 [JZ4770_CLK_VPU] = { 362 [JZ4770_CLK_VPU] = {
363 "vpu", CGU_CLK_GATE, 363 "vpu", CGU_CLK_GATE,
364 .parents = { JZ4770_CLK_H1CLK, }, 364 .parents = { JZ4770_CLK_H1CLK, },
365 .gate = { CGU_REG_CLKGR1, 7 }, 365 .gate = { CGU_REG_LCR, 30 },
366 }, 366 },
367 [JZ4770_CLK_MMC0] = { 367 [JZ4770_CLK_MMC0] = {
368 "mmc0", CGU_CLK_GATE, 368 "mmc0", CGU_CLK_GATE,