10 files changed, 656 insertions, 120 deletions

diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
index 2390e4e9c84c..eaf7e9b7ce6b 100644
--- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
+++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
@@ -7,33 +7,26 @@ Required properties:
 - compatible: "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795
               SoC.
 - reg: offset and length of the partial USB 2.0 Host register block.
-- reg-names: must be "usb2_host".
 - clocks: clock phandle and specifier pair(s).
 - #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
 
 Optional properties:
 To use a USB channel where USB 2.0 Host and HSUSB (USB 2.0 Peripheral) are
-combined, the device tree node should set HSUSB properties to reg and reg-names
-properties. This is because HSUSB has registers to select USB 2.0 host or
-peripheral at that channel:
-- reg: offset and length of the partial HSUSB register block.
-- reg-names: must be "hsusb".
+combined, the device tree node should set interrupt properties to use the
+channel as USB OTG:
 - interrupts: interrupt specifier for the PHY.
 
 Example (R-Car H3):
 
         usb-phy@ee080200 {
                 compatible = "renesas,usb2-phy-r8a7795";
-                reg = <0 0xee080200 0 0x700>, <0 0xe6590100 0 0x100>;
-                reg-names = "usb2_host", "hsusb";
+                reg = <0 0xee080200 0 0x700>;
                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&mstp7_clks R8A7795_CLK_EHCI0>,
-                         <&mstp7_clks R8A7795_CLK_HSUSB>;
+                clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;
         };
 
         usb-phy@ee0a0200 {
                 compatible = "renesas,usb2-phy-r8a7795";
                 reg = <0 0xee0a0200 0 0x700>;
-                reg-names = "usb2_host";
                 clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;
         };
diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
new file mode 100644
index 000000000000..50c4f9b00adf
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
@@ -0,0 +1,22 @@
+Rockchip specific extensions to the Analogix Display Port PHY
+------------------------------------
+
+Required properties:
+- compatible : should be one of the following supported values:
+         - "rockchip.rk3288-dp-phy"
+- clocks: from common clock binding: handle to dp clock.
+        of memory mapped region.
+- clock-names: from common clock binding:
+        Required elements: "24m"
+- rockchip,grf: phandle to the syscon managing the "general register files"
+- #phy-cells : from the generic PHY bindings, must be 0;
+
+Example:
+
+edp_phy: edp-phy {
+        compatible = "rockchip,rk3288-dp-phy";
+        rockchip,grf = <&grf>;
+        clocks = <&cru SCLK_EDP_24M>;
+        clock-names = "24m";
+        #phy-cells = <0>;
+};
diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
new file mode 100644
index 000000000000..61916f15a949
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
@@ -0,0 +1,19 @@
+Rockchip EMMC PHY
+-----------------------
+
+Required properties:
+ - compatible: rockchip,rk3399-emmc-phy
+ - rockchip,grf : phandle to the syscon managing the "general
+   register files"
+ - #phy-cells: must be 0
+ - reg: PHY configure reg address offset in "general
+   register files"
+
+Example:
+
+emmcphy: phy {
+        compatible = "rockchip,rk3399-emmc-phy";
+        rockchip,grf = <&grf>;
+        reg = <0xf780>;
+        #phy-cells = <0>;
+};
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 9a53c929f017..8a6c6c02f916 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -3491,6 +3491,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 
         ro              [KNL] Mount root device read-only on boot
 
+        rockchip.usb_uart
+                        Enable the uart passthrough on the designated usb port
+                        on Rockchip SoCs. When active, the signals of the
+                        debug-uart get routed to the D+ and D- pins of the usb
+                        port and the regular usb controller gets disabled.
+
         root=           [KNL] Root filesystem
                         See name_to_dev_t comment in init/do_mounts.c.
 
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 0124d17bd9fe..26566db09de0 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -32,7 +32,7 @@ config PHY_BERLIN_SATA
 config ARMADA375_USBCLUSTER_PHY
         def_bool y
         depends on MACH_ARMADA_375 || COMPILE_TEST
-        depends on OF
+        depends on OF && HAS_IOMEM
         select GENERIC_PHY
 
 config PHY_DM816X_USB
@@ -337,6 +337,20 @@ config PHY_ROCKCHIP_USB
         help
           Enable this to support the Rockchip USB 2.0 PHY.
 
+config PHY_ROCKCHIP_EMMC
+        tristate "Rockchip EMMC PHY Driver"
+        depends on ARCH_ROCKCHIP && OF
+        select GENERIC_PHY
+        help
+          Enable this to support the Rockchip EMMC PHY.
+
+config PHY_ROCKCHIP_DP
+        tristate "Rockchip Display Port PHY Driver"
+        depends on ARCH_ROCKCHIP && OF
+        select GENERIC_PHY
+        help
+          Enable this to support the Rockchip Display Port PHY.
+
 config PHY_ST_SPEAR1310_MIPHY
         tristate "ST SPEAR1310-MIPHY driver"
         select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index c80f09df3bb8..24596a96a887 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -37,6 +37,8 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)        += phy-exynos5-usbdrd.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)     += phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
+obj-$(CONFIG_PHY_ROCKCHIP_DP)           += phy-rockchip-dp.o
 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)     += phy-qcom-ipq806x-sata.o
 obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)    += phy-spear1310-miphy.o
 obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)    += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rcar-gen3-usb2.c b/drivers/phy/phy-rcar-gen3-usb2.c
index ef332ef4abc7..bc4f7dd821aa 100644
--- a/drivers/phy/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/phy-rcar-gen3-usb2.c
@@ -74,20 +74,6 @@
 #define USB2_ADPCTRL_IDPULLUP           BIT(5)  /* 1 = ID sampling is enabled */
 #define USB2_ADPCTRL_DRVVBUS            BIT(4)
 
-/******* HSUSB registers (original offset is +0x100) *******/
-#define HSUSB_LPSTS                     0x02
-#define HSUSB_UGCTRL2                   0x84
-
-/* Low Power Status register (LPSTS) */
-#define HSUSB_LPSTS_SUSPM               0x4000
-
-/* USB General control register 2 (UGCTRL2) */
-#define HSUSB_UGCTRL2_MASK              0x00000031 /* bit[31:6] should be 0 */
-#define HSUSB_UGCTRL2_USB0SEL           0x00000030
-#define HSUSB_UGCTRL2_USB0SEL_HOST      0x00000010
-#define HSUSB_UGCTRL2_USB0SEL_HS_USB    0x00000020
-#define HSUSB_UGCTRL2_USB0SEL_OTG       0x00000030
-
 struct rcar_gen3_data {
         void __iomem *base;
         struct clk *clk;
@@ -95,8 +81,8 @@ struct rcar_gen3_data {
 
 struct rcar_gen3_chan {
         struct rcar_gen3_data usb2;
-        struct rcar_gen3_data hsusb;
         struct phy *phy;
+        bool has_otg;
 };
 
 static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host)
@@ -202,24 +188,15 @@ static int rcar_gen3_phy_usb2_init(struct phy *p)
 {
         struct rcar_gen3_chan *channel = phy_get_drvdata(p);
         void __iomem *usb2_base = channel->usb2.base;
-        void __iomem *hsusb_base = channel->hsusb.base;
-        u32 val;
 
         /* Initialize USB2 part */
         writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE);
         writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
         writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
 
-        /* Initialize HSUSB part */
-        if (hsusb_base) {
-                val = readl(hsusb_base + HSUSB_UGCTRL2);
-                val = (val & ~HSUSB_UGCTRL2_USB0SEL) |
-                      HSUSB_UGCTRL2_USB0SEL_OTG;
-                writel(val & HSUSB_UGCTRL2_MASK, hsusb_base + HSUSB_UGCTRL2);
-
-                /* Initialize otg part */
+        /* Initialize otg part */
+        if (channel->has_otg)
                 rcar_gen3_init_otg(channel);
-        }
 
         return 0;
 }
@@ -237,7 +214,6 @@ static int rcar_gen3_phy_usb2_power_on(struct phy *p)
 {
         struct rcar_gen3_chan *channel = phy_get_drvdata(p);
         void __iomem *usb2_base = channel->usb2.base;
-        void __iomem *hsusb_base = channel->hsusb.base;
         u32 val;
 
         val = readl(usb2_base + USB2_USBCTR);
@@ -246,33 +222,6 @@ static int rcar_gen3_phy_usb2_power_on(struct phy *p)
         val &= ~USB2_USBCTR_PLL_RST;
         writel(val, usb2_base + USB2_USBCTR);
 
-        /*
-         * TODO: To reduce power consuming, this driver should set the SUSPM
-         *      after the PHY detects ID pin as peripheral.
-         */
-        if (hsusb_base) {
-                /* Power on HSUSB PHY */
-                val = readw(hsusb_base + HSUSB_LPSTS);
-                val |= HSUSB_LPSTS_SUSPM;
-                writew(val, hsusb_base + HSUSB_LPSTS);
-        }
-
-        return 0;
-}
-
-static int rcar_gen3_phy_usb2_power_off(struct phy *p)
-{
-        struct rcar_gen3_chan *channel = phy_get_drvdata(p);
-        void __iomem *hsusb_base = channel->hsusb.base;
-        u32 val;
-
-        if (hsusb_base) {
-                /* Power off HSUSB PHY */
-                val = readw(hsusb_base + HSUSB_LPSTS);
-                val &= ~HSUSB_LPSTS_SUSPM;
-                writew(val, hsusb_base + HSUSB_LPSTS);
-        }
-
         return 0;
 }
 
@@ -280,7 +229,6 @@ static struct phy_ops rcar_gen3_phy_usb2_ops = {
         .init           = rcar_gen3_phy_usb2_init,
         .exit           = rcar_gen3_phy_usb2_exit,
         .power_on       = rcar_gen3_phy_usb2_power_on,
-        .power_off      = rcar_gen3_phy_usb2_power_off,
         .owner          = THIS_MODULE,
 };
 
@@ -313,6 +261,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
         struct rcar_gen3_chan *channel;
         struct phy_provider *provider;
         struct resource *res;
+        int irq;
 
         if (!dev->of_node) {
                 dev_err(dev, "This driver needs device tree\n");
@@ -323,29 +272,19 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
         if (!channel)
                 return -ENOMEM;
 
-        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usb2_host");
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         channel->usb2.base = devm_ioremap_resource(dev, res);
         if (IS_ERR(channel->usb2.base))
                 return PTR_ERR(channel->usb2.base);
 
-        /* "hsusb" memory resource is optional */
-        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsusb");
-
-        /* To avoid error message by devm_ioremap_resource() */
-        if (res) {
-                int irq;
-
-                channel->hsusb.base = devm_ioremap_resource(dev, res);
-                if (IS_ERR(channel->hsusb.base))
-                        channel->hsusb.base = NULL;
-                /* call request_irq for OTG */
-                irq = platform_get_irq(pdev, 0);
-                if (irq >= 0)
-                        irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
-                                               IRQF_SHARED, dev_name(dev),
-                                               channel);
+        /* call request_irq for OTG */
+        irq = platform_get_irq(pdev, 0);
+        if (irq >= 0) {
+                irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
+                                       IRQF_SHARED, dev_name(dev), channel);
                 if (irq < 0)
                         dev_err(dev, "No irq handler (%d)\n", irq);
+                channel->has_otg = true;
         }
 
         /* devm_phy_create() will call pm_runtime_enable(dev); */
diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
new file mode 100644
index 000000000000..77e2d02e6bee
--- /dev/null
+++ b/drivers/phy/phy-rockchip-dp.c
@@ -0,0 +1,151 @@
+/*
+ * Rockchip DP PHY driver
+ *
+ * Copyright (C) 2016 FuZhou Rockchip Co., Ltd.
+ * Author: Yakir Yang <ykk@@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#define GRF_SOC_CON12                           0x0274
+
+#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK   BIT(20)
+#define GRF_EDP_REF_CLK_SEL_INTER               BIT(4)
+
+#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK           BIT(21)
+#define GRF_EDP_PHY_SIDDQ_ON                    0
+#define GRF_EDP_PHY_SIDDQ_OFF                   BIT(5)
+
+struct rockchip_dp_phy {
+        struct device  *dev;
+        struct regmap  *grf;
+        struct clk     *phy_24m;
+};
+
+static int rockchip_set_phy_state(struct phy *phy, bool enable)
+{
+        struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
+        int ret;
+
+        if (enable) {
+                ret = regmap_write(dp->grf, GRF_SOC_CON12,
+                                   GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
+                                   GRF_EDP_PHY_SIDDQ_ON);
+                if (ret < 0) {
+                        dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
+                        return ret;
+                }
+
+                ret = clk_prepare_enable(dp->phy_24m);
+        } else {
+                clk_disable_unprepare(dp->phy_24m);
+
+                ret = regmap_write(dp->grf, GRF_SOC_CON12,
+                                   GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
+                                   GRF_EDP_PHY_SIDDQ_OFF);
+        }
+
+        return ret;
+}
+
+static int rockchip_dp_phy_power_on(struct phy *phy)
+{
+        return rockchip_set_phy_state(phy, true);
+}
+
+static int rockchip_dp_phy_power_off(struct phy *phy)
+{
+        return rockchip_set_phy_state(phy, false);
+}
+
+static const struct phy_ops rockchip_dp_phy_ops = {
+        .power_on       = rockchip_dp_phy_power_on,
+        .power_off      = rockchip_dp_phy_power_off,
+        .owner          = THIS_MODULE,
+};
+
+static int rockchip_dp_phy_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct device_node *np = dev->of_node;
+        struct phy_provider *phy_provider;
+        struct rockchip_dp_phy *dp;
+        struct phy *phy;
+        int ret;
+
+        if (!np)
+                return -ENODEV;
+
+        dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+        if (IS_ERR(dp))
+                return -ENOMEM;
+
+        dp->dev = dev;
+
+        dp->phy_24m = devm_clk_get(dev, "24m");
+        if (IS_ERR(dp->phy_24m)) {
+                dev_err(dev, "cannot get clock 24m\n");
+                return PTR_ERR(dp->phy_24m);
+        }
+
+        ret = clk_set_rate(dp->phy_24m, 24000000);
+        if (ret < 0) {
+                dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
+                return ret;
+        }
+
+        dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+        if (IS_ERR(dp->grf)) {
+                dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
+                return PTR_ERR(dp->grf);
+        }
+
+        ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
+                           GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK);
+        if (ret != 0) {
+                dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
+                return ret;
+        }
+
+        phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
+        if (IS_ERR(phy)) {
+                dev_err(dev, "failed to create phy\n");
+                return PTR_ERR(phy);
+        }
+        phy_set_drvdata(phy, dp);
+
+        phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+        return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
+        { .compatible = "rockchip,rk3288-dp-phy" },
+        {}
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
+
+static struct platform_driver rockchip_dp_phy_driver = {
+        .probe          = rockchip_dp_phy_probe,
+        .driver         = {
+                .name   = "rockchip-dp-phy",
+                .of_match_table = rockchip_dp_phy_dt_ids,
+        },
+};
+
+module_platform_driver(rockchip_dp_phy_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip DP PHY driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c
new file mode 100644
index 000000000000..887b4c27195f
--- /dev/null
+++ b/drivers/phy/phy-rockchip-emmc.c
@@ -0,0 +1,229 @@
+/*
+ * Rockchip emmc PHY driver
+ *
+ * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
+ * Copyright (C) 2016 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(x + 16) set to 1 the BIT(x) can be written.
+ */
+#define HIWORD_UPDATE(val, mask, shift) \
+                ((val) << (shift) | (mask) << ((shift) + 16))
+
+/* Register definition */
+#define GRF_EMMCPHY_CON0        0x0
+#define GRF_EMMCPHY_CON1        0x4
+#define GRF_EMMCPHY_CON2        0x8
+#define GRF_EMMCPHY_CON3        0xc
+#define GRF_EMMCPHY_CON4        0x10
+#define GRF_EMMCPHY_CON5        0x14
+#define GRF_EMMCPHY_CON6        0x18
+#define GRF_EMMCPHY_STATUS      0x20
+
+#define PHYCTRL_PDB_MASK        0x1
+#define PHYCTRL_PDB_SHIFT       0x0
+#define PHYCTRL_PDB_PWR_ON      0x1
+#define PHYCTRL_PDB_PWR_OFF     0x0
+#define PHYCTRL_ENDLL_MASK      0x1
+#define PHYCTRL_ENDLL_SHIFT     0x1
+#define PHYCTRL_ENDLL_ENABLE    0x1
+#define PHYCTRL_ENDLL_DISABLE   0x0
+#define PHYCTRL_CALDONE_MASK    0x1
+#define PHYCTRL_CALDONE_SHIFT   0x6
+#define PHYCTRL_CALDONE_DONE    0x1
+#define PHYCTRL_CALDONE_GOING   0x0
+#define PHYCTRL_DLLRDY_MASK     0x1
+#define PHYCTRL_DLLRDY_SHIFT    0x5
+#define PHYCTRL_DLLRDY_DONE     0x1
+#define PHYCTRL_DLLRDY_GOING    0x0
+
+struct rockchip_emmc_phy {
+        unsigned int    reg_offset;
+        struct regmap   *reg_base;
+};
+
+static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
+                                   bool on_off)
+{
+        unsigned int caldone;
+        unsigned int dllrdy;
+
+        /*
+         * Keep phyctrl_pdb and phyctrl_endll low to allow
+         * initialization of CALIO state M/C DFFs
+         */
+        regmap_write(rk_phy->reg_base,
+                     rk_phy->reg_offset + GRF_EMMCPHY_CON6,
+                     HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
+                                   PHYCTRL_PDB_MASK,
+                                   PHYCTRL_PDB_SHIFT));
+        regmap_write(rk_phy->reg_base,
+                     rk_phy->reg_offset + GRF_EMMCPHY_CON6,
+                     HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
+                                   PHYCTRL_ENDLL_MASK,
+                                   PHYCTRL_ENDLL_SHIFT));
+
+        /* Already finish power_off above */
+        if (on_off == PHYCTRL_PDB_PWR_OFF)
+                return 0;
+
+        /*
+         * According to the user manual, calpad calibration
+         * cycle takes more than 2us without the minimal recommended
+         * value, so we may need a little margin here
+         */
+        udelay(3);
+        regmap_write(rk_phy->reg_base,
+                     rk_phy->reg_offset + GRF_EMMCPHY_CON6,
+                     HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
+                                   PHYCTRL_PDB_MASK,
+                                   PHYCTRL_PDB_SHIFT));
+
+        /*
+         * According to the user manual, it asks driver to
+         * wait 5us for calpad busy trimming
+         */
+        udelay(5);
+        regmap_read(rk_phy->reg_base,
+                    rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
+                    &caldone);
+        caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
+        if (caldone != PHYCTRL_CALDONE_DONE) {
+                pr_err("rockchip_emmc_phy_power: caldone timeout.\n");
+                return -ETIMEDOUT;
+        }
+
+        regmap_write(rk_phy->reg_base,
+                     rk_phy->reg_offset + GRF_EMMCPHY_CON6,
+                     HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
+                                   PHYCTRL_ENDLL_MASK,
+                                   PHYCTRL_ENDLL_SHIFT));
+        /*
+         * After enable analog DLL circuits, we need extra 10.2us
+         * for dll to be ready for work.
+         */
+        udelay(11);
+        regmap_read(rk_phy->reg_base,
+                    rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
+                    &dllrdy);
+        dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
+        if (dllrdy != PHYCTRL_DLLRDY_DONE) {
+                pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
+                return -ETIMEDOUT;
+        }
+
+        return 0;
+}
+
+static int rockchip_emmc_phy_power_off(struct phy *phy)
+{
+        struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
+        int ret = 0;
+
+        /* Power down emmc phy analog blocks */
+        ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_OFF);
+        if (ret)
+                return ret;
+
+        return 0;
+}
+
+static int rockchip_emmc_phy_power_on(struct phy *phy)
+{
+        struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
+        int ret = 0;
+
+        /* Power up emmc phy analog blocks */
+        ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_ON);
+        if (ret)
+                return ret;
+
+        return 0;
+}
+
+static const struct phy_ops ops = {
+        .power_on       = rockchip_emmc_phy_power_on,
+        .power_off      = rockchip_emmc_phy_power_off,
+        .owner          = THIS_MODULE,
+};
+
+static int rockchip_emmc_phy_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct rockchip_emmc_phy *rk_phy;
+        struct phy *generic_phy;
+        struct phy_provider *phy_provider;
+        struct regmap *grf;
+        unsigned int reg_offset;
+
+        grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
+        if (IS_ERR(grf)) {
+                dev_err(dev, "Missing rockchip,grf property\n");
+                return PTR_ERR(grf);
+        }
+
+        rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
+        if (!rk_phy)
+                return -ENOMEM;
+
+        if (of_property_read_u32(dev->of_node, "reg", &reg_offset)) {
+                dev_err(dev, "missing reg property in node %s\n",
+                        dev->of_node->name);
+                return -EINVAL;
+        }
+
+        rk_phy->reg_offset = reg_offset;
+        rk_phy->reg_base = grf;
+
+        generic_phy = devm_phy_create(dev, dev->of_node, &ops);
+        if (IS_ERR(generic_phy)) {
+                dev_err(dev, "failed to create PHY\n");
+                return PTR_ERR(generic_phy);
+        }
+
+        phy_set_drvdata(generic_phy, rk_phy);
+        phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+        return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
+        { .compatible = "rockchip,rk3399-emmc-phy" },
+        {}
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
+
+static struct platform_driver rockchip_emmc_driver = {
+        .probe          = rockchip_emmc_phy_probe,
+        .driver         = {
+                .name   = "rockchip-emmc-phy",
+                .of_match_table = rockchip_emmc_phy_dt_ids,
+        },
+};
+
+module_platform_driver(rockchip_emmc_driver);
+
+MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
index 33a80eba1cb4..f62d899063a3 100644
--- a/drivers/phy/phy-rockchip-usb.c
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -30,21 +30,23 @@
 #include <linux/regmap.h>
 #include <linux/mfd/syscon.h>
 
-/*
- * The higher 16-bit of this register is used for write protection
- * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
- */
-#define SIDDQ_WRITE_ENA BIT(29)
-#define SIDDQ_ON                BIT(13)
-#define SIDDQ_OFF               (0 << 13)
+static int enable_usb_uart;
+
+#define HIWORD_UPDATE(val, mask) \
+                ((val) | (mask) << 16)
+
+#define UOC_CON0_SIDDQ BIT(13)
 
 struct rockchip_usb_phys {
         int reg;
         const char *pll_name;
 };
 
+struct rockchip_usb_phy_base;
 struct rockchip_usb_phy_pdata {
         struct rockchip_usb_phys *phys;
+        int (*init_usb_uart)(struct regmap *grf);
+        int usb_uart_phy;
 };
 
 struct rockchip_usb_phy_base {
@@ -61,13 +63,15 @@ struct rockchip_usb_phy {
         struct clk      *clk480m;
         struct clk_hw   clk480m_hw;
         struct phy      *phy;
+        bool            uart_enabled;
 };
 
 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
                                            bool siddq)
 {
-        return regmap_write(phy->base->reg_base, phy->reg_offset,
-                            SIDDQ_WRITE_ENA | (siddq ? SIDDQ_ON : SIDDQ_OFF));
+        u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ);
+
+        return regmap_write(phy->base->reg_base, phy->reg_offset, val);
 }
 
 static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw,
@@ -108,7 +112,7 @@ static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw)
         if (ret < 0)
                 return ret;
 
-        return (val & SIDDQ_ON) ? 0 : 1;
+        return (val & UOC_CON0_SIDDQ) ? 0 : 1;
 }
 
 static const struct clk_ops rockchip_usb_phy480m_ops = {
@@ -122,6 +126,9 @@ static int rockchip_usb_phy_power_off(struct phy *_phy)
 {
         struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
 
+        if (phy->uart_enabled)
+                return -EBUSY;
+
         clk_disable_unprepare(phy->clk480m);
 
         return 0;
@@ -131,6 +138,9 @@ static int rockchip_usb_phy_power_on(struct phy *_phy)
 {
         struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
 
+        if (phy->uart_enabled)
+                return -EBUSY;
+
         return clk_prepare_enable(phy->clk480m);
 }
 
@@ -144,8 +154,10 @@ static void rockchip_usb_phy_action(void *data)
 {
         struct rockchip_usb_phy *rk_phy = data;
 
-        of_clk_del_provider(rk_phy->np);
-        clk_unregister(rk_phy->clk480m);
+        if (!rk_phy->uart_enabled) {
+                of_clk_del_provider(rk_phy->np);
+                clk_unregister(rk_phy->clk480m);
+        }
 
         if (rk_phy->clk)
                 clk_put(rk_phy->clk);
@@ -194,30 +206,35 @@ static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
                 return -EINVAL;
         }
 
-        if (rk_phy->clk) {
-                clk_name = __clk_get_name(rk_phy->clk);
-                init.flags = 0;
-                init.parent_names = &clk_name;
-                init.num_parents = 1;
+        if (enable_usb_uart && base->pdata->usb_uart_phy == i) {
+                dev_dbg(base->dev, "phy%d used as uart output\n", i);
+                rk_phy->uart_enabled = true;
         } else {
-                init.flags = CLK_IS_ROOT;
-                init.parent_names = NULL;
-                init.num_parents = 0;
-        }
+                if (rk_phy->clk) {
+                        clk_name = __clk_get_name(rk_phy->clk);
+                        init.flags = 0;
+                        init.parent_names = &clk_name;
+                        init.num_parents = 1;
+                } else {
+                        init.flags = CLK_IS_ROOT;
+                        init.parent_names = NULL;
+                        init.num_parents = 0;
+                }
 
-        init.ops = &rockchip_usb_phy480m_ops;
-        rk_phy->clk480m_hw.init = &init;
+                init.ops = &rockchip_usb_phy480m_ops;
+                rk_phy->clk480m_hw.init = &init;
 
-        rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
-        if (IS_ERR(rk_phy->clk480m)) {
-                err = PTR_ERR(rk_phy->clk480m);
-                goto err_clk;
-        }
+                rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
+                if (IS_ERR(rk_phy->clk480m)) {
+                        err = PTR_ERR(rk_phy->clk480m);
+                        goto err_clk;
+                }
 
-        err = of_clk_add_provider(child, of_clk_src_simple_get,
-                                  rk_phy->clk480m);
-        if (err < 0)
-                goto err_clk_prov;
+                err = of_clk_add_provider(child, of_clk_src_simple_get,
+                                        rk_phy->clk480m);
+                if (err < 0)
+                        goto err_clk_prov;
+        }
 
         err = devm_add_action(base->dev, rockchip_usb_phy_action, rk_phy);
         if (err)
@@ -230,13 +247,21 @@ static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
         }
         phy_set_drvdata(rk_phy->phy, rk_phy);
 
-        /* only power up usb phy when it use, so disable it when init*/
-        return rockchip_usb_phy_power(rk_phy, 1);
+        /*
+         * When acting as uart-pipe, just keep clock on otherwise
+         * only power up usb phy when it use, so disable it when init
+         */
+        if (rk_phy->uart_enabled)
+                return clk_prepare_enable(rk_phy->clk);
+        else
+                return rockchip_usb_phy_power(rk_phy, 1);
 
 err_devm_action:
-        of_clk_del_provider(child);
+        if (!rk_phy->uart_enabled)
+                of_clk_del_provider(child);
 err_clk_prov:
-        clk_unregister(rk_phy->clk480m);
+        if (!rk_phy->uart_enabled)
+                clk_unregister(rk_phy->clk480m);
 err_clk:
         if (rk_phy->clk)
                 clk_put(rk_phy->clk);
@@ -259,6 +284,86 @@ static const struct rockchip_usb_phy_pdata rk3188_pdata = {
         },
 };
 
+#define RK3288_UOC0_CON0                                0x320
+#define RK3288_UOC0_CON0_COMMON_ON_N                    BIT(0)
+#define RK3288_UOC0_CON0_DISABLE                        BIT(4)
+
+#define RK3288_UOC0_CON2                                0x328
+#define RK3288_UOC0_CON2_SOFT_CON_SEL                   BIT(2)
+
+#define RK3288_UOC0_CON3                                0x32c
+#define RK3288_UOC0_CON3_UTMI_SUSPENDN                  BIT(0)
+#define RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING          (1 << 1)
+#define RK3288_UOC0_CON3_UTMI_OPMODE_MASK               (3 << 1)
+#define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_FSTRANSC       (1 << 3)
+#define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_MASK           (3 << 3)
+#define RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED         BIT(5)
+#define RK3288_UOC0_CON3_BYPASSDMEN                     BIT(6)
+#define RK3288_UOC0_CON3_BYPASSSEL                      BIT(7)
+
+/*
+ * Enable the bypass of uart2 data through the otg usb phy.
+ * Original description in the TRM.
+ * 1. Disable the OTG block by setting OTGDISABLE0 to 1’b1.
+ * 2. Disable the pull-up resistance on the D+ line by setting
+ *    OPMODE0[1:0] to 2’b01.
+ * 3. To ensure that the XO, Bias, and PLL blocks are powered down in Suspend
+ *    mode, set COMMONONN to 1’b1.
+ * 4. Place the USB PHY in Suspend mode by setting SUSPENDM0 to 1’b0.
+ * 5. Set BYPASSSEL0 to 1’b1.
+ * 6. To transmit data, controls BYPASSDMEN0, and BYPASSDMDATA0.
+ * To receive data, monitor FSVPLUS0.
+ *
+ * The actual code in the vendor kernel does some things differently.
+ */
+static int __init rk3288_init_usb_uart(struct regmap *grf)
+{
+        u32 val;
+        int ret;
+
+        /*
+         * COMMON_ON and DISABLE settings are described in the TRM,
+         * but were not present in the original code.
+         * Also disable the analog phy components to save power.
+         */
+        val = HIWORD_UPDATE(RK3288_UOC0_CON0_COMMON_ON_N
+                                | RK3288_UOC0_CON0_DISABLE
+                                | UOC_CON0_SIDDQ,
+                            RK3288_UOC0_CON0_COMMON_ON_N
+                                | RK3288_UOC0_CON0_DISABLE
+                                | UOC_CON0_SIDDQ);
+        ret = regmap_write(grf, RK3288_UOC0_CON0, val);
+        if (ret)
+                return ret;
+
+        val = HIWORD_UPDATE(RK3288_UOC0_CON2_SOFT_CON_SEL,
+                            RK3288_UOC0_CON2_SOFT_CON_SEL);
+        ret = regmap_write(grf, RK3288_UOC0_CON2, val);
+        if (ret)
+                return ret;
+
+        val = HIWORD_UPDATE(RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING
+                                | RK3288_UOC0_CON3_UTMI_XCVRSEELCT_FSTRANSC
+                                | RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED,
+                            RK3288_UOC0_CON3_UTMI_SUSPENDN
+                                | RK3288_UOC0_CON3_UTMI_OPMODE_MASK
+                                | RK3288_UOC0_CON3_UTMI_XCVRSEELCT_MASK
+                                | RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED);
+        ret = regmap_write(grf, RK3288_UOC0_CON3, val);
+        if (ret)
+                return ret;
+
+        val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL
+                                | RK3288_UOC0_CON3_BYPASSDMEN,
+                            RK3288_UOC0_CON3_BYPASSSEL
+                                | RK3288_UOC0_CON3_BYPASSDMEN);
+        ret = regmap_write(grf, RK3288_UOC0_CON3, val);
+        if (ret)
+                return ret;
+
+        return 0;
+}
+
 static const struct rockchip_usb_phy_pdata rk3288_pdata = {
         .phys = (struct rockchip_usb_phys[]){
                 { .reg = 0x320, .pll_name = "sclk_otgphy0_480m" },
@@ -266,6 +371,8 @@ static const struct rockchip_usb_phy_pdata rk3288_pdata = {
                 { .reg = 0x348, .pll_name = "sclk_otgphy2_480m" },
                 { /* sentinel */ }
         },
+        .init_usb_uart = rk3288_init_usb_uart,
+        .usb_uart_phy = 0,
 };
 
 static int rockchip_usb_phy_probe(struct platform_device *pdev)
@@ -328,6 +435,60 @@ static struct platform_driver rockchip_usb_driver = {
 
 module_platform_driver(rockchip_usb_driver);
 
+#ifndef MODULE
+static int __init rockchip_init_usb_uart(void)
+{
+        const struct of_device_id *match;
+        const struct rockchip_usb_phy_pdata *data;
+        struct device_node *np;
+        struct regmap *grf;
+        int ret;
+
+        if (!enable_usb_uart)
+                return 0;
+
+        np = of_find_matching_node_and_match(NULL, rockchip_usb_phy_dt_ids,
+                                             &match);
+        if (!np) {
+                pr_err("%s: failed to find usbphy node\n", __func__);
+                return -ENOTSUPP;
+        }
+
+        pr_debug("%s: using settings for %s\n", __func__, match->compatible);
+        data = match->data;
+
+        if (!data->init_usb_uart) {
+                pr_err("%s: usb-uart not available on %s\n",
+                       __func__, match->compatible);
+                return -ENOTSUPP;
+        }
+
+        grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+        if (IS_ERR(grf)) {
+                pr_err("%s: Missing rockchip,grf property, %lu\n",
+                       __func__, PTR_ERR(grf));
+                return PTR_ERR(grf);
+        }
+
+        ret = data->init_usb_uart(grf);
+        if (ret) {
+                pr_err("%s: could not init usb_uart, %d\n", __func__, ret);
+                enable_usb_uart = 0;
+                return ret;
+        }
+
+        return 0;
+}
+early_initcall(rockchip_init_usb_uart);
+
+static int __init rockchip_usb_uart(char *buf)
+{
+        enable_usb_uart = true;
+        return 0;
+}
+early_param("rockchip.usb_uart", rockchip_usb_uart);
+#endif
+
 MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>");
 MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver");
 MODULE_LICENSE("GPL v2");