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-rw-r--r--Documentation/devicetree/bindings/clock/imx6sll-clock.txt36
-rw-r--r--Documentation/devicetree/bindings/clock/intc_stratix10.txt20
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/bcm/clk-bcm2835.c8
-rw-r--r--drivers/clk/clk-cs2000-cp.c2
-rw-r--r--drivers/clk/imx/Makefile1
-rw-r--r--drivers/clk/imx/clk-busy.c4
-rw-r--r--drivers/clk/imx/clk-imx6sll.c340
-rw-r--r--drivers/clk/imx/clk-imx6sx.c14
-rw-r--r--drivers/clk/imx/clk-imx6ul.c5
-rw-r--r--drivers/clk/imx/clk-imx7d.c116
-rw-r--r--drivers/clk/imx/clk-pllv2.c6
-rw-r--r--drivers/clk/imx/clk.h14
-rw-r--r--drivers/clk/socfpga/Makefile9
-rw-r--r--drivers/clk/socfpga/clk-gate-s10.c125
-rw-r--r--drivers/clk/socfpga/clk-periph-s10.c149
-rw-r--r--drivers/clk/socfpga/clk-pll-s10.c146
-rw-r--r--drivers/clk/socfpga/clk-s10.c345
-rw-r--r--drivers/clk/socfpga/clk.h4
-rw-r--r--drivers/clk/socfpga/stratix10-clk.h80
-rw-r--r--include/dt-bindings/clock/imx6sll-clock.h202
-rw-r--r--include/dt-bindings/clock/imx7d-clock.h5
-rw-r--r--include/dt-bindings/clock/stratix10-clock.h84
23 files changed, 1645 insertions, 71 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx6sll-clock.txt b/Documentation/devicetree/bindings/clock/imx6sll-clock.txt
new file mode 100644
index 000000000000..fee849d5fdd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6sll-clock.txt
@@ -0,0 +1,36 @@
1* Clock bindings for Freescale i.MX6 SLL
2
3Required properties:
4- compatible: Should be "fsl,imx6sll-ccm"
5- reg: Address and length of the register set
6- #clock-cells: Should be <1>
7- clocks: list of clock specifiers, must contain an entry for each required
8 entry in clock-names
9- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
10
11The clock consumer should specify the desired clock by having the clock
12ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sll-clock.h
13for the full list of i.MX6 SLL clock IDs.
14
15Examples:
16
17#include <dt-bindings/clock/imx6sll-clock.h>
18
19clks: clock-controller@20c4000 {
20 compatible = "fsl,imx6sll-ccm";
21 reg = <0x020c4000 0x4000>;
22 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
23 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
24 #clock-cells = <1>;
25 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
26 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
27};
28
29uart1: serial@2020000 {
30 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
31 reg = <0x02020000 0x4000>;
32 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
33 clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
34 <&clks IMX6SLL_CLK_UART1_SERIAL>;
35 clock-names = "ipg", "per";
36};
diff --git a/Documentation/devicetree/bindings/clock/intc_stratix10.txt b/Documentation/devicetree/bindings/clock/intc_stratix10.txt
new file mode 100644
index 000000000000..9f4ec5cb5c6b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/intc_stratix10.txt
@@ -0,0 +1,20 @@
1Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be
9 "intel,stratix10-clkmgr"
10
11- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
12
13- #clock-cells : from common clock binding, shall be set to 1.
14
15Example:
16 clkmgr: clock-controller@ffd10000 {
17 compatible = "intel,stratix10-clkmgr";
18 reg = <0xffd10000 0x1000>;
19 #clock-cells = <1>;
20 };
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index fdbffc5249f3..f0aeffc3abd6 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -91,6 +91,7 @@ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
91obj-$(CONFIG_PLAT_SPEAR) += spear/ 91obj-$(CONFIG_PLAT_SPEAR) += spear/
92obj-$(CONFIG_ARCH_SPRD) += sprd/ 92obj-$(CONFIG_ARCH_SPRD) += sprd/
93obj-$(CONFIG_ARCH_STI) += st/ 93obj-$(CONFIG_ARCH_STI) += st/
94obj-$(CONFIG_ARCH_STRATIX10) += socfpga/
94obj-$(CONFIG_ARCH_SUNXI) += sunxi/ 95obj-$(CONFIG_ARCH_SUNXI) += sunxi/
95obj-$(CONFIG_ARCH_SUNXI) += sunxi-ng/ 96obj-$(CONFIG_ARCH_SUNXI) += sunxi-ng/
96obj-$(CONFIG_ARCH_TEGRA) += tegra/ 97obj-$(CONFIG_ARCH_TEGRA) += tegra/
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 44301a3d9963..40acb8ebfb42 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -602,9 +602,7 @@ static void bcm2835_pll_off(struct clk_hw *hw)
602 const struct bcm2835_pll_data *data = pll->data; 602 const struct bcm2835_pll_data *data = pll->data;
603 603
604 spin_lock(&cprman->regs_lock); 604 spin_lock(&cprman->regs_lock);
605 cprman_write(cprman, data->cm_ctrl_reg, 605 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
606 cprman_read(cprman, data->cm_ctrl_reg) |
607 CM_PLL_ANARST);
608 cprman_write(cprman, data->a2w_ctrl_reg, 606 cprman_write(cprman, data->a2w_ctrl_reg,
609 cprman_read(cprman, data->a2w_ctrl_reg) | 607 cprman_read(cprman, data->a2w_ctrl_reg) |
610 A2W_PLL_CTRL_PWRDN); 608 A2W_PLL_CTRL_PWRDN);
@@ -638,6 +636,10 @@ static int bcm2835_pll_on(struct clk_hw *hw)
638 cpu_relax(); 636 cpu_relax();
639 } 637 }
640 638
639 cprman_write(cprman, data->a2w_ctrl_reg,
640 cprman_read(cprman, data->a2w_ctrl_reg) |
641 A2W_PLL_CTRL_PRST_DISABLE);
642
641 return 0; 643 return 0;
642} 644}
643 645
diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c
index e8ea81c30f0c..c58019750b7e 100644
--- a/drivers/clk/clk-cs2000-cp.c
+++ b/drivers/clk/clk-cs2000-cp.c
@@ -549,7 +549,7 @@ static int cs2000_resume(struct device *dev)
549} 549}
550 550
551static const struct dev_pm_ops cs2000_pm_ops = { 551static const struct dev_pm_ops cs2000_pm_ops = {
552 .resume_early = cs2000_resume, 552 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, cs2000_resume)
553}; 553};
554 554
555static struct i2c_driver cs2000_driver = { 555static struct i2c_driver cs2000_driver = {
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index f91f2b2e11cd..8c3baa7e6496 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_SOC_IMX35) += clk-imx35.o
22obj-$(CONFIG_SOC_IMX5) += clk-imx51-imx53.o 22obj-$(CONFIG_SOC_IMX5) += clk-imx51-imx53.o
23obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o 23obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o
24obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o 24obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o
25obj-$(CONFIG_SOC_IMX6SLL) += clk-imx6sll.o
25obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o 26obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o
26obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o 27obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o
27obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o 28obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o
diff --git a/drivers/clk/imx/clk-busy.c b/drivers/clk/imx/clk-busy.c
index 6df3389687bc..99036527eb0d 100644
--- a/drivers/clk/imx/clk-busy.c
+++ b/drivers/clk/imx/clk-busy.c
@@ -101,7 +101,7 @@ struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
101 101
102 init.name = name; 102 init.name = name;
103 init.ops = &clk_busy_divider_ops; 103 init.ops = &clk_busy_divider_ops;
104 init.flags = CLK_SET_RATE_PARENT; 104 init.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL;
105 init.parent_names = &parent_name; 105 init.parent_names = &parent_name;
106 init.num_parents = 1; 106 init.num_parents = 1;
107 107
@@ -175,7 +175,7 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
175 175
176 init.name = name; 176 init.name = name;
177 init.ops = &clk_busy_mux_ops; 177 init.ops = &clk_busy_mux_ops;
178 init.flags = 0; 178 init.flags = CLK_IS_CRITICAL;
179 init.parent_names = parent_names; 179 init.parent_names = parent_names;
180 init.num_parents = num_parents; 180 init.num_parents = num_parents;
181 181
diff --git a/drivers/clk/imx/clk-imx6sll.c b/drivers/clk/imx/clk-imx6sll.c
new file mode 100644
index 000000000000..3651c77fbabe
--- /dev/null
+++ b/drivers/clk/imx/clk-imx6sll.c
@@ -0,0 +1,340 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP.
5 */
6
7#include <dt-bindings/clock/imx6sll-clock.h>
8#include <linux/clk.h>
9#include <linux/clkdev.h>
10#include <linux/err.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15
16#include "clk.h"
17
18#define CCM_ANALOG_PLL_BYPASS (0x1 << 16)
19#define BM_CCM_CCDR_MMDC_CH0_MASK (0x2 << 16)
20#define xPLL_CLR(offset) (offset + 0x8)
21
22static const char *pll_bypass_src_sels[] = { "osc", "dummy", };
23static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
24static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
25static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
26static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
27static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
28static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
29static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
30static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
31static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
32static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", };
33static const char *axi_sels[] = {"periph", "axi_alt_sel", };
34static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
35static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", };
36static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", };
37static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", };
38static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
39static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
40static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
41static const char *ssi_sels[] = {"pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", "dummy",};
42static const char *spdif_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
43static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
44static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
45static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", };
46static const char *ldb_di1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
47static const char *lcdif_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };
48static const char *ecspi_sels[] = { "pll3_60m", "osc", };
49static const char *uart_sels[] = { "pll3_80m", "osc", };
50static const char *perclk_sels[] = { "ipg", "osc", };
51static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
52
53static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
54static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
55
56static struct clk *clks[IMX6SLL_CLK_END];
57static struct clk_onecell_data clk_data;
58
59static const struct clk_div_table post_div_table[] = {
60 { .val = 2, .div = 1, },
61 { .val = 1, .div = 2, },
62 { .val = 0, .div = 4, },
63 { }
64};
65
66static const struct clk_div_table video_div_table[] = {
67 { .val = 0, .div = 1, },
68 { .val = 1, .div = 2, },
69 { .val = 2, .div = 1, },
70 { .val = 3, .div = 4, },
71 { }
72};
73
74static u32 share_count_audio;
75static u32 share_count_ssi1;
76static u32 share_count_ssi2;
77static u32 share_count_ssi3;
78
79static void __init imx6sll_clocks_init(struct device_node *ccm_node)
80{
81 struct device_node *np;
82 void __iomem *base;
83
84 clks[IMX6SLL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
85
86 clks[IMX6SLL_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil");
87 clks[IMX6SLL_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc");
88
89 /* ipp_di clock is external input */
90 clks[IMX6SLL_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
91 clks[IMX6SLL_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
92
93 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop");
94 base = of_iomap(np, 0);
95 WARN_ON(!base);
96
97 /* Do not bypass PLLs initially */
98 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0));
99 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10));
100 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20));
101 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30));
102 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x70));
103 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xa0));
104 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xe0));
105
106 clks[IMX6SLL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
107 clks[IMX6SLL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
108 clks[IMX6SLL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
109 clks[IMX6SLL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
110 clks[IMX6SLL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
111 clks[IMX6SLL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
112 clks[IMX6SLL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
113
114 clks[IMX6SLL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
115 clks[IMX6SLL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
116 clks[IMX6SLL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
117 clks[IMX6SLL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
118 clks[IMX6SLL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
119 clks[IMX6SLL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
120 clks[IMX6SLL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
121
122 clks[IMX6SLL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
123 clks[IMX6SLL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
124 clks[IMX6SLL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
125 clks[IMX6SLL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
126 clks[IMX6SLL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
127 clks[IMX6SLL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
128 clks[IMX6SLL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
129
130 clks[IMX6SLL_CLK_PLL1_SYS] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1);
131 clks[IMX6SLL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
132 clks[IMX6SLL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
133 clks[IMX6SLL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
134 clks[IMX6SLL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
135 clks[IMX6SLL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
136 clks[IMX6SLL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
137
138 /*
139 * Bit 20 is the reserved and read-only bit, we do this only for:
140 * - Do nothing for usbphy clk_enable/disable
141 * - Keep refcount when do usbphy clk_enable/disable, in that case,
142 * the clk framework many need to enable/disable usbphy's parent
143 */
144 clks[IMX6SLL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
145 clks[IMX6SLL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
146
147 /*
148 * usbphy*_gate needs to be on after system boots up, and software
149 * never needs to control it anymore.
150 */
151 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
152 clks[IMX6SLL_CLK_USBPHY1_GATE] = imx_clk_gate_flags("usbphy1_gate", "dummy", base + 0x10, 6, CLK_IS_CRITICAL);
153 clks[IMX6SLL_CLK_USBPHY2_GATE] = imx_clk_gate_flags("usbphy2_gate", "dummy", base + 0x20, 6, CLK_IS_CRITICAL);
154 }
155
156 /* name parent_name reg idx */
157 clks[IMX6SLL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
158 clks[IMX6SLL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
159 clks[IMX6SLL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
160 clks[IMX6SLL_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3);
161 clks[IMX6SLL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
162 clks[IMX6SLL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
163 clks[IMX6SLL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
164 clks[IMX6SLL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
165
166 clks[IMX6SLL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio",
167 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
168 clks[IMX6SLL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
169 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock);
170 clks[IMX6SLL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video",
171 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
172 clks[IMX6SLL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
173 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
174
175 /* name parent_name mult div */
176 clks[IMX6SLL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
177 clks[IMX6SLL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
178 clks[IMX6SLL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
179 clks[IMX6SLL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
180
181 np = ccm_node;
182 base = of_iomap(np, 0);
183 WARN_ON(!base);
184
185 clks[IMX6SLL_CLK_STEP] = imx_clk_mux("step", base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels));
186 clks[IMX6SLL_CLK_PLL1_SW] = imx_clk_mux_flags("pll1_sw", base + 0x0c, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels), 0);
187 clks[IMX6SLL_CLK_AXI_ALT_SEL] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels));
188 clks[IMX6SLL_CLK_AXI_SEL] = imx_clk_mux_flags("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels), 0);
189 clks[IMX6SLL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
190 clks[IMX6SLL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels));
191 clks[IMX6SLL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
192 clks[IMX6SLL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
193 clks[IMX6SLL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
194 clks[IMX6SLL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
195 clks[IMX6SLL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
196 clks[IMX6SLL_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
197 clks[IMX6SLL_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
198 clks[IMX6SLL_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
199 clks[IMX6SLL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels));
200 clks[IMX6SLL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
201 clks[IMX6SLL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels));
202 clks[IMX6SLL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x30, 7, 2, spdif_sels, ARRAY_SIZE(spdif_sels));
203 clks[IMX6SLL_CLK_EPDC_PRE_SEL] = imx_clk_mux("epdc_pre_sel", base + 0x34, 15, 3, epdc_pre_sels, ARRAY_SIZE(epdc_pre_sels));
204 clks[IMX6SLL_CLK_EPDC_SEL] = imx_clk_mux("epdc_sel", base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels));
205 clks[IMX6SLL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
206 clks[IMX6SLL_CLK_LCDIF_PRE_SEL] = imx_clk_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels));
207 clks[IMX6SLL_CLK_LCDIF_SEL] = imx_clk_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels));
208
209 clks[IMX6SLL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
210 clks[IMX6SLL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
211
212 clks[IMX6SLL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
213 clks[IMX6SLL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
214 clks[IMX6SLL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
215 clks[IMX6SLL_CLK_LCDIF_PODF] = imx_clk_divider("lcdif_podf", "lcdif_pred", base + 0x18, 23, 3);
216 clks[IMX6SLL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6);
217 clks[IMX6SLL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
218 clks[IMX6SLL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
219 clks[IMX6SLL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
220 clks[IMX6SLL_CLK_UART_PODF] = imx_clk_divider("uart_podf", "uart_sel", base + 0x24, 0, 6);
221 clks[IMX6SLL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
222 clks[IMX6SLL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
223 clks[IMX6SLL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
224 clks[IMX6SLL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
225 clks[IMX6SLL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
226 clks[IMX6SLL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
227 clks[IMX6SLL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
228 clks[IMX6SLL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
229 clks[IMX6SLL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel", base + 0x30, 12, 3);
230 clks[IMX6SLL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x30, 9, 3);
231 clks[IMX6SLL_CLK_EPDC_PODF] = imx_clk_divider("epdc_podf", "epdc_pre_sel", base + 0x34, 12, 3);
232 clks[IMX6SLL_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6);
233 clks[IMX6SLL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3);
234
235 clks[IMX6SLL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
236 clks[IMX6SLL_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
237 clks[IMX6SLL_CLK_AXI_PODF] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
238 clks[IMX6SLL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
239
240 clks[IMX6SLL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
241 clks[IMX6SLL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
242 clks[IMX6SLL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
243 clks[IMX6SLL_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7);
244
245 clks[IMX6SLL_CLK_LDB_DI0_SEL] = imx_clk_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels));
246 clks[IMX6SLL_CLK_LDB_DI1_SEL] = imx_clk_mux("ldb_di1_sel", base + 0x1c, 7, 3, ldb_di1_sels, ARRAY_SIZE(ldb_di1_sels));
247 clks[IMX6SLL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));
248 clks[IMX6SLL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux("ldb_di1_div_sel", base + 0x20, 10, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels));
249
250 /* CCGR0 */
251 clks[IMX6SLL_CLK_AIPSTZ1] = imx_clk_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL);
252 clks[IMX6SLL_CLK_AIPSTZ2] = imx_clk_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL);
253 clks[IMX6SLL_CLK_DCP] = imx_clk_gate2("dcp", "ahb", base + 0x68, 10);
254 clks[IMX6SLL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28);
255 clks[IMX6SLL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
256
257 /* CCGR1 */
258 clks[IMX6SLL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
259 clks[IMX6SLL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2);
260 clks[IMX6SLL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4);
261 clks[IMX6SLL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6);
262 clks[IMX6SLL_CLK_UART3_IPG] = imx_clk_gate2("uart3_ipg", "ipg", base + 0x6c, 10);
263 clks[IMX6SLL_CLK_UART3_SERIAL] = imx_clk_gate2("uart3_serial", "uart_podf", base + 0x6c, 10);
264 clks[IMX6SLL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12);
265 clks[IMX6SLL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14);
266 clks[IMX6SLL_CLK_GPT_BUS] = imx_clk_gate2("gpt1_bus", "perclk", base + 0x6c, 20);
267 clks[IMX6SLL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22);
268 clks[IMX6SLL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
269 clks[IMX6SLL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24);
270
271 /* CCGR2 */
272 clks[IMX6SLL_CLK_CSI] = imx_clk_gate2("csi", "axi", base + 0x70, 2);
273 clks[IMX6SLL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6);
274 clks[IMX6SLL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8);
275 clks[IMX6SLL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
276 clks[IMX6SLL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
277 clks[IMX6SLL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28);
278 clks[IMX6SLL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30);
279
280 /* CCGR3 */
281 clks[IMX6SLL_CLK_UART5_IPG] = imx_clk_gate2("uart5_ipg", "ipg", base + 0x74, 2);
282 clks[IMX6SLL_CLK_UART5_SERIAL] = imx_clk_gate2("uart5_serial", "uart_podf", base + 0x74, 2);
283 clks[IMX6SLL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_aclk", "axi", base + 0x74, 4);
284 clks[IMX6SLL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_podf", base + 0x74, 4);
285 clks[IMX6SLL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10);
286 clks[IMX6SLL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16);
287 clks[IMX6SLL_CLK_MMDC_P0_FAST] = imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL);
288 clks[IMX6SLL_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
289 clks[IMX6SLL_CLK_OCRAM] = imx_clk_gate_flags("ocram","ahb", base + 0x74, 28, CLK_IS_CRITICAL);
290
291 /* CCGR4 */
292 clks[IMX6SLL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16);
293 clks[IMX6SLL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18);
294 clks[IMX6SLL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
295 clks[IMX6SLL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
296
297 /* CCGR5 */
298 clks[IMX6SLL_CLK_ROM] = imx_clk_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL);
299 clks[IMX6SLL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
300 clks[IMX6SLL_CLK_WDOG2] = imx_clk_gate2("wdog2", "ipg", base + 0x7c, 10);
301 clks[IMX6SLL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
302 clks[IMX6SLL_CLK_EXTERN_AUDIO] = imx_clk_gate2_shared("extern_audio", "extern_audio_podf", base + 0x7c, 14, &share_count_audio);
303 clks[IMX6SLL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio);
304 clks[IMX6SLL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio);
305 clks[IMX6SLL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
306 clks[IMX6SLL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
307 clks[IMX6SLL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
308 clks[IMX6SLL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
309 clks[IMX6SLL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
310 clks[IMX6SLL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
311 clks[IMX6SLL_CLK_UART1_IPG] = imx_clk_gate2("uart1_ipg", "ipg", base + 0x7c, 24);
312 clks[IMX6SLL_CLK_UART1_SERIAL] = imx_clk_gate2("uart1_serial", "uart_podf", base + 0x7c, 24);
313
314 /* CCGR6 */
315 clks[IMX6SLL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
316 clks[IMX6SLL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
317 clks[IMX6SLL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
318 clks[IMX6SLL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
319
320 /* mask handshake of mmdc */
321 writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + 0x4);
322
323 imx_check_clocks(clks, ARRAY_SIZE(clks));
324
325 clk_data.clks = clks;
326 clk_data.clk_num = ARRAY_SIZE(clks);
327 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
328
329 /* Lower the AHB clock rate before changing the clock source. */
330 clk_set_rate(clks[IMX6SLL_CLK_AHB], 99000000);
331
332 /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
333 clk_set_parent(clks[IMX6SLL_CLK_PERIPH_CLK2_SEL], clks[IMX6SLL_CLK_PLL3_USB_OTG]);
334 clk_set_parent(clks[IMX6SLL_CLK_PERIPH], clks[IMX6SLL_CLK_PERIPH_CLK2]);
335 clk_set_parent(clks[IMX6SLL_CLK_PERIPH_PRE], clks[IMX6SLL_CLK_PLL2_BUS]);
336 clk_set_parent(clks[IMX6SLL_CLK_PERIPH], clks[IMX6SLL_CLK_PERIPH_PRE]);
337
338 clk_set_rate(clks[IMX6SLL_CLK_AHB], 132000000);
339}
340CLK_OF_DECLARE_DRIVER(imx6sll, "fsl,imx6sll-ccm", imx6sll_clocks_init);
diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
index e6d389e333d7..bc3f9ebf2d9e 100644
--- a/drivers/clk/imx/clk-imx6sx.c
+++ b/drivers/clk/imx/clk-imx6sx.c
@@ -63,17 +63,17 @@ static const char *lcdif2_sels[] = { "lcdif2_podf", "ipp_di0", "ipp_di1", "ldb_d
63static const char *display_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll3_usb_otg", "pll3_pfd1_540m", }; 63static const char *display_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll3_usb_otg", "pll3_pfd1_540m", };
64static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; 64static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
65static const char *cko1_sels[] = { 65static const char *cko1_sels[] = {
66 "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", 66 "dummy", "dummy", "dummy", "dummy",
67 "dummy", "ocram", "dummy", "pxp_axi", "epdc_axi", "lcdif_pix", 67 "vadc", "ocram", "qspi2", "m4", "enet_ahb", "lcdif2_pix",
68 "epdc_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div", 68 "lcdif1_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
69}; 69};
70static const char *cko2_sels[] = { 70static const char *cko2_sels[] = {
71 "dummy", "mmdc_p0_fast", "usdhc4", "usdhc1", "dummy", "wrck", 71 "dummy", "mmdc_p0_fast", "usdhc4", "usdhc1", "dummy", "wrck",
72 "ecspi_root", "dummy", "usdhc3", "pcie", "arm", "csi_core", 72 "ecspi_root", "dummy", "usdhc3", "pcie", "arm", "csi_core",
73 "lcdif_axi", "dummy", "osc", "dummy", "gpu2d_ovg_core", 73 "display_axi", "dummy", "osc", "dummy", "dummy",
74 "usdhc2", "ssi1", "ssi2", "ssi3", "gpu2d_core", "dummy", 74 "usdhc2", "ssi1", "ssi2", "ssi3", "gpu_axi_podf", "dummy",
75 "dummy", "dummy", "dummy", "esai_extal", "eim_slow", "uart_serial", 75 "can_podf", "lvds1_out", "qspi1", "esai_extal", "eim_slow",
76 "spdif", "asrc", "dummy", 76 "uart_serial", "spdif", "audio", "dummy",
77}; 77};
78static const char *cko_sels[] = { "cko1", "cko2", }; 78static const char *cko_sels[] = { "cko1", "cko2", };
79static const char *lvds_sels[] = { 79static const char *lvds_sels[] = {
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 85c118164469..114ecbb94ec5 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -308,7 +308,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
308 clks[IMX6UL_CLK_SAI2_PODF] = imx_clk_divider("sai2_podf", "sai2_pred", base + 0x2c, 0, 6); 308 clks[IMX6UL_CLK_SAI2_PODF] = imx_clk_divider("sai2_podf", "sai2_pred", base + 0x2c, 0, 6);
309 clks[IMX6UL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); 309 clks[IMX6UL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
310 clks[IMX6UL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); 310 clks[IMX6UL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
311 clks[IMX6UL_CLK_SIM_PODF] = imx_clk_divider("sim_podf", "sim_pre_sel", base + 0x34, 12, 3); 311 if (clk_on_imx6ul())
312 clks[IMX6UL_CLK_SIM_PODF] = imx_clk_divider("sim_podf", "sim_pre_sel", base + 0x34, 12, 3);
313 else if (clk_on_imx6ull())
314 clks[IMX6ULL_CLK_EPDC_PODF] = imx_clk_divider("epdc_podf", "epdc_pre_sel", base + 0x34, 12, 3);
312 clks[IMX6UL_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6); 315 clks[IMX6UL_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6);
313 clks[IMX6UL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3); 316 clks[IMX6UL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3);
314 clks[IMX6UL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); 317 clks[IMX6UL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 80dc211eb74b..975a20d3cc94 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -51,20 +51,20 @@ static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk",
51 51
52static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk", 52static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk",
53 "pll_enet_250m_clk", "pll_sys_pfd2_270m_clk", 53 "pll_enet_250m_clk", "pll_sys_pfd2_270m_clk",
54 "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk", 54 "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div",
55 "pll_usb_main_clk", }; 55 "pll_usb_main_clk", };
56 56
57static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk", 57static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
58 "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk", 58 "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk",
59 "pll_audio_post_div", "pll_video_main_clk", "pll_sys_pfd7_clk", }; 59 "pll_audio_post_div", "pll_video_post_div", "pll_sys_pfd7_clk", };
60 60
61static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk", 61static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
62 "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd6_clk", 62 "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd6_clk",
63 "pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_main_clk", }; 63 "pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_post_div", };
64 64
65static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk", 65static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
66 "pll_dram_533m_clk", "pll_enet_250m_clk", 66 "pll_dram_533m_clk", "pll_enet_250m_clk",
67 "pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_main_clk", 67 "pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_post_div",
68 "pll_sys_pfd4_clk", }; 68 "pll_sys_pfd4_clk", };
69 69
70static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk", 70static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
@@ -74,8 +74,8 @@ static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
74 74
75static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk", 75static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
76 "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", 76 "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk",
77 "pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_post_div", 77 "pll_enet_250m_clk", "pll_usb_main_clk", "pll_audio_post_div",
78 "pll_video_main_clk", }; 78 "pll_video_post_div", };
79 79
80static const char *dram_phym_sel[] = { "pll_dram_main_clk", 80static const char *dram_phym_sel[] = { "pll_dram_main_clk",
81 "dram_phym_alt_clk", }; 81 "dram_phym_alt_clk", };
@@ -86,7 +86,7 @@ static const char *dram_sel[] = { "pll_dram_main_clk",
86static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk", 86static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk",
87 "pll_sys_main_clk", "pll_enet_500m_clk", 87 "pll_sys_main_clk", "pll_enet_500m_clk",
88 "pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_post_div", 88 "pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_post_div",
89 "pll_video_main_clk", }; 89 "pll_video_post_div", };
90 90
91static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk", 91static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk",
92 "pll_sys_main_clk", "pll_enet_500m_clk", 92 "pll_sys_main_clk", "pll_enet_500m_clk",
@@ -108,62 +108,62 @@ static const char *pcie_phy_sel[] = { "osc", "pll_enet_100m_clk",
108 108
109static const char *epdc_pixel_sel[] = { "osc", "pll_sys_pfd1_332m_clk", 109static const char *epdc_pixel_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
110 "pll_dram_533m_clk", "pll_sys_main_clk", "pll_sys_pfd5_clk", 110 "pll_dram_533m_clk", "pll_sys_main_clk", "pll_sys_pfd5_clk",
111 "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_main_clk", }; 111 "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_post_div", };
112 112
113static const char *lcdif_pixel_sel[] = { "osc", "pll_sys_pfd5_clk", 113static const char *lcdif_pixel_sel[] = { "osc", "pll_sys_pfd5_clk",
114 "pll_dram_533m_clk", "ext_clk_3", "pll_sys_pfd4_clk", 114 "pll_dram_533m_clk", "ext_clk_3", "pll_sys_pfd4_clk",
115 "pll_sys_pfd2_270m_clk", "pll_video_main_clk", 115 "pll_sys_pfd2_270m_clk", "pll_video_post_div",
116 "pll_usb_main_clk", }; 116 "pll_usb_main_clk", };
117 117
118static const char *mipi_dsi_sel[] = { "osc", "pll_sys_pfd5_clk", 118static const char *mipi_dsi_sel[] = { "osc", "pll_sys_pfd5_clk",
119 "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk", 119 "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk",
120 "pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_post_div", }; 120 "pll_dram_533m_clk", "pll_video_post_div", "pll_audio_post_div", };
121 121
122static const char *mipi_csi_sel[] = { "osc", "pll_sys_pfd4_clk", 122static const char *mipi_csi_sel[] = { "osc", "pll_sys_pfd4_clk",
123 "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk", 123 "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk",
124 "pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_post_div", }; 124 "pll_dram_533m_clk", "pll_video_post_div", "pll_audio_post_div", };
125 125
126static const char *mipi_dphy_sel[] = { "osc", "pll_sys_main_120m_clk", 126static const char *mipi_dphy_sel[] = { "osc", "pll_sys_main_120m_clk",
127 "pll_dram_533m_clk", "pll_sys_pfd5_clk", "ref_1m_clk", "ext_clk_2", 127 "pll_dram_533m_clk", "pll_sys_pfd5_clk", "ref_1m_clk", "ext_clk_2",
128 "pll_video_main_clk", "ext_clk_3", }; 128 "pll_video_post_div", "ext_clk_3", };
129 129
130static const char *sai1_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 130static const char *sai1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
131 "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk", 131 "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
132 "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", }; 132 "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", };
133 133
134static const char *sai2_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 134static const char *sai2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
135 "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk", 135 "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
136 "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", }; 136 "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", };
137 137
138static const char *sai3_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 138static const char *sai3_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
139 "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk", 139 "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
140 "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_3", }; 140 "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_3", };
141 141
142static const char *spdif_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 142static const char *spdif_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
143 "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk", 143 "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
144 "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_3_clk", }; 144 "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_3_clk", };
145 145
146static const char *enet1_ref_sel[] = { "osc", "pll_enet_125m_clk", 146static const char *enet1_ref_sel[] = { "osc", "pll_enet_125m_clk",
147 "pll_enet_50m_clk", "pll_enet_25m_clk", 147 "pll_enet_50m_clk", "pll_enet_25m_clk",
148 "pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main_clk", 148 "pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_post_div",
149 "ext_clk_4", }; 149 "ext_clk_4", };
150 150
151static const char *enet1_time_sel[] = { "osc", "pll_enet_100m_clk", 151static const char *enet1_time_sel[] = { "osc", "pll_enet_100m_clk",
152 "pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3", 152 "pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3",
153 "ext_clk_4", "pll_video_main_clk", }; 153 "ext_clk_4", "pll_video_post_div", };
154 154
155static const char *enet2_ref_sel[] = { "osc", "pll_enet_125m_clk", 155static const char *enet2_ref_sel[] = { "osc", "pll_enet_125m_clk",
156 "pll_enet_50m_clk", "pll_enet_25m_clk", 156 "pll_enet_50m_clk", "pll_enet_25m_clk",
157 "pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main_clk", 157 "pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_post_div",
158 "ext_clk_4", }; 158 "ext_clk_4", };
159 159
160static const char *enet2_time_sel[] = { "osc", "pll_enet_100m_clk", 160static const char *enet2_time_sel[] = { "osc", "pll_enet_100m_clk",
161 "pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3", 161 "pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3",
162 "ext_clk_4", "pll_video_main_clk", }; 162 "ext_clk_4", "pll_video_post_div", };
163 163
164static const char *enet_phy_ref_sel[] = { "osc", "pll_enet_25m_clk", 164static const char *enet_phy_ref_sel[] = { "osc", "pll_enet_25m_clk",
165 "pll_enet_50m_clk", "pll_enet_125m_clk", 165 "pll_enet_50m_clk", "pll_enet_125m_clk",
166 "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk", 166 "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div",
167 "pll_sys_pfd3_clk", }; 167 "pll_sys_pfd3_clk", };
168 168
169static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 169static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
@@ -174,7 +174,7 @@ static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
174static const char *nand_sel[] = { "osc", "pll_sys_main_clk", 174static const char *nand_sel[] = { "osc", "pll_sys_main_clk",
175 "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd3_clk", 175 "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd3_clk",
176 "pll_enet_500m_clk", "pll_enet_250m_clk", 176 "pll_enet_500m_clk", "pll_enet_250m_clk",
177 "pll_video_main_clk", }; 177 "pll_video_post_div", };
178 178
179static const char *qspi_sel[] = { "osc", "pll_sys_pfd4_clk", 179static const char *qspi_sel[] = { "osc", "pll_sys_pfd4_clk",
180 "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd3_clk", 180 "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd3_clk",
@@ -204,22 +204,22 @@ static const char *can2_sel[] = { "osc", "pll_sys_main_120m_clk",
204 204
205static const char *i2c1_sel[] = { "osc", "pll_sys_main_120m_clk", 205static const char *i2c1_sel[] = { "osc", "pll_sys_main_120m_clk",
206 "pll_enet_50m_clk", "pll_dram_533m_clk", 206 "pll_enet_50m_clk", "pll_dram_533m_clk",
207 "pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk", 207 "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
208 "pll_sys_pfd2_135m_clk", }; 208 "pll_sys_pfd2_135m_clk", };
209 209
210static const char *i2c2_sel[] = { "osc", "pll_sys_main_120m_clk", 210static const char *i2c2_sel[] = { "osc", "pll_sys_main_120m_clk",
211 "pll_enet_50m_clk", "pll_dram_533m_clk", 211 "pll_enet_50m_clk", "pll_dram_533m_clk",
212 "pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk", 212 "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
213 "pll_sys_pfd2_135m_clk", }; 213 "pll_sys_pfd2_135m_clk", };
214 214
215static const char *i2c3_sel[] = { "osc", "pll_sys_main_120m_clk", 215static const char *i2c3_sel[] = { "osc", "pll_sys_main_120m_clk",
216 "pll_enet_50m_clk", "pll_dram_533m_clk", 216 "pll_enet_50m_clk", "pll_dram_533m_clk",
217 "pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk", 217 "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
218 "pll_sys_pfd2_135m_clk", }; 218 "pll_sys_pfd2_135m_clk", };
219 219
220static const char *i2c4_sel[] = { "osc", "pll_sys_main_120m_clk", 220static const char *i2c4_sel[] = { "osc", "pll_sys_main_120m_clk",
221 "pll_enet_50m_clk", "pll_dram_533m_clk", 221 "pll_enet_50m_clk", "pll_dram_533m_clk",
222 "pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk", 222 "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
223 "pll_sys_pfd2_135m_clk", }; 223 "pll_sys_pfd2_135m_clk", };
224 224
225static const char *uart1_sel[] = { "osc", "pll_sys_main_240m_clk", 225static const char *uart1_sel[] = { "osc", "pll_sys_main_240m_clk",
@@ -279,27 +279,27 @@ static const char *ecspi4_sel[] = { "osc", "pll_sys_main_240m_clk",
279 279
280static const char *pwm1_sel[] = { "osc", "pll_enet_100m_clk", 280static const char *pwm1_sel[] = { "osc", "pll_enet_100m_clk",
281 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", 281 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
282 "ext_clk_1", "ref_1m_clk", "pll_video_main_clk", }; 282 "ext_clk_1", "ref_1m_clk", "pll_video_post_div", };
283 283
284static const char *pwm2_sel[] = { "osc", "pll_enet_100m_clk", 284static const char *pwm2_sel[] = { "osc", "pll_enet_100m_clk",
285 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", 285 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
286 "ext_clk_1", "ref_1m_clk", "pll_video_main_clk", }; 286 "ext_clk_1", "ref_1m_clk", "pll_video_post_div", };
287 287
288static const char *pwm3_sel[] = { "osc", "pll_enet_100m_clk", 288static const char *pwm3_sel[] = { "osc", "pll_enet_100m_clk",
289 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", 289 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
290 "ext_clk_2", "ref_1m_clk", "pll_video_main_clk", }; 290 "ext_clk_2", "ref_1m_clk", "pll_video_post_div", };
291 291
292static const char *pwm4_sel[] = { "osc", "pll_enet_100m_clk", 292static const char *pwm4_sel[] = { "osc", "pll_enet_100m_clk",
293 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", 293 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
294 "ext_clk_2", "ref_1m_clk", "pll_video_main_clk", }; 294 "ext_clk_2", "ref_1m_clk", "pll_video_post_div", };
295 295
296static const char *flextimer1_sel[] = { "osc", "pll_enet_100m_clk", 296static const char *flextimer1_sel[] = { "osc", "pll_enet_100m_clk",
297 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", 297 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
298 "ext_clk_3", "ref_1m_clk", "pll_video_main_clk", }; 298 "ext_clk_3", "ref_1m_clk", "pll_video_post_div", };
299 299
300static const char *flextimer2_sel[] = { "osc", "pll_enet_100m_clk", 300static const char *flextimer2_sel[] = { "osc", "pll_enet_100m_clk",
301 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", 301 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
302 "ext_clk_3", "ref_1m_clk", "pll_video_main_clk", }; 302 "ext_clk_3", "ref_1m_clk", "pll_video_post_div", };
303 303
304static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 304static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
305 "pll_sys_main_120m_clk", "pll_dram_533m_clk", 305 "pll_sys_main_120m_clk", "pll_dram_533m_clk",
@@ -308,23 +308,23 @@ static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
308 308
309static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 309static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
310 "pll_sys_main_120m_clk", "pll_dram_533m_clk", 310 "pll_sys_main_120m_clk", "pll_dram_533m_clk",
311 "pll_usb_main_clk", "pll_video_main_clk", "pll_enet_125m_clk", 311 "pll_usb_main_clk", "pll_video_post_div", "pll_enet_125m_clk",
312 "pll_sys_pfd7_clk", }; 312 "pll_sys_pfd7_clk", };
313 313
314static const char *gpt1_sel[] = { "osc", "pll_enet_100m_clk", 314static const char *gpt1_sel[] = { "osc", "pll_enet_100m_clk",
315 "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", 315 "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
316 "ref_1m_clk", "pll_audio_post_div", "ext_clk_1", }; 316 "ref_1m_clk", "pll_audio_post_div", "ext_clk_1", };
317 317
318static const char *gpt2_sel[] = { "osc", "pll_enet_100m_clk", 318static const char *gpt2_sel[] = { "osc", "pll_enet_100m_clk",
319 "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", 319 "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
320 "ref_1m_clk", "pll_audio_post_div", "ext_clk_2", }; 320 "ref_1m_clk", "pll_audio_post_div", "ext_clk_2", };
321 321
322static const char *gpt3_sel[] = { "osc", "pll_enet_100m_clk", 322static const char *gpt3_sel[] = { "osc", "pll_enet_100m_clk",
323 "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", 323 "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
324 "ref_1m_clk", "pll_audio_post_div", "ext_clk_3", }; 324 "ref_1m_clk", "pll_audio_post_div", "ext_clk_3", };
325 325
326static const char *gpt4_sel[] = { "osc", "pll_enet_100m_clk", 326static const char *gpt4_sel[] = { "osc", "pll_enet_100m_clk",
327 "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", 327 "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
328 "ref_1m_clk", "pll_audio_post_div", "ext_clk_4", }; 328 "ref_1m_clk", "pll_audio_post_div", "ext_clk_4", };
329 329
330static const char *trace_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 330static const char *trace_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
@@ -339,12 +339,12 @@ static const char *wdog_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
339 339
340static const char *csi_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 340static const char *csi_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
341 "pll_sys_main_120m_clk", "pll_dram_533m_clk", 341 "pll_sys_main_120m_clk", "pll_dram_533m_clk",
342 "pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main_clk", 342 "pll_enet_125m_clk", "pll_audio_post_div", "pll_video_post_div",
343 "pll_usb_main_clk", }; 343 "pll_usb_main_clk", };
344 344
345static const char *audio_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 345static const char *audio_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
346 "pll_sys_main_120m_clk", "pll_dram_533m_clk", 346 "pll_sys_main_120m_clk", "pll_dram_533m_clk",
347 "pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main_clk", 347 "pll_enet_125m_clk", "pll_audio_post_div", "pll_video_post_div",
348 "pll_usb_main_clk", }; 348 "pll_usb_main_clk", };
349 349
350static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk", 350static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk",
@@ -358,13 +358,13 @@ static const char *clko1_sel[] = { "osc", "pll_sys_main_clk",
358 358
359static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk", 359static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk",
360 "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk", 360 "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk",
361 "pll_audio_post_div", "pll_video_main_clk", "ckil", }; 361 "pll_audio_post_div", "pll_video_post_div", "ckil", };
362 362
363static const char *lvds1_sel[] = { "pll_arm_main_clk", 363static const char *lvds1_sel[] = { "pll_arm_main_clk",
364 "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk", 364 "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk",
365 "pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk", 365 "pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk",
366 "pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", 366 "pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk",
367 "pll_audio_post_div", "pll_video_main_clk", "pll_enet_500m_clk", 367 "pll_audio_post_div", "pll_video_post_div", "pll_enet_500m_clk",
368 "pll_enet_250m_clk", "pll_enet_125m_clk", "pll_enet_100m_clk", 368 "pll_enet_250m_clk", "pll_enet_125m_clk", "pll_enet_100m_clk",
369 "pll_enet_50m_clk", "pll_enet_40m_clk", "pll_enet_25m_clk", 369 "pll_enet_50m_clk", "pll_enet_40m_clk", "pll_enet_25m_clk",
370 "pll_dram_main_clk", }; 370 "pll_dram_main_clk", };
@@ -433,23 +433,22 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
433 clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT); 433 clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT);
434 clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT); 434 clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT);
435 435
436 clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
437 clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
438 clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
439 clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
440 clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
441 clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
442
443 clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13); 436 clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
444 clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13); 437 clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_test_div", base + 0x70, 13);
445 clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13); 438 clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
446 clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13); 439 clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13);
447 clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13); 440 clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13);
448 441
442 clks[IMX7D_PLL_DRAM_TEST_DIV] = clk_register_divider_table(NULL, "pll_dram_test_div", "pll_dram_main_bypass",
443 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 21, 2, 0, test_div_table, &imx_ccm_lock);
449 clks[IMX7D_PLL_AUDIO_TEST_DIV] = clk_register_divider_table(NULL, "pll_audio_test_div", "pll_audio_main_clk", 444 clks[IMX7D_PLL_AUDIO_TEST_DIV] = clk_register_divider_table(NULL, "pll_audio_test_div", "pll_audio_main_clk",
450 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock); 445 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock);
451 clks[IMX7D_PLL_AUDIO_POST_DIV] = clk_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_test_div", 446 clks[IMX7D_PLL_AUDIO_POST_DIV] = clk_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_test_div",
452 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock); 447 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock);
448 clks[IMX7D_PLL_VIDEO_TEST_DIV] = clk_register_divider_table(NULL, "pll_video_test_div", "pll_video_main_clk",
449 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 19, 2, 0, test_div_table, &imx_ccm_lock);
450 clks[IMX7D_PLL_VIDEO_POST_DIV] = clk_register_divider_table(NULL, "pll_video_post_div", "pll_video_test_div",
451 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock);
453 452
454 clks[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0); 453 clks[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0);
455 clks[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1); 454 clks[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1);
@@ -795,7 +794,9 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
795 clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0); 794 clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0);
796 clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate4("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0); 795 clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate4("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0);
797 clks[IMX7D_OCOTP_CLK] = imx_clk_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0); 796 clks[IMX7D_OCOTP_CLK] = imx_clk_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0);
798 clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0); 797 clks[IMX7D_SNVS_CLK] = imx_clk_gate4("snvs_clk", "ipg_root_clk", base + 0x4250, 0);
798 clks[IMX7D_CAAM_CLK] = imx_clk_gate4("caam_clk", "ipg_root_clk", base + 0x4240, 0);
799 clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4690, 0);
799 clks[IMX7D_SDMA_CORE_CLK] = imx_clk_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0); 800 clks[IMX7D_SDMA_CORE_CLK] = imx_clk_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0);
800 clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0); 801 clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0);
801 clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0); 802 clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0);
@@ -857,9 +858,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
857 clks[IMX7D_WDOG2_ROOT_CLK] = imx_clk_gate4("wdog2_root_clk", "wdog_post_div", base + 0x49d0, 0); 858 clks[IMX7D_WDOG2_ROOT_CLK] = imx_clk_gate4("wdog2_root_clk", "wdog_post_div", base + 0x49d0, 0);
858 clks[IMX7D_WDOG3_ROOT_CLK] = imx_clk_gate4("wdog3_root_clk", "wdog_post_div", base + 0x49e0, 0); 859 clks[IMX7D_WDOG3_ROOT_CLK] = imx_clk_gate4("wdog3_root_clk", "wdog_post_div", base + 0x49e0, 0);
859 clks[IMX7D_WDOG4_ROOT_CLK] = imx_clk_gate4("wdog4_root_clk", "wdog_post_div", base + 0x49f0, 0); 860 clks[IMX7D_WDOG4_ROOT_CLK] = imx_clk_gate4("wdog4_root_clk", "wdog_post_div", base + 0x49f0, 0);
861 clks[IMX7D_KPP_ROOT_CLK] = imx_clk_gate4("kpp_root_clk", "ipg_root_clk", base + 0x4aa0, 0);
860 clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate4("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0); 862 clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate4("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0);
861 clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate4("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0); 863 clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate4("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0);
862 clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate4("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0); 864 clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate4("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0);
865 clks[IMX7D_USB_CTRL_CLK] = imx_clk_gate4("usb_ctrl_clk", "ahb_root_clk", base + 0x4680, 0);
866 clks[IMX7D_USB_PHY1_CLK] = imx_clk_gate4("usb_phy1_clk", "pll_usb1_main_clk", base + 0x46a0, 0);
867 clks[IMX7D_USB_PHY2_CLK] = imx_clk_gate4("usb_phy2_clk", "pll_usb_main_clk", base + 0x46b0, 0);
863 clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0); 868 clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0);
864 869
865 clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); 870 clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
@@ -879,12 +884,23 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
879 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 884 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
880 clk_prepare_enable(clks[clks_init_on[i]]); 885 clk_prepare_enable(clks[clks_init_on[i]]);
881 886
887 clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
888 clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
889 clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
890 clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
891 clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
892 clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
893
882 /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */ 894 /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
883 clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); 895 clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
884 896
885 /* set uart module clock's parent clock source that must be great then 80MHz */ 897 /* set uart module clock's parent clock source that must be great then 80MHz */
886 clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); 898 clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
887 899
900 /* Set clock rate for USBPHY, the USB_PLL at CCM is from USBOTG2 */
901 clks[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);
902 clks[IMX7D_USB_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb_main_clk", "osc", 20, 1);
903
888 imx_register_uart_clocks(uart_clks); 904 imx_register_uart_clocks(uart_clks);
889 905
890} 906}
diff --git a/drivers/clk/imx/clk-pllv2.c b/drivers/clk/imx/clk-pllv2.c
index 85b5cbe9744c..eeba3cb14e2d 100644
--- a/drivers/clk/imx/clk-pllv2.c
+++ b/drivers/clk/imx/clk-pllv2.c
@@ -182,8 +182,12 @@ static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate,
182 unsigned long *prate) 182 unsigned long *prate)
183{ 183{
184 u32 dp_op, dp_mfd, dp_mfn; 184 u32 dp_op, dp_mfd, dp_mfn;
185 int ret;
186
187 ret = __clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn);
188 if (ret)
189 return ret;
185 190
186 __clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn);
187 return __clk_pllv2_recalc_rate(*prate, MXC_PLL_DP_CTL_DPDCK0_2_EN, 191 return __clk_pllv2_recalc_rate(*prate, MXC_PLL_DP_CTL_DPDCK0_2_EN,
188 dp_op, dp_mfd, dp_mfn); 192 dp_op, dp_mfd, dp_mfn);
189} 193}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index d69c4bbf3597..8076ec040f37 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -123,6 +123,13 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent,
123 shift, 0, &imx_ccm_lock); 123 shift, 0, &imx_ccm_lock);
124} 124}
125 125
126static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
127 void __iomem *reg, u8 shift, unsigned long flags)
128{
129 return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
130 shift, 0, &imx_ccm_lock);
131}
132
126static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, 133static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
127 void __iomem *reg, u8 shift) 134 void __iomem *reg, u8 shift)
128{ 135{
@@ -137,6 +144,13 @@ static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
137 shift, 0x3, 0, &imx_ccm_lock, NULL); 144 shift, 0x3, 0, &imx_ccm_lock, NULL);
138} 145}
139 146
147static inline struct clk *imx_clk_gate2_flags(const char *name, const char *parent,
148 void __iomem *reg, u8 shift, unsigned long flags)
149{
150 return clk_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
151 shift, 0x3, 0, &imx_ccm_lock, NULL);
152}
153
140static inline struct clk *imx_clk_gate2_shared(const char *name, 154static inline struct clk *imx_clk_gate2_shared(const char *name,
141 const char *parent, void __iomem *reg, u8 shift, 155 const char *parent, void __iomem *reg, u8 shift,
142 unsigned int *share_count) 156 unsigned int *share_count)
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
index 9146c20fe21f..ce5aa7802eb8 100644
--- a/drivers/clk/socfpga/Makefile
+++ b/drivers/clk/socfpga/Makefile
@@ -1,6 +1,5 @@
1# SPDX-License-Identifier: GPL-2.0 1# SPDX-License-Identifier: GPL-2.0
2obj-y += clk.o 2obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o
3obj-y += clk-gate.o 3obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
4obj-y += clk-pll.o 4obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o
5obj-y += clk-periph.o 5obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
6obj-y += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
diff --git a/drivers/clk/socfpga/clk-gate-s10.c b/drivers/clk/socfpga/clk-gate-s10.c
new file mode 100644
index 000000000000..eee2d48ab656
--- /dev/null
+++ b/drivers/clk/socfpga/clk-gate-s10.c
@@ -0,0 +1,125 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017, Intel Corporation
4 */
5#include <linux/clk-provider.h>
6#include <linux/slab.h>
7#include "stratix10-clk.h"
8#include "clk.h"
9
10#define SOCFPGA_CS_PDBG_CLK "cs_pdbg_clk"
11#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
12
13static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
14 unsigned long parent_rate)
15{
16 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
17 u32 div = 1, val;
18
19 if (socfpgaclk->fixed_div) {
20 div = socfpgaclk->fixed_div;
21 } else if (socfpgaclk->div_reg) {
22 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
23 val &= GENMASK(socfpgaclk->width - 1, 0);
24 div = (1 << val);
25 }
26 return parent_rate / div;
27}
28
29static unsigned long socfpga_dbg_clk_recalc_rate(struct clk_hw *hwclk,
30 unsigned long parent_rate)
31{
32 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
33 u32 div = 1, val;
34
35 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
36 val &= GENMASK(socfpgaclk->width - 1, 0);
37 div = (1 << val);
38 div = div ? 4 : 1;
39
40 return parent_rate / div;
41}
42
43static u8 socfpga_gate_get_parent(struct clk_hw *hwclk)
44{
45 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
46 u32 mask;
47 u8 parent = 0;
48
49 if (socfpgaclk->bypass_reg) {
50 mask = (0x1 << socfpgaclk->bypass_shift);
51 parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
52 socfpgaclk->bypass_shift);
53 }
54 return parent;
55}
56
57static struct clk_ops gateclk_ops = {
58 .recalc_rate = socfpga_gate_clk_recalc_rate,
59 .get_parent = socfpga_gate_get_parent,
60};
61
62static const struct clk_ops dbgclk_ops = {
63 .recalc_rate = socfpga_dbg_clk_recalc_rate,
64 .get_parent = socfpga_gate_get_parent,
65};
66
67struct clk *s10_register_gate(const char *name, const char *parent_name,
68 const char * const *parent_names,
69 u8 num_parents, unsigned long flags,
70 void __iomem *regbase, unsigned long gate_reg,
71 unsigned long gate_idx, unsigned long div_reg,
72 unsigned long div_offset, u8 div_width,
73 unsigned long bypass_reg, u8 bypass_shift,
74 u8 fixed_div)
75{
76 struct clk *clk;
77 struct socfpga_gate_clk *socfpga_clk;
78 struct clk_init_data init;
79
80 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
81 if (!socfpga_clk)
82 return NULL;
83
84 socfpga_clk->hw.reg = regbase + gate_reg;
85 socfpga_clk->hw.bit_idx = gate_idx;
86
87 gateclk_ops.enable = clk_gate_ops.enable;
88 gateclk_ops.disable = clk_gate_ops.disable;
89
90 socfpga_clk->fixed_div = fixed_div;
91
92 if (div_reg)
93 socfpga_clk->div_reg = regbase + div_reg;
94 else
95 socfpga_clk->div_reg = NULL;
96
97 socfpga_clk->width = div_width;
98 socfpga_clk->shift = div_offset;
99
100 if (bypass_reg)
101 socfpga_clk->bypass_reg = regbase + bypass_reg;
102 else
103 socfpga_clk->bypass_reg = NULL;
104 socfpga_clk->bypass_shift = bypass_shift;
105
106 if (streq(name, "cs_pdbg_clk"))
107 init.ops = &dbgclk_ops;
108 else
109 init.ops = &gateclk_ops;
110
111 init.name = name;
112 init.flags = flags;
113
114 init.num_parents = num_parents;
115 init.parent_names = parent_names ? parent_names : &parent_name;
116 socfpga_clk->hw.hw.init = &init;
117
118 clk = clk_register(NULL, &socfpga_clk->hw.hw);
119 if (WARN_ON(IS_ERR(clk))) {
120 kfree(socfpga_clk);
121 return NULL;
122 }
123
124 return clk;
125}
diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c
new file mode 100644
index 000000000000..568f59b58ddf
--- /dev/null
+++ b/drivers/clk/socfpga/clk-periph-s10.c
@@ -0,0 +1,149 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017, Intel Corporation
4 */
5#include <linux/slab.h>
6#include <linux/clk-provider.h>
7
8#include "stratix10-clk.h"
9#include "clk.h"
10
11#define CLK_MGR_FREE_SHIFT 16
12#define CLK_MGR_FREE_MASK 0x7
13#define SWCTRLBTCLKSEN_SHIFT 8
14
15#define to_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
16
17static unsigned long clk_peri_c_clk_recalc_rate(struct clk_hw *hwclk,
18 unsigned long parent_rate)
19{
20 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
21 unsigned long div = 1;
22 u32 val;
23
24 val = readl(socfpgaclk->hw.reg);
25 val &= GENMASK(SWCTRLBTCLKSEN_SHIFT - 1, 0);
26 parent_rate /= val;
27
28 return parent_rate / div;
29}
30
31static unsigned long clk_peri_cnt_clk_recalc_rate(struct clk_hw *hwclk,
32 unsigned long parent_rate)
33{
34 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
35 unsigned long div = 1;
36
37 if (socfpgaclk->fixed_div) {
38 div = socfpgaclk->fixed_div;
39 } else {
40 if (!socfpgaclk->bypass_reg)
41 div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
42 }
43
44 return parent_rate / div;
45}
46
47static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
48{
49 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
50 u32 clk_src, mask;
51 u8 parent;
52
53 if (socfpgaclk->bypass_reg) {
54 mask = (0x1 << socfpgaclk->bypass_shift);
55 parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
56 socfpgaclk->bypass_shift);
57 } else {
58 clk_src = readl(socfpgaclk->hw.reg);
59 parent = (clk_src >> CLK_MGR_FREE_SHIFT) &
60 CLK_MGR_FREE_MASK;
61 }
62 return parent;
63}
64
65static const struct clk_ops peri_c_clk_ops = {
66 .recalc_rate = clk_peri_c_clk_recalc_rate,
67 .get_parent = clk_periclk_get_parent,
68};
69
70static const struct clk_ops peri_cnt_clk_ops = {
71 .recalc_rate = clk_peri_cnt_clk_recalc_rate,
72 .get_parent = clk_periclk_get_parent,
73};
74
75struct clk *s10_register_periph(const char *name, const char *parent_name,
76 const char * const *parent_names,
77 u8 num_parents, unsigned long flags,
78 void __iomem *reg, unsigned long offset)
79{
80 struct clk *clk;
81 struct socfpga_periph_clk *periph_clk;
82 struct clk_init_data init;
83
84 periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
85 if (WARN_ON(!periph_clk))
86 return NULL;
87
88 periph_clk->hw.reg = reg + offset;
89
90 init.name = name;
91 init.ops = &peri_c_clk_ops;
92 init.flags = flags;
93
94 init.num_parents = num_parents;
95 init.parent_names = parent_names ? parent_names : &parent_name;
96
97 periph_clk->hw.hw.init = &init;
98
99 clk = clk_register(NULL, &periph_clk->hw.hw);
100 if (WARN_ON(IS_ERR(clk))) {
101 kfree(periph_clk);
102 return NULL;
103 }
104 return clk;
105}
106
107struct clk *s10_register_cnt_periph(const char *name, const char *parent_name,
108 const char * const *parent_names,
109 u8 num_parents, unsigned long flags,
110 void __iomem *regbase, unsigned long offset,
111 u8 fixed_divider, unsigned long bypass_reg,
112 unsigned long bypass_shift)
113{
114 struct clk *clk;
115 struct socfpga_periph_clk *periph_clk;
116 struct clk_init_data init;
117
118 periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
119 if (WARN_ON(!periph_clk))
120 return NULL;
121
122 if (offset)
123 periph_clk->hw.reg = regbase + offset;
124 else
125 periph_clk->hw.reg = NULL;
126
127 if (bypass_reg)
128 periph_clk->bypass_reg = regbase + bypass_reg;
129 else
130 periph_clk->bypass_reg = NULL;
131 periph_clk->bypass_shift = bypass_shift;
132 periph_clk->fixed_div = fixed_divider;
133
134 init.name = name;
135 init.ops = &peri_cnt_clk_ops;
136 init.flags = flags;
137
138 init.num_parents = num_parents;
139 init.parent_names = parent_names ? parent_names : &parent_name;
140
141 periph_clk->hw.hw.init = &init;
142
143 clk = clk_register(NULL, &periph_clk->hw.hw);
144 if (WARN_ON(IS_ERR(clk))) {
145 kfree(periph_clk);
146 return NULL;
147 }
148 return clk;
149}
diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
new file mode 100644
index 000000000000..2d5d8b43727e
--- /dev/null
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -0,0 +1,146 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017, Intel Corporation
4 */
5#include <linux/slab.h>
6#include <linux/clk-provider.h>
7
8#include "stratix10-clk.h"
9#include "clk.h"
10
11/* Clock Manager offsets */
12#define CLK_MGR_PLL_CLK_SRC_SHIFT 16
13#define CLK_MGR_PLL_CLK_SRC_MASK 0x3
14
15/* PLL Clock enable bits */
16#define SOCFPGA_PLL_POWER 0
17#define SOCFPGA_PLL_RESET_MASK 0x2
18#define SOCFPGA_PLL_REFDIV_MASK 0x00003F00
19#define SOCFPGA_PLL_REFDIV_SHIFT 8
20#define SOCFPGA_PLL_MDIV_MASK 0xFF000000
21#define SOCFPGA_PLL_MDIV_SHIFT 24
22#define SWCTRLBTCLKSEL_MASK 0x200
23#define SWCTRLBTCLKSEL_SHIFT 9
24
25#define SOCFPGA_BOOT_CLK "boot_clk"
26
27#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
28
29static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
30 unsigned long parent_rate)
31{
32 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
33 unsigned long mdiv;
34 unsigned long refdiv;
35 unsigned long reg;
36 unsigned long long vco_freq;
37
38 /* read VCO1 reg for numerator and denominator */
39 reg = readl(socfpgaclk->hw.reg);
40 refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
41 vco_freq = (unsigned long long)parent_rate / refdiv;
42
43 /* Read mdiv and fdiv from the fdbck register */
44 reg = readl(socfpgaclk->hw.reg + 0x4);
45 mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;
46 vco_freq = (unsigned long long)parent_rate * (mdiv + 6);
47
48 return (unsigned long)vco_freq;
49}
50
51static unsigned long clk_boot_clk_recalc_rate(struct clk_hw *hwclk,
52 unsigned long parent_rate)
53{
54 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
55 u32 div = 1;
56
57 div = ((readl(socfpgaclk->hw.reg) &
58 SWCTRLBTCLKSEL_MASK) >>
59 SWCTRLBTCLKSEL_SHIFT);
60 div += 1;
61 return parent_rate /= div;
62}
63
64
65static u8 clk_pll_get_parent(struct clk_hw *hwclk)
66{
67 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
68 u32 pll_src;
69
70 pll_src = readl(socfpgaclk->hw.reg);
71 return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
72 CLK_MGR_PLL_CLK_SRC_MASK;
73}
74
75static u8 clk_boot_get_parent(struct clk_hw *hwclk)
76{
77 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
78 u32 pll_src;
79
80 pll_src = readl(socfpgaclk->hw.reg);
81 return (pll_src >> SWCTRLBTCLKSEL_SHIFT) &
82 SWCTRLBTCLKSEL_MASK;
83}
84
85static int clk_pll_prepare(struct clk_hw *hwclk)
86{
87 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
88 u32 reg;
89
90 /* Bring PLL out of reset */
91 reg = readl(socfpgaclk->hw.reg);
92 reg |= SOCFPGA_PLL_RESET_MASK;
93 writel(reg, socfpgaclk->hw.reg);
94
95 return 0;
96}
97
98static struct clk_ops clk_pll_ops = {
99 .recalc_rate = clk_pll_recalc_rate,
100 .get_parent = clk_pll_get_parent,
101 .prepare = clk_pll_prepare,
102};
103
104static struct clk_ops clk_boot_ops = {
105 .recalc_rate = clk_boot_clk_recalc_rate,
106 .get_parent = clk_boot_get_parent,
107 .prepare = clk_pll_prepare,
108};
109
110struct clk *s10_register_pll(const char *name, const char * const *parent_names,
111 u8 num_parents, unsigned long flags,
112 void __iomem *reg, unsigned long offset)
113{
114 struct clk *clk;
115 struct socfpga_pll *pll_clk;
116 struct clk_init_data init;
117
118 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
119 if (WARN_ON(!pll_clk))
120 return NULL;
121
122 pll_clk->hw.reg = reg + offset;
123
124 if (streq(name, SOCFPGA_BOOT_CLK))
125 init.ops = &clk_boot_ops;
126 else
127 init.ops = &clk_pll_ops;
128
129 init.name = name;
130 init.flags = flags;
131
132 init.num_parents = num_parents;
133 init.parent_names = parent_names;
134 pll_clk->hw.hw.init = &init;
135
136 pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
137 clk_pll_ops.enable = clk_gate_ops.enable;
138 clk_pll_ops.disable = clk_gate_ops.disable;
139
140 clk = clk_register(NULL, &pll_clk->hw.hw);
141 if (WARN_ON(IS_ERR(clk))) {
142 kfree(pll_clk);
143 return NULL;
144 }
145 return clk;
146}
diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
new file mode 100644
index 000000000000..3a11c382a663
--- /dev/null
+++ b/drivers/clk/socfpga/clk-s10.c
@@ -0,0 +1,345 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017, Intel Corporation
4 */
5#include <linux/slab.h>
6#include <linux/clk-provider.h>
7#include <linux/of_device.h>
8#include <linux/of_address.h>
9#include <linux/platform_device.h>
10
11#include <dt-bindings/clock/stratix10-clock.h>
12
13#include "stratix10-clk.h"
14
15static const char * const pll_mux[] = { "osc1", "cb_intosc_hs_div2_clk",
16 "f2s_free_clk",};
17static const char * const cntr_mux[] = { "main_pll", "periph_pll",
18 "osc1", "cb_intosc_hs_div2_clk",
19 "f2s_free_clk"};
20static const char * const boot_mux[] = { "osc1", "cb_intosc_hs_div2_clk",};
21
22static const char * const noc_free_mux[] = {"main_noc_base_clk",
23 "peri_noc_base_clk",
24 "osc1", "cb_intosc_hs_div2_clk",
25 "f2s_free_clk"};
26
27static const char * const emaca_free_mux[] = {"peri_emaca_clk", "boot_clk"};
28static const char * const emacb_free_mux[] = {"peri_emacb_clk", "boot_clk"};
29static const char * const emac_ptp_free_mux[] = {"peri_emac_ptp_clk", "boot_clk"};
30static const char * const gpio_db_free_mux[] = {"peri_gpio_db_clk", "boot_clk"};
31static const char * const sdmmc_free_mux[] = {"peri_sdmmc_clk", "boot_clk"};
32static const char * const s2f_usr1_free_mux[] = {"peri_s2f_usr1_clk", "boot_clk"};
33static const char * const psi_ref_free_mux[] = {"peri_psi_ref_clk", "boot_clk"};
34static const char * const mpu_mux[] = { "mpu_free_clk", "boot_clk",};
35
36static const char * const s2f_usr0_mux[] = {"f2s_free_clk", "boot_clk"};
37static const char * const emac_mux[] = {"emaca_free_clk", "emacb_free_clk"};
38static const char * const noc_mux[] = {"noc_free_clk", "boot_clk"};
39
40/* clocks in AO (always on) controller */
41static const struct stratix10_pll_clock s10_pll_clks[] = {
42 { STRATIX10_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
43 0x0},
44 { STRATIX10_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
45 0, 0x74},
46 { STRATIX10_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
47 0, 0xe4},
48};
49
50static const struct stratix10_perip_c_clock s10_main_perip_c_clks[] = {
51 { STRATIX10_MAIN_MPU_BASE_CLK, "main_mpu_base_clk", "main_pll", NULL, 1, 0, 0x84},
52 { STRATIX10_MAIN_NOC_BASE_CLK, "main_noc_base_clk", "main_pll", NULL, 1, 0, 0x88},
53 { STRATIX10_PERI_MPU_BASE_CLK, "peri_mpu_base_clk", "periph_pll", NULL, 1, 0,
54 0xF4},
55 { STRATIX10_PERI_NOC_BASE_CLK, "peri_noc_base_clk", "periph_pll", NULL, 1, 0,
56 0xF8},
57};
58
59static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = {
60 { STRATIX10_MPU_FREE_CLK, "mpu_free_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
61 0, 0x48, 0, 0, 0},
62 { STRATIX10_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
63 0, 0x4C, 0, 0, 0},
64 { STRATIX10_MAIN_EMACA_CLK, "main_emaca_clk", "main_noc_base_clk", NULL, 1, 0,
65 0x50, 0, 0, 0},
66 { STRATIX10_MAIN_EMACB_CLK, "main_emacb_clk", "main_noc_base_clk", NULL, 1, 0,
67 0x54, 0, 0, 0},
68 { STRATIX10_MAIN_EMAC_PTP_CLK, "main_emac_ptp_clk", "main_noc_base_clk", NULL, 1, 0,
69 0x58, 0, 0, 0},
70 { STRATIX10_MAIN_GPIO_DB_CLK, "main_gpio_db_clk", "main_noc_base_clk", NULL, 1, 0,
71 0x5C, 0, 0, 0},
72 { STRATIX10_MAIN_SDMMC_CLK, "main_sdmmc_clk", "main_noc_base_clk", NULL, 1, 0,
73 0x60, 0, 0, 0},
74 { STRATIX10_MAIN_S2F_USR0_CLK, "main_s2f_usr0_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
75 0, 0x64, 0, 0, 0},
76 { STRATIX10_MAIN_S2F_USR1_CLK, "main_s2f_usr1_clk", "main_noc_base_clk", NULL, 1, 0,
77 0x68, 0, 0, 0},
78 { STRATIX10_MAIN_PSI_REF_CLK, "main_psi_ref_clk", "main_noc_base_clk", NULL, 1, 0,
79 0x6C, 0, 0, 0},
80 { STRATIX10_PERI_EMACA_CLK, "peri_emaca_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
81 0, 0xBC, 0, 0, 0},
82 { STRATIX10_PERI_EMACB_CLK, "peri_emacb_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
83 0, 0xC0, 0, 0, 0},
84 { STRATIX10_PERI_EMAC_PTP_CLK, "peri_emac_ptp_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
85 0, 0xC4, 0, 0, 0},
86 { STRATIX10_PERI_GPIO_DB_CLK, "peri_gpio_db_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
87 0, 0xC8, 0, 0, 0},
88 { STRATIX10_PERI_SDMMC_CLK, "peri_sdmmc_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
89 0, 0xCC, 0, 0, 0},
90 { STRATIX10_PERI_S2F_USR0_CLK, "peri_s2f_usr0_clk", "peri_noc_base_clk", NULL, 1, 0,
91 0xD0, 0, 0, 0},
92 { STRATIX10_PERI_S2F_USR1_CLK, "peri_s2f_usr1_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
93 0, 0xD4, 0, 0, 0},
94 { STRATIX10_PERI_PSI_REF_CLK, "peri_psi_ref_clk", "peri_noc_base_clk", NULL, 1, 0,
95 0xD8, 0, 0, 0},
96 { STRATIX10_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0,
97 0, 4, 0, 0},
98 { STRATIX10_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
99 0, 0, 0, 0x3C, 1},
100 { STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
101 0, 0, 4, 0xB0, 0},
102 { STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
103 0, 0, 4, 0xB0, 1},
104 { STRATIX10_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
105 ARRAY_SIZE(emac_ptp_free_mux), 0, 0, 4, 0xB0, 2},
106 { STRATIX10_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
107 ARRAY_SIZE(gpio_db_free_mux), 0, 0, 0, 0xB0, 3},
108 { STRATIX10_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
109 ARRAY_SIZE(sdmmc_free_mux), 0, 0, 0, 0xB0, 4},
110 { STRATIX10_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
111 ARRAY_SIZE(s2f_usr1_free_mux), 0, 0, 0, 0xB0, 5},
112 { STRATIX10_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
113 ARRAY_SIZE(psi_ref_free_mux), 0, 0, 0, 0xB0, 6},
114};
115
116static const struct stratix10_gate_clock s10_gate_clks[] = {
117 { STRATIX10_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x30,
118 0, 0, 0, 0, 0x3C, 0, 0},
119 { STRATIX10_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x30,
120 0, 0, 0, 0, 0, 0, 4},
121 { STRATIX10_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x30,
122 0, 0, 0, 0, 0, 0, 2},
123 { STRATIX10_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x30,
124 1, 0x70, 0, 2, 0, 0, 0},
125 { STRATIX10_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x30,
126 2, 0x70, 8, 2, 0, 0, 0},
127 { STRATIX10_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x30,
128 3, 0x70, 16, 2, 0, 0, 0},
129 { STRATIX10_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x30,
130 4, 0x70, 24, 2, 0, 0, 0},
131 { STRATIX10_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x30,
132 4, 0x70, 26, 2, 0, 0, 0},
133 { STRATIX10_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x30,
134 4, 0x70, 28, 1, 0, 0, 0},
135 { STRATIX10_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x30,
136 5, 0, 0, 0, 0, 0, 0},
137 { STRATIX10_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x30,
138 6, 0, 0, 0, 0, 0, 0},
139 { STRATIX10_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
140 0, 0, 0, 0, 0xDC, 26, 0},
141 { STRATIX10_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
142 1, 0, 0, 0, 0xDC, 27, 0},
143 { STRATIX10_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
144 2, 0, 0, 0, 0xDC, 28, 0},
145 { STRATIX10_EMAC_PTP_CLK, "emac_ptp_clk", "emac_ptp_free_clk", NULL, 1, 0, 0xA4,
146 3, 0, 0, 0, 0, 0, 0},
147 { STRATIX10_GPIO_DB_CLK, "gpio_db_clk", "gpio_db_free_clk", NULL, 1, 0, 0xA4,
148 4, 0xE0, 0, 16, 0, 0, 0},
149 { STRATIX10_SDMMC_CLK, "sdmmc_clk", "sdmmc_free_clk", NULL, 1, 0, 0xA4,
150 5, 0, 0, 0, 0, 0, 4},
151 { STRATIX10_S2F_USER1_CLK, "s2f_user1_clk", "s2f_user1_free_clk", NULL, 1, 0, 0xA4,
152 6, 0, 0, 0, 0, 0, 0},
153 { STRATIX10_PSI_REF_CLK, "psi_ref_clk", "psi_ref_free_clk", NULL, 1, 0, 0xA4,
154 7, 0, 0, 0, 0, 0, 0},
155 { STRATIX10_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
156 8, 0, 0, 0, 0, 0, 0},
157 { STRATIX10_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
158 9, 0, 0, 0, 0, 0, 0},
159 { STRATIX10_NAND_CLK, "nand_clk", "l4_main_clk", NULL, 1, 0, 0xA4,
160 10, 0, 0, 0, 0, 0, 0},
161};
162
163static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
164 int nums, struct stratix10_clock_data *data)
165{
166 struct clk *clk;
167 void __iomem *base = data->base;
168 int i;
169
170 for (i = 0; i < nums; i++) {
171 clk = s10_register_periph(clks[i].name, clks[i].parent_name,
172 clks[i].parent_names, clks[i].num_parents,
173 clks[i].flags, base, clks[i].offset);
174 if (IS_ERR(clk)) {
175 pr_err("%s: failed to register clock %s\n",
176 __func__, clks[i].name);
177 continue;
178 }
179 data->clk_data.clks[clks[i].id] = clk;
180 }
181 return 0;
182}
183
184static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
185 int nums, struct stratix10_clock_data *data)
186{
187 struct clk *clk;
188 void __iomem *base = data->base;
189 int i;
190
191 for (i = 0; i < nums; i++) {
192 clk = s10_register_cnt_periph(clks[i].name, clks[i].parent_name,
193 clks[i].parent_names,
194 clks[i].num_parents,
195 clks[i].flags, base,
196 clks[i].offset,
197 clks[i].fixed_divider,
198 clks[i].bypass_reg,
199 clks[i].bypass_shift);
200 if (IS_ERR(clk)) {
201 pr_err("%s: failed to register clock %s\n",
202 __func__, clks[i].name);
203 continue;
204 }
205 data->clk_data.clks[clks[i].id] = clk;
206 }
207
208 return 0;
209}
210
211static int s10_clk_register_gate(const struct stratix10_gate_clock *clks,
212 int nums, struct stratix10_clock_data *data)
213{
214 struct clk *clk;
215 void __iomem *base = data->base;
216 int i;
217
218 for (i = 0; i < nums; i++) {
219 clk = s10_register_gate(clks[i].name, clks[i].parent_name,
220 clks[i].parent_names,
221 clks[i].num_parents,
222 clks[i].flags, base,
223 clks[i].gate_reg,
224 clks[i].gate_idx, clks[i].div_reg,
225 clks[i].div_offset, clks[i].div_width,
226 clks[i].bypass_reg,
227 clks[i].bypass_shift,
228 clks[i].fixed_div);
229 if (IS_ERR(clk)) {
230 pr_err("%s: failed to register clock %s\n",
231 __func__, clks[i].name);
232 continue;
233 }
234 data->clk_data.clks[clks[i].id] = clk;
235 }
236
237 return 0;
238}
239
240static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
241 int nums, struct stratix10_clock_data *data)
242{
243 struct clk *clk;
244 void __iomem *base = data->base;
245 int i;
246
247 for (i = 0; i < nums; i++) {
248 clk = s10_register_pll(clks[i].name, clks[i].parent_names,
249 clks[i].num_parents,
250 clks[i].flags, base,
251 clks[i].offset);
252 if (IS_ERR(clk)) {
253 pr_err("%s: failed to register clock %s\n",
254 __func__, clks[i].name);
255 continue;
256 }
257 data->clk_data.clks[clks[i].id] = clk;
258 }
259
260 return 0;
261}
262
263static struct stratix10_clock_data *__socfpga_s10_clk_init(struct device_node *np,
264 int nr_clks)
265{
266 struct stratix10_clock_data *clk_data;
267 struct clk **clk_table;
268 void __iomem *base;
269
270 base = of_iomap(np, 0);
271 if (!base) {
272 pr_err("%s: failed to map clock registers\n", __func__);
273 goto err;
274 }
275
276 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
277 if (!clk_data)
278 goto err;
279
280 clk_data->base = base;
281 clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL);
282 if (!clk_table)
283 goto err_data;
284
285 clk_data->clk_data.clks = clk_table;
286 clk_data->clk_data.clk_num = nr_clks;
287 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
288 return clk_data;
289
290err_data:
291 kfree(clk_data);
292err:
293 return NULL;
294}
295
296static int s10_clkmgr_init(struct device_node *np)
297{
298 struct stratix10_clock_data *clk_data;
299
300 clk_data = __socfpga_s10_clk_init(np, STRATIX10_NUM_CLKS);
301 if (!clk_data)
302 return -ENOMEM;
303
304 s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
305
306 s10_clk_register_c_perip(s10_main_perip_c_clks,
307 ARRAY_SIZE(s10_main_perip_c_clks), clk_data);
308
309 s10_clk_register_cnt_perip(s10_main_perip_cnt_clks,
310 ARRAY_SIZE(s10_main_perip_cnt_clks),
311 clk_data);
312
313 s10_clk_register_gate(s10_gate_clks, ARRAY_SIZE(s10_gate_clks),
314 clk_data);
315 return 0;
316}
317
318static int s10_clkmgr_probe(struct platform_device *pdev)
319{
320 struct device_node *np = pdev->dev.of_node;
321
322 s10_clkmgr_init(np);
323
324 return 0;
325}
326
327static const struct of_device_id stratix10_clkmgr_match_table[] = {
328 { .compatible = "intel,stratix10-clkmgr",
329 .data = s10_clkmgr_init },
330 { }
331};
332
333static struct platform_driver stratix10_clkmgr_driver = {
334 .probe = s10_clkmgr_probe,
335 .driver = {
336 .name = "stratix10-clkmgr",
337 .of_match_table = stratix10_clkmgr_match_table,
338 },
339};
340
341static int __init s10_clk_init(void)
342{
343 return platform_driver_register(&stratix10_clkmgr_driver);
344}
345core_initcall(s10_clk_init);
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index 9cf1230115b1..26c3a265cf78 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -54,9 +54,11 @@ struct socfpga_gate_clk {
54 char *parent_name; 54 char *parent_name;
55 u32 fixed_div; 55 u32 fixed_div;
56 void __iomem *div_reg; 56 void __iomem *div_reg;
57 void __iomem *bypass_reg;
57 struct regmap *sys_mgr_base_addr; 58 struct regmap *sys_mgr_base_addr;
58 u32 width; /* only valid if div_reg != 0 */ 59 u32 width; /* only valid if div_reg != 0 */
59 u32 shift; /* only valid if div_reg != 0 */ 60 u32 shift; /* only valid if div_reg != 0 */
61 u32 bypass_shift; /* only valid if bypass_reg != 0 */
60 u32 clk_phase[2]; 62 u32 clk_phase[2];
61}; 63};
62 64
@@ -65,8 +67,10 @@ struct socfpga_periph_clk {
65 char *parent_name; 67 char *parent_name;
66 u32 fixed_div; 68 u32 fixed_div;
67 void __iomem *div_reg; 69 void __iomem *div_reg;
70 void __iomem *bypass_reg;
68 u32 width; /* only valid if div_reg != 0 */ 71 u32 width; /* only valid if div_reg != 0 */
69 u32 shift; /* only valid if div_reg != 0 */ 72 u32 shift; /* only valid if div_reg != 0 */
73 u32 bypass_shift; /* only valid if bypass_reg != 0 */
70}; 74};
71 75
72#endif /* SOCFPGA_CLK_H */ 76#endif /* SOCFPGA_CLK_H */
diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h
new file mode 100644
index 000000000000..e8e121907952
--- /dev/null
+++ b/drivers/clk/socfpga/stratix10-clk.h
@@ -0,0 +1,80 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2017, Intel Corporation
4 */
5
6#ifndef __STRATIX10_CLK_H
7#define __STRATIX10_CLK_H
8
9struct stratix10_clock_data {
10 struct clk_onecell_data clk_data;
11 void __iomem *base;
12};
13
14struct stratix10_pll_clock {
15 unsigned int id;
16 const char *name;
17 const char *const *parent_names;
18 u8 num_parents;
19 unsigned long flags;
20 unsigned long offset;
21};
22
23struct stratix10_perip_c_clock {
24 unsigned int id;
25 const char *name;
26 const char *parent_name;
27 const char *const *parent_names;
28 u8 num_parents;
29 unsigned long flags;
30 unsigned long offset;
31};
32
33struct stratix10_perip_cnt_clock {
34 unsigned int id;
35 const char *name;
36 const char *parent_name;
37 const char *const *parent_names;
38 u8 num_parents;
39 unsigned long flags;
40 unsigned long offset;
41 u8 fixed_divider;
42 unsigned long bypass_reg;
43 unsigned long bypass_shift;
44};
45
46struct stratix10_gate_clock {
47 unsigned int id;
48 const char *name;
49 const char *parent_name;
50 const char *const *parent_names;
51 u8 num_parents;
52 unsigned long flags;
53 unsigned long gate_reg;
54 u8 gate_idx;
55 unsigned long div_reg;
56 u8 div_offset;
57 u8 div_width;
58 unsigned long bypass_reg;
59 u8 bypass_shift;
60 u8 fixed_div;
61};
62
63struct clk *s10_register_pll(const char *, const char *const *, u8,
64 unsigned long, void __iomem *, unsigned long);
65
66struct clk *s10_register_periph(const char *, const char *,
67 const char * const *, u8, unsigned long,
68 void __iomem *, unsigned long);
69struct clk *s10_register_cnt_periph(const char *, const char *,
70 const char * const *, u8,
71 unsigned long, void __iomem *,
72 unsigned long, u8, unsigned long,
73 unsigned long);
74struct clk *s10_register_gate(const char *, const char *,
75 const char * const *, u8,
76 unsigned long, void __iomem *,
77 unsigned long, unsigned long,
78 unsigned long, unsigned long, u8,
79 unsigned long, u8, u8);
80#endif /* __STRATIX10_CLK_H */
diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h
new file mode 100644
index 000000000000..151111e68f4f
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sll-clock.h
@@ -0,0 +1,202 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP.
5 *
6 */
7
8#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H
9#define __DT_BINDINGS_CLOCK_IMX6SLL_H
10
11#define IMX6SLL_CLK_DUMMY 0
12#define IMX6SLL_CLK_CKIL 1
13#define IMX6SLL_CLK_OSC 2
14#define IMX6SLL_PLL1_BYPASS_SRC 3
15#define IMX6SLL_PLL2_BYPASS_SRC 4
16#define IMX6SLL_PLL3_BYPASS_SRC 5
17#define IMX6SLL_PLL4_BYPASS_SRC 6
18#define IMX6SLL_PLL5_BYPASS_SRC 7
19#define IMX6SLL_PLL6_BYPASS_SRC 8
20#define IMX6SLL_PLL7_BYPASS_SRC 9
21#define IMX6SLL_CLK_PLL1 10
22#define IMX6SLL_CLK_PLL2 11
23#define IMX6SLL_CLK_PLL3 12
24#define IMX6SLL_CLK_PLL4 13
25#define IMX6SLL_CLK_PLL5 14
26#define IMX6SLL_CLK_PLL6 15
27#define IMX6SLL_CLK_PLL7 16
28#define IMX6SLL_PLL1_BYPASS 17
29#define IMX6SLL_PLL2_BYPASS 18
30#define IMX6SLL_PLL3_BYPASS 19
31#define IMX6SLL_PLL4_BYPASS 20
32#define IMX6SLL_PLL5_BYPASS 21
33#define IMX6SLL_PLL6_BYPASS 22
34#define IMX6SLL_PLL7_BYPASS 23
35#define IMX6SLL_CLK_PLL1_SYS 24
36#define IMX6SLL_CLK_PLL2_BUS 25
37#define IMX6SLL_CLK_PLL3_USB_OTG 26
38#define IMX6SLL_CLK_PLL4_AUDIO 27
39#define IMX6SLL_CLK_PLL5_VIDEO 28
40#define IMX6SLL_CLK_PLL6_ENET 29
41#define IMX6SLL_CLK_PLL7_USB_HOST 30
42#define IMX6SLL_CLK_USBPHY1 31
43#define IMX6SLL_CLK_USBPHY2 32
44#define IMX6SLL_CLK_USBPHY1_GATE 33
45#define IMX6SLL_CLK_USBPHY2_GATE 34
46#define IMX6SLL_CLK_PLL2_PFD0 35
47#define IMX6SLL_CLK_PLL2_PFD1 36
48#define IMX6SLL_CLK_PLL2_PFD2 37
49#define IMX6SLL_CLK_PLL2_PFD3 38
50#define IMX6SLL_CLK_PLL3_PFD0 39
51#define IMX6SLL_CLK_PLL3_PFD1 40
52#define IMX6SLL_CLK_PLL3_PFD2 41
53#define IMX6SLL_CLK_PLL3_PFD3 42
54#define IMX6SLL_CLK_PLL4_POST_DIV 43
55#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44
56#define IMX6SLL_CLK_PLL5_POST_DIV 45
57#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46
58#define IMX6SLL_CLK_PLL2_198M 47
59#define IMX6SLL_CLK_PLL3_120M 48
60#define IMX6SLL_CLK_PLL3_80M 49
61#define IMX6SLL_CLK_PLL3_60M 50
62#define IMX6SLL_CLK_STEP 51
63#define IMX6SLL_CLK_PLL1_SW 52
64#define IMX6SLL_CLK_AXI_ALT_SEL 53
65#define IMX6SLL_CLK_AXI_SEL 54
66#define IMX6SLL_CLK_PERIPH_PRE 55
67#define IMX6SLL_CLK_PERIPH2_PRE 56
68#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57
69#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58
70#define IMX6SLL_CLK_PERCLK_SEL 59
71#define IMX6SLL_CLK_USDHC1_SEL 60
72#define IMX6SLL_CLK_USDHC2_SEL 61
73#define IMX6SLL_CLK_USDHC3_SEL 62
74#define IMX6SLL_CLK_SSI1_SEL 63
75#define IMX6SLL_CLK_SSI2_SEL 64
76#define IMX6SLL_CLK_SSI3_SEL 65
77#define IMX6SLL_CLK_PXP_SEL 66
78#define IMX6SLL_CLK_LCDIF_PRE_SEL 67
79#define IMX6SLL_CLK_LCDIF_SEL 68
80#define IMX6SLL_CLK_EPDC_PRE_SEL 69
81#define IMX6SLL_CLK_SPDIF_SEL 70
82#define IMX6SLL_CLK_ECSPI_SEL 71
83#define IMX6SLL_CLK_UART_SEL 72
84#define IMX6SLL_CLK_ARM 73
85#define IMX6SLL_CLK_PERIPH 74
86#define IMX6SLL_CLK_PERIPH2 75
87#define IMX6SLL_CLK_PERIPH2_CLK2 76
88#define IMX6SLL_CLK_PERIPH_CLK2 77
89#define IMX6SLL_CLK_MMDC_PODF 78
90#define IMX6SLL_CLK_AXI_PODF 79
91#define IMX6SLL_CLK_AHB 80
92#define IMX6SLL_CLK_IPG 81
93#define IMX6SLL_CLK_PERCLK 82
94#define IMX6SLL_CLK_USDHC1_PODF 83
95#define IMX6SLL_CLK_USDHC2_PODF 84
96#define IMX6SLL_CLK_USDHC3_PODF 85
97#define IMX6SLL_CLK_SSI1_PRED 86
98#define IMX6SLL_CLK_SSI2_PRED 87
99#define IMX6SLL_CLK_SSI3_PRED 88
100#define IMX6SLL_CLK_SSI1_PODF 89
101#define IMX6SLL_CLK_SSI2_PODF 90
102#define IMX6SLL_CLK_SSI3_PODF 91
103#define IMX6SLL_CLK_PXP_PODF 92
104#define IMX6SLL_CLK_LCDIF_PRED 93
105#define IMX6SLL_CLK_LCDIF_PODF 94
106#define IMX6SLL_CLK_EPDC_SEL 95
107#define IMX6SLL_CLK_EPDC_PODF 96
108#define IMX6SLL_CLK_SPDIF_PRED 97
109#define IMX6SLL_CLK_SPDIF_PODF 98
110#define IMX6SLL_CLK_ECSPI_PODF 99
111#define IMX6SLL_CLK_UART_PODF 100
112
113/* CCGR 0 */
114#define IMX6SLL_CLK_AIPSTZ1 101
115#define IMX6SLL_CLK_AIPSTZ2 102
116#define IMX6SLL_CLK_DCP 103
117#define IMX6SLL_CLK_UART2_IPG 104
118#define IMX6SLL_CLK_UART2_SERIAL 105
119
120/* CCGR 1 */
121#define IMX6SLL_CLK_ECSPI1 106
122#define IMX6SLL_CLK_ECSPI2 107
123#define IMX6SLL_CLK_ECSPI3 108
124#define IMX6SLL_CLK_ECSPI4 109
125#define IMX6SLL_CLK_UART3_IPG 110
126#define IMX6SLL_CLK_UART3_SERIAL 111
127#define IMX6SLL_CLK_UART4_IPG 112
128#define IMX6SLL_CLK_UART4_SERIAL 113
129#define IMX6SLL_CLK_EPIT1 114
130#define IMX6SLL_CLK_EPIT2 115
131#define IMX6SLL_CLK_GPT_BUS 116
132#define IMX6SLL_CLK_GPT_SERIAL 117
133
134/* CCGR2 */
135#define IMX6SLL_CLK_CSI 118
136#define IMX6SLL_CLK_I2C1 119
137#define IMX6SLL_CLK_I2C2 120
138#define IMX6SLL_CLK_I2C3 121
139#define IMX6SLL_CLK_OCOTP 122
140#define IMX6SLL_CLK_LCDIF_APB 123
141#define IMX6SLL_CLK_PXP 124
142
143/* CCGR3 */
144#define IMX6SLL_CLK_UART5_IPG 125
145#define IMX6SLL_CLK_UART5_SERIAL 126
146#define IMX6SLL_CLK_EPDC_AXI 127
147#define IMX6SLL_CLK_EPDC_PIX 128
148#define IMX6SLL_CLK_LCDIF_PIX 129
149#define IMX6SLL_CLK_WDOG1 130
150#define IMX6SLL_CLK_MMDC_P0_FAST 131
151#define IMX6SLL_CLK_MMDC_P0_IPG 132
152#define IMX6SLL_CLK_OCRAM 133
153
154/* CCGR4 */
155#define IMX6SLL_CLK_PWM1 134
156#define IMX6SLL_CLK_PWM2 135
157#define IMX6SLL_CLK_PWM3 136
158#define IMX6SLL_CLK_PWM4 137
159
160/* CCGR 5 */
161#define IMX6SLL_CLK_ROM 138
162#define IMX6SLL_CLK_SDMA 139
163#define IMX6SLL_CLK_KPP 140
164#define IMX6SLL_CLK_WDOG2 141
165#define IMX6SLL_CLK_SPBA 142
166#define IMX6SLL_CLK_SPDIF 143
167#define IMX6SLL_CLK_SPDIF_GCLK 144
168#define IMX6SLL_CLK_SSI1 145
169#define IMX6SLL_CLK_SSI1_IPG 146
170#define IMX6SLL_CLK_SSI2 147
171#define IMX6SLL_CLK_SSI2_IPG 148
172#define IMX6SLL_CLK_SSI3 149
173#define IMX6SLL_CLK_SSI3_IPG 150
174#define IMX6SLL_CLK_UART1_IPG 151
175#define IMX6SLL_CLK_UART1_SERIAL 152
176
177/* CCGR 6 */
178#define IMX6SLL_CLK_USBOH3 153
179#define IMX6SLL_CLK_USDHC1 154
180#define IMX6SLL_CLK_USDHC2 155
181#define IMX6SLL_CLK_USDHC3 156
182
183#define IMX6SLL_CLK_IPP_DI0 157
184#define IMX6SLL_CLK_IPP_DI1 158
185#define IMX6SLL_CLK_LDB_DI0_SEL 159
186#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160
187#define IMX6SLL_CLK_LDB_DI0_DIV_7 161
188#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162
189#define IMX6SLL_CLK_LDB_DI0 163
190#define IMX6SLL_CLK_LDB_DI1_SEL 164
191#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165
192#define IMX6SLL_CLK_LDB_DI1_DIV_7 166
193#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167
194#define IMX6SLL_CLK_LDB_DI1 168
195#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169
196#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170
197#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171
198#define IMX6SLL_CLK_EXTERN_AUDIO 172
199
200#define IMX6SLL_CLK_END 173
201
202#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
index e2f99ae72d5c..b2325d3e236a 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -452,5 +452,8 @@
452#define IMX7D_OCOTP_CLK 439 452#define IMX7D_OCOTP_CLK 439
453#define IMX7D_NAND_RAWNAND_CLK 440 453#define IMX7D_NAND_RAWNAND_CLK 440
454#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 454#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
455#define IMX7D_CLK_END 442 455#define IMX7D_SNVS_CLK 442
456#define IMX7D_CAAM_CLK 443
457#define IMX7D_KPP_ROOT_CLK 444
458#define IMX7D_CLK_END 445
456#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ 459#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/include/dt-bindings/clock/stratix10-clock.h b/include/dt-bindings/clock/stratix10-clock.h
new file mode 100644
index 000000000000..0ac1c90a18bf
--- /dev/null
+++ b/include/dt-bindings/clock/stratix10-clock.h
@@ -0,0 +1,84 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2017, Intel Corporation
4 */
5
6#ifndef __STRATIX10_CLOCK_H
7#define __STRATIX10_CLOCK_H
8
9/* fixed rate clocks */
10#define STRATIX10_OSC1 0
11#define STRATIX10_CB_INTOSC_HS_DIV2_CLK 1
12#define STRATIX10_CB_INTOSC_LS_CLK 2
13#define STRATIX10_F2S_FREE_CLK 3
14
15/* fixed factor clocks */
16#define STRATIX10_L4_SYS_FREE_CLK 4
17#define STRATIX10_MPU_PERIPH_CLK 5
18#define STRATIX10_MPU_L2RAM_CLK 6
19#define STRATIX10_SDMMC_CIU_CLK 7
20
21/* PLL clocks */
22#define STRATIX10_MAIN_PLL_CLK 8
23#define STRATIX10_PERIPH_PLL_CLK 9
24#define STRATIX10_BOOT_CLK 10
25
26/* Periph clocks */
27#define STRATIX10_MAIN_MPU_BASE_CLK 11
28#define STRATIX10_MAIN_NOC_BASE_CLK 12
29#define STRATIX10_MAIN_EMACA_CLK 13
30#define STRATIX10_MAIN_EMACB_CLK 14
31#define STRATIX10_MAIN_EMAC_PTP_CLK 15
32#define STRATIX10_MAIN_GPIO_DB_CLK 16
33#define STRATIX10_MAIN_SDMMC_CLK 17
34#define STRATIX10_MAIN_S2F_USR0_CLK 18
35#define STRATIX10_MAIN_S2F_USR1_CLK 19
36#define STRATIX10_MAIN_PSI_REF_CLK 20
37
38#define STRATIX10_PERI_MPU_BASE_CLK 21
39#define STRATIX10_PERI_NOC_BASE_CLK 22
40#define STRATIX10_PERI_EMACA_CLK 23
41#define STRATIX10_PERI_EMACB_CLK 24
42#define STRATIX10_PERI_EMAC_PTP_CLK 25
43#define STRATIX10_PERI_GPIO_DB_CLK 26
44#define STRATIX10_PERI_SDMMC_CLK 27
45#define STRATIX10_PERI_S2F_USR0_CLK 28
46#define STRATIX10_PERI_S2F_USR1_CLK 29
47#define STRATIX10_PERI_PSI_REF_CLK 30
48
49#define STRATIX10_MPU_FREE_CLK 31
50#define STRATIX10_NOC_FREE_CLK 32
51#define STRATIX10_S2F_USR0_CLK 33
52#define STRATIX10_NOC_CLK 34
53#define STRATIX10_EMAC_A_FREE_CLK 35
54#define STRATIX10_EMAC_B_FREE_CLK 36
55#define STRATIX10_EMAC_PTP_FREE_CLK 37
56#define STRATIX10_GPIO_DB_FREE_CLK 38
57#define STRATIX10_SDMMC_FREE_CLK 39
58#define STRATIX10_S2F_USER1_FREE_CLK 40
59#define STRATIX10_PSI_REF_FREE_CLK 41
60
61/* Gate clocks */
62#define STRATIX10_MPU_CLK 42
63#define STRATIX10_L4_MAIN_CLK 43
64#define STRATIX10_L4_MP_CLK 44
65#define STRATIX10_L4_SP_CLK 45
66#define STRATIX10_CS_AT_CLK 46
67#define STRATIX10_CS_TRACE_CLK 47
68#define STRATIX10_CS_PDBG_CLK 48
69#define STRATIX10_CS_TIMER_CLK 49
70#define STRATIX10_S2F_USER0_CLK 50
71#define STRATIX10_S2F_USER1_CLK 51
72#define STRATIX10_EMAC0_CLK 52
73#define STRATIX10_EMAC1_CLK 53
74#define STRATIX10_EMAC2_CLK 54
75#define STRATIX10_EMAC_PTP_CLK 55
76#define STRATIX10_GPIO_DB_CLK 56
77#define STRATIX10_SDMMC_CLK 57
78#define STRATIX10_PSI_REF_CLK 58
79#define STRATIX10_USB_CLK 59
80#define STRATIX10_SPI_M_CLK 60
81#define STRATIX10_NAND_CLK 61
82#define STRATIX10_NUM_CLKS 62
83
84#endif /* __STRATIX10_CLOCK_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-31 04:33:30 -0500