diff options
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 24 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra186.dtsi | 214 |
2 files changed, 238 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 8daadadec63a..d45356fa1751 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | |||
| @@ -49,6 +49,30 @@ | |||
| 49 | vmmc-supply = <&vdd_sd>; | 49 | vmmc-supply = <&vdd_sd>; |
| 50 | }; | 50 | }; |
| 51 | 51 | ||
| 52 | pcie@10003000 { | ||
| 53 | status = "okay"; | ||
| 54 | |||
| 55 | dvdd-pex-supply = <&vdd_pex>; | ||
| 56 | hvdd-pex-pll-supply = <&vdd_1v8>; | ||
| 57 | hvdd-pex-supply = <&vdd_1v8>; | ||
| 58 | vddio-pexctl-aud-supply = <&vdd_1v8>; | ||
| 59 | |||
| 60 | pci@1,0 { | ||
| 61 | nvidia,num-lanes = <4>; | ||
| 62 | status = "okay"; | ||
| 63 | }; | ||
| 64 | |||
| 65 | pci@2,0 { | ||
| 66 | nvidia,num-lanes = <0>; | ||
| 67 | status = "disabled"; | ||
| 68 | }; | ||
| 69 | |||
| 70 | pci@3,0 { | ||
| 71 | nvidia,num-lanes = <1>; | ||
| 72 | status = "disabled"; | ||
| 73 | }; | ||
| 74 | }; | ||
| 75 | |||
| 52 | gpio-keys { | 76 | gpio-keys { |
| 53 | compatible = "gpio-keys"; | 77 | compatible = "gpio-keys"; |
| 54 | 78 | ||
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 0b0552c9f7dd..0693dadadcb8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi | |||
| @@ -4,6 +4,7 @@ | |||
| 4 | #include <dt-bindings/mailbox/tegra186-hsp.h> | 4 | #include <dt-bindings/mailbox/tegra186-hsp.h> |
| 5 | #include <dt-bindings/power/tegra186-powergate.h> | 5 | #include <dt-bindings/power/tegra186-powergate.h> |
| 6 | #include <dt-bindings/reset/tegra186-reset.h> | 6 | #include <dt-bindings/reset/tegra186-reset.h> |
| 7 | #include <dt-bindings/thermal/tegra186-bpmp-thermal.h> | ||
| 7 | 8 | ||
| 8 | / { | 9 | / { |
| 9 | compatible = "nvidia,tegra186"; | 10 | compatible = "nvidia,tegra186"; |
| @@ -355,6 +356,116 @@ | |||
| 355 | nvidia,bpmp = <&bpmp>; | 356 | nvidia,bpmp = <&bpmp>; |
| 356 | }; | 357 | }; |
| 357 | 358 | ||
| 359 | pcie@10003000 { | ||
| 360 | compatible = "nvidia,tegra186-pcie"; | ||
| 361 | power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; | ||
| 362 | device_type = "pci"; | ||
| 363 | reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ | ||
| 364 | 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ | ||
| 365 | 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ | ||
| 366 | reg-names = "pads", "afi", "cs"; | ||
| 367 | |||
| 368 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ | ||
| 369 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ | ||
| 370 | interrupt-names = "intr", "msi"; | ||
| 371 | |||
| 372 | #interrupt-cells = <1>; | ||
| 373 | interrupt-map-mask = <0 0 0 0>; | ||
| 374 | interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | ||
| 375 | |||
| 376 | bus-range = <0x00 0xff>; | ||
| 377 | #address-cells = <3>; | ||
| 378 | #size-cells = <2>; | ||
| 379 | |||
| 380 | ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ | ||
| 381 | 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ | ||
| 382 | 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ | ||
| 383 | 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ | ||
| 384 | 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ | ||
| 385 | 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ | ||
| 386 | |||
| 387 | clocks = <&bpmp TEGRA186_CLK_AFI>, | ||
| 388 | <&bpmp TEGRA186_CLK_PCIE>, | ||
| 389 | <&bpmp TEGRA186_CLK_PLLE>; | ||
| 390 | clock-names = "afi", "pex", "pll_e"; | ||
| 391 | |||
| 392 | resets = <&bpmp TEGRA186_RESET_AFI>, | ||
| 393 | <&bpmp TEGRA186_RESET_PCIE>, | ||
| 394 | <&bpmp TEGRA186_RESET_PCIEXCLK>; | ||
| 395 | reset-names = "afi", "pex", "pcie_x"; | ||
| 396 | |||
| 397 | status = "disabled"; | ||
| 398 | |||
| 399 | pci@1,0 { | ||
| 400 | device_type = "pci"; | ||
| 401 | assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; | ||
| 402 | reg = <0x000800 0 0 0 0>; | ||
| 403 | status = "disabled"; | ||
| 404 | |||
| 405 | #address-cells = <3>; | ||
| 406 | #size-cells = <2>; | ||
| 407 | ranges; | ||
| 408 | |||
| 409 | nvidia,num-lanes = <2>; | ||
| 410 | }; | ||
| 411 | |||
| 412 | pci@2,0 { | ||
| 413 | device_type = "pci"; | ||
| 414 | assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; | ||
| 415 | reg = <0x001000 0 0 0 0>; | ||
| 416 | status = "disabled"; | ||
| 417 | |||
| 418 | #address-cells = <3>; | ||
| 419 | #size-cells = <2>; | ||
| 420 | ranges; | ||
| 421 | |||
| 422 | nvidia,num-lanes = <1>; | ||
| 423 | }; | ||
| 424 | |||
| 425 | pci@3,0 { | ||
| 426 | device_type = "pci"; | ||
| 427 | assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; | ||
| 428 | reg = <0x001800 0 0 0 0>; | ||
| 429 | status = "disabled"; | ||
| 430 | |||
| 431 | #address-cells = <3>; | ||
| 432 | #size-cells = <2>; | ||
| 433 | ranges; | ||
| 434 | |||
| 435 | nvidia,num-lanes = <1>; | ||
| 436 | }; | ||
| 437 | }; | ||
| 438 | |||
| 439 | host1x@13e00000 { | ||
| 440 | compatible = "nvidia,tegra186-host1x", "simple-bus"; | ||
| 441 | reg = <0x0 0x13e00000 0x0 0x10000>, | ||
| 442 | <0x0 0x13e10000 0x0 0x10000>; | ||
| 443 | reg-names = "hypervisor", "vm"; | ||
| 444 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, | ||
| 445 | <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; | ||
| 446 | clocks = <&bpmp TEGRA186_CLK_HOST1X>; | ||
| 447 | clock-names = "host1x"; | ||
| 448 | resets = <&bpmp TEGRA186_RESET_HOST1X>; | ||
| 449 | reset-names = "host1x"; | ||
| 450 | |||
| 451 | #address-cells = <1>; | ||
| 452 | #size-cells = <1>; | ||
| 453 | |||
| 454 | ranges = <0x15000000 0x0 0x15000000 0x01000000>; | ||
| 455 | |||
| 456 | vic@15340000 { | ||
| 457 | compatible = "nvidia,tegra186-vic"; | ||
| 458 | reg = <0x15340000 0x40000>; | ||
| 459 | interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; | ||
| 460 | clocks = <&bpmp TEGRA186_CLK_VIC>; | ||
| 461 | clock-names = "vic"; | ||
| 462 | resets = <&bpmp TEGRA186_RESET_VIC>; | ||
| 463 | reset-names = "vic"; | ||
| 464 | |||
| 465 | power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; | ||
| 466 | }; | ||
| 467 | }; | ||
| 468 | |||
| 358 | gpu@17000000 { | 469 | gpu@17000000 { |
| 359 | compatible = "nvidia,gp10b"; | 470 | compatible = "nvidia,gp10b"; |
| 360 | reg = <0x0 0x17000000 0x0 0x1000000>, | 471 | reg = <0x0 0x17000000 0x0 0x1000000>, |
| @@ -443,6 +554,7 @@ | |||
| 443 | shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; | 554 | shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; |
| 444 | #clock-cells = <1>; | 555 | #clock-cells = <1>; |
| 445 | #reset-cells = <1>; | 556 | #reset-cells = <1>; |
| 557 | #power-domain-cells = <1>; | ||
| 446 | 558 | ||
| 447 | bpmp_i2c: i2c { | 559 | bpmp_i2c: i2c { |
| 448 | compatible = "nvidia,tegra186-bpmp-i2c"; | 560 | compatible = "nvidia,tegra186-bpmp-i2c"; |
| @@ -451,6 +563,108 @@ | |||
| 451 | #size-cells = <0>; | 563 | #size-cells = <0>; |
| 452 | status = "disabled"; | 564 | status = "disabled"; |
| 453 | }; | 565 | }; |
| 566 | |||
| 567 | bpmp_thermal: thermal { | ||
| 568 | compatible = "nvidia,tegra186-bpmp-thermal"; | ||
| 569 | #thermal-sensor-cells = <1>; | ||
| 570 | }; | ||
| 571 | }; | ||
| 572 | |||
| 573 | thermal-zones { | ||
| 574 | a57 { | ||
| 575 | polling-delay = <0>; | ||
| 576 | polling-delay-passive = <1000>; | ||
| 577 | |||
| 578 | thermal-sensors = | ||
| 579 | <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; | ||
| 580 | |||
| 581 | trips { | ||
| 582 | critical { | ||
| 583 | temperature = <101000>; | ||
| 584 | hysteresis = <0>; | ||
| 585 | type = "critical"; | ||
| 586 | }; | ||
| 587 | }; | ||
| 588 | |||
| 589 | cooling-maps { | ||
| 590 | }; | ||
| 591 | }; | ||
| 592 | |||
| 593 | denver { | ||
| 594 | polling-delay = <0>; | ||
| 595 | polling-delay-passive = <1000>; | ||
| 596 | |||
| 597 | thermal-sensors = | ||
| 598 | <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; | ||
| 599 | |||
| 600 | trips { | ||
| 601 | critical { | ||
| 602 | temperature = <101000>; | ||
| 603 | hysteresis = <0>; | ||
| 604 | type = "critical"; | ||
| 605 | }; | ||
| 606 | }; | ||
| 607 | |||
| 608 | cooling-maps { | ||
| 609 | }; | ||
| 610 | }; | ||
| 611 | |||
| 612 | gpu { | ||
| 613 | polling-delay = <0>; | ||
| 614 | polling-delay-passive = <1000>; | ||
| 615 | |||
| 616 | thermal-sensors = | ||
| 617 | <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; | ||
| 618 | |||
| 619 | trips { | ||
| 620 | critical { | ||
| 621 | temperature = <101000>; | ||
| 622 | hysteresis = <0>; | ||
| 623 | type = "critical"; | ||
| 624 | }; | ||
| 625 | }; | ||
| 626 | |||
| 627 | cooling-maps { | ||
| 628 | }; | ||
| 629 | }; | ||
| 630 | |||
| 631 | pll { | ||
| 632 | polling-delay = <0>; | ||
| 633 | polling-delay-passive = <1000>; | ||
| 634 | |||
| 635 | thermal-sensors = | ||
| 636 | <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; | ||
| 637 | |||
| 638 | trips { | ||
| 639 | critical { | ||
| 640 | temperature = <101000>; | ||
| 641 | hysteresis = <0>; | ||
| 642 | type = "critical"; | ||
| 643 | }; | ||
| 644 | }; | ||
| 645 | |||
| 646 | cooling-maps { | ||
| 647 | }; | ||
| 648 | }; | ||
| 649 | |||
| 650 | always_on { | ||
| 651 | polling-delay = <0>; | ||
| 652 | polling-delay-passive = <1000>; | ||
| 653 | |||
| 654 | thermal-sensors = | ||
| 655 | <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; | ||
| 656 | |||
| 657 | trips { | ||
| 658 | critical { | ||
| 659 | temperature = <101000>; | ||
| 660 | hysteresis = <0>; | ||
| 661 | type = "critical"; | ||
| 662 | }; | ||
| 663 | }; | ||
| 664 | |||
| 665 | cooling-maps { | ||
| 666 | }; | ||
| 667 | }; | ||
| 454 | }; | 668 | }; |
| 455 | 669 | ||
| 456 | timer { | 670 | timer { |
