1 files changed, 31 insertions, 17 deletions

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 7aa11b1fbee3..9493b97436c3 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -126,6 +126,9 @@ static int __init pcie_port_pm_setup(char *str)
 }
 __setup("pcie_port_pm=", pcie_port_pm_setup);
 
+/* Time to wait after a reset for device to become responsive */
+#define PCIE_RESET_READY_POLL_MS 60000
+
 /**
  * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
  * @bus: pointer to PCI bus structure to search
@@ -4017,20 +4020,13 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev)
 }
 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
 
-static int pci_flr_wait(struct pci_dev *dev)
+static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
 {
-        int delay = 1, timeout = 60000;
+        int delay = 1;
         u32 id;
 
         /*
-         * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within
-         * 100ms, but may silently discard requests while the FLR is in
-         * progress.  Wait 100ms before trying to access the device.
-         */
-        msleep(100);
-
-        /*
-         * After 100ms, the device should not silently discard config
+         * After reset, the device should not silently discard config
          * requests, but it may still indicate that it needs more time by
          * responding to them with CRS completions.  The Root Port will
          * generally synthesize ~0 data to complete the read (except when
@@ -4044,14 +4040,14 @@ static int pci_flr_wait(struct pci_dev *dev)
         pci_read_config_dword(dev, PCI_COMMAND, &id);
         while (id == ~0) {
                 if (delay > timeout) {
-                        pci_warn(dev, "not ready %dms after FLR; giving up\n",
-                                 100 + delay - 1);
+                        pci_warn(dev, "not ready %dms after %s; giving up\n",
+                                 delay - 1, reset_type);
                         return -ENOTTY;
                 }
 
                 if (delay > 1000)
-                        pci_info(dev, "not ready %dms after FLR; waiting\n",
-                                 100 + delay - 1);
+                        pci_info(dev, "not ready %dms after %s; waiting\n",
+                                 delay - 1, reset_type);
 
                 msleep(delay);
                 delay *= 2;
@@ -4059,7 +4055,8 @@ static int pci_flr_wait(struct pci_dev *dev)
         }
 
         if (delay > 1000)
-                pci_info(dev, "ready %dms after FLR\n", 100 + delay - 1);
+                pci_info(dev, "ready %dms after %s\n", delay - 1,
+                         reset_type);
 
         return 0;
 }
@@ -4096,7 +4093,15 @@ int pcie_flr(struct pci_dev *dev)
                 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
 
         pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
-        return pci_flr_wait(dev);
+
+        /*
+         * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
+         * 100ms, but may silently discard requests while the FLR is in
+         * progress.  Wait 100ms before trying to access the device.
+         */
+        msleep(100);
+
+        return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
 }
 EXPORT_SYMBOL_GPL(pcie_flr);
 
@@ -4129,7 +4134,16 @@ static int pci_af_flr(struct pci_dev *dev, int probe)
                 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
 
         pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
-        return pci_flr_wait(dev);
+
+        /*
+         * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
+         * updated 27 July 2006; a device must complete an FLR within
+         * 100ms, but may silently discard requests while the FLR is in
+         * progress.  Wait 100ms before trying to access the device.
+         */
+        msleep(100);
+
+        return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
 }
 
 /**