5 files changed, 28 insertions, 14 deletions
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index fb00a2fca990..5701f5cecd31 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -282,7 +282,9 @@
 #define X86_FEATURE_AMD_IBPB            (13*32+12) /* "" Indirect Branch Prediction Barrier */
 #define X86_FEATURE_AMD_IBRS            (13*32+14) /* "" Indirect Branch Restricted Speculation */
 #define X86_FEATURE_AMD_STIBP           (13*32+15) /* "" Single Thread Indirect Branch Predictors */
+#define X86_FEATURE_AMD_SSBD            (13*32+24) /* "" Speculative Store Bypass Disable */
 #define X86_FEATURE_VIRT_SSBD           (13*32+25) /* Virtualized Speculative Store Bypass Disable */
+#define X86_FEATURE_AMD_SSB_NO          (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
 #define X86_FEATURE_DTHERM              (14*32+ 0) /* Digital Thermal Sensor */
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 7416fc206b4a..cd0fda1fff6d 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -529,18 +529,15 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
        if (mode == SPEC_STORE_BYPASS_DISABLE) {
                setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
                /*
-                 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
+                 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
-                 * a completely different MSR and bit dependent on family.
+                 * use a completely different MSR and bit dependent on family.
                 */
-                switch (boot_cpu_data.x86_vendor) {
+                if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
-                case X86_VENDOR_INTEL:
+                        x86_amd_ssb_disable();
+                else {
                        x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
                        x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
                        wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
-                        break;
-                case X86_VENDOR_AMD:
-                        x86_amd_ssb_disable();
-                        break;
                }
        }
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 95c8e507580d..910b47ee8078 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -803,6 +803,12 @@ static void init_speculation_control(struct cpuinfo_x86 *c)
                set_cpu_cap(c, X86_FEATURE_STIBP);
                set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
        }
+        if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
+                set_cpu_cap(c, X86_FEATURE_SSBD);
+                set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
+                clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
+        }
 }
 void get_cpu_cap(struct cpuinfo_x86 *c)
@@ -992,7 +998,8 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
                rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
        if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
-           !(ia32_cap & ARCH_CAP_SSB_NO))
+           !(ia32_cap & ARCH_CAP_SSB_NO) &&
+           !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
                setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
        if (x86_match_cpu(cpu_no_meltdown))
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 92bf2f2e7cdd..f4f30d0c25c4 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -379,7 +379,8 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
        /* cpuid 0x80000008.ebx */
        const u32 kvm_cpuid_8000_0008_ebx_x86_features =
-                F(AMD_IBPB) | F(AMD_IBRS) | F(VIRT_SSBD);
+                F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
+                F(AMD_SSB_NO);
        /* cpuid 0xC0000001.edx */
        const u32 kvm_cpuid_C000_0001_edx_x86_features =
@@ -664,7 +665,12 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
                        entry->ebx |= F(VIRT_SSBD);
                entry->ebx &= kvm_cpuid_8000_0008_ebx_x86_features;
                cpuid_mask(&entry->ebx, CPUID_8000_0008_EBX);
-                if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
+                /*
+                 * The preference is to use SPEC CTRL MSR instead of the
+                 * VIRT_SPEC MSR.
+                 */
+                if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
+                    !boot_cpu_has(X86_FEATURE_AMD_SSBD))
                        entry->ebx |= F(VIRT_SSBD);
                break;
        }
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 26110c202b19..950ec50f77c3 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -4115,7 +4115,8 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                break;
        case MSR_IA32_SPEC_CTRL:
                if (!msr_info->host_initiated &&
-                    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
+                    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
+                    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
                        return 1;
                msr_info->data = svm->spec_ctrl;
@@ -4217,11 +4218,12 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
                break;
        case MSR_IA32_SPEC_CTRL:
                if (!msr->host_initiated &&
-                    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
+                    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
+                    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
                        return 1;
                /* The STIBP bit doesn't fault even if it's not advertised */
-                if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP))
+                if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
                        return 1;
                svm->spec_ctrl = data;