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-rw-r--r--arch/arm/mach-rockchip/pm.c11
-rw-r--r--arch/arm/mach-rockchip/pm.h2
2 files changed, 10 insertions, 3 deletions
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
index a3ab3979923c..b07d88602073 100644
--- a/arch/arm/mach-rockchip/pm.c
+++ b/arch/arm/mach-rockchip/pm.c
@@ -75,9 +75,13 @@ static void rk3288_slp_mode_set(int level)
75 regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON, 75 regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
76 &rk3288_pmu_pwr_mode_con); 76 &rk3288_pmu_pwr_mode_con);
77 77
78 /* set bit 8 so that system will resume to FAST_BOOT_ADDR */ 78 /*
79 * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR
80 * PCLK_WDT_GATE - disable WDT during suspend.
81 */
79 regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, 82 regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
80 SGRF_FAST_BOOT_EN | SGRF_FAST_BOOT_EN_WRITE); 83 SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN
84 | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE);
81 85
82 /* booting address of resuming system is from this register value */ 86 /* booting address of resuming system is from this register value */
83 regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR, 87 regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
@@ -122,7 +126,8 @@ static void rk3288_slp_mode_set_resume(void)
122 rk3288_pmu_pwr_mode_con); 126 rk3288_pmu_pwr_mode_con);
123 127
124 regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, 128 regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
125 rk3288_sgrf_soc_con0 | SGRF_FAST_BOOT_EN_WRITE); 129 rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE
130 | SGRF_FAST_BOOT_EN_WRITE);
126} 131}
127 132
128static int rockchip_lpmode_enter(unsigned long arg) 133static int rockchip_lpmode_enter(unsigned long arg)
diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h
index 91a542df5791..03ff31d8282d 100644
--- a/arch/arm/mach-rockchip/pm.h
+++ b/arch/arm/mach-rockchip/pm.h
@@ -50,6 +50,8 @@ static inline void rockchip_suspend_init(void)
50 50
51#define RK3288_SGRF_SOC_CON0 (0x0000) 51#define RK3288_SGRF_SOC_CON0 (0x0000)
52#define RK3288_SGRF_FAST_BOOT_ADDR (0x0120) 52#define RK3288_SGRF_FAST_BOOT_ADDR (0x0120)
53#define SGRF_PCLK_WDT_GATE BIT(6)
54#define SGRF_PCLK_WDT_GATE_WRITE BIT(22)
53#define SGRF_FAST_BOOT_EN BIT(8) 55#define SGRF_FAST_BOOT_EN BIT(8)
54#define SGRF_FAST_BOOT_EN_WRITE BIT(24) 56#define SGRF_FAST_BOOT_EN_WRITE BIT(24)
55 57