diff options
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index 0202841ae639..1d988ef1978e 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | |||
@@ -4650,20 +4650,26 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr, | |||
4650 | if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO) | 4650 | if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO) |
4651 | return -EINVAL; | 4651 | return -EINVAL; |
4652 | 4652 | ||
4653 | tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr); | 4653 | if (smum_is_dpm_running(hwmgr)) { |
4654 | PP_ASSERT_WITH_CODE(!tmp_result, | 4654 | if (!data->sclk_dpm_key_disabled) |
4655 | "Failed to freeze SCLK MCLK DPM!", | 4655 | smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel); |
4656 | result = tmp_result); | 4656 | |
4657 | if (!data->mclk_dpm_key_disabled) | ||
4658 | smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel); | ||
4659 | } | ||
4657 | 4660 | ||
4658 | tmp_result = smum_populate_requested_graphic_levels(hwmgr, request); | 4661 | tmp_result = smum_populate_requested_graphic_levels(hwmgr, request); |
4659 | PP_ASSERT_WITH_CODE(!tmp_result, | 4662 | PP_ASSERT_WITH_CODE(!tmp_result, |
4660 | "Failed to populate requested graphic levels!", | 4663 | "Failed to populate requested graphic levels!", |
4661 | result = tmp_result); | 4664 | result = tmp_result); |
4662 | 4665 | ||
4663 | tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr); | 4666 | if (smum_is_dpm_running(hwmgr)) { |
4664 | PP_ASSERT_WITH_CODE(!tmp_result, | 4667 | if (!data->sclk_dpm_key_disabled) |
4665 | "Failed to unfreeze SCLK MCLK DPM!", | 4668 | smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel); |
4666 | result = tmp_result); | 4669 | |
4670 | if (!data->mclk_dpm_key_disabled) | ||
4671 | smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel); | ||
4672 | } | ||
4667 | 4673 | ||
4668 | smu7_find_min_clock_masks(hwmgr, &sclk_mask, &mclk_mask, | 4674 | smu7_find_min_clock_masks(hwmgr, &sclk_mask, &mclk_mask, |
4669 | request->min_sclk, request->min_mclk); | 4675 | request->min_sclk, request->min_mclk); |