1 files changed, 7 insertions, 14 deletions

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 3d627f94a166..ea2617712a3b 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -89,9 +89,8 @@ struct imx6_pcie {
 };
 
 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
-#define PHY_PLL_LOCK_WAIT_MAX_RETRIES   2000
-#define PHY_PLL_LOCK_WAIT_USLEEP_MIN    50
 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX    200
+#define PHY_PLL_LOCK_WAIT_TIMEOUT       (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX)
 
 /* PCIe Root Complex registers (memory-mapped) */
 #define PCIE_RC_IMX6_MSI_CAP                    0x50
@@ -488,20 +487,14 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
 {
         u32 val;
-        unsigned int retries;
         struct device *dev = imx6_pcie->pci->dev;
 
-        for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES; retries++) {
-                regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR22, &val);
-
-                if (val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED)
-                        return;
-
-                usleep_range(PHY_PLL_LOCK_WAIT_USLEEP_MIN,
-                             PHY_PLL_LOCK_WAIT_USLEEP_MAX);
-        }
-
-        dev_err(dev, "PCIe PLL lock timeout\n");
+        if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
+                                     IOMUXC_GPR22, val,
+                                     val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
+                                     PHY_PLL_LOCK_WAIT_USLEEP_MAX,
+                                     PHY_PLL_LOCK_WAIT_TIMEOUT))
+                dev_err(dev, "PCIe PLL lock timeout\n");
 }
 
 static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)