diff options
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c69a5b844f5a..40a8f59fa418 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
| @@ -11130,7 +11130,7 @@ intel_display_capture_error_state(struct drm_device *dev) | |||
| 11130 | if (INTEL_INFO(dev)->num_pipes == 0) | 11130 | if (INTEL_INFO(dev)->num_pipes == 0) |
| 11131 | return NULL; | 11131 | return NULL; |
| 11132 | 11132 | ||
| 11133 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | 11133 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
| 11134 | if (error == NULL) | 11134 | if (error == NULL) |
| 11135 | return NULL; | 11135 | return NULL; |
| 11136 | 11136 | ||
| @@ -11138,6 +11138,9 @@ intel_display_capture_error_state(struct drm_device *dev) | |||
| 11138 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); | 11138 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
| 11139 | 11139 | ||
| 11140 | for_each_pipe(i) { | 11140 | for_each_pipe(i) { |
| 11141 | if (!intel_display_power_enabled(dev, POWER_DOMAIN_PIPE(i))) | ||
| 11142 | continue; | ||
| 11143 | |||
| 11141 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { | 11144 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
| 11142 | error->cursor[i].control = I915_READ(CURCNTR(i)); | 11145 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
| 11143 | error->cursor[i].position = I915_READ(CURPOS(i)); | 11146 | error->cursor[i].position = I915_READ(CURPOS(i)); |
| @@ -11171,6 +11174,10 @@ intel_display_capture_error_state(struct drm_device *dev) | |||
| 11171 | for (i = 0; i < error->num_transcoders; i++) { | 11174 | for (i = 0; i < error->num_transcoders; i++) { |
| 11172 | enum transcoder cpu_transcoder = transcoders[i]; | 11175 | enum transcoder cpu_transcoder = transcoders[i]; |
| 11173 | 11176 | ||
| 11177 | if (!intel_display_power_enabled(dev, | ||
| 11178 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) | ||
| 11179 | continue; | ||
| 11180 | |||
| 11174 | error->transcoder[i].cpu_transcoder = cpu_transcoder; | 11181 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
| 11175 | 11182 | ||
| 11176 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | 11183 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
| @@ -11182,12 +11189,6 @@ intel_display_capture_error_state(struct drm_device *dev) | |||
| 11182 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | 11189 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); |
| 11183 | } | 11190 | } |
| 11184 | 11191 | ||
| 11185 | /* In the code above we read the registers without checking if the power | ||
| 11186 | * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to | ||
| 11187 | * prevent the next I915_WRITE from detecting it and printing an error | ||
| 11188 | * message. */ | ||
| 11189 | intel_uncore_clear_errors(dev); | ||
| 11190 | |||
| 11191 | return error; | 11192 | return error; |
| 11192 | } | 11193 | } |
| 11193 | 11194 | ||
