diff options
-rw-r--r-- | arch/powerpc/sysdev/xive/native.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c index 311185b9960a..39ab5ad58297 100644 --- a/arch/powerpc/sysdev/xive/native.c +++ b/arch/powerpc/sysdev/xive/native.c | |||
@@ -109,7 +109,7 @@ int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) | |||
109 | rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq); | 109 | rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq); |
110 | if (rc != OPAL_BUSY) | 110 | if (rc != OPAL_BUSY) |
111 | break; | 111 | break; |
112 | msleep(1); | 112 | msleep(OPAL_BUSY_DELAY_MS); |
113 | } | 113 | } |
114 | return rc == 0 ? 0 : -ENXIO; | 114 | return rc == 0 ? 0 : -ENXIO; |
115 | } | 115 | } |
@@ -163,7 +163,7 @@ int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, | |||
163 | rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags); | 163 | rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags); |
164 | if (rc != OPAL_BUSY) | 164 | if (rc != OPAL_BUSY) |
165 | break; | 165 | break; |
166 | msleep(1); | 166 | msleep(OPAL_BUSY_DELAY_MS); |
167 | } | 167 | } |
168 | if (rc) { | 168 | if (rc) { |
169 | pr_err("Error %lld setting queue for prio %d\n", rc, prio); | 169 | pr_err("Error %lld setting queue for prio %d\n", rc, prio); |
@@ -190,7 +190,7 @@ static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) | |||
190 | rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0); | 190 | rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0); |
191 | if (rc != OPAL_BUSY) | 191 | if (rc != OPAL_BUSY) |
192 | break; | 192 | break; |
193 | msleep(1); | 193 | msleep(OPAL_BUSY_DELAY_MS); |
194 | } | 194 | } |
195 | if (rc) | 195 | if (rc) |
196 | pr_err("Error %lld disabling queue for prio %d\n", rc, prio); | 196 | pr_err("Error %lld disabling queue for prio %d\n", rc, prio); |
@@ -253,7 +253,7 @@ static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc) | |||
253 | for (;;) { | 253 | for (;;) { |
254 | irq = opal_xive_allocate_irq(chip_id); | 254 | irq = opal_xive_allocate_irq(chip_id); |
255 | if (irq == OPAL_BUSY) { | 255 | if (irq == OPAL_BUSY) { |
256 | msleep(1); | 256 | msleep(OPAL_BUSY_DELAY_MS); |
257 | continue; | 257 | continue; |
258 | } | 258 | } |
259 | if (irq < 0) { | 259 | if (irq < 0) { |
@@ -275,7 +275,7 @@ u32 xive_native_alloc_irq(void) | |||
275 | rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP); | 275 | rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP); |
276 | if (rc != OPAL_BUSY) | 276 | if (rc != OPAL_BUSY) |
277 | break; | 277 | break; |
278 | msleep(1); | 278 | msleep(OPAL_BUSY_DELAY_MS); |
279 | } | 279 | } |
280 | if (rc < 0) | 280 | if (rc < 0) |
281 | return 0; | 281 | return 0; |
@@ -289,7 +289,7 @@ void xive_native_free_irq(u32 irq) | |||
289 | s64 rc = opal_xive_free_irq(irq); | 289 | s64 rc = opal_xive_free_irq(irq); |
290 | if (rc != OPAL_BUSY) | 290 | if (rc != OPAL_BUSY) |
291 | break; | 291 | break; |
292 | msleep(1); | 292 | msleep(OPAL_BUSY_DELAY_MS); |
293 | } | 293 | } |
294 | } | 294 | } |
295 | EXPORT_SYMBOL_GPL(xive_native_free_irq); | 295 | EXPORT_SYMBOL_GPL(xive_native_free_irq); |
@@ -305,7 +305,7 @@ static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc) | |||
305 | for (;;) { | 305 | for (;;) { |
306 | rc = opal_xive_free_irq(xc->hw_ipi); | 306 | rc = opal_xive_free_irq(xc->hw_ipi); |
307 | if (rc == OPAL_BUSY) { | 307 | if (rc == OPAL_BUSY) { |
308 | msleep(1); | 308 | msleep(OPAL_BUSY_DELAY_MS); |
309 | continue; | 309 | continue; |
310 | } | 310 | } |
311 | xc->hw_ipi = 0; | 311 | xc->hw_ipi = 0; |
@@ -400,7 +400,7 @@ static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc) | |||
400 | rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0); | 400 | rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0); |
401 | if (rc != OPAL_BUSY) | 401 | if (rc != OPAL_BUSY) |
402 | break; | 402 | break; |
403 | msleep(1); | 403 | msleep(OPAL_BUSY_DELAY_MS); |
404 | } | 404 | } |
405 | if (rc) { | 405 | if (rc) { |
406 | pr_err("Failed to enable pool VP on CPU %d\n", cpu); | 406 | pr_err("Failed to enable pool VP on CPU %d\n", cpu); |
@@ -444,7 +444,7 @@ static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) | |||
444 | rc = opal_xive_set_vp_info(vp, 0, 0); | 444 | rc = opal_xive_set_vp_info(vp, 0, 0); |
445 | if (rc != OPAL_BUSY) | 445 | if (rc != OPAL_BUSY) |
446 | break; | 446 | break; |
447 | msleep(1); | 447 | msleep(OPAL_BUSY_DELAY_MS); |
448 | } | 448 | } |
449 | } | 449 | } |
450 | 450 | ||
@@ -645,7 +645,7 @@ u32 xive_native_alloc_vp_block(u32 max_vcpus) | |||
645 | rc = opal_xive_alloc_vp_block(order); | 645 | rc = opal_xive_alloc_vp_block(order); |
646 | switch (rc) { | 646 | switch (rc) { |
647 | case OPAL_BUSY: | 647 | case OPAL_BUSY: |
648 | msleep(1); | 648 | msleep(OPAL_BUSY_DELAY_MS); |
649 | break; | 649 | break; |
650 | case OPAL_XIVE_PROVISIONING: | 650 | case OPAL_XIVE_PROVISIONING: |
651 | if (!xive_native_provision_pages()) | 651 | if (!xive_native_provision_pages()) |
@@ -687,7 +687,7 @@ int xive_native_enable_vp(u32 vp_id, bool single_escalation) | |||
687 | rc = opal_xive_set_vp_info(vp_id, flags, 0); | 687 | rc = opal_xive_set_vp_info(vp_id, flags, 0); |
688 | if (rc != OPAL_BUSY) | 688 | if (rc != OPAL_BUSY) |
689 | break; | 689 | break; |
690 | msleep(1); | 690 | msleep(OPAL_BUSY_DELAY_MS); |
691 | } | 691 | } |
692 | return rc ? -EIO : 0; | 692 | return rc ? -EIO : 0; |
693 | } | 693 | } |
@@ -701,7 +701,7 @@ int xive_native_disable_vp(u32 vp_id) | |||
701 | rc = opal_xive_set_vp_info(vp_id, 0, 0); | 701 | rc = opal_xive_set_vp_info(vp_id, 0, 0); |
702 | if (rc != OPAL_BUSY) | 702 | if (rc != OPAL_BUSY) |
703 | break; | 703 | break; |
704 | msleep(1); | 704 | msleep(OPAL_BUSY_DELAY_MS); |
705 | } | 705 | } |
706 | return rc ? -EIO : 0; | 706 | return rc ? -EIO : 0; |
707 | } | 707 | } |