diff options
-rw-r--r-- | drivers/net/ethernet/marvell/mvneta.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 577f7ca7deba..58808718d114 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c | |||
@@ -260,7 +260,6 @@ | |||
260 | 260 | ||
261 | #define MVNETA_VLAN_TAG_LEN 4 | 261 | #define MVNETA_VLAN_TAG_LEN 4 |
262 | 262 | ||
263 | #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 | ||
264 | #define MVNETA_TX_CSUM_DEF_SIZE 1600 | 263 | #define MVNETA_TX_CSUM_DEF_SIZE 1600 |
265 | #define MVNETA_TX_CSUM_MAX_SIZE 9800 | 264 | #define MVNETA_TX_CSUM_MAX_SIZE 9800 |
266 | #define MVNETA_ACC_MODE_EXT1 1 | 265 | #define MVNETA_ACC_MODE_EXT1 1 |
@@ -300,7 +299,7 @@ | |||
300 | #define MVNETA_RX_PKT_SIZE(mtu) \ | 299 | #define MVNETA_RX_PKT_SIZE(mtu) \ |
301 | ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ | 300 | ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ |
302 | ETH_HLEN + ETH_FCS_LEN, \ | 301 | ETH_HLEN + ETH_FCS_LEN, \ |
303 | MVNETA_CPU_D_CACHE_LINE_SIZE) | 302 | L1_CACHE_BYTES) |
304 | 303 | ||
305 | #define IS_TSO_HEADER(txq, addr) \ | 304 | #define IS_TSO_HEADER(txq, addr) \ |
306 | ((addr >= txq->tso_hdrs_phys) && \ | 305 | ((addr >= txq->tso_hdrs_phys) && \ |
@@ -2764,9 +2763,6 @@ static int mvneta_rxq_init(struct mvneta_port *pp, | |||
2764 | if (rxq->descs == NULL) | 2763 | if (rxq->descs == NULL) |
2765 | return -ENOMEM; | 2764 | return -ENOMEM; |
2766 | 2765 | ||
2767 | BUG_ON(rxq->descs != | ||
2768 | PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); | ||
2769 | |||
2770 | rxq->last_desc = rxq->size - 1; | 2766 | rxq->last_desc = rxq->size - 1; |
2771 | 2767 | ||
2772 | /* Set Rx descriptors queue starting address */ | 2768 | /* Set Rx descriptors queue starting address */ |
@@ -2837,10 +2833,6 @@ static int mvneta_txq_init(struct mvneta_port *pp, | |||
2837 | if (txq->descs == NULL) | 2833 | if (txq->descs == NULL) |
2838 | return -ENOMEM; | 2834 | return -ENOMEM; |
2839 | 2835 | ||
2840 | /* Make sure descriptor address is cache line size aligned */ | ||
2841 | BUG_ON(txq->descs != | ||
2842 | PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); | ||
2843 | |||
2844 | txq->last_desc = txq->size - 1; | 2836 | txq->last_desc = txq->size - 1; |
2845 | 2837 | ||
2846 | /* Set maximum bandwidth for enabled TXQs */ | 2838 | /* Set maximum bandwidth for enabled TXQs */ |