4 files changed, 146 insertions, 18 deletions

diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 4f3111b3113e..aeadb4d66f3e 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -122,6 +122,11 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
 };
 
 static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
+        DEF_MOD("tmu4",                  121,   R8A774C0_CLK_S0D6C),
+        DEF_MOD("tmu3",                  122,   R8A774C0_CLK_S3D2C),
+        DEF_MOD("tmu2",                  123,   R8A774C0_CLK_S3D2C),
+        DEF_MOD("tmu1",                  124,   R8A774C0_CLK_S3D2C),
+        DEF_MOD("tmu0",                  125,   R8A774C0_CLK_CP),
         DEF_MOD("scif5",                 202,   R8A774C0_CLK_S3D4C),
         DEF_MOD("scif4",                 203,   R8A774C0_CLK_S3D4C),
         DEF_MOD("scif3",                 204,   R8A774C0_CLK_S3D4C),
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c
index 25a3083b6764..f9e07fcc0d96 100644
--- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -41,6 +41,7 @@ enum clk_ids {
         CLK_S2,
         CLK_S3,
         CLK_SDSRC,
+        CLK_RPCSRC,
         CLK_OCO,
 
         /* Module Clocks */
@@ -65,8 +66,14 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
         DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
         DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
         DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
+        DEF_BASE(".rpcsrc",     CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
         DEF_RATE(".oco",        CLK_OCO,           32768),
 
+        DEF_BASE("rpc",         R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
+                 CLK_RPCSRC),
+        DEF_BASE("rpcd2",       R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+                 R8A77980_CLK_RPC),
+
         /* Core Clock Outputs */
         DEF_FIXED("ztr",        R8A77980_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
         DEF_FIXED("ztrd2",      R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
@@ -164,6 +171,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
         DEF_MOD("gpio1",                 911,   R8A77980_CLK_CP),
         DEF_MOD("gpio0",                 912,   R8A77980_CLK_CP),
         DEF_MOD("can-fd",                914,   R8A77980_CLK_S3D2),
+        DEF_MOD("rpc-if",                917,   R8A77980_CLK_RPC),
         DEF_MOD("i2c4",                  927,   R8A77980_CLK_S0D6),
         DEF_MOD("i2c3",                  928,   R8A77980_CLK_S0D6),
         DEF_MOD("i2c2",                  929,   R8A77980_CLK_S3D2),
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index be2ccbd6d623..9a8071a8114d 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -30,6 +30,21 @@
 
 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
 
+static spinlock_t cpg_lock;
+
+static void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set)
+{
+        unsigned long flags;
+        u32 val;
+
+        spin_lock_irqsave(&cpg_lock, flags);
+        val = readl(reg);
+        val &= ~clear;
+        val |= set;
+        writel(val, reg);
+        spin_unlock_irqrestore(&cpg_lock, flags);
+};
+
 struct cpg_simple_notifier {
         struct notifier_block nb;
         void __iomem *reg;
@@ -118,7 +133,6 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
         struct cpg_z_clk *zclk = to_z_clk(hw);
         unsigned int mult;
         unsigned int i;
-        u32 val, kick;
 
         /* Factor of 2 is for fixed divider */
         mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate);
@@ -127,17 +141,14 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
         if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
                 return -EBUSY;
 
-        val = readl(zclk->reg) & ~zclk->mask;
-        val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask;
-        writel(val, zclk->reg);
+        cpg_reg_modify(zclk->reg, zclk->mask,
+                       ((32 - mult) << __ffs(zclk->mask)) & zclk->mask);
 
         /*
          * Set KICK bit in FRQCRB to update hardware setting and wait for
          * clock change completion.
          */
-        kick = readl(zclk->kick_reg);
-        kick |= CPG_FRQCRB_KICK;
-        writel(kick, zclk->kick_reg);
+        cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
 
         /*
          * Note: There is no HW information about the worst case latency.
@@ -266,12 +277,10 @@ static const struct sd_div_table cpg_sd_div_table[] = {
 static int cpg_sd_clock_enable(struct clk_hw *hw)
 {
         struct sd_clock *clock = to_sd_clock(hw);
-        u32 val = readl(clock->csn.reg);
-
-        val &= ~(CPG_SD_STP_MASK);
-        val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK;
 
-        writel(val, clock->csn.reg);
+        cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK,
+                       clock->div_table[clock->cur_div_idx].val &
+                       CPG_SD_STP_MASK);
 
         return 0;
 }
@@ -280,7 +289,7 @@ static void cpg_sd_clock_disable(struct clk_hw *hw)
 {
         struct sd_clock *clock = to_sd_clock(hw);
 
-        writel(readl(clock->csn.reg) | CPG_SD_STP_MASK, clock->csn.reg);
+        cpg_reg_modify(clock->csn.reg, 0, CPG_SD_STP_MASK);
 }
 
 static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
@@ -327,7 +336,6 @@ static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
 {
         struct sd_clock *clock = to_sd_clock(hw);
         unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
-        u32 val;
         unsigned int i;
 
         for (i = 0; i < clock->div_num; i++)
@@ -339,10 +347,9 @@ static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
 
         clock->cur_div_idx = i;
 
-        val = readl(clock->csn.reg);
-        val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
-        val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
-        writel(val, clock->csn.reg);
+        cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK | CPG_SD_FC_MASK,
+                       clock->div_table[i].val &
+                       (CPG_SD_STP_MASK | CPG_SD_FC_MASK));
 
         return 0;
 }
@@ -415,6 +422,92 @@ free_clock:
         return clk;
 }
 
+struct rpc_clock {
+        struct clk_divider div;
+        struct clk_gate gate;
+        /*
+         * One notifier covers both RPC and RPCD2 clocks as they are both
+         * controlled by the same RPCCKCR register...
+         */
+        struct cpg_simple_notifier csn;
+};
+
+static const struct clk_div_table cpg_rpcsrc_div_table[] = {
+        { 2, 5 }, { 3, 6 }, { 0, 0 },
+};
+
+static const struct clk_div_table cpg_rpc_div_table[] = {
+        { 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 },
+};
+
+static struct clk * __init cpg_rpc_clk_register(const char *name,
+        void __iomem *base, const char *parent_name,
+        struct raw_notifier_head *notifiers)
+{
+        struct rpc_clock *rpc;
+        struct clk *clk;
+
+        rpc = kzalloc(sizeof(*rpc), GFP_KERNEL);
+        if (!rpc)
+                return ERR_PTR(-ENOMEM);
+
+        rpc->div.reg = base + CPG_RPCCKCR;
+        rpc->div.width = 3;
+        rpc->div.table = cpg_rpc_div_table;
+        rpc->div.lock = &cpg_lock;
+
+        rpc->gate.reg = base + CPG_RPCCKCR;
+        rpc->gate.bit_idx = 8;
+        rpc->gate.flags = CLK_GATE_SET_TO_DISABLE;
+        rpc->gate.lock = &cpg_lock;
+
+        rpc->csn.reg = base + CPG_RPCCKCR;
+
+        clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
+                                     &rpc->div.hw,  &clk_divider_ops,
+                                     &rpc->gate.hw, &clk_gate_ops, 0);
+        if (IS_ERR(clk)) {
+                kfree(rpc);
+                return clk;
+        }
+
+        cpg_simple_notifier_register(notifiers, &rpc->csn);
+        return clk;
+}
+
+struct rpcd2_clock {
+        struct clk_fixed_factor fixed;
+        struct clk_gate gate;
+};
+
+static struct clk * __init cpg_rpcd2_clk_register(const char *name,
+                                                  void __iomem *base,
+                                                  const char *parent_name)
+{
+        struct rpcd2_clock *rpcd2;
+        struct clk *clk;
+
+        rpcd2 = kzalloc(sizeof(*rpcd2), GFP_KERNEL);
+        if (!rpcd2)
+                return ERR_PTR(-ENOMEM);
+
+        rpcd2->fixed.mult = 1;
+        rpcd2->fixed.div = 2;
+
+        rpcd2->gate.reg = base + CPG_RPCCKCR;
+        rpcd2->gate.bit_idx = 9;
+        rpcd2->gate.flags = CLK_GATE_SET_TO_DISABLE;
+        rpcd2->gate.lock = &cpg_lock;
+
+        clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
+                                     &rpcd2->fixed.hw, &clk_fixed_factor_ops,
+                                     &rpcd2->gate.hw, &clk_gate_ops, 0);
+        if (IS_ERR(clk))
+                kfree(rpcd2);
+
+        return clk;
+}
+
 
 static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
 static unsigned int cpg_clk_extalr __initdata;
@@ -593,6 +686,21 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
                 }
                 break;
 
+        case CLK_TYPE_GEN3_RPCSRC:
+                return clk_register_divider_table(NULL, core->name,
+                                                  __clk_get_name(parent), 0,
+                                                  base + CPG_RPCCKCR, 3, 2, 0,
+                                                  cpg_rpcsrc_div_table,
+                                                  &cpg_lock);
+
+        case CLK_TYPE_GEN3_RPC:
+                return cpg_rpc_clk_register(core->name, base,
+                                            __clk_get_name(parent), notifiers);
+
+        case CLK_TYPE_GEN3_RPCD2:
+                return cpg_rpcd2_clk_register(core->name, base,
+                                              __clk_get_name(parent));
+
         default:
                 return ERR_PTR(-EINVAL);
         }
@@ -613,5 +721,8 @@ int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
         if (attr)
                 cpg_quirks = (uintptr_t)attr->data;
         pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
+
+        spin_lock_init(&cpg_lock);
+
         return 0;
 }
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index f4fb6cf16688..eac1b057455a 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -23,6 +23,9 @@ enum rcar_gen3_clk_types {
         CLK_TYPE_GEN3_Z2,
         CLK_TYPE_GEN3_OSC,      /* OSC EXTAL predivider and fixed divider */
         CLK_TYPE_GEN3_RCKSEL,   /* Select parent/divider using RCKCR.CKSEL */
+        CLK_TYPE_GEN3_RPCSRC,
+        CLK_TYPE_GEN3_RPC,
+        CLK_TYPE_GEN3_RPCD2,
 
         /* SoC specific definitions start here */
         CLK_TYPE_GEN3_SOC_BASE,
@@ -57,6 +60,7 @@ struct rcar_gen3_cpg_pll_config {
         u8 osc_prediv;
 };
 
+#define CPG_RPCCKCR     0x238
 #define CPG_RCKCR       0x240
 
 struct clk *rcar_gen3_cpg_clk_register(struct device *dev,