2 files changed, 346 insertions, 248 deletions
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
index d6cb083b90a2..0c80c2677104 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
@@ -12,253 +12,9 @@ Required properties :
 - clocks : Should contain phandle and clock specifiers for two clocks:
  the 32 KHz "32k_in", and the board-specific oscillator "osc".
 - #clock-cells : Should be 1.
-  In clock consumers, this cell represents the clock ID exposed by the CAR.
+  In clock consumers, this cell represents the clock ID exposed by the
+  CAR. The assignments may be found in header file
-  The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+  <dt-bindings/clock/tegra114-car.h>.
-  registers. These IDs often match those in the CAR's RST_DEVICES registers,
-  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
-  this case, those clocks are assigned IDs above 160 in order to highlight
-  this issue. Implementations that interpret these clock IDs as bit values
-  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
-  explicitly handle these special cases.
-  The balance of the clocks controlled by the CAR are assigned IDs of 160 and
-  above.
-  0     unassigned
-  1     unassigned
-  2     unassigned
-  3     unassigned
-  4     rtc
-  5     timer
-  6     uarta
-  7     unassigned      (register bit affects uartb and vfir)
-  8     unassigned
-  9     sdmmc2
-  10    unassigned      (register bit affects spdif_in and spdif_out)
-  11    i2s1
-  12    i2c1
-  13    ndflash
-  14    sdmmc1
-  15    sdmmc4
-  16    unassigned
-  17    pwm
-  18    i2s2
-  19    epp
-  20    unassigned      (register bit affects vi and vi_sensor)
-  21    2d
-  22    usbd
-  23    isp
-  24    3d
-  25    unassigned
-  26    disp2
-  27    disp1
-  28    host1x
-  29    vcp
-  30    i2s0
-  31    unassigned
-  32    unassigned
-  33    unassigned
-  34    apbdma
-  35    unassigned
-  36    kbc
-  37    unassigned
-  38    unassigned
-  39    unassigned      (register bit affects fuse and fuse_burn)
-  40    kfuse
-  41    sbc1
-  42    nor
-  43    unassigned
-  44    sbc2
-  45    unassigned
-  46    sbc3
-  47    i2c5
-  48    dsia
-  49    unassigned
-  50    mipi
-  51    hdmi
-  52    csi
-  53    unassigned
-  54    i2c2
-  55    uartc
-  56    mipi-cal
-  57    emc
-  58    usb2
-  59    usb3
-  60    msenc
-  61    vde
-  62    bsea
-  63    bsev
-  64    unassigned
-  65    uartd
-  66    unassigned
-  67    i2c3
-  68    sbc4
-  69    sdmmc3
-  70    unassigned
-  71    owr
-  72    afi
-  73    csite
-  74    unassigned
-  75    unassigned
-  76    la
-  77    trace
-  78    soc_therm
-  79    dtv
-  80    ndspeed
-  81    i2cslow
-  82    dsib
-  83    tsec
-  84    unassigned
-  85    unassigned
-  86    unassigned
-  87    unassigned
-  88    unassigned
-  89    xusb_host
-  90    unassigned
-  91    msenc
-  92    csus
-  93    unassigned
-  94    unassigned
-  95    unassigned      (bit affects xusb_dev and xusb_dev_src)
-  96    unassigned
-  97    unassigned
-  98    unassigned
-  99    mselect
-  100   tsensor
-  101   i2s3
-  102   i2s4
-  103   i2c4
-  104   sbc5
-  105   sbc6
-  106   d_audio
-  107   apbif
-  108   dam0
-  109   dam1
-  110   dam2
-  111   hda2codec_2x
-  112   unassigned
-  113   audio0_2x
-  114   audio1_2x
-  115   audio2_2x
-  116   audio3_2x
-  117   audio4_2x
-  118   spdif_2x
-  119   actmon
-  120   extern1
-  121   extern2
-  122   extern3
-  123   unassigned
-  124   unassigned
-  125   hda
-  126   unassigned
-  127   se
-  128   hda2hdmi
-  129   unassigned
-  130   unassigned
-  131   unassigned
-  132   unassigned
-  133   unassigned
-  134   unassigned
-  135   unassigned
-  136   unassigned
-  137   unassigned
-  138   unassigned
-  139   unassigned
-  140   unassigned
-  141   unassigned
-  142   unassigned
-  143   unassigned      (bit affects xusb_falcon_src, xusb_fs_src,
-                         xusb_host_src and xusb_ss_src)
-  144   cilab
-  145   cilcd
-  146   cile
-  147   dsialp
-  148   dsiblp
-  149   unassigned
-  150   dds
-  151   unassigned
-  152   dp2
-  153   amx
-  154   adx
-  155   unassigned      (bit affects dfll_ref and dfll_soc)
-  156   xusb_ss
-  192   uartb
-  193   vfir
-  194   spdif_in
-  195   spdif_out
-  196   vi
-  197   vi_sensor
-  198   fuse
-  199   fuse_burn
-  200   clk_32k
-  201   clk_m
-  202   clk_m_div2
-  203   clk_m_div4
-  204   pll_ref
-  205   pll_c
-  206   pll_c_out1
-  207   pll_c2
-  208   pll_c3
-  209   pll_m
-  210   pll_m_out1
-  211   pll_p
-  212   pll_p_out1
-  213   pll_p_out2
-  214   pll_p_out3
-  215   pll_p_out4
-  216   pll_a
-  217   pll_a_out0
-  218   pll_d
-  219   pll_d_out0
-  220   pll_d2
-  221   pll_d2_out0
-  222   pll_u
-  223   pll_u_480M
-  224   pll_u_60M
-  225   pll_u_48M
-  226   pll_u_12M
-  227   pll_x
-  228   pll_x_out0
-  229   pll_re_vco
-  230   pll_re_out
-  231   pll_e_out0
-  232   spdif_in_sync
-  233   i2s0_sync
-  234   i2s1_sync
-  235   i2s2_sync
-  236   i2s3_sync
-  237   i2s4_sync
-  238   vimclk_sync
-  239   audio0
-  240   audio1
-  241   audio2
-  242   audio3
-  243   audio4
-  244   spdif
-  245   clk_out_1
-  246   clk_out_2
-  247   clk_out_3
-  248   blink
-  252   xusb_host_src
-  253   xusb_falcon_src
-  254   xusb_fs_src
-  255   xusb_ss_src
-  256   xusb_dev_src
-  257   xusb_dev
-  258   xusb_hs_src
-  259   sclk
-  260   hclk
-  261   pclk
-  262   cclk_g
-  263   cclk_lp
-  264   dfll_ref
-  265   dfll_soc
 Example SoC include file:
@@ -270,7 +26,7 @@ Example SoC include file:
        };
        usb@c5004000 {
-                clocks = <&tegra_car 58>; /* usb2 */
+                clocks = <&tegra_car TEGRA114_CLK_USB2>;
        };
 };
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
new file mode 100644
index 000000000000..614aec417902
--- /dev/null
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -0,0 +1,342 @@
+/*
+ * This header provides constants for binding nvidia,tegra114-car.
+ *
+ * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 160 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
+ * above.
+ */
+#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
+/* 0 */
+/* 1 */
+/* 2 */
+/* 3 */
+#define TEGRA114_CLK_RTC 4
+#define TEGRA114_CLK_TIMER 5
+#define TEGRA114_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+/* 8 */
+#define TEGRA114_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA114_CLK_I2S1 11
+#define TEGRA114_CLK_I2C1 12
+#define TEGRA114_CLK_NDFLASH 13
+#define TEGRA114_CLK_SDMMC1 14
+#define TEGRA114_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA114_CLK_PWM 17
+#define TEGRA114_CLK_I2S2 18
+#define TEGRA114_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA114_CLK_GR_2D 21
+#define TEGRA114_CLK_USBD 22
+#define TEGRA114_CLK_ISP 23
+#define TEGRA114_CLK_GR_3D 24
+/* 25 */
+#define TEGRA114_CLK_DISP2 26
+#define TEGRA114_CLK_DISP1 27
+#define TEGRA114_CLK_HOST1X 28
+#define TEGRA114_CLK_VCP 29
+#define TEGRA114_CLK_I2S0 30
+/* 31 */
+/* 32 */
+/* 33 */
+#define TEGRA114_CLK_APBDMA 34
+/* 35 */
+#define TEGRA114_CLK_KBC 36
+/* 37 */
+/* 38 */
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA114_CLK_KFUSE 40
+#define TEGRA114_CLK_SBC1 41
+#define TEGRA114_CLK_NOR 42
+/* 43 */
+#define TEGRA114_CLK_SBC2 44
+/* 45 */
+#define TEGRA114_CLK_SBC3 46
+#define TEGRA114_CLK_I2C5 47
+#define TEGRA114_CLK_DSIA 48
+/* 49 */
+#define TEGRA114_CLK_MIPI 50
+#define TEGRA114_CLK_HDMI 51
+#define TEGRA114_CLK_CSI 52
+/* 53 */
+#define TEGRA114_CLK_I2C2 54
+#define TEGRA114_CLK_UARTC 55
+#define TEGRA114_CLK_MIPI_CAL 56
+#define TEGRA114_CLK_EMC 57
+#define TEGRA114_CLK_USB2 58
+#define TEGRA114_CLK_USB3 59
+/* 60 */
+#define TEGRA114_CLK_VDE 61
+#define TEGRA114_CLK_BSEA 62
+#define TEGRA114_CLK_BSEV 63
+/* 64 */
+#define TEGRA114_CLK_UARTD 65
+/* 66 */
+#define TEGRA114_CLK_I2C3 67
+#define TEGRA114_CLK_SBC4 68
+#define TEGRA114_CLK_SDMMC3 69
+/* 70 */
+#define TEGRA114_CLK_OWR 71
+/* 72 */
+#define TEGRA114_CLK_CSITE 73
+/* 74 */
+/* 75 */
+#define TEGRA114_CLK_LA 76
+#define TEGRA114_CLK_TRACE 77
+#define TEGRA114_CLK_SOC_THERM 78
+#define TEGRA114_CLK_DTV 79
+#define TEGRA114_CLK_NDSPEED 80
+#define TEGRA114_CLK_I2CSLOW 81
+#define TEGRA114_CLK_DSIB 82
+#define TEGRA114_CLK_TSEC 83
+/* 84 */
+/* 85 */
+/* 86 */
+/* 87 */
+/* 88 */
+#define TEGRA114_CLK_XUSB_HOST 89
+/* 90 */
+#define TEGRA114_CLK_MSENC 91
+#define TEGRA114_CLK_CSUS 92
+/* 93 */
+/* 94 */
+/* 95 (bit affects xusb_dev and xusb_dev_src) */
+/* 96 */
+/* 97 */
+/* 98 */
+#define TEGRA114_CLK_MSELECT 99
+#define TEGRA114_CLK_TSENSOR 100
+#define TEGRA114_CLK_I2S3 101
+#define TEGRA114_CLK_I2S4 102
+#define TEGRA114_CLK_I2C4 103
+#define TEGRA114_CLK_SBC5 104
+#define TEGRA114_CLK_SBC6 105
+#define TEGRA114_CLK_D_AUDIO 106
+#define TEGRA114_CLK_APBIF 107
+#define TEGRA114_CLK_DAM0 108
+#define TEGRA114_CLK_DAM1 109
+#define TEGRA114_CLK_DAM2 110
+#define TEGRA114_CLK_HDA2CODEC_2X 111
+/* 112 */
+#define TEGRA114_CLK_AUDIO0_2X 113
+#define TEGRA114_CLK_AUDIO1_2X 114
+#define TEGRA114_CLK_AUDIO2_2X 115
+#define TEGRA114_CLK_AUDIO3_2X 116
+#define TEGRA114_CLK_AUDIO4_2X 117
+#define TEGRA114_CLK_SPDIF_2X 118
+#define TEGRA114_CLK_ACTMON 119
+#define TEGRA114_CLK_EXTERN1 120
+#define TEGRA114_CLK_EXTERN2 121
+#define TEGRA114_CLK_EXTERN3 122
+/* 123 */
+/* 124 */
+#define TEGRA114_CLK_HDA 125
+/* 126 */
+#define TEGRA114_CLK_SE 127
+#define TEGRA114_CLK_HDA2HDMI 128
+/* 129 */
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+/* 136 */
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
+/*      xusb_host_src and xusb_ss_src) */
+#define TEGRA114_CLK_CILAB 144
+#define TEGRA114_CLK_CILCD 145
+#define TEGRA114_CLK_CILE 146
+#define TEGRA114_CLK_DSIALP 147
+#define TEGRA114_CLK_DSIBLP 148
+/* 149 */
+#define TEGRA114_CLK_DDS 150
+/* 151 */
+#define TEGRA114_CLK_DP2 152
+#define TEGRA114_CLK_AMX 153
+#define TEGRA114_CLK_ADX 154
+/* 155 (bit affects dfll_ref and dfll_soc) */
+#define TEGRA114_CLK_XUSB_SS 156
+/* 157 */
+/* 158 */
+/* 159 */
+/* 160 */
+/* 161 */
+/* 162 */
+/* 163 */
+/* 164 */
+/* 165 */
+/* 166 */
+/* 167 */
+/* 168 */
+/* 169 */
+/* 170 */
+/* 171 */
+/* 172 */
+/* 173 */
+/* 174 */
+/* 175 */
+/* 176 */
+/* 177 */
+/* 178 */
+/* 179 */
+/* 180 */
+/* 181 */
+/* 182 */
+/* 183 */
+/* 184 */
+/* 185 */
+/* 186 */
+/* 187 */
+/* 188 */
+/* 189 */
+/* 190 */
+/* 191 */
+#define TEGRA114_CLK_UARTB 192
+#define TEGRA114_CLK_VFIR 193
+#define TEGRA114_CLK_SPDIF_IN 194
+#define TEGRA114_CLK_SPDIF_OUT 195
+#define TEGRA114_CLK_VI 196
+#define TEGRA114_CLK_VI_SENSOR 197
+#define TEGRA114_CLK_FUSE 198
+#define TEGRA114_CLK_FUSE_BURN 199
+#define TEGRA114_CLK_CLK_32K 200
+#define TEGRA114_CLK_CLK_M 201
+#define TEGRA114_CLK_CLK_M_DIV2 202
+#define TEGRA114_CLK_CLK_M_DIV4 203
+#define TEGRA114_CLK_PLL_REF 204
+#define TEGRA114_CLK_PLL_C 205
+#define TEGRA114_CLK_PLL_C_OUT1 206
+#define TEGRA114_CLK_PLL_C2 207
+#define TEGRA114_CLK_PLL_C3 208
+#define TEGRA114_CLK_PLL_M 209
+#define TEGRA114_CLK_PLL_M_OUT1 210
+#define TEGRA114_CLK_PLL_P 211
+#define TEGRA114_CLK_PLL_P_OUT1 212
+#define TEGRA114_CLK_PLL_P_OUT2 213
+#define TEGRA114_CLK_PLL_P_OUT3 214
+#define TEGRA114_CLK_PLL_P_OUT4 215
+#define TEGRA114_CLK_PLL_A 216
+#define TEGRA114_CLK_PLL_A_OUT0 217
+#define TEGRA114_CLK_PLL_D 218
+#define TEGRA114_CLK_PLL_D_OUT0 219
+#define TEGRA114_CLK_PLL_D2 220
+#define TEGRA114_CLK_PLL_D2_OUT0 221
+#define TEGRA114_CLK_PLL_U 222
+#define TEGRA114_CLK_PLL_U_480M 223
+#define TEGRA114_CLK_PLL_U_60M 224
+#define TEGRA114_CLK_PLL_U_48M 225
+#define TEGRA114_CLK_PLL_U_12M 226
+#define TEGRA114_CLK_PLL_X 227
+#define TEGRA114_CLK_PLL_X_OUT0 228
+#define TEGRA114_CLK_PLL_RE_VCO 229
+#define TEGRA114_CLK_PLL_RE_OUT 230
+#define TEGRA114_CLK_PLL_E_OUT0 231
+#define TEGRA114_CLK_SPDIF_IN_SYNC 232
+#define TEGRA114_CLK_I2S0_SYNC 233
+#define TEGRA114_CLK_I2S1_SYNC 234
+#define TEGRA114_CLK_I2S2_SYNC 235
+#define TEGRA114_CLK_I2S3_SYNC 236
+#define TEGRA114_CLK_I2S4_SYNC 237
+#define TEGRA114_CLK_VIMCLK_SYNC 238
+#define TEGRA114_CLK_AUDIO0 239
+#define TEGRA114_CLK_AUDIO1 240
+#define TEGRA114_CLK_AUDIO2 241
+#define TEGRA114_CLK_AUDIO3 242
+#define TEGRA114_CLK_AUDIO4 243
+#define TEGRA114_CLK_SPDIF 244
+#define TEGRA114_CLK_CLK_OUT_1 245
+#define TEGRA114_CLK_CLK_OUT_2 246
+#define TEGRA114_CLK_CLK_OUT_3 247
+#define TEGRA114_CLK_BLINK 248
+/* 249 */
+/* 250 */
+/* 251 */
+#define TEGRA114_CLK_XUSB_HOST_SRC 252
+#define TEGRA114_CLK_XUSB_FALCON_SRC 253
+#define TEGRA114_CLK_XUSB_FS_SRC 254
+#define TEGRA114_CLK_XUSB_SS_SRC 255
+#define TEGRA114_CLK_XUSB_DEV_SRC 256
+#define TEGRA114_CLK_XUSB_DEV 257
+#define TEGRA114_CLK_XUSB_HS_SRC 258
+#define TEGRA114_CLK_SCLK 259
+#define TEGRA114_CLK_HCLK 260
+#define TEGRA114_CLK_PCLK 261
+#define TEGRA114_CLK_CCLK_G 262
+#define TEGRA114_CLK_CCLK_LP 263
+/* 264 */
+/* 265 */
+/* 266 */
+/* 267 */
+/* 268 */
+/* 269 */
+/* 270 */
+/* 271 */
+/* 272 */
+/* 273 */
+/* 274 */
+/* 275 */
+/* 276 */
+/* 277 */
+/* 278 */
+/* 279 */
+/* 280 */
+/* 281 */
+/* 282 */
+/* 283 */
+/* 284 */
+/* 285 */
+/* 286 */
+/* 287 */
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA114_CLK_AUDIO0_MUX 300
+#define TEGRA114_CLK_AUDIO1_MUX 301
+#define TEGRA114_CLK_AUDIO2_MUX 302
+#define TEGRA114_CLK_AUDIO3_MUX 303
+#define TEGRA114_CLK_AUDIO4_MUX 304
+#define TEGRA114_CLK_SPDIF_MUX 305
+#define TEGRA114_CLK_CLK_OUT_1_MUX 306
+#define TEGRA114_CLK_CLK_OUT_2_MUX 307
+#define TEGRA114_CLK_CLK_OUT_3_MUX 308
+#define TEGRA114_CLK_DSIA_MUX 309
+#define TEGRA114_CLK_DSIB_MUX 310
+#define TEGRA114_CLK_CLK_MAX 311
+#endif  /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt index d6cb083b90a2..0c80c2677104 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
@@ -12,253 +12,9 @@ Required properties :
12	- clocks : Should contain phandle and clock specifiers for two clocks:	12	- clocks : Should contain phandle and clock specifiers for two clocks:
13	the 32 KHz "32k_in", and the board-specific oscillator "osc".	13	the 32 KHz "32k_in", and the board-specific oscillator "osc".
14	- #clock-cells : Should be 1.	14	- #clock-cells : Should be 1.
15	In clock consumers, this cell represents the clock ID exposed by the CAR.	15	In clock consumers, this cell represents the clock ID exposed by the
16		16	CAR. The assignments may be found in header file
17	The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB	17	<dt-bindings/clock/tegra114-car.h>.
18	registers. These IDs often match those in the CAR's RST_DEVICES registers,
19	but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
20	this case, those clocks are assigned IDs above 160 in order to highlight
21	this issue. Implementations that interpret these clock IDs as bit values
22	within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
23	explicitly handle these special cases.
24
25	The balance of the clocks controlled by the CAR are assigned IDs of 160 and
26	above.
27
28	0 unassigned
29	1 unassigned
30	2 unassigned
31	3 unassigned
32	4 rtc
33	5 timer
34	6 uarta
35	7 unassigned (register bit affects uartb and vfir)
36	8 unassigned
37	9 sdmmc2
38	10 unassigned (register bit affects spdif_in and spdif_out)
39	11 i2s1
40	12 i2c1
41	13 ndflash
42	14 sdmmc1
43	15 sdmmc4
44	16 unassigned
45	17 pwm
46	18 i2s2
47	19 epp
48	20 unassigned (register bit affects vi and vi_sensor)
49	21 2d
50	22 usbd
51	23 isp
52	24 3d
53	25 unassigned
54	26 disp2
55	27 disp1
56	28 host1x
57	29 vcp
58	30 i2s0
59	31 unassigned
60
61	32 unassigned
62	33 unassigned
63	34 apbdma
64	35 unassigned
65	36 kbc
66	37 unassigned
67	38 unassigned
68	39 unassigned (register bit affects fuse and fuse_burn)
69	40 kfuse
70	41 sbc1
71	42 nor
72	43 unassigned
73	44 sbc2
74	45 unassigned
75	46 sbc3
76	47 i2c5
77	48 dsia
78	49 unassigned
79	50 mipi
80	51 hdmi
81	52 csi
82	53 unassigned
83	54 i2c2
84	55 uartc
85	56 mipi-cal
86	57 emc
87	58 usb2
88	59 usb3
89	60 msenc
90	61 vde
91	62 bsea
92	63 bsev
93
94	64 unassigned
95	65 uartd
96	66 unassigned
97	67 i2c3
98	68 sbc4
99	69 sdmmc3
100	70 unassigned
101	71 owr
102	72 afi
103	73 csite
104	74 unassigned
105	75 unassigned
106	76 la
107	77 trace
108	78 soc_therm
109	79 dtv
110	80 ndspeed
111	81 i2cslow
112	82 dsib
113	83 tsec
114	84 unassigned
115	85 unassigned
116	86 unassigned
117	87 unassigned
118	88 unassigned
119	89 xusb_host
120	90 unassigned
121	91 msenc
122	92 csus
123	93 unassigned
124	94 unassigned
125	95 unassigned (bit affects xusb_dev and xusb_dev_src)
126
127	96 unassigned
128	97 unassigned
129	98 unassigned
130	99 mselect
131	100 tsensor
132	101 i2s3
133	102 i2s4
134	103 i2c4
135	104 sbc5
136	105 sbc6
137	106 d_audio
138	107 apbif
139	108 dam0
140	109 dam1
141	110 dam2
142	111 hda2codec_2x
143	112 unassigned
144	113 audio0_2x
145	114 audio1_2x
146	115 audio2_2x
147	116 audio3_2x
148	117 audio4_2x
149	118 spdif_2x
150	119 actmon
151	120 extern1
152	121 extern2
153	122 extern3
154	123 unassigned
155	124 unassigned
156	125 hda
157	126 unassigned
158	127 se
159
160	128 hda2hdmi
161	129 unassigned
162	130 unassigned
163	131 unassigned
164	132 unassigned
165	133 unassigned
166	134 unassigned
167	135 unassigned
168	136 unassigned
169	137 unassigned
170	138 unassigned
171	139 unassigned
172	140 unassigned
173	141 unassigned
174	142 unassigned
175	143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
176	xusb_host_src and xusb_ss_src)
177	144 cilab
178	145 cilcd
179	146 cile
180	147 dsialp
181	148 dsiblp
182	149 unassigned
183	150 dds
184	151 unassigned
185	152 dp2
186	153 amx
187	154 adx
188	155 unassigned (bit affects dfll_ref and dfll_soc)
189	156 xusb_ss
190
191	192 uartb
192	193 vfir
193	194 spdif_in
194	195 spdif_out
195	196 vi
196	197 vi_sensor
197	198 fuse
198	199 fuse_burn
199	200 clk_32k
200	201 clk_m
201	202 clk_m_div2
202	203 clk_m_div4
203	204 pll_ref
204	205 pll_c
205	206 pll_c_out1
206	207 pll_c2
207	208 pll_c3
208	209 pll_m
209	210 pll_m_out1
210	211 pll_p
211	212 pll_p_out1
212	213 pll_p_out2
213	214 pll_p_out3
214	215 pll_p_out4
215	216 pll_a
216	217 pll_a_out0
217	218 pll_d
218	219 pll_d_out0
219	220 pll_d2
220	221 pll_d2_out0
221	222 pll_u
222	223 pll_u_480M
223	224 pll_u_60M
224	225 pll_u_48M
225	226 pll_u_12M
226	227 pll_x
227	228 pll_x_out0
228	229 pll_re_vco
229	230 pll_re_out
230	231 pll_e_out0
231	232 spdif_in_sync
232	233 i2s0_sync
233	234 i2s1_sync
234	235 i2s2_sync
235	236 i2s3_sync
236	237 i2s4_sync
237	238 vimclk_sync
238	239 audio0
239	240 audio1
240	241 audio2
241	242 audio3
242	243 audio4
243	244 spdif
244	245 clk_out_1
245	246 clk_out_2
246	247 clk_out_3
247	248 blink
248	252 xusb_host_src
249	253 xusb_falcon_src
250	254 xusb_fs_src
251	255 xusb_ss_src
252	256 xusb_dev_src
253	257 xusb_dev
254	258 xusb_hs_src
255	259 sclk
256	260 hclk
257	261 pclk
258	262 cclk_g
259	263 cclk_lp
260	264 dfll_ref
261	265 dfll_soc
262		18
263	Example SoC include file:	19	Example SoC include file:
264		20
@@ -270,7 +26,7 @@ Example SoC include file:
270	};	26	};
271		27
272	usb@c5004000 {	28	usb@c5004000 {
273	clocks = <&tegra_car 58>; /* usb2 */	29	clocks = <&tegra_car TEGRA114_CLK_USB2>;
274	};	30	};
275	};	31	};
276		32


diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h new file mode 100644 index 000000000000..614aec417902 --- /dev/null +++ b/include/dt-bindings/clock/tegra114-car.h
@@ -0,0 +1,342 @@
		1	/*
		2	* This header provides constants for binding nvidia,tegra114-car.
		3	*
		4	* The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
		5	* registers. These IDs often match those in the CAR's RST_DEVICES registers,
		6	* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
		7	* this case, those clocks are assigned IDs above 160 in order to highlight
		8	* this issue. Implementations that interpret these clock IDs as bit values
		9	* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
		10	* explicitly handle these special cases.
		11	*
		12	* The balance of the clocks controlled by the CAR are assigned IDs of 160 and
		13	* above.
		14	*/
		15
		16	#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
		17	#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
		18
		19	/* 0 */
		20	/* 1 */
		21	/* 2 */
		22	/* 3 */
		23	#define TEGRA114_CLK_RTC 4
		24	#define TEGRA114_CLK_TIMER 5
		25	#define TEGRA114_CLK_UARTA 6
		26	/* 7 (register bit affects uartb and vfir) */
		27	/* 8 */
		28	#define TEGRA114_CLK_SDMMC2 9
		29	/* 10 (register bit affects spdif_in and spdif_out) */
		30	#define TEGRA114_CLK_I2S1 11
		31	#define TEGRA114_CLK_I2C1 12
		32	#define TEGRA114_CLK_NDFLASH 13
		33	#define TEGRA114_CLK_SDMMC1 14
		34	#define TEGRA114_CLK_SDMMC4 15
		35	/* 16 */
		36	#define TEGRA114_CLK_PWM 17
		37	#define TEGRA114_CLK_I2S2 18
		38	#define TEGRA114_CLK_EPP 19
		39	/* 20 (register bit affects vi and vi_sensor) */
		40	#define TEGRA114_CLK_GR_2D 21
		41	#define TEGRA114_CLK_USBD 22
		42	#define TEGRA114_CLK_ISP 23
		43	#define TEGRA114_CLK_GR_3D 24
		44	/* 25 */
		45	#define TEGRA114_CLK_DISP2 26
		46	#define TEGRA114_CLK_DISP1 27
		47	#define TEGRA114_CLK_HOST1X 28
		48	#define TEGRA114_CLK_VCP 29
		49	#define TEGRA114_CLK_I2S0 30
		50	/* 31 */
		51
		52	/* 32 */
		53	/* 33 */
		54	#define TEGRA114_CLK_APBDMA 34
		55	/* 35 */
		56	#define TEGRA114_CLK_KBC 36
		57	/* 37 */
		58	/* 38 */
		59	/* 39 (register bit affects fuse and fuse_burn) */
		60	#define TEGRA114_CLK_KFUSE 40
		61	#define TEGRA114_CLK_SBC1 41
		62	#define TEGRA114_CLK_NOR 42
		63	/* 43 */
		64	#define TEGRA114_CLK_SBC2 44
		65	/* 45 */
		66	#define TEGRA114_CLK_SBC3 46
		67	#define TEGRA114_CLK_I2C5 47
		68	#define TEGRA114_CLK_DSIA 48
		69	/* 49 */
		70	#define TEGRA114_CLK_MIPI 50
		71	#define TEGRA114_CLK_HDMI 51
		72	#define TEGRA114_CLK_CSI 52
		73	/* 53 */
		74	#define TEGRA114_CLK_I2C2 54
		75	#define TEGRA114_CLK_UARTC 55
		76	#define TEGRA114_CLK_MIPI_CAL 56
		77	#define TEGRA114_CLK_EMC 57
		78	#define TEGRA114_CLK_USB2 58
		79	#define TEGRA114_CLK_USB3 59
		80	/* 60 */
		81	#define TEGRA114_CLK_VDE 61
		82	#define TEGRA114_CLK_BSEA 62
		83	#define TEGRA114_CLK_BSEV 63
		84
		85	/* 64 */
		86	#define TEGRA114_CLK_UARTD 65
		87	/* 66 */
		88	#define TEGRA114_CLK_I2C3 67
		89	#define TEGRA114_CLK_SBC4 68
		90	#define TEGRA114_CLK_SDMMC3 69
		91	/* 70 */
		92	#define TEGRA114_CLK_OWR 71
		93	/* 72 */
		94	#define TEGRA114_CLK_CSITE 73
		95	/* 74 */
		96	/* 75 */
		97	#define TEGRA114_CLK_LA 76
		98	#define TEGRA114_CLK_TRACE 77
		99	#define TEGRA114_CLK_SOC_THERM 78
		100	#define TEGRA114_CLK_DTV 79
		101	#define TEGRA114_CLK_NDSPEED 80
		102	#define TEGRA114_CLK_I2CSLOW 81
		103	#define TEGRA114_CLK_DSIB 82
		104	#define TEGRA114_CLK_TSEC 83
		105	/* 84 */
		106	/* 85 */
		107	/* 86 */
		108	/* 87 */
		109	/* 88 */
		110	#define TEGRA114_CLK_XUSB_HOST 89
		111	/* 90 */
		112	#define TEGRA114_CLK_MSENC 91
		113	#define TEGRA114_CLK_CSUS 92
		114	/* 93 */
		115	/* 94 */
		116	/* 95 (bit affects xusb_dev and xusb_dev_src) */
		117
		118	/* 96 */
		119	/* 97 */
		120	/* 98 */
		121	#define TEGRA114_CLK_MSELECT 99
		122	#define TEGRA114_CLK_TSENSOR 100
		123	#define TEGRA114_CLK_I2S3 101
		124	#define TEGRA114_CLK_I2S4 102
		125	#define TEGRA114_CLK_I2C4 103
		126	#define TEGRA114_CLK_SBC5 104
		127	#define TEGRA114_CLK_SBC6 105
		128	#define TEGRA114_CLK_D_AUDIO 106
		129	#define TEGRA114_CLK_APBIF 107
		130	#define TEGRA114_CLK_DAM0 108
		131	#define TEGRA114_CLK_DAM1 109
		132	#define TEGRA114_CLK_DAM2 110
		133	#define TEGRA114_CLK_HDA2CODEC_2X 111
		134	/* 112 */
		135	#define TEGRA114_CLK_AUDIO0_2X 113
		136	#define TEGRA114_CLK_AUDIO1_2X 114
		137	#define TEGRA114_CLK_AUDIO2_2X 115
		138	#define TEGRA114_CLK_AUDIO3_2X 116
		139	#define TEGRA114_CLK_AUDIO4_2X 117
		140	#define TEGRA114_CLK_SPDIF_2X 118
		141	#define TEGRA114_CLK_ACTMON 119
		142	#define TEGRA114_CLK_EXTERN1 120
		143	#define TEGRA114_CLK_EXTERN2 121
		144	#define TEGRA114_CLK_EXTERN3 122
		145	/* 123 */
		146	/* 124 */
		147	#define TEGRA114_CLK_HDA 125
		148	/* 126 */
		149	#define TEGRA114_CLK_SE 127
		150
		151	#define TEGRA114_CLK_HDA2HDMI 128
		152	/* 129 */
		153	/* 130 */
		154	/* 131 */
		155	/* 132 */
		156	/* 133 */
		157	/* 134 */
		158	/* 135 */
		159	/* 136 */
		160	/* 137 */
		161	/* 138 */
		162	/* 139 */
		163	/* 140 */
		164	/* 141 */
		165	/* 142 */
		166	/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
		167	/* xusb_host_src and xusb_ss_src) */
		168	#define TEGRA114_CLK_CILAB 144
		169	#define TEGRA114_CLK_CILCD 145
		170	#define TEGRA114_CLK_CILE 146
		171	#define TEGRA114_CLK_DSIALP 147
		172	#define TEGRA114_CLK_DSIBLP 148
		173	/* 149 */
		174	#define TEGRA114_CLK_DDS 150
		175	/* 151 */
		176	#define TEGRA114_CLK_DP2 152
		177	#define TEGRA114_CLK_AMX 153
		178	#define TEGRA114_CLK_ADX 154
		179	/* 155 (bit affects dfll_ref and dfll_soc) */
		180	#define TEGRA114_CLK_XUSB_SS 156
		181	/* 157 */
		182	/* 158 */
		183	/* 159 */
		184
		185	/* 160 */
		186	/* 161 */
		187	/* 162 */
		188	/* 163 */
		189	/* 164 */
		190	/* 165 */
		191	/* 166 */
		192	/* 167 */
		193	/* 168 */
		194	/* 169 */
		195	/* 170 */
		196	/* 171 */
		197	/* 172 */
		198	/* 173 */
		199	/* 174 */
		200	/* 175 */
		201	/* 176 */
		202	/* 177 */
		203	/* 178 */
		204	/* 179 */
		205	/* 180 */
		206	/* 181 */
		207	/* 182 */
		208	/* 183 */
		209	/* 184 */
		210	/* 185 */
		211	/* 186 */
		212	/* 187 */
		213	/* 188 */
		214	/* 189 */
		215	/* 190 */
		216	/* 191 */
		217
		218	#define TEGRA114_CLK_UARTB 192
		219	#define TEGRA114_CLK_VFIR 193
		220	#define TEGRA114_CLK_SPDIF_IN 194
		221	#define TEGRA114_CLK_SPDIF_OUT 195
		222	#define TEGRA114_CLK_VI 196
		223	#define TEGRA114_CLK_VI_SENSOR 197
		224	#define TEGRA114_CLK_FUSE 198
		225	#define TEGRA114_CLK_FUSE_BURN 199
		226	#define TEGRA114_CLK_CLK_32K 200
		227	#define TEGRA114_CLK_CLK_M 201
		228	#define TEGRA114_CLK_CLK_M_DIV2 202
		229	#define TEGRA114_CLK_CLK_M_DIV4 203
		230	#define TEGRA114_CLK_PLL_REF 204
		231	#define TEGRA114_CLK_PLL_C 205
		232	#define TEGRA114_CLK_PLL_C_OUT1 206
		233	#define TEGRA114_CLK_PLL_C2 207
		234	#define TEGRA114_CLK_PLL_C3 208
		235	#define TEGRA114_CLK_PLL_M 209
		236	#define TEGRA114_CLK_PLL_M_OUT1 210
		237	#define TEGRA114_CLK_PLL_P 211
		238	#define TEGRA114_CLK_PLL_P_OUT1 212
		239	#define TEGRA114_CLK_PLL_P_OUT2 213
		240	#define TEGRA114_CLK_PLL_P_OUT3 214
		241	#define TEGRA114_CLK_PLL_P_OUT4 215
		242	#define TEGRA114_CLK_PLL_A 216
		243	#define TEGRA114_CLK_PLL_A_OUT0 217
		244	#define TEGRA114_CLK_PLL_D 218
		245	#define TEGRA114_CLK_PLL_D_OUT0 219
		246	#define TEGRA114_CLK_PLL_D2 220
		247	#define TEGRA114_CLK_PLL_D2_OUT0 221
		248	#define TEGRA114_CLK_PLL_U 222
		249	#define TEGRA114_CLK_PLL_U_480M 223
		250
		251	#define TEGRA114_CLK_PLL_U_60M 224
		252	#define TEGRA114_CLK_PLL_U_48M 225
		253	#define TEGRA114_CLK_PLL_U_12M 226
		254	#define TEGRA114_CLK_PLL_X 227
		255	#define TEGRA114_CLK_PLL_X_OUT0 228
		256	#define TEGRA114_CLK_PLL_RE_VCO 229
		257	#define TEGRA114_CLK_PLL_RE_OUT 230
		258	#define TEGRA114_CLK_PLL_E_OUT0 231
		259	#define TEGRA114_CLK_SPDIF_IN_SYNC 232
		260	#define TEGRA114_CLK_I2S0_SYNC 233
		261	#define TEGRA114_CLK_I2S1_SYNC 234
		262	#define TEGRA114_CLK_I2S2_SYNC 235
		263	#define TEGRA114_CLK_I2S3_SYNC 236
		264	#define TEGRA114_CLK_I2S4_SYNC 237
		265	#define TEGRA114_CLK_VIMCLK_SYNC 238
		266	#define TEGRA114_CLK_AUDIO0 239
		267	#define TEGRA114_CLK_AUDIO1 240
		268	#define TEGRA114_CLK_AUDIO2 241
		269	#define TEGRA114_CLK_AUDIO3 242
		270	#define TEGRA114_CLK_AUDIO4 243
		271	#define TEGRA114_CLK_SPDIF 244
		272	#define TEGRA114_CLK_CLK_OUT_1 245
		273	#define TEGRA114_CLK_CLK_OUT_2 246
		274	#define TEGRA114_CLK_CLK_OUT_3 247
		275	#define TEGRA114_CLK_BLINK 248
		276	/* 249 */
		277	/* 250 */
		278	/* 251 */
		279	#define TEGRA114_CLK_XUSB_HOST_SRC 252
		280	#define TEGRA114_CLK_XUSB_FALCON_SRC 253
		281	#define TEGRA114_CLK_XUSB_FS_SRC 254
		282	#define TEGRA114_CLK_XUSB_SS_SRC 255
		283
		284	#define TEGRA114_CLK_XUSB_DEV_SRC 256
		285	#define TEGRA114_CLK_XUSB_DEV 257
		286	#define TEGRA114_CLK_XUSB_HS_SRC 258
		287	#define TEGRA114_CLK_SCLK 259
		288	#define TEGRA114_CLK_HCLK 260
		289	#define TEGRA114_CLK_PCLK 261
		290	#define TEGRA114_CLK_CCLK_G 262
		291	#define TEGRA114_CLK_CCLK_LP 263
		292	/* 264 */
		293	/* 265 */
		294	/* 266 */
		295	/* 267 */
		296	/* 268 */
		297	/* 269 */
		298	/* 270 */
		299	/* 271 */
		300	/* 272 */
		301	/* 273 */
		302	/* 274 */
		303	/* 275 */
		304	/* 276 */
		305	/* 277 */
		306	/* 278 */
		307	/* 279 */
		308	/* 280 */
		309	/* 281 */
		310	/* 282 */
		311	/* 283 */
		312	/* 284 */
		313	/* 285 */
		314	/* 286 */
		315	/* 287 */
		316
		317	/* 288 */
		318	/* 289 */
		319	/* 290 */
		320	/* 291 */
		321	/* 292 */
		322	/* 293 */
		323	/* 294 */
		324	/* 295 */
		325	/* 296 */
		326	/* 297 */
		327	/* 298 */
		328	/* 299 */
		329	#define TEGRA114_CLK_AUDIO0_MUX 300
		330	#define TEGRA114_CLK_AUDIO1_MUX 301
		331	#define TEGRA114_CLK_AUDIO2_MUX 302
		332	#define TEGRA114_CLK_AUDIO3_MUX 303
		333	#define TEGRA114_CLK_AUDIO4_MUX 304
		334	#define TEGRA114_CLK_SPDIF_MUX 305
		335	#define TEGRA114_CLK_CLK_OUT_1_MUX 306
		336	#define TEGRA114_CLK_CLK_OUT_2_MUX 307
		337	#define TEGRA114_CLK_CLK_OUT_3_MUX 308
		338	#define TEGRA114_CLK_DSIA_MUX 309
		339	#define TEGRA114_CLK_DSIB_MUX 310
		340	#define TEGRA114_CLK_CLK_MAX 311
		341
		342	#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */