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-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt2
-rw-r--r--arch/arm64/boot/dts/mediatek/mt2712-evb.dts4
-rw-r--r--arch/arm64/boot/dts/mediatek/mt2712e.dtsi9
-rw-r--r--arch/arm64/boot/dts/mediatek/mt6380.dtsi86
-rw-r--r--arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts469
-rw-r--r--arch/arm64/boot/dts/mediatek/mt7622.dtsi675
8 files changed, 1243 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
index 6cc7840ff37a..8f5335b480ac 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
@@ -9,6 +9,7 @@ Required Properties:
9 - "mediatek,mt2701-ethsys", "syscon" 9 - "mediatek,mt2701-ethsys", "syscon"
10 - "mediatek,mt7622-ethsys", "syscon" 10 - "mediatek,mt7622-ethsys", "syscon"
11- #clock-cells: Must be 1 11- #clock-cells: Must be 1
12- #reset-cells: Must be 1
12 13
13The ethsys controller uses the common clk binding from 14The ethsys controller uses the common clk binding from
14Documentation/devicetree/bindings/clock/clock-bindings.txt 15Documentation/devicetree/bindings/clock/clock-bindings.txt
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
index d5d5f1227665..7fe5dc6097a6 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be: 8- compatible: Should be:
9 - "mediatek,mt7622-pciesys", "syscon" 9 - "mediatek,mt7622-pciesys", "syscon"
10- #clock-cells: Must be 1 10- #clock-cells: Must be 1
11- #reset-cells: Must be 1
11 12
12The PCIESYS controller uses the common clk binding from 13The PCIESYS controller uses the common clk binding from
13Documentation/devicetree/bindings/clock/clock-bindings.txt 14Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 {
19 compatible = "mediatek,mt7622-pciesys", "syscon"; 20 compatible = "mediatek,mt7622-pciesys", "syscon";
20 reg = <0 0x1a100800 0 0x1000>; 21 reg = <0 0x1a100800 0 0x1000>;
21 #clock-cells = <1>; 22 #clock-cells = <1>;
23 #reset-cells = <1>;
22}; 24};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
index 00760019da00..b8184da2508c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be: 8- compatible: Should be:
9 - "mediatek,mt7622-ssusbsys", "syscon" 9 - "mediatek,mt7622-ssusbsys", "syscon"
10- #clock-cells: Must be 1 10- #clock-cells: Must be 1
11- #reset-cells: Must be 1
11 12
12The SSUSBSYS controller uses the common clk binding from 13The SSUSBSYS controller uses the common clk binding from
13Documentation/devicetree/bindings/clock/clock-bindings.txt 14Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 {
19 compatible = "mediatek,mt7622-ssusbsys", "syscon"; 20 compatible = "mediatek,mt7622-ssusbsys", "syscon";
20 reg = <0 0x1a000000 0 0x1000>; 21 reg = <0 0x1a000000 0 0x1000>;
21 #clock-cells = <1>; 22 #clock-cells = <1>;
23 #reset-cells = <1>;
22}; 24};
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
index 10f9c76cd105..4ce9d6ca0bf7 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -41,6 +41,10 @@
41 41
42}; 42};
43 43
44&auxadc {
45 status = "okay";
46};
47
44&cpu0 { 48&cpu0 {
45 proc-supply = <&cpus_fixed_vproc0>; 49 proc-supply = <&cpus_fixed_vproc0>;
46}; 50};
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index fdf66f4fe7c3..9d88f41aefa0 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -289,6 +289,15 @@
289 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; 289 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
290 }; 290 };
291 291
292 auxadc: adc@11001000 {
293 compatible = "mediatek,mt2712-auxadc";
294 reg = <0 0x11001000 0 0x1000>;
295 clocks = <&pericfg CLK_PERI_AUXADC>;
296 clock-names = "main";
297 #io-channel-cells = <1>;
298 status = "disabled";
299 };
300
292 uart0: serial@11002000 { 301 uart0: serial@11002000 {
293 compatible = "mediatek,mt2712-uart", 302 compatible = "mediatek,mt2712-uart",
294 "mediatek,mt6577-uart"; 303 "mediatek,mt6577-uart";
diff --git a/arch/arm64/boot/dts/mediatek/mt6380.dtsi b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
new file mode 100644
index 000000000000..53b335d2de5f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
@@ -0,0 +1,86 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for MediaTek MT6380 regulator
4 *
5 * Copyright (c) 2018 MediaTek Inc.
6 * Author: Chenglin Xu <chenglin.xu@mediatek.com>
7 * Sean Wang <sean.wang@mediatek.com>
8 */
9
10&pwrap {
11 regulators {
12 compatible = "mediatek,mt6380-regulator";
13
14 mt6380_vcpu_reg: buck-vcore1 {
15 regulator-name = "vcore1";
16 regulator-min-microvolt = < 600000>;
17 regulator-max-microvolt = <1393750>;
18 regulator-ramp-delay = <6250>;
19 regulator-always-on;
20 regulator-boot-on;
21 };
22
23 mt6380_vcore_reg: buck-vcore {
24 regulator-name = "vcore";
25 regulator-min-microvolt = <600000>;
26 regulator-max-microvolt = <1393750>;
27 regulator-ramp-delay = <6250>;
28 regulator-always-on;
29 regulator-boot-on;
30 };
31
32 mt6380_vrf_reg: buck-vrf {
33 regulator-name = "vrf";
34 regulator-min-microvolt = <1200000>;
35 regulator-max-microvolt = <1575000>;
36 regulator-ramp-delay = <0>;
37 regulator-always-on;
38 regulator-boot-on;
39 };
40
41 mt6380_vm_reg: ldo-vm {
42 regulator-name = "vm";
43 regulator-min-microvolt = <1050000>;
44 regulator-max-microvolt = <1400000>;
45 regulator-ramp-delay = <0>;
46 regulator-always-on;
47 regulator-boot-on;
48 };
49
50 mt6380_va_reg: ldo-va {
51 regulator-name = "va";
52 regulator-min-microvolt = <2200000>;
53 regulator-max-microvolt = <3300000>;
54 regulator-ramp-delay = <0>;
55 regulator-always-on;
56 regulator-boot-on;
57 };
58
59 mt6380_vphy_reg: ldo-vphy {
60 regulator-name = "vphy";
61 regulator-min-microvolt = <1800000>;
62 regulator-max-microvolt = <1800000>;
63 regulator-ramp-delay = <0>;
64 regulator-always-on;
65 regulator-boot-on;
66 };
67
68 mt6380_vddr_reg: ldo-vddr {
69 regulator-name = "vddr";
70 regulator-min-microvolt = <1240000>;
71 regulator-max-microvolt = <1840000>;
72 regulator-ramp-delay = <0>;
73 regulator-always-on;
74 regulator-boot-on;
75 };
76
77 mt6380_vt_reg: ldo-vt {
78 regulator-name = "vt";
79 regulator-min-microvolt = <2200000>;
80 regulator-max-microvolt = <3300000>;
81 regulator-ramp-delay = <0>;
82 regulator-always-on;
83 regulator-boot-on;
84 };
85 };
86};
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index c08309df2cc7..45d8655ee423 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -7,7 +7,11 @@
7 */ 7 */
8 8
9/dts-v1/; 9/dts-v1/;
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/gpio/gpio.h>
12
10#include "mt7622.dtsi" 13#include "mt7622.dtsi"
14#include "mt6380.dtsi"
11 15
12/ { 16/ {
13 model = "MediaTek MT7622 RFB1 board"; 17 model = "MediaTek MT7622 RFB1 board";
@@ -17,11 +21,476 @@
17 bootargs = "console=ttyS0,115200n1"; 21 bootargs = "console=ttyS0,115200n1";
18 }; 22 };
19 23
24 cpus {
25 cpu@0 {
26 proc-supply = <&mt6380_vcpu_reg>;
27 sram-supply = <&mt6380_vm_reg>;
28 };
29
30 cpu@1 {
31 proc-supply = <&mt6380_vcpu_reg>;
32 sram-supply = <&mt6380_vm_reg>;
33 };
34 };
35
36 gpio-keys {
37 compatible = "gpio-keys-polled";
38 poll-interval = <100>;
39
40 factory {
41 label = "factory";
42 linux,code = <BTN_0>;
43 gpios = <&pio 0 0>;
44 };
45
46 wps {
47 label = "wps";
48 linux,code = <KEY_WPS_BUTTON>;
49 gpios = <&pio 102 0>;
50 };
51 };
52
20 memory { 53 memory {
21 reg = <0 0x40000000 0 0x3F000000>; 54 reg = <0 0x40000000 0 0x3F000000>;
22 }; 55 };
56
57 reg_1p8v: regulator-1p8v {
58 compatible = "regulator-fixed";
59 regulator-name = "fixed-1.8V";
60 regulator-min-microvolt = <1800000>;
61 regulator-max-microvolt = <1800000>;
62 regulator-always-on;
63 };
64
65 reg_3p3v: regulator-3p3v {
66 compatible = "regulator-fixed";
67 regulator-name = "fixed-3.3V";
68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <3300000>;
70 regulator-boot-on;
71 regulator-always-on;
72 };
73
74 reg_5v: regulator-5v {
75 compatible = "regulator-fixed";
76 regulator-name = "fixed-5V";
77 regulator-min-microvolt = <5000000>;
78 regulator-max-microvolt = <5000000>;
79 regulator-boot-on;
80 regulator-always-on;
81 };
82};
83
84&pcie {
85 pinctrl-names = "default";
86 pinctrl-0 = <&pcie0_pins>;
87 status = "okay";
88
89 pcie@0,0 {
90 status = "okay";
91 };
92};
93
94&pio {
95 /* eMMC is shared pin with parallel NAND */
96 emmc_pins_default: emmc-pins-default {
97 mux {
98 function = "emmc", "emmc_rst";
99 groups = "emmc";
100 };
101
102 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
103 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
104 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
105 */
106 conf-cmd-dat {
107 pins = "NDL0", "NDL1", "NDL2",
108 "NDL3", "NDL4", "NDL5",
109 "NDL6", "NDL7", "NRB";
110 input-enable;
111 bias-pull-up;
112 };
113
114 conf-clk {
115 pins = "NCLE";
116 bias-pull-down;
117 };
118 };
119
120 emmc_pins_uhs: emmc-pins-uhs {
121 mux {
122 function = "emmc";
123 groups = "emmc";
124 };
125
126 conf-cmd-dat {
127 pins = "NDL0", "NDL1", "NDL2",
128 "NDL3", "NDL4", "NDL5",
129 "NDL6", "NDL7", "NRB";
130 input-enable;
131 drive-strength = <4>;
132 bias-pull-up;
133 };
134
135 conf-clk {
136 pins = "NCLE";
137 drive-strength = <4>;
138 bias-pull-down;
139 };
140 };
141
142 eth_pins: eth-pins {
143 mux {
144 function = "eth";
145 groups = "mdc_mdio", "rgmii_via_gmac2";
146 };
147 };
148
149 i2c1_pins: i2c1-pins {
150 mux {
151 function = "i2c";
152 groups = "i2c1_0";
153 };
154 };
155
156 i2c2_pins: i2c2-pins {
157 mux {
158 function = "i2c";
159 groups = "i2c2_0";
160 };
161 };
162
163 i2s1_pins: i2s1-pins {
164 mux {
165 function = "i2s";
166 groups = "i2s_out_bclk_ws_mclk",
167 "i2s1_in_data",
168 "i2s1_out_data";
169 };
170 };
171
172 irrx_pins: irrx-pins {
173 mux {
174 function = "ir";
175 groups = "ir_1_rx";
176 };
177 };
178
179 irtx_pins: irtx-pins {
180 mux {
181 function = "ir";
182 groups = "ir_1_tx";
183 };
184 };
185
186 /* Parallel nand is shared pin with eMMC */
187 parallel_nand_pins: parallel-nand-pins {
188 mux {
189 function = "flash";
190 groups = "par_nand";
191 };
192 };
193
194 pcie0_pins: pcie0-pins {
195 mux {
196 function = "pcie";
197 groups = "pcie0_pad_perst",
198 "pcie0_1_waken",
199 "pcie0_1_clkreq";
200 };
201 };
202
203 pcie1_pins: pcie1-pins {
204 mux {
205 function = "pcie";
206 groups = "pcie1_pad_perst",
207 "pcie1_0_waken",
208 "pcie1_0_clkreq";
209 };
210 };
211
212 pmic_bus_pins: pmic-bus-pins {
213 mux {
214 function = "pmic";
215 groups = "pmic_bus";
216 };
217 };
218
219 pwm7_pins: pwm1-2-pins {
220 mux {
221 function = "pwm";
222 groups = "pwm_ch7_2";
223 };
224 };
225
226 wled_pins: wled-pins {
227 mux {
228 function = "led";
229 groups = "wled";
230 };
231 };
232
233 sd0_pins_default: sd0-pins-default {
234 mux {
235 function = "sd";
236 groups = "sd_0";
237 };
238
239 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
240 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
241 * DAT2, DAT3, CMD, CLK for SD respectively.
242 */
243 conf-cmd-data {
244 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
245 "I2S2_IN","I2S4_OUT";
246 input-enable;
247 drive-strength = <8>;
248 bias-pull-up;
249 };
250 conf-clk {
251 pins = "I2S3_OUT";
252 drive-strength = <12>;
253 bias-pull-down;
254 };
255 conf-cd {
256 pins = "TXD3";
257 bias-pull-up;
258 };
259 };
260
261 sd0_pins_uhs: sd0-pins-uhs {
262 mux {
263 function = "sd";
264 groups = "sd_0";
265 };
266
267 conf-cmd-data {
268 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
269 "I2S2_IN","I2S4_OUT";
270 input-enable;
271 bias-pull-up;
272 };
273
274 conf-clk {
275 pins = "I2S3_OUT";
276 bias-pull-down;
277 };
278 };
279
280 /* Serial NAND is shared pin with SPI-NOR */
281 serial_nand_pins: serial-nand-pins {
282 mux {
283 function = "flash";
284 groups = "snfi";
285 };
286 };
287
288 spic0_pins: spic0-pins {
289 mux {
290 function = "spi";
291 groups = "spic0_0";
292 };
293 };
294
295 spic1_pins: spic1-pins {
296 mux {
297 function = "spi";
298 groups = "spic1_0";
299 };
300 };
301
302 /* SPI-NOR is shared pin with serial NAND */
303 spi_nor_pins: spi-nor-pins {
304 mux {
305 function = "flash";
306 groups = "spi_nor";
307 };
308 };
309
310 /* serial NAND is shared pin with SPI-NOR */
311 serial_nand_pins: serial-nand-pins {
312 mux {
313 function = "flash";
314 groups = "snfi";
315 };
316 };
317
318 uart0_pins: uart0-pins {
319 mux {
320 function = "uart";
321 groups = "uart0_0_tx_rx" ;
322 };
323 };
324
325 uart2_pins: uart2-pins {
326 mux {
327 function = "uart";
328 groups = "uart2_1_tx_rx" ;
329 };
330 };
331
332 watchdog_pins: watchdog-pins {
333 mux {
334 function = "watchdog";
335 groups = "watchdog";
336 };
337 };
338};
339
340&bch {
341 status = "disabled";
342};
343
344&btif {
345 status = "okay";
346};
347
348&cir {
349 pinctrl-names = "default";
350 pinctrl-0 = <&irrx_pins>;
351 status = "okay";
352};
353
354&eth {
355 pinctrl-names = "default";
356 pinctrl-0 = <&eth_pins>;
357 status = "okay";
358
359 gmac1: mac@1 {
360 compatible = "mediatek,eth-mac";
361 reg = <1>;
362 phy-handle = <&phy5>;
363 };
364
365 mdio-bus {
366 #address-cells = <1>;
367 #size-cells = <0>;
368
369 phy5: ethernet-phy@5 {
370 reg = <5>;
371 phy-mode = "sgmii";
372 };
373 };
374};
375
376&i2c1 {
377 pinctrl-names = "default";
378 pinctrl-0 = <&i2c1_pins>;
379 status = "okay";
380};
381
382&i2c2 {
383 pinctrl-names = "default";
384 pinctrl-0 = <&i2c2_pins>;
385 status = "okay";
386};
387
388&mmc0 {
389 pinctrl-names = "default", "state_uhs";
390 pinctrl-0 = <&emmc_pins_default>;
391 pinctrl-1 = <&emmc_pins_uhs>;
392 status = "okay";
393 bus-width = <8>;
394 max-frequency = <50000000>;
395 cap-mmc-highspeed;
396 mmc-hs200-1_8v;
397 vmmc-supply = <&reg_3p3v>;
398 vqmmc-supply = <&reg_1p8v>;
399 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
400 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
401 non-removable;
402};
403
404&mmc1 {
405 pinctrl-names = "default", "state_uhs";
406 pinctrl-0 = <&sd0_pins_default>;
407 pinctrl-1 = <&sd0_pins_uhs>;
408 status = "okay";
409 bus-width = <4>;
410 max-frequency = <50000000>;
411 cap-sd-highspeed;
412 r_smpl = <1>;
413 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
414 vmmc-supply = <&reg_3p3v>;
415 vqmmc-supply = <&reg_3p3v>;
416 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
417 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
418};
419
420&nandc {
421 pinctrl-names = "default";
422 pinctrl-0 = <&parallel_nand_pins>;
423 status = "disabled";
424};
425
426&nor_flash {
427 pinctrl-names = "default";
428 pinctrl-0 = <&spi_nor_pins>;
429 status = "disabled";
430
431 flash@0 {
432 compatible = "jedec,spi-nor";
433 reg = <0>;
434 };
435};
436
437&pwm {
438 pinctrl-names = "default";
439 pinctrl-0 = <&pwm7_pins>;
440 status = "okay";
441};
442
443&pwrap {
444 pinctrl-names = "default";
445 pinctrl-0 = <&pmic_bus_pins>;
446
447 status = "okay";
448};
449
450&sata {
451 status = "okay";
452};
453
454&sata_phy {
455 status = "okay";
456};
457
458&spi0 {
459 pinctrl-names = "default";
460 pinctrl-0 = <&spic0_pins>;
461 status = "okay";
462};
463
464&spi1 {
465 pinctrl-names = "default";
466 pinctrl-0 = <&spic1_pins>;
467 status = "okay";
468};
469
470&ssusb {
471 vusb33-supply = <&reg_3p3v>;
472 vbus-supply = <&reg_5v>;
473 status = "okay";
474};
475
476&u3phy {
477 status = "okay";
23}; 478};
24 479
25&uart0 { 480&uart0 {
481 pinctrl-names = "default";
482 pinctrl-0 = <&uart0_pins>;
483 status = "okay";
484};
485
486&uart2 {
487 pinctrl-names = "default";
488 pinctrl-0 = <&uart2_pins>;
489 status = "okay";
490};
491
492&watchdog {
493 pinctrl-names = "default";
494 pinctrl-0 = <&watchdog_pins>;
26 status = "okay"; 495 status = "okay";
27}; 496};
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index b111fec2ed9d..e9d5130df8d1 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -8,6 +8,11 @@
8 8
9#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/clock/mt7622-clk.h>
12#include <dt-bindings/phy/phy.h>
13#include <dt-bindings/power/mt7622-power.h>
14#include <dt-bindings/reset/mt7622-reset.h>
15#include <dt-bindings/thermal/thermal.h>
11 16
12/ { 17/ {
13 compatible = "mediatek,mt7622"; 18 compatible = "mediatek,mt7622";
@@ -15,6 +20,50 @@
15 #address-cells = <2>; 20 #address-cells = <2>;
16 #size-cells = <2>; 21 #size-cells = <2>;
17 22
23 cpu_opp_table: opp-table {
24 compatible = "operating-points-v2";
25 opp-shared;
26 opp-300000000 {
27 opp-hz = /bits/ 64 <30000000>;
28 opp-microvolt = <950000>;
29 };
30
31 opp-437500000 {
32 opp-hz = /bits/ 64 <437500000>;
33 opp-microvolt = <1000000>;
34 };
35
36 opp-600000000 {
37 opp-hz = /bits/ 64 <600000000>;
38 opp-microvolt = <1050000>;
39 };
40
41 opp-812500000 {
42 opp-hz = /bits/ 64 <812500000>;
43 opp-microvolt = <1100000>;
44 };
45
46 opp-1025000000 {
47 opp-hz = /bits/ 64 <1025000000>;
48 opp-microvolt = <1150000>;
49 };
50
51 opp-1137500000 {
52 opp-hz = /bits/ 64 <1137500000>;
53 opp-microvolt = <1200000>;
54 };
55
56 opp-1262500000 {
57 opp-hz = /bits/ 64 <1262500000>;
58 opp-microvolt = <1250000>;
59 };
60
61 opp-1350000000 {
62 opp-hz = /bits/ 64 <1350000000>;
63 opp-microvolt = <1310000>;
64 };
65 };
66
18 cpus { 67 cpus {
19 #address-cells = <2>; 68 #address-cells = <2>;
20 #size-cells = <0>; 69 #size-cells = <0>;
@@ -23,6 +72,11 @@
23 device_type = "cpu"; 72 device_type = "cpu";
24 compatible = "arm,cortex-a53", "arm,armv8"; 73 compatible = "arm,cortex-a53", "arm,armv8";
25 reg = <0x0 0x0>; 74 reg = <0x0 0x0>;
75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
76 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
77 clock-names = "cpu", "intermediate";
78 operating-points-v2 = <&cpu_opp_table>;
79 #cooling-cells = <2>;
26 enable-method = "psci"; 80 enable-method = "psci";
27 clock-frequency = <1300000000>; 81 clock-frequency = <1300000000>;
28 }; 82 };
@@ -31,21 +85,26 @@
31 device_type = "cpu"; 85 device_type = "cpu";
32 compatible = "arm,cortex-a53", "arm,armv8"; 86 compatible = "arm,cortex-a53", "arm,armv8";
33 reg = <0x0 0x1>; 87 reg = <0x0 0x1>;
88 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
89 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
90 clock-names = "cpu", "intermediate";
91 operating-points-v2 = <&cpu_opp_table>;
34 enable-method = "psci"; 92 enable-method = "psci";
35 clock-frequency = <1300000000>; 93 clock-frequency = <1300000000>;
36 }; 94 };
37 }; 95 };
38 96
39 uart_clk: dummy25m { 97 pwrap_clk: dummy40m {
40 compatible = "fixed-clock"; 98 compatible = "fixed-clock";
99 clock-frequency = <40000000>;
41 #clock-cells = <0>; 100 #clock-cells = <0>;
42 clock-frequency = <25000000>;
43 }; 101 };
44 102
45 bus_clk: dummy280m { 103 clk25m: oscillator {
46 compatible = "fixed-clock"; 104 compatible = "fixed-clock";
47 #clock-cells = <0>; 105 #clock-cells = <0>;
48 clock-frequency = <280000000>; 106 clock-frequency = <25000000>;
107 clock-output-names = "clkxtal";
49 }; 108 };
50 109
51 psci { 110 psci {
@@ -65,6 +124,58 @@
65 }; 124 };
66 }; 125 };
67 126
127 thermal-zones {
128 cpu_thermal: cpu-thermal {
129 polling-delay-passive = <1000>;
130 polling-delay = <1000>;
131
132 thermal-sensors = <&thermal 0>;
133
134 trips {
135 cpu_passive: cpu-passive {
136 temperature = <47000>;
137 hysteresis = <2000>;
138 type = "passive";
139 };
140
141 cpu_active: cpu-active {
142 temperature = <67000>;
143 hysteresis = <2000>;
144 type = "active";
145 };
146
147 cpu_hot: cpu-hot {
148 temperature = <87000>;
149 hysteresis = <2000>;
150 type = "hot";
151 };
152
153 cpu-crit {
154 temperature = <107000>;
155 hysteresis = <2000>;
156 type = "critical";
157 };
158 };
159
160 cooling-maps {
161 map0 {
162 trip = <&cpu_passive>;
163 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
164 };
165
166 map1 {
167 trip = <&cpu_active>;
168 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
169 };
170
171 map2 {
172 trip = <&cpu_hot>;
173 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
174 };
175 };
176 };
177 };
178
68 timer { 179 timer {
69 compatible = "arm,armv8-timer"; 180 compatible = "arm,armv8-timer";
70 interrupt-parent = <&gic>; 181 interrupt-parent = <&gic>;
@@ -78,6 +189,58 @@
78 IRQ_TYPE_LEVEL_HIGH)>; 189 IRQ_TYPE_LEVEL_HIGH)>;
79 }; 190 };
80 191
192 infracfg: infracfg@10000000 {
193 compatible = "mediatek,mt7622-infracfg",
194 "syscon";
195 reg = <0 0x10000000 0 0x1000>;
196 #clock-cells = <1>;
197 #reset-cells = <1>;
198 };
199
200 pwrap: pwrap@10001000 {
201 compatible = "mediatek,mt7622-pwrap";
202 reg = <0 0x10001000 0 0x250>;
203 reg-names = "pwrap";
204 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
205 clock-names = "spi", "wrap";
206 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
207 reset-names = "pwrap";
208 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
209 status = "disabled";
210 };
211
212 pericfg: pericfg@10002000 {
213 compatible = "mediatek,mt7622-pericfg",
214 "syscon";
215 reg = <0 0x10002000 0 0x1000>;
216 #clock-cells = <1>;
217 #reset-cells = <1>;
218 };
219
220 scpsys: scpsys@10006000 {
221 compatible = "mediatek,mt7622-scpsys",
222 "syscon";
223 #power-domain-cells = <1>;
224 reg = <0 0x10006000 0 0x1000>;
225 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
226 <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
227 <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
228 <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
229 infracfg = <&infracfg>;
230 clocks = <&topckgen CLK_TOP_HIF_SEL>;
231 clock-names = "hif_sel";
232 };
233
234 cir: cir@10009000 {
235 compatible = "mediatek,mt7622-cir";
236 reg = <0 0x10009000 0 0x1000>;
237 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
238 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
239 <&topckgen CLK_TOP_AXI_SEL>;
240 clock-names = "clk", "bus";
241 status = "disabled";
242 };
243
81 sysirq: interrupt-controller@10200620 { 244 sysirq: interrupt-controller@10200620 {
82 compatible = "mediatek,mt7622-sysirq", 245 compatible = "mediatek,mt7622-sysirq",
83 "mediatek,mt6577-sysirq"; 246 "mediatek,mt6577-sysirq";
@@ -87,6 +250,62 @@
87 reg = <0 0x10200620 0 0x20>; 250 reg = <0 0x10200620 0 0x20>;
88 }; 251 };
89 252
253 efuse: efuse@10206000 {
254 compatible = "mediatek,mt7622-efuse",
255 "mediatek,efuse";
256 reg = <0 0x10206000 0 0x1000>;
257 #address-cells = <1>;
258 #size-cells = <1>;
259
260 thermal_calibration: calib@198 {
261 reg = <0x198 0xc>;
262 };
263 };
264
265 apmixedsys: apmixedsys@10209000 {
266 compatible = "mediatek,mt7622-apmixedsys",
267 "syscon";
268 reg = <0 0x10209000 0 0x1000>;
269 #clock-cells = <1>;
270 };
271
272 topckgen: topckgen@10210000 {
273 compatible = "mediatek,mt7622-topckgen",
274 "syscon";
275 reg = <0 0x10210000 0 0x1000>;
276 #clock-cells = <1>;
277 };
278
279 rng: rng@1020f000 {
280 compatible = "mediatek,mt7622-rng",
281 "mediatek,mt7623-rng";
282 reg = <0 0x1020f000 0 0x1000>;
283 clocks = <&infracfg CLK_INFRA_TRNG>;
284 clock-names = "rng";
285 };
286
287 pio: pinctrl@10211000 {
288 compatible = "mediatek,mt7622-pinctrl";
289 reg = <0 0x10211000 0 0x1000>;
290 gpio-controller;
291 #gpio-cells = <2>;
292 };
293
294 watchdog: watchdog@10212000 {
295 compatible = "mediatek,mt7622-wdt",
296 "mediatek,mt6589-wdt";
297 reg = <0 0x10212000 0 0x800>;
298 };
299
300 rtc: rtc@10212800 {
301 compatible = "mediatek,mt7622-rtc",
302 "mediatek,soc-rtc";
303 reg = <0 0x10212800 0 0x200>;
304 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
305 clocks = <&topckgen CLK_TOP_RTC>;
306 clock-names = "rtc";
307 };
308
90 gic: interrupt-controller@10300000 { 309 gic: interrupt-controller@10300000 {
91 compatible = "arm,gic-400"; 310 compatible = "arm,gic-400";
92 interrupt-controller; 311 interrupt-controller;
@@ -98,13 +317,459 @@
98 <0 0x10360000 0 0x2000>; 317 <0 0x10360000 0 0x2000>;
99 }; 318 };
100 319
320 auxadc: adc@11001000 {
321 compatible = "mediatek,mt7622-auxadc";
322 reg = <0 0x11001000 0 0x1000>;
323 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
324 clock-names = "main";
325 #io-channel-cells = <1>;
326 };
327
101 uart0: serial@11002000 { 328 uart0: serial@11002000 {
102 compatible = "mediatek,mt7622-uart", 329 compatible = "mediatek,mt7622-uart",
103 "mediatek,mt6577-uart"; 330 "mediatek,mt6577-uart";
104 reg = <0 0x11002000 0 0x400>; 331 reg = <0 0x11002000 0 0x400>;
105 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 332 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
106 clocks = <&uart_clk>, <&bus_clk>; 333 clocks = <&topckgen CLK_TOP_UART_SEL>,
334 <&pericfg CLK_PERI_UART1_PD>;
335 clock-names = "baud", "bus";
336 status = "disabled";
337 };
338
339 uart1: serial@11003000 {
340 compatible = "mediatek,mt7622-uart",
341 "mediatek,mt6577-uart";
342 reg = <0 0x11003000 0 0x400>;
343 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
344 clocks = <&topckgen CLK_TOP_UART_SEL>,
345 <&pericfg CLK_PERI_UART1_PD>;
346 clock-names = "baud", "bus";
347 status = "disabled";
348 };
349
350 uart2: serial@11004000 {
351 compatible = "mediatek,mt7622-uart",
352 "mediatek,mt6577-uart";
353 reg = <0 0x11004000 0 0x400>;
354 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
355 clocks = <&topckgen CLK_TOP_UART_SEL>,
356 <&pericfg CLK_PERI_UART2_PD>;
357 clock-names = "baud", "bus";
358 status = "disabled";
359 };
360
361 uart3: serial@11005000 {
362 compatible = "mediatek,mt7622-uart",
363 "mediatek,mt6577-uart";
364 reg = <0 0x11005000 0 0x400>;
365 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
366 clocks = <&topckgen CLK_TOP_UART_SEL>,
367 <&pericfg CLK_PERI_UART3_PD>;
368 clock-names = "baud", "bus";
369 status = "disabled";
370 };
371
372 pwm: pwm@11006000 {
373 compatible = "mediatek,mt7622-pwm";
374 reg = <0 0x11006000 0 0x1000>;
375 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
376 clocks = <&topckgen CLK_TOP_PWM_SEL>,
377 <&pericfg CLK_PERI_PWM_PD>,
378 <&pericfg CLK_PERI_PWM1_PD>,
379 <&pericfg CLK_PERI_PWM2_PD>,
380 <&pericfg CLK_PERI_PWM3_PD>,
381 <&pericfg CLK_PERI_PWM4_PD>,
382 <&pericfg CLK_PERI_PWM5_PD>,
383 <&pericfg CLK_PERI_PWM6_PD>;
384 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
385 "pwm5", "pwm6";
386 status = "disabled";
387 };
388
389 i2c0: i2c@11007000 {
390 compatible = "mediatek,mt7622-i2c";
391 reg = <0 0x11007000 0 0x90>,
392 <0 0x11000100 0 0x80>;
393 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
394 clock-div = <16>;
395 clocks = <&pericfg CLK_PERI_I2C0_PD>,
396 <&pericfg CLK_PERI_AP_DMA_PD>;
397 clock-names = "main", "dma";
398 #address-cells = <1>;
399 #size-cells = <0>;
400 status = "disabled";
401 };
402
403 i2c1: i2c@11008000 {
404 compatible = "mediatek,mt7622-i2c";
405 reg = <0 0x11008000 0 0x90>,
406 <0 0x11000180 0 0x80>;
407 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
408 clock-div = <16>;
409 clocks = <&pericfg CLK_PERI_I2C1_PD>,
410 <&pericfg CLK_PERI_AP_DMA_PD>;
411 clock-names = "main", "dma";
412 #address-cells = <1>;
413 #size-cells = <0>;
414 status = "disabled";
415 };
416
417 i2c2: i2c@11009000 {
418 compatible = "mediatek,mt7622-i2c";
419 reg = <0 0x11009000 0 0x90>,
420 <0 0x11000200 0 0x80>;
421 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
422 clock-div = <16>;
423 clocks = <&pericfg CLK_PERI_I2C2_PD>,
424 <&pericfg CLK_PERI_AP_DMA_PD>;
425 clock-names = "main", "dma";
426 #address-cells = <1>;
427 #size-cells = <0>;
428 status = "disabled";
429 };
430
431 spi0: spi@1100a000 {
432 compatible = "mediatek,mt7622-spi";
433 reg = <0 0x1100a000 0 0x100>;
434 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
435 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
436 <&topckgen CLK_TOP_SPI0_SEL>,
437 <&pericfg CLK_PERI_SPI0_PD>;
438 clock-names = "parent-clk", "sel-clk", "spi-clk";
439 #address-cells = <1>;
440 #size-cells = <0>;
441 status = "disabled";
442 };
443
444 thermal: thermal@1100b000 {
445 #thermal-sensor-cells = <1>;
446 compatible = "mediatek,mt7622-thermal";
447 reg = <0 0x1100b000 0 0x1000>;
448 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
449 clocks = <&pericfg CLK_PERI_THERM_PD>,
450 <&pericfg CLK_PERI_AUXADC_PD>;
451 clock-names = "therm", "auxadc";
452 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
453 reset-names = "therm";
454 mediatek,auxadc = <&auxadc>;
455 mediatek,apmixedsys = <&apmixedsys>;
456 nvmem-cells = <&thermal_calibration>;
457 nvmem-cell-names = "calibration-data";
458 };
459
460 btif: serial@1100c000 {
461 compatible = "mediatek,mt7622-btif",
462 "mediatek,mtk-btif";
463 reg = <0 0x1100c000 0 0x1000>;
464 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
465 clocks = <&pericfg CLK_PERI_BTIF_PD>;
466 clock-names = "main";
467 reg-shift = <2>;
468 reg-io-width = <4>;
469 status = "disabled";
470 };
471
472 nandc: nfi@1100d000 {
473 compatible = "mediatek,mt7622-nfc";
474 reg = <0 0x1100D000 0 0x1000>;
475 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
476 clocks = <&pericfg CLK_PERI_NFI_PD>,
477 <&pericfg CLK_PERI_SNFI_PD>;
478 clock-names = "nfi_clk", "pad_clk";
479 ecc-engine = <&bch>;
480 #address-cells = <1>;
481 #size-cells = <0>;
482 status = "disabled";
483 };
484
485 bch: ecc@1100e000 {
486 compatible = "mediatek,mt7622-ecc";
487 reg = <0 0x1100e000 0 0x1000>;
488 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
489 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
490 clock-names = "nfiecc_clk";
491 status = "disabled";
492 };
493
494 nor_flash: spi@11014000 {
495 compatible = "mediatek,mt7622-nor",
496 "mediatek,mt8173-nor";
497 reg = <0 0x11014000 0 0xe0>;
498 clocks = <&pericfg CLK_PERI_FLASH_PD>,
499 <&topckgen CLK_TOP_FLASH_SEL>;
500 clock-names = "spi", "sf";
501 #address-cells = <1>;
502 #size-cells = <0>;
503 status = "disabled";
504 };
505
506 spi1: spi@11016000 {
507 compatible = "mediatek,mt7622-spi";
508 reg = <0 0x11016000 0 0x100>;
509 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
510 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
511 <&topckgen CLK_TOP_SPI1_SEL>,
512 <&pericfg CLK_PERI_SPI1_PD>;
513 clock-names = "parent-clk", "sel-clk", "spi-clk";
514 #address-cells = <1>;
515 #size-cells = <0>;
516 status = "disabled";
517 };
518
519 uart4: serial@11019000 {
520 compatible = "mediatek,mt7622-uart",
521 "mediatek,mt6577-uart";
522 reg = <0 0x11019000 0 0x400>;
523 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
524 clocks = <&topckgen CLK_TOP_UART_SEL>,
525 <&pericfg CLK_PERI_UART4_PD>;
107 clock-names = "baud", "bus"; 526 clock-names = "baud", "bus";
108 status = "disabled"; 527 status = "disabled";
109 }; 528 };
529
530 mmc0: mmc@11230000 {
531 compatible = "mediatek,mt7622-mmc";
532 reg = <0 0x11230000 0 0x1000>;
533 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
534 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
535 <&topckgen CLK_TOP_MSDC50_0_SEL>;
536 clock-names = "source", "hclk";
537 status = "disabled";
538 };
539
540 mmc1: mmc@11240000 {
541 compatible = "mediatek,mt7622-mmc";
542 reg = <0 0x11240000 0 0x1000>;
543 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
544 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
545 <&topckgen CLK_TOP_AXI_SEL>;
546 clock-names = "source", "hclk";
547 status = "disabled";
548 };
549
550 ssusbsys: ssusbsys@1a000000 {
551 compatible = "mediatek,mt7622-ssusbsys",
552 "syscon";
553 reg = <0 0x1a000000 0 0x1000>;
554 #clock-cells = <1>;
555 #reset-cells = <1>;
556 };
557
558 ssusb: usb@1a0c0000 {
559 compatible = "mediatek,mt7622-xhci",
560 "mediatek,mtk-xhci";
561 reg = <0 0x1a0c0000 0 0x01000>,
562 <0 0x1a0c4700 0 0x0100>;
563 reg-names = "mac", "ippc";
564 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
565 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
566 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
567 <&ssusbsys CLK_SSUSB_REF_EN>,
568 <&ssusbsys CLK_SSUSB_MCU_EN>,
569 <&ssusbsys CLK_SSUSB_DMA_EN>;
570 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
571 phys = <&u2port0 PHY_TYPE_USB2>,
572 <&u3port0 PHY_TYPE_USB3>,
573 <&u2port1 PHY_TYPE_USB2>;
574
575 status = "disabled";
576 };
577
578 u3phy: usb-phy@1a0c4000 {
579 compatible = "mediatek,mt7622-u3phy",
580 "mediatek,generic-tphy-v1";
581 reg = <0 0x1a0c4000 0 0x700>;
582 #address-cells = <2>;
583 #size-cells = <2>;
584 ranges;
585 status = "disabled";
586
587 u2port0: usb-phy@1a0c4800 {
588 reg = <0 0x1a0c4800 0 0x0100>;
589 #phy-cells = <1>;
590 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
591 clock-names = "ref";
592 };
593
594 u3port0: usb-phy@1a0c4900 {
595 reg = <0 0x1a0c4900 0 0x0700>;
596 #phy-cells = <1>;
597 clocks = <&clk25m>;
598 clock-names = "ref";
599 };
600
601 u2port1: usb-phy@1a0c5000 {
602 reg = <0 0x1a0c5000 0 0x0100>;
603 #phy-cells = <1>;
604 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
605 clock-names = "ref";
606 };
607 };
608
609 pciesys: pciesys@1a100800 {
610 compatible = "mediatek,mt7622-pciesys",
611 "syscon";
612 reg = <0 0x1a100800 0 0x1000>;
613 #clock-cells = <1>;
614 #reset-cells = <1>;
615 };
616
617 pcie: pcie@1a140000 {
618 compatible = "mediatek,mt7622-pcie";
619 device_type = "pci";
620 reg = <0 0x1a140000 0 0x1000>,
621 <0 0x1a143000 0 0x1000>,
622 <0 0x1a145000 0 0x1000>;
623 reg-names = "subsys", "port0", "port1";
624 #address-cells = <3>;
625 #size-cells = <2>;
626 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
627 <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
628 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
629 <&pciesys CLK_PCIE_P1_MAC_EN>,
630 <&pciesys CLK_PCIE_P0_AHB_EN>,
631 <&pciesys CLK_PCIE_P0_AHB_EN>,
632 <&pciesys CLK_PCIE_P0_AUX_EN>,
633 <&pciesys CLK_PCIE_P1_AUX_EN>,
634 <&pciesys CLK_PCIE_P0_AXI_EN>,
635 <&pciesys CLK_PCIE_P1_AXI_EN>,
636 <&pciesys CLK_PCIE_P0_OBFF_EN>,
637 <&pciesys CLK_PCIE_P1_OBFF_EN>,
638 <&pciesys CLK_PCIE_P0_PIPE_EN>,
639 <&pciesys CLK_PCIE_P1_PIPE_EN>;
640 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
641 "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
642 "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
643 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
644 bus-range = <0x00 0xff>;
645 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
646 status = "disabled";
647
648 pcie0: pcie@0,0 {
649 reg = <0x0000 0 0 0 0>;
650 #address-cells = <3>;
651 #size-cells = <2>;
652 #interrupt-cells = <1>;
653 ranges;
654 status = "disabled";
655
656 num-lanes = <1>;
657 interrupt-map-mask = <0 0 0 7>;
658 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
659 <0 0 0 2 &pcie_intc0 1>,
660 <0 0 0 3 &pcie_intc0 2>,
661 <0 0 0 4 &pcie_intc0 3>;
662 pcie_intc0: interrupt-controller {
663 interrupt-controller;
664 #address-cells = <0>;
665 #interrupt-cells = <1>;
666 };
667 };
668
669 pcie1: pcie@1,0 {
670 reg = <0x0800 0 0 0 0>;
671 #address-cells = <3>;
672 #size-cells = <2>;
673 #interrupt-cells = <1>;
674 ranges;
675 status = "disabled";
676
677 num-lanes = <1>;
678 interrupt-map-mask = <0 0 0 7>;
679 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
680 <0 0 0 2 &pcie_intc1 1>,
681 <0 0 0 3 &pcie_intc1 2>,
682 <0 0 0 4 &pcie_intc1 3>;
683 pcie_intc1: interrupt-controller {
684 interrupt-controller;
685 #address-cells = <0>;
686 #interrupt-cells = <1>;
687 };
688 };
689 };
690
691 sata: sata@1a200000 {
692 compatible = "mediatek,mt7622-ahci",
693 "mediatek,mtk-ahci";
694 reg = <0 0x1a200000 0 0x1100>;
695 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
696 interrupt-names = "hostc";
697 clocks = <&pciesys CLK_SATA_AHB_EN>,
698 <&pciesys CLK_SATA_AXI_EN>,
699 <&pciesys CLK_SATA_ASIC_EN>,
700 <&pciesys CLK_SATA_RBC_EN>,
701 <&pciesys CLK_SATA_PM_EN>;
702 clock-names = "ahb", "axi", "asic", "rbc", "pm";
703 phys = <&sata_port PHY_TYPE_SATA>;
704 phy-names = "sata-phy";
705 ports-implemented = <0x1>;
706 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
707 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
708 <&pciesys MT7622_SATA_PHY_SW_RST>,
709 <&pciesys MT7622_SATA_PHY_REG_RST>;
710 reset-names = "axi", "sw", "reg";
711 mediatek,phy-mode = <&pciesys>;
712 status = "disabled";
713 };
714
715 sata_phy: sata-phy@1a243000 {
716 compatible = "mediatek,generic-tphy-v1";
717 #address-cells = <2>;
718 #size-cells = <2>;
719 ranges;
720 status = "disabled";
721
722 sata_port: sata-phy@1a243000 {
723 reg = <0 0x1a243000 0 0x0100>;
724 clocks = <&topckgen CLK_TOP_ETH_500M>;
725 clock-names = "ref";
726 #phy-cells = <1>;
727 };
728 };
729
730 ethsys: syscon@1b000000 {
731 compatible = "mediatek,mt7622-ethsys",
732 "syscon";
733 reg = <0 0x1b000000 0 0x1000>;
734 #clock-cells = <1>;
735 #reset-cells = <1>;
736 };
737
738 eth: ethernet@1b100000 {
739 compatible = "mediatek,mt7622-eth",
740 "mediatek,mt2701-eth",
741 "syscon";
742 reg = <0 0x1b100000 0 0x20000>;
743 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
744 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
745 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
746 clocks = <&topckgen CLK_TOP_ETH_SEL>,
747 <&ethsys CLK_ETH_ESW_EN>,
748 <&ethsys CLK_ETH_GP0_EN>,
749 <&ethsys CLK_ETH_GP1_EN>,
750 <&ethsys CLK_ETH_GP2_EN>,
751 <&sgmiisys CLK_SGMII_TX250M_EN>,
752 <&sgmiisys CLK_SGMII_RX250M_EN>,
753 <&sgmiisys CLK_SGMII_CDR_REF>,
754 <&sgmiisys CLK_SGMII_CDR_FB>,
755 <&topckgen CLK_TOP_SGMIIPLL>,
756 <&apmixedsys CLK_APMIXED_ETH2PLL>;
757 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
758 "sgmii_tx250m", "sgmii_rx250m",
759 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
760 "eth2pll";
761 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
762 mediatek,ethsys = <&ethsys>;
763 mediatek,sgmiisys = <&sgmiisys>;
764 #address-cells = <1>;
765 #size-cells = <0>;
766 status = "disabled";
767 };
768
769 sgmiisys: sgmiisys@1b128000 {
770 compatible = "mediatek,mt7622-sgmiisys",
771 "syscon";
772 reg = <0 0x1b128000 0 0x1000>;
773 #clock-cells = <1>;
774 };
110}; 775};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 17:07:40 -0400