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-rw-r--r--Documentation/devicetree/bindings/arm/atmel-aic.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/atmel-at91.txt3
-rw-r--r--Documentation/devicetree/bindings/clock/at91-clock.txt339
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/animeo_ip.dts31
-rw-r--r--arch/arm/boot/dts/at91-cosino.dtsi122
-rw-r--r--arch/arm/boot/dts/at91-cosino_mega2560.dts84
-rw-r--r--arch/arm/boot/dts/at91rm9200.dtsi4
-rw-r--r--arch/arm/boot/dts/at91rm9200ek.dts57
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi37
-rw-r--r--arch/arm/boot/dts/at91sam9263ek.dts30
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi67
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts29
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi405
-rw-r--r--arch/arm/boot/dts/sama5d3_can.dtsi20
-rw-r--r--arch/arm/boot/dts/sama5d3_emac.dtsi11
-rw-r--r--arch/arm/boot/dts/sama5d3_gmac.dtsi11
-rw-r--r--arch/arm/boot/dts/sama5d3_lcd.dtsi17
-rw-r--r--arch/arm/boot/dts/sama5d3_mci2.dtsi12
-rw-r--r--arch/arm/boot/dts/sama5d3_tcb1.dtsi12
-rw-r--r--arch/arm/boot/dts/sama5d3_uart.dtsi26
-rw-r--r--arch/arm/boot/dts/sama5d3xcm.dtsi17
-rw-r--r--arch/arm/boot/dts/sama5d3xdm.dtsi1
-rw-r--r--arch/arm/mach-at91/Kconfig43
-rw-r--r--arch/arm/mach-at91/Kconfig.non_dt6
-rw-r--r--arch/arm/mach-at91/Makefile2
-rw-r--r--arch/arm/mach-at91/at91rm9200.c2
-rw-r--r--arch/arm/mach-at91/at91sam9260.c2
-rw-r--r--arch/arm/mach-at91/at91sam9261.c2
-rw-r--r--arch/arm/mach-at91/at91sam9263.c2
-rw-r--r--arch/arm/mach-at91/at91sam926x_time.c14
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c2
-rw-r--r--arch/arm/mach-at91/at91sam9n12.c2
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c2
-rw-r--r--arch/arm/mach-at91/at91sam9x5.c2
-rw-r--r--arch/arm/mach-at91/board-dt-sama5.c10
-rw-r--r--arch/arm/mach-at91/clock.c7
-rw-r--r--arch/arm/mach-at91/generic.h3
-rw-r--r--arch/arm/mach-at91/pm.c2
-rw-r--r--arch/arm/mach-at91/pm_slowclock.S2
-rw-r--r--arch/arm/mach-at91/sama5d3.c344
-rw-r--r--arch/arm/mach-at91/setup.c8
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/at91/Makefile12
-rw-r--r--drivers/clk/at91/clk-main.c187
-rw-r--r--drivers/clk/at91/clk-master.c270
-rw-r--r--drivers/clk/at91/clk-peripheral.c410
-rw-r--r--drivers/clk/at91/clk-pll.c531
-rw-r--r--drivers/clk/at91/clk-plldiv.c135
-rw-r--r--drivers/clk/at91/clk-programmable.c366
-rw-r--r--drivers/clk/at91/clk-smd.c171
-rw-r--r--drivers/clk/at91/clk-system.c135
-rw-r--r--drivers/clk/at91/clk-usb.c398
-rw-r--r--drivers/clk/at91/clk-utmi.c159
-rw-r--r--drivers/clk/at91/pmc.c397
-rw-r--r--drivers/clk/at91/pmc.h116
-rw-r--r--drivers/usb/gadget/atmel_usba_udc.c2
-rw-r--r--include/dt-bindings/clk/at91.h22
-rw-r--r--include/linux/clk/at91_pmc.h (renamed from arch/arm/mach-at91/include/mach/at91_pmc.h)4
59 files changed, 4694 insertions, 416 deletions
diff --git a/Documentation/devicetree/bindings/arm/atmel-aic.txt b/Documentation/devicetree/bindings/arm/atmel-aic.txt
index ad031211b5b8..2742e9cfd6b1 100644
--- a/Documentation/devicetree/bindings/arm/atmel-aic.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-aic.txt
@@ -2,6 +2,7 @@
2 2
3Required properties: 3Required properties:
4- compatible: Should be "atmel,<chip>-aic" 4- compatible: Should be "atmel,<chip>-aic"
5 <chip> can be "at91rm9200" or "sama5d3"
5- interrupt-controller: Identifies the node as an interrupt controller. 6- interrupt-controller: Identifies the node as an interrupt controller.
6- interrupt-parent: For single AIC system, it is an empty property. 7- interrupt-parent: For single AIC system, it is an empty property.
7- #interrupt-cells: The number of cells to define the interrupts. It should be 3. 8- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 1196290082d1..d2170e780f0b 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -50,7 +50,8 @@ Example:
50 }; 50 };
51 51
52RAMC SDRAM/DDR Controller required properties: 52RAMC SDRAM/DDR Controller required properties:
53- compatible: Should be "atmel,at91sam9260-sdramc", 53- compatible: Should be "atmel,at91rm9200-sdramc",
54 "atmel,at91sam9260-sdramc",
54 "atmel,at91sam9g45-ddramc", 55 "atmel,at91sam9g45-ddramc",
55- reg: Should contain registers location and length 56- reg: Should contain registers location and length
56 For at91sam9263 and at91sam9g45 you must specify 2 entries. 57 For at91sam9263 and at91sam9g45 you must specify 2 entries.
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt
new file mode 100644
index 000000000000..cd5e23912888
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/at91-clock.txt
@@ -0,0 +1,339 @@
1Device Tree Clock bindings for arch-at91
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be one of the following:
9 "atmel,at91rm9200-pmc" or
10 "atmel,at91sam9g45-pmc" or
11 "atmel,at91sam9n12-pmc" or
12 "atmel,at91sam9x5-pmc" or
13 "atmel,sama5d3-pmc":
14 at91 PMC (Power Management Controller)
15 All at91 specific clocks (clocks defined below) must be child
16 node of the PMC node.
17
18 "atmel,at91rm9200-clk-main":
19 at91 main oscillator
20
21 "atmel,at91rm9200-clk-master" or
22 "atmel,at91sam9x5-clk-master":
23 at91 master clock
24
25 "atmel,at91sam9x5-clk-peripheral" or
26 "atmel,at91rm9200-clk-peripheral":
27 at91 peripheral clocks
28
29 "atmel,at91rm9200-clk-pll" or
30 "atmel,at91sam9g45-clk-pll" or
31 "atmel,at91sam9g20-clk-pllb" or
32 "atmel,sama5d3-clk-pll":
33 at91 pll clocks
34
35 "atmel,at91sam9x5-clk-plldiv":
36 at91 plla divisor
37
38 "atmel,at91rm9200-clk-programmable" or
39 "atmel,at91sam9g45-clk-programmable" or
40 "atmel,at91sam9x5-clk-programmable":
41 at91 programmable clocks
42
43 "atmel,at91sam9x5-clk-smd":
44 at91 SMD (Soft Modem) clock
45
46 "atmel,at91rm9200-clk-system":
47 at91 system clocks
48
49 "atmel,at91rm9200-clk-usb" or
50 "atmel,at91sam9x5-clk-usb" or
51 "atmel,at91sam9n12-clk-usb":
52 at91 usb clock
53
54 "atmel,at91sam9x5-clk-utmi":
55 at91 utmi clock
56
57Required properties for PMC node:
58- reg : defines the IO memory reserved for the PMC.
59- #size-cells : shall be 0 (reg is used to encode clk id).
60- #address-cells : shall be 1 (reg is used to encode clk id).
61- interrupts : shall be set to PMC interrupt line.
62- interrupt-controller : tell that the PMC is an interrupt controller.
63- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
64 and reflect the bit position in the PMC_ER/DR/SR registers.
65 You can use the dt macros defined in dt-bindings/clk/at91.h.
66 0 (AT91_PMC_MOSCS) -> main oscillator ready
67 1 (AT91_PMC_LOCKA) -> PLL A ready
68 2 (AT91_PMC_LOCKB) -> PLL B ready
69 3 (AT91_PMC_MCKRDY) -> master clock ready
70 6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready
71 8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready
72 16 (AT91_PMC_MOSCSELS) -> main oscillator selected
73 17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized
74 18 (AT91_PMC_CFDEV) -> clock failure detected
75
76For example:
77 pmc: pmc@fffffc00 {
78 compatible = "atmel,sama5d3-pmc";
79 interrupts = <1 4 7>;
80 interrupt-controller;
81 #interrupt-cells = <2>;
82 #size-cells = <0>;
83 #address-cells = <1>;
84
85 /* put at91 clocks here */
86 };
87
88Required properties for main clock:
89- interrupt-parent : must reference the PMC node.
90- interrupts : shall be set to "<0>".
91- #clock-cells : from common clock binding; shall be set to 0.
92- clocks (optional if clock-frequency is provided) : shall be the slow clock
93 phandle. This clock is used to calculate the main clock rate if
94 "clock-frequency" is not provided.
95- clock-frequency : the main oscillator frequency.Prefer the use of
96 "clock-frequency" over automatic clock rate calculation.
97
98For example:
99 main: mainck {
100 compatible = "atmel,at91rm9200-clk-main";
101 interrupt-parent = <&pmc>;
102 interrupts = <0>;
103 #clock-cells = <0>;
104 clocks = <&ck32k>;
105 clock-frequency = <18432000>;
106 };
107
108Required properties for master clock:
109- interrupt-parent : must reference the PMC node.
110- interrupts : shall be set to "<3>".
111- #clock-cells : from common clock binding; shall be set to 0.
112- clocks : shall be the master clock sources (see atmel datasheet) phandles.
113 e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
114- atmel,clk-output-range : minimum and maximum clock frequency (two u32
115 fields).
116 e.g. output = <0 133000000>; <=> 0 to 133MHz.
117- atmel,clk-divisors : master clock divisors table (four u32 fields).
118 0 <=> reserved value.
119 e.g. divisors = <1 2 4 6>;
120- atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the
121 PRES field as CLOCK_DIV3 (e.g sam9x5).
122
123For example:
124 mck: mck {
125 compatible = "atmel,at91rm9200-clk-master";
126 interrupt-parent = <&pmc>;
127 interrupts = <3>;
128 #clock-cells = <0>;
129 atmel,clk-output-range = <0 133000000>;
130 atmel,clk-divisors = <1 2 4 0>;
131 };
132
133Required properties for peripheral clocks:
134- #size-cells : shall be 0 (reg is used to encode clk id).
135- #address-cells : shall be 1 (reg is used to encode clk id).
136- clocks : shall be the master clock phandle.
137 e.g. clocks = <&mck>;
138- name: device tree node describing a specific system clock.
139 * #clock-cells : from common clock binding; shall be set to 0.
140 * reg: peripheral id. See Atmel's datasheets to get a full
141 list of peripheral ids.
142 * atmel,clk-output-range : minimum and maximum clock frequency
143 (two u32 fields). Only valid on at91sam9x5-clk-peripheral
144 compatible IPs.
145
146For example:
147 periph: periphck {
148 compatible = "atmel,at91sam9x5-clk-peripheral";
149 #size-cells = <0>;
150 #address-cells = <1>;
151 clocks = <&mck>;
152
153 ssc0_clk {
154 #clock-cells = <0>;
155 reg = <2>;
156 atmel,clk-output-range = <0 133000000>;
157 };
158
159 usart0_clk {
160 #clock-cells = <0>;
161 reg = <3>;
162 atmel,clk-output-range = <0 66000000>;
163 };
164 };
165
166
167Required properties for pll clocks:
168- interrupt-parent : must reference the PMC node.
169- interrupts : shall be set to "<1>".
170- #clock-cells : from common clock binding; shall be set to 0.
171- clocks : shall be the main clock phandle.
172- reg : pll id.
173 0 -> PLL A
174 1 -> PLL B
175- atmel,clk-input-range : minimum and maximum source clock frequency (two u32
176 fields).
177 e.g. input = <1 32000000>; <=> 1 to 32MHz.
178- #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
179 range description. Sould be set to 2, 3
180 or 4.
181 * 1st and 2nd cells represent the frequency range (min-max).
182 * 3rd cell is optional and represents the OUT field value for the given
183 range.
184 * 4th cell is optional and represents the ICPLL field (PLLICPR
185 register)
186- atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
187 depending on #atmel,pll-output-range-cells
188 property value.
189
190For example:
191 plla: pllack {
192 compatible = "atmel,at91sam9g45-clk-pll";
193 interrupt-parent = <&pmc>;
194 interrupts = <1>;
195 #clock-cells = <0>;
196 clocks = <&main>;
197 reg = <0>;
198 atmel,clk-input-range = <2000000 32000000>;
199 #atmel,pll-clk-output-range-cells = <4>;
200 atmel,pll-clk-output-ranges = <74500000 800000000 0 0
201 69500000 750000000 1 0
202 64500000 700000000 2 0
203 59500000 650000000 3 0
204 54500000 600000000 0 1
205 49500000 550000000 1 1
206 44500000 500000000 2 1
207 40000000 450000000 3 1>;
208 };
209
210Required properties for plldiv clocks (plldiv = pll / 2):
211- #clock-cells : from common clock binding; shall be set to 0.
212- clocks : shall be the plla clock phandle.
213
214The pll divisor is equal to 2 and cannot be changed.
215
216For example:
217 plladiv: plladivck {
218 compatible = "atmel,at91sam9x5-clk-plldiv";
219 #clock-cells = <0>;
220 clocks = <&plla>;
221 };
222
223Required properties for programmable clocks:
224- interrupt-parent : must reference the PMC node.
225- #size-cells : shall be 0 (reg is used to encode clk id).
226- #address-cells : shall be 1 (reg is used to encode clk id).
227- clocks : shall be the programmable clock source phandles.
228 e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
229- name: device tree node describing a specific prog clock.
230 * #clock-cells : from common clock binding; shall be set to 0.
231 * reg : programmable clock id (register offset from PCKx
232 register).
233 * interrupts : shall be set to "<(8 + id)>".
234
235For example:
236 prog: progck {
237 compatible = "atmel,at91sam9g45-clk-programmable";
238 #size-cells = <0>;
239 #address-cells = <1>;
240 interrupt-parent = <&pmc>;
241 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
242
243 prog0 {
244 #clock-cells = <0>;
245 reg = <0>;
246 interrupts = <8>;
247 };
248
249 prog1 {
250 #clock-cells = <0>;
251 reg = <1>;
252 interrupts = <9>;
253 };
254 };
255
256
257Required properties for smd clock:
258- #clock-cells : from common clock binding; shall be set to 0.
259- clocks : shall be the smd clock source phandles.
260 e.g. clocks = <&plladiv>, <&utmi>;
261
262For example:
263 smd: smdck {
264 compatible = "atmel,at91sam9x5-clk-smd";
265 #clock-cells = <0>;
266 clocks = <&plladiv>, <&utmi>;
267 };
268
269Required properties for system clocks:
270- #size-cells : shall be 0 (reg is used to encode clk id).
271- #address-cells : shall be 1 (reg is used to encode clk id).
272- name: device tree node describing a specific system clock.
273 * #clock-cells : from common clock binding; shall be set to 0.
274 * reg: system clock id (bit position in SCER/SCDR/SCSR registers).
275 See Atmel's datasheet to get a full list of system clock ids.
276
277For example:
278 system: systemck {
279 compatible = "atmel,at91rm9200-clk-system";
280 #address-cells = <1>;
281 #size-cells = <0>;
282
283 ddrck {
284 #clock-cells = <0>;
285 reg = <2>;
286 clocks = <&mck>;
287 };
288
289 uhpck {
290 #clock-cells = <0>;
291 reg = <6>;
292 clocks = <&usb>;
293 };
294
295 udpck {
296 #clock-cells = <0>;
297 reg = <7>;
298 clocks = <&usb>;
299 };
300 };
301
302
303Required properties for usb clock:
304- #clock-cells : from common clock binding; shall be set to 0.
305- clocks : shall be the smd clock source phandles.
306 e.g. clocks = <&pllb>;
307- atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"):
308 usb clock divisor table.
309 e.g. divisors = <1 2 4 0>;
310
311For example:
312 usb: usbck {
313 compatible = "atmel,at91sam9x5-clk-usb";
314 #clock-cells = <0>;
315 clocks = <&plladiv>, <&utmi>;
316 };
317
318 usb: usbck {
319 compatible = "atmel,at91rm9200-clk-usb";
320 #clock-cells = <0>;
321 clocks = <&pllb>;
322 atmel,clk-divisors = <1 2 4 0>;
323 };
324
325
326Required properties for utmi clock:
327- interrupt-parent : must reference the PMC node.
328- interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>".
329- #clock-cells : from common clock binding; shall be set to 0.
330- clocks : shall be the main clock source phandle.
331
332For example:
333 utmi: utmick {
334 compatible = "atmel,at91sam9x5-clk-utmi";
335 interrupt-parent = <&pmc>;
336 interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>;
337 #clock-cells = <0>;
338 clocks = <&main>;
339 };
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a65b24f..772a30e06e48 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
30dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb 30dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
31# sam9x5 31# sam9x5
32dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb 32dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb
33dtb-$(CONFIG_ARCH_AT91) += at91-cosino_mega2560.dtb
33dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb 34dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
34dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb 35dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
35dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb 36dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index 3a1de9eb5111..3c4f6d983cbd 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -90,34 +90,19 @@
90 nand-on-flash-bbt; 90 nand-on-flash-bbt;
91 status = "okay"; 91 status = "okay";
92 92
93 at91bootstrap@0 { 93 barebox@0 {
94 label = "at91bootstrap";
95 reg = <0x0 0x8000>;
96 };
97
98 barebox@8000 {
99 label = "barebox"; 94 label = "barebox";
100 reg = <0x8000 0x40000>; 95 reg = <0x0 0x58000>;
101 };
102
103 bareboxenv@48000 {
104 label = "bareboxenv";
105 reg = <0x48000 0x8000>;
106 };
107
108 user_block@0x50000 {
109 label = "user_block";
110 reg = <0x50000 0xb0000>;
111 }; 96 };
112 97
113 kernel@100000 { 98 u_boot_env@58000 {
114 label = "kernel"; 99 label = "u_boot_env";
115 reg = <0x100000 0x1b0000>; 100 reg = <0x58000 0x8000>;
116 }; 101 };
117 102
118 root@2b0000 { 103 ubi@60000 {
119 label = "root"; 104 label = "ubi";
120 reg = <0x2b0000 0x1D50000>; 105 reg = <0x60000 0x1FA0000>;
121 }; 106 };
122 }; 107 };
123 108
diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi
new file mode 100644
index 000000000000..2093c4d7cd6a
--- /dev/null
+++ b/arch/arm/boot/dts/at91-cosino.dtsi
@@ -0,0 +1,122 @@
1/*
2 * at91-cosino.dtsi - Device Tree file for Cosino core module
3 *
4 * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it>
5 * HCE Engineering
6 *
7 * Derived from at91sam9x5ek.dtsi by:
8 * Copyright (C) 2012 Atmel,
9 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
10 *
11 * Licensed under GPLv2 or later.
12 */
13
14#include "at91sam9g35.dtsi"
15
16/ {
17 model = "HCE Cosino core module";
18 compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9";
19
20 chosen {
21 bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait";
22 };
23
24 memory {
25 reg = <0x20000000 0x8000000>;
26 };
27
28 clocks {
29 #address-cells = <1>;
30 #size-cells = <1>;
31 ranges;
32
33 main_clock: clock@0 {
34 compatible = "atmel,osc", "fixed-clock";
35 clock-frequency = <12000000>;
36 };
37 };
38
39 ahb {
40 apb {
41 mmc0: mmc@f0008000 {
42 pinctrl-0 = <
43 &pinctrl_board_mmc0
44 &pinctrl_mmc0_slot0_clk_cmd_dat0
45 &pinctrl_mmc0_slot0_dat1_3>;
46 status = "okay";
47 slot@0 {
48 reg = <0>;
49 bus-width = <4>;
50 cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
51 };
52 };
53
54 dbgu: serial@fffff200 {
55 status = "okay";
56 };
57
58 usart0: serial@f801c000 {
59 status = "okay";
60 };
61
62 i2c0: i2c@f8010000 {
63 status = "okay";
64 };
65
66 adc0: adc@f804c000 {
67 atmel,adc-clock-rate = <1000000>;
68 atmel,adc-ts-wires = <4>;
69 atmel,adc-ts-pressure-threshold = <10000>;
70 status = "okay";
71 };
72
73 pinctrl@fffff400 {
74 mmc0 {
75 pinctrl_board_mmc0: mmc0-board {
76 atmel,pins =
77 <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */
78 };
79 };
80 };
81
82 watchdog@fffffe40 {
83 status = "okay";
84 };
85 };
86
87 nand0: nand@40000000 {
88 nand-bus-width = <8>;
89 nand-ecc-mode = "hw";
90 atmel,has-pmecc; /* Enable PMECC */
91 atmel,pmecc-cap = <4>;
92 atmel,pmecc-sector-size = <512>;
93 nand-on-flash-bbt;
94 status = "okay";
95
96 at91bootstrap@0 {
97 label = "at91bootstrap";
98 reg = <0x0 0x40000>;
99 };
100
101 uboot@40000 {
102 label = "u-boot";
103 reg = <0x40000 0x80000>;
104 };
105
106 ubootenv@c0000 {
107 label = "U-Boot Env";
108 reg = <0xc0000 0x140000>;
109 };
110
111 kernel@200000 {
112 label = "kernel";
113 reg = <0x200000 0x600000>;
114 };
115
116 rootfs@800000 {
117 label = "rootfs";
118 reg = <0x800000 0x0f800000>;
119 };
120 };
121 };
122};
diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts
new file mode 100644
index 000000000000..f9415dd11f17
--- /dev/null
+++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts
@@ -0,0 +1,84 @@
1/*
2 * at91-cosino_mega2560.dts - Device Tree file for Cosino board with
3 * Mega 2560 extension
4 *
5 * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it>
6 * HCE Engineering
7 *
8 * Derived from at91sam9g35ek.dts by:
9 * Copyright (C) 2012 Atmel,
10 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
11 *
12 * Licensed under GPLv2 or later.
13 */
14
15/dts-v1/;
16#include "at91-cosino.dtsi"
17
18/ {
19 model = "HCE Cosino Mega 2560";
20 compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9";
21
22 ahb {
23 apb {
24 macb0: ethernet@f802c000 {
25 phy-mode = "rmii";
26 status = "okay";
27 };
28
29 adc0: adc@f804c000 {
30 atmel,adc-clock-rate = <1000000>;
31 atmel,adc-ts-wires = <4>;
32 atmel,adc-ts-pressure-threshold = <10000>;
33 status = "okay";
34 };
35
36
37 tsadcc: tsadcc@f804c000 {
38 status = "okay";
39 };
40
41 rtc@fffffeb0 {
42 status = "okay";
43 };
44
45 usart1: serial@f8020000 {
46 status = "okay";
47 };
48
49 usart2: serial@f8024000 {
50 status = "okay";
51 };
52
53 usb2: gadget@f803c000 {
54 atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
55 status = "okay";
56 };
57
58 mmc1: mmc@f000c000 {
59 pinctrl-0 = <
60 &pinctrl_mmc1_slot0_clk_cmd_dat0
61 &pinctrl_mmc1_slot0_dat1_3>;
62 status = "okay";
63 slot@0 {
64 reg = <0>;
65 bus-width = <4>;
66 non-removable;
67 };
68 };
69 };
70
71 usb0: ohci@00600000 {
72 status = "okay";
73 num-ports = <3>;
74 atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */
75 &pioD 19 GPIO_ACTIVE_LOW
76 &pioD 20 GPIO_ACTIVE_LOW
77 >;
78 };
79
80 usb1: ehci@00700000 {
81 status = "okay";
82 };
83 };
84};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index f77065506f1e..c61b16fba79b 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -191,12 +191,12 @@
191 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */ 191 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */
192 }; 192 };
193 193
194 pinctrl_uart0_rts: uart0_rts-0 { 194 pinctrl_uart0_cts: uart0_cts-0 {
195 atmel,pins = 195 atmel,pins =
196 <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */ 196 <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */
197 }; 197 };
198 198
199 pinctrl_uart0_cts: uart0_cts-0 { 199 pinctrl_uart0_rts: uart0_rts-0 {
200 atmel,pins = 200 atmel,pins =
201 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ 201 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
202 }; 202 };
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index d2d72c3b44c4..df6b0aa0e4dd 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -29,10 +29,22 @@
29 29
30 ahb { 30 ahb {
31 apb { 31 apb {
32 dbgu: serial@fffff200 { 32 usb1: gadget@fffb0000 {
33 atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
34 atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>;
33 status = "okay"; 35 status = "okay";
34 }; 36 };
35 37
38 macb0: ethernet@fffbc000 {
39 phy-mode = "rmii";
40 status = "okay";
41
42 phy0: ethernet-phy {
43 interrupt-parent = <&pioC>;
44 interrupts = <4 IRQ_TYPE_EDGE_BOTH>;
45 };
46 };
47
36 usart1: serial@fffc4000 { 48 usart1: serial@fffc4000 {
37 pinctrl-0 = 49 pinctrl-0 =
38 <&pinctrl_uart1 50 <&pinctrl_uart1
@@ -44,16 +56,6 @@
44 status = "okay"; 56 status = "okay";
45 }; 57 };
46 58
47 macb0: ethernet@fffbc000 {
48 phy-mode = "rmii";
49 status = "okay";
50 };
51
52 usb1: gadget@fffb0000 {
53 atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
54 status = "okay";
55 };
56
57 spi0: spi@fffe0000 { 59 spi0: spi@fffe0000 {
58 status = "okay"; 60 status = "okay";
59 cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; 61 cs-gpios = <&pioA 3 0>, <0>, <0>, <0>;
@@ -63,12 +65,45 @@
63 reg = <0>; 65 reg = <0>;
64 }; 66 };
65 }; 67 };
68
69 dbgu: serial@fffff200 {
70 status = "okay";
71 };
66 }; 72 };
67 73
68 usb0: ohci@00300000 { 74 usb0: ohci@00300000 {
69 num-ports = <2>; 75 num-ports = <2>;
70 status = "okay"; 76 status = "okay";
71 }; 77 };
78
79 nor_flash@10000000 {
80 compatible = "cfi-flash";
81 reg = <0x10000000 0x800000>;
82 linux,mtd-name = "physmap-flash.0";
83 bank-width = <2>;
84 #address-cells = <1>;
85 #size-cells = <1>;
86
87 barebox@0 {
88 label = "barebox";
89 reg = <0x00000 0x40000>;
90 };
91
92 bareboxenv@40000 {
93 label = "bareboxenv";
94 reg = <0x40000 0x10000>;
95 };
96
97 kernel@50000 {
98 label = "kernel";
99 reg = <0x50000 0x300000>;
100 };
101
102 root@350000 {
103 label = "root";
104 reg = <0x350000 0x4B0000>;
105 };
106 };
72 }; 107 };
73 108
74 leds { 109 leds {
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index d5bd65f74602..22e255ab6963 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -366,6 +366,34 @@
366 }; 366 };
367 }; 367 };
368 368
369 fb {
370 pinctrl_fb: fb-0 {
371 atmel,pins =
372 <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A */
373 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A */
374 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A */
375 AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB9 periph B */
376 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A */
377 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A */
378 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A */
379 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 periph A */
380 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 periph A */
381 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A */
382 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A */
383 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A */
384 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A */
385 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC12 periph B */
386 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC18 periph A */
387 AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A */
388 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A */
389 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A */
390 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC24 periph A */
391 AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC17 periph B */
392 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC26 periph A */
393 AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC27 periph A */
394 };
395 };
396
369 pioA: gpio@fffff200 { 397 pioA: gpio@fffff200 {
370 compatible = "atmel,at91rm9200-gpio"; 398 compatible = "atmel,at91rm9200-gpio";
371 reg = <0xfffff200 0x200>; 399 reg = <0xfffff200 0x200>;
@@ -549,6 +577,15 @@
549 }; 577 };
550 }; 578 };
551 579
580 fb0: fb@0x00700000 {
581 compatible = "atmel,at91sam9263-lcdc";
582 reg = <0x00700000 0x1000>;
583 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_fb>;
586 status = "disabled";
587 };
588
552 nand0: nand@40000000 { 589 nand0: nand@40000000 {
553 compatible = "atmel,at91rm9200-nand"; 590 compatible = "atmel,at91rm9200-nand";
554 #address-cells = <1>; 591 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 70f835b55c0b..15009c9f2293 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -95,6 +95,36 @@
95 }; 95 };
96 }; 96 };
97 97
98 fb0: fb@0x00700000 {
99 display = <&display0>;
100 status = "okay";
101
102 display0: display {
103 bits-per-pixel = <16>;
104 atmel,lcdcon-backlight;
105 atmel,dmacon = <0x1>;
106 atmel,lcdcon2 = <0x80008002>;
107 atmel,guard-time = <1>;
108
109 display-timings {
110 native-mode = <&timing0>;
111 timing0: timing0 {
112 clock-frequency = <4965000>;
113 hactive = <240>;
114 vactive = <320>;
115 hback-porch = <1>;
116 hfront-porch = <33>;
117 vback-porch = <1>;
118 vfront-porch = <0>;
119 hsync-len = <5>;
120 vsync-len = <1>;
121 hsync-active = <1>;
122 vsync-active = <1>;
123 };
124 };
125 };
126 };
127
98 nand0: nand@40000000 { 128 nand0: nand@40000000 {
99 nand-bus-width = <8>; 129 nand-bus-width = <8>;
100 nand-ecc-mode = "soft"; 130 nand-ecc-mode = "soft";
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index c3e514837074..d7af9ecb85d2 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -143,6 +143,22 @@
143 }; 143 };
144 }; 144 };
145 145
146 i2c0 {
147 pinctrl_i2c0: i2c0-0 {
148 atmel,pins =
149 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */
150 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */
151 };
152 };
153
154 i2c1 {
155 pinctrl_i2c1: i2c1-0 {
156 atmel,pins =
157 <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */
158 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */
159 };
160 };
161
146 usart0 { 162 usart0 {
147 pinctrl_usart0: usart0-0 { 163 pinctrl_usart0: usart0-0 {
148 atmel,pins = 164 atmel,pins =
@@ -425,6 +441,42 @@
425 }; 441 };
426 }; 442 };
427 443
444 fb {
445 pinctrl_fb: fb-0 {
446 atmel,pins =
447 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */
448 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */
449 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */
450 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */
451 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */
452 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */
453 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */
454 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */
455 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */
456 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */
457 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */
458 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */
459 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */
460 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */
461 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */
462 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */
463 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */
464 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */
465 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */
466 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */
467 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
468 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */
469 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
470 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
471 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
472 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
473 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
474 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
475 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
476 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
477 };
478 };
479
428 pioA: gpio@fffff200 { 480 pioA: gpio@fffff200 {
429 compatible = "atmel,at91rm9200-gpio"; 481 compatible = "atmel,at91rm9200-gpio";
430 reg = <0xfffff200 0x200>; 482 reg = <0xfffff200 0x200>;
@@ -542,6 +594,8 @@
542 compatible = "atmel,at91sam9g10-i2c"; 594 compatible = "atmel,at91sam9g10-i2c";
543 reg = <0xfff84000 0x100>; 595 reg = <0xfff84000 0x100>;
544 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; 596 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
597 pinctrl-names = "default";
598 pinctrl-0 = <&pinctrl_i2c0>;
545 #address-cells = <1>; 599 #address-cells = <1>;
546 #size-cells = <0>; 600 #size-cells = <0>;
547 status = "disabled"; 601 status = "disabled";
@@ -551,6 +605,8 @@
551 compatible = "atmel,at91sam9g10-i2c"; 605 compatible = "atmel,at91sam9g10-i2c";
552 reg = <0xfff88000 0x100>; 606 reg = <0xfff88000 0x100>;
553 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; 607 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
608 pinctrl-names = "default";
609 pinctrl-0 = <&pinctrl_i2c1>;
554 #address-cells = <1>; 610 #address-cells = <1>;
555 #size-cells = <0>; 611 #size-cells = <0>;
556 status = "disabled"; 612 status = "disabled";
@@ -618,6 +674,7 @@
618 compatible = "atmel,hsmci"; 674 compatible = "atmel,hsmci";
619 reg = <0xfff80000 0x600>; 675 reg = <0xfff80000 0x600>;
620 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 676 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
677 pinctrl-names = "default";
621 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; 678 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
622 dma-names = "rxtx"; 679 dma-names = "rxtx";
623 #address-cells = <1>; 680 #address-cells = <1>;
@@ -629,6 +686,7 @@
629 compatible = "atmel,hsmci"; 686 compatible = "atmel,hsmci";
630 reg = <0xfffd0000 0x600>; 687 reg = <0xfffd0000 0x600>;
631 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; 688 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
689 pinctrl-names = "default";
632 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; 690 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
633 dma-names = "rxtx"; 691 dma-names = "rxtx";
634 #address-cells = <1>; 692 #address-cells = <1>;
@@ -727,6 +785,15 @@
727 }; 785 };
728 }; 786 };
729 787
788 fb0: fb@0x00500000 {
789 compatible = "atmel,at91sam9g45-lcdc";
790 reg = <0x00500000 0x1000>;
791 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
792 pinctrl-names = "default";
793 pinctrl-0 = <&pinctrl_fb>;
794 status = "disabled";
795 };
796
730 nand0: nand@40000000 { 797 nand0: nand@40000000 {
731 compatible = "atmel,at91rm9200-nand"; 798 compatible = "atmel,at91rm9200-nand";
732 #address-cells = <1>; 799 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a4b00e5c61c0..7b76dbde8c41 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -123,6 +123,35 @@
123 }; 123 };
124 }; 124 };
125 125
126 fb0: fb@0x00500000 {
127 display = <&display0>;
128 status = "okay";
129
130 display0: display {
131 bits-per-pixel = <32>;
132 atmel,lcdcon-backlight;
133 atmel,dmacon = <0x1>;
134 atmel,lcdcon2 = <0x80008002>;
135 atmel,guard-time = <9>;
136 atmel,lcd-wiring-mode = "RGB";
137
138 display-timings {
139 native-mode = <&timing0>;
140 timing0: timing0 {
141 clock-frequency = <9000000>;
142 hactive = <480>;
143 vactive = <272>;
144 hback-porch = <1>;
145 hfront-porch = <1>;
146 vback-porch = <40>;
147 vfront-porch = <1>;
148 hsync-len = <45>;
149 vsync-len = <1>;
150 };
151 };
152 };
153 };
154
126 nand0: nand@40000000 { 155 nand0: nand@40000000 {
127 nand-bus-width = <8>; 156 nand-bus-width = <8>;
128 nand-ecc-mode = "soft"; 157 nand-ecc-mode = "soft";
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 5cdaba4cea86..070c5c3a2291 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -13,6 +13,7 @@
13#include <dt-bindings/pinctrl/at91.h> 13#include <dt-bindings/pinctrl/at91.h>
14#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/clk/at91.h>
16 17
17/ { 18/ {
18 model = "Atmel SAMA5D3 family SoC"; 19 model = "Atmel SAMA5D3 family SoC";
@@ -56,6 +57,14 @@
56 reg = <0x20000000 0x8000000>; 57 reg = <0x20000000 0x8000000>;
57 }; 58 };
58 59
60 clocks {
61 adc_op_clk: adc_op_clk{
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <20000000>;
65 };
66 };
67
59 ahb { 68 ahb {
60 compatible = "simple-bus"; 69 compatible = "simple-bus";
61 #address-cells = <1>; 70 #address-cells = <1>;
@@ -79,6 +88,8 @@
79 status = "disabled"; 88 status = "disabled";
80 #address-cells = <1>; 89 #address-cells = <1>;
81 #size-cells = <0>; 90 #size-cells = <0>;
91 clocks = <&mci0_clk>;
92 clock-names = "mci_clk";
82 }; 93 };
83 94
84 spi0: spi@f0004000 { 95 spi0: spi@f0004000 {
@@ -92,6 +103,8 @@
92 dma-names = "tx", "rx"; 103 dma-names = "tx", "rx";
93 pinctrl-names = "default"; 104 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_spi0>; 105 pinctrl-0 = <&pinctrl_spi0>;
106 clocks = <&spi0_clk>;
107 clock-names = "spi_clk";
95 status = "disabled"; 108 status = "disabled";
96 }; 109 };
97 110
@@ -101,6 +114,8 @@
101 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; 114 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
102 pinctrl-names = "default"; 115 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 116 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
117 clocks = <&ssc0_clk>;
118 clock-names = "pclk";
104 status = "disabled"; 119 status = "disabled";
105 }; 120 };
106 121
@@ -108,6 +123,8 @@
108 compatible = "atmel,at91sam9x5-tcb"; 123 compatible = "atmel,at91sam9x5-tcb";
109 reg = <0xf0010000 0x100>; 124 reg = <0xf0010000 0x100>;
110 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 125 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
126 clocks = <&tcb0_clk>;
127 clock-names = "t0_clk";
111 }; 128 };
112 129
113 i2c0: i2c@f0014000 { 130 i2c0: i2c@f0014000 {
@@ -121,6 +138,7 @@
121 pinctrl-0 = <&pinctrl_i2c0>; 138 pinctrl-0 = <&pinctrl_i2c0>;
122 #address-cells = <1>; 139 #address-cells = <1>;
123 #size-cells = <0>; 140 #size-cells = <0>;
141 clocks = <&twi0_clk>;
124 status = "disabled"; 142 status = "disabled";
125 }; 143 };
126 144
@@ -135,6 +153,7 @@
135 pinctrl-0 = <&pinctrl_i2c1>; 153 pinctrl-0 = <&pinctrl_i2c1>;
136 #address-cells = <1>; 154 #address-cells = <1>;
137 #size-cells = <0>; 155 #size-cells = <0>;
156 clocks = <&twi1_clk>;
138 status = "disabled"; 157 status = "disabled";
139 }; 158 };
140 159
@@ -144,6 +163,8 @@
144 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; 163 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
145 pinctrl-names = "default"; 164 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_usart0>; 165 pinctrl-0 = <&pinctrl_usart0>;
166 clocks = <&usart0_clk>;
167 clock-names = "usart";
147 status = "disabled"; 168 status = "disabled";
148 }; 169 };
149 170
@@ -153,6 +174,8 @@
153 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; 174 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
154 pinctrl-names = "default"; 175 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_usart1>; 176 pinctrl-0 = <&pinctrl_usart1>;
177 clocks = <&usart1_clk>;
178 clock-names = "usart";
156 status = "disabled"; 179 status = "disabled";
157 }; 180 };
158 181
@@ -174,6 +197,8 @@
174 status = "disabled"; 197 status = "disabled";
175 #address-cells = <1>; 198 #address-cells = <1>;
176 #size-cells = <0>; 199 #size-cells = <0>;
200 clocks = <&mci1_clk>;
201 clock-names = "mci_clk";
177 }; 202 };
178 203
179 spi1: spi@f8008000 { 204 spi1: spi@f8008000 {
@@ -187,6 +212,8 @@
187 dma-names = "tx", "rx"; 212 dma-names = "tx", "rx";
188 pinctrl-names = "default"; 213 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_spi1>; 214 pinctrl-0 = <&pinctrl_spi1>;
215 clocks = <&spi1_clk>;
216 clock-names = "spi_clk";
190 status = "disabled"; 217 status = "disabled";
191 }; 218 };
192 219
@@ -196,6 +223,8 @@
196 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; 223 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
197 pinctrl-names = "default"; 224 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 225 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
226 clocks = <&ssc1_clk>;
227 clock-names = "pclk";
199 status = "disabled"; 228 status = "disabled";
200 }; 229 };
201 230
@@ -219,6 +248,9 @@
219 &pinctrl_adc0_ad10 248 &pinctrl_adc0_ad10
220 &pinctrl_adc0_ad11 249 &pinctrl_adc0_ad11
221 >; 250 >;
251 clocks = <&adc_clk>,
252 <&adc_op_clk>;
253 clock-names = "adc_clk", "adc_op_clk";
222 atmel,adc-channel-base = <0x50>; 254 atmel,adc-channel-base = <0x50>;
223 atmel,adc-channels-used = <0xfff>; 255 atmel,adc-channels-used = <0xfff>;
224 atmel,adc-drdy-mask = <0x1000000>; 256 atmel,adc-drdy-mask = <0x1000000>;
@@ -272,8 +304,11 @@
272 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, 304 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
273 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; 305 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
274 dma-names = "tx", "rx"; 306 dma-names = "tx", "rx";
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_i2c2>;
275 #address-cells = <1>; 309 #address-cells = <1>;
276 #size-cells = <0>; 310 #size-cells = <0>;
311 clocks = <&twi2_clk>;
277 status = "disabled"; 312 status = "disabled";
278 }; 313 };
279 314
@@ -283,6 +318,8 @@
283 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 318 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
284 pinctrl-names = "default"; 319 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_usart2>; 320 pinctrl-0 = <&pinctrl_usart2>;
321 clocks = <&usart2_clk>;
322 clock-names = "usart";
286 status = "disabled"; 323 status = "disabled";
287 }; 324 };
288 325
@@ -292,25 +329,35 @@
292 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 329 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
293 pinctrl-names = "default"; 330 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_usart3>; 331 pinctrl-0 = <&pinctrl_usart3>;
332 clocks = <&usart3_clk>;
333 clock-names = "usart";
295 status = "disabled"; 334 status = "disabled";
296 }; 335 };
297 336
298 sha@f8034000 { 337 sha@f8034000 {
299 compatible = "atmel,sam9g46-sha"; 338 compatible = "atmel,at91sam9g46-sha";
300 reg = <0xf8034000 0x100>; 339 reg = <0xf8034000 0x100>;
301 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; 340 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
341 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
342 dma-names = "tx";
302 }; 343 };
303 344
304 aes@f8038000 { 345 aes@f8038000 {
305 compatible = "atmel,sam9g46-aes"; 346 compatible = "atmel,at91sam9g46-aes";
306 reg = <0xf8038000 0x100>; 347 reg = <0xf8038000 0x100>;
307 interrupts = <43 4 0>; 348 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
349 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
350 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
351 dma-names = "tx", "rx";
308 }; 352 };
309 353
310 tdes@f803c000 { 354 tdes@f803c000 {
311 compatible = "atmel,sam9g46-tdes"; 355 compatible = "atmel,at91sam9g46-tdes";
312 reg = <0xf803c000 0x100>; 356 reg = <0xf803c000 0x100>;
313 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; 357 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
358 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
359 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
360 dma-names = "tx", "rx";
314 }; 361 };
315 362
316 dma0: dma-controller@ffffe600 { 363 dma0: dma-controller@ffffe600 {
@@ -318,6 +365,8 @@
318 reg = <0xffffe600 0x200>; 365 reg = <0xffffe600 0x200>;
319 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; 366 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
320 #dma-cells = <2>; 367 #dma-cells = <2>;
368 clocks = <&dma0_clk>;
369 clock-names = "dma_clk";
321 }; 370 };
322 371
323 dma1: dma-controller@ffffe800 { 372 dma1: dma-controller@ffffe800 {
@@ -325,6 +374,8 @@
325 reg = <0xffffe800 0x200>; 374 reg = <0xffffe800 0x200>;
326 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 375 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
327 #dma-cells = <2>; 376 #dma-cells = <2>;
377 clocks = <&dma1_clk>;
378 clock-names = "dma_clk";
328 }; 379 };
329 380
330 ramc0: ramc@ffffea00 { 381 ramc0: ramc@ffffea00 {
@@ -338,6 +389,8 @@
338 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; 389 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
339 pinctrl-names = "default"; 390 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_dbgu>; 391 pinctrl-0 = <&pinctrl_dbgu>;
392 clocks = <&dbgu_clk>;
393 clock-names = "usart";
341 status = "disabled"; 394 status = "disabled";
342 }; 395 };
343 396
@@ -443,6 +496,14 @@
443 }; 496 };
444 }; 497 };
445 498
499 i2c2 {
500 pinctrl_i2c2: i2c2-0 {
501 atmel,pins =
502 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
503 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
504 };
505 };
506
446 isi { 507 isi {
447 pinctrl_isi: isi-0 { 508 pinctrl_isi: isi-0 {
448 atmel,pins = 509 atmel,pins =
@@ -626,6 +687,7 @@
626 gpio-controller; 687 gpio-controller;
627 interrupt-controller; 688 interrupt-controller;
628 #interrupt-cells = <2>; 689 #interrupt-cells = <2>;
690 clocks = <&pioA_clk>;
629 }; 691 };
630 692
631 pioB: gpio@fffff400 { 693 pioB: gpio@fffff400 {
@@ -636,6 +698,7 @@
636 gpio-controller; 698 gpio-controller;
637 interrupt-controller; 699 interrupt-controller;
638 #interrupt-cells = <2>; 700 #interrupt-cells = <2>;
701 clocks = <&pioB_clk>;
639 }; 702 };
640 703
641 pioC: gpio@fffff600 { 704 pioC: gpio@fffff600 {
@@ -646,6 +709,7 @@
646 gpio-controller; 709 gpio-controller;
647 interrupt-controller; 710 interrupt-controller;
648 #interrupt-cells = <2>; 711 #interrupt-cells = <2>;
712 clocks = <&pioC_clk>;
649 }; 713 };
650 714
651 pioD: gpio@fffff800 { 715 pioD: gpio@fffff800 {
@@ -656,6 +720,7 @@
656 gpio-controller; 720 gpio-controller;
657 interrupt-controller; 721 interrupt-controller;
658 #interrupt-cells = <2>; 722 #interrupt-cells = <2>;
723 clocks = <&pioD_clk>;
659 }; 724 };
660 725
661 pioE: gpio@fffffa00 { 726 pioE: gpio@fffffa00 {
@@ -666,12 +731,334 @@
666 gpio-controller; 731 gpio-controller;
667 interrupt-controller; 732 interrupt-controller;
668 #interrupt-cells = <2>; 733 #interrupt-cells = <2>;
734 clocks = <&pioE_clk>;
669 }; 735 };
670 }; 736 };
671 737
672 pmc: pmc@fffffc00 { 738 pmc: pmc@fffffc00 {
673 compatible = "atmel,at91rm9200-pmc"; 739 compatible = "atmel,sama5d3-pmc";
674 reg = <0xfffffc00 0x120>; 740 reg = <0xfffffc00 0x120>;
741 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
742 interrupt-controller;
743 #address-cells = <1>;
744 #size-cells = <0>;
745 #interrupt-cells = <1>;
746
747 clk32k: slck {
748 compatible = "fixed-clock";
749 #clock-cells = <0>;
750 clock-frequency = <32768>;
751 };
752
753 main: mainck {
754 compatible = "atmel,at91rm9200-clk-main";
755 #clock-cells = <0>;
756 interrupt-parent = <&pmc>;
757 interrupts = <AT91_PMC_MOSCS>;
758 clocks = <&clk32k>;
759 };
760
761 plla: pllack {
762 compatible = "atmel,sama5d3-clk-pll";
763 #clock-cells = <0>;
764 interrupt-parent = <&pmc>;
765 interrupts = <AT91_PMC_LOCKA>;
766 clocks = <&main>;
767 reg = <0>;
768 atmel,clk-input-range = <8000000 50000000>;
769 #atmel,pll-clk-output-range-cells = <4>;
770 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
771 };
772
773 plladiv: plladivck {
774 compatible = "atmel,at91sam9x5-clk-plldiv";
775 #clock-cells = <0>;
776 clocks = <&plla>;
777 };
778
779 utmi: utmick {
780 compatible = "atmel,at91sam9x5-clk-utmi";
781 #clock-cells = <0>;
782 interrupt-parent = <&pmc>;
783 interrupts = <AT91_PMC_LOCKU>;
784 clocks = <&main>;
785 };
786
787 mck: masterck {
788 compatible = "atmel,at91sam9x5-clk-master";
789 #clock-cells = <0>;
790 interrupt-parent = <&pmc>;
791 interrupts = <AT91_PMC_MCKRDY>;
792 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
793 atmel,clk-output-range = <0 166000000>;
794 atmel,clk-divisors = <1 2 4 3>;
795 };
796
797 usb: usbck {
798 compatible = "atmel,at91sam9x5-clk-usb";
799 #clock-cells = <0>;
800 clocks = <&plladiv>, <&utmi>;
801 };
802
803 prog: progck {
804 compatible = "atmel,at91sam9x5-clk-programmable";
805 #address-cells = <1>;
806 #size-cells = <0>;
807 interrupt-parent = <&pmc>;
808 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
809
810 prog0: prog0 {
811 #clock-cells = <0>;
812 reg = <0>;
813 interrupts = <AT91_PMC_PCKRDY(0)>;
814 };
815
816 prog1: prog1 {
817 #clock-cells = <0>;
818 reg = <1>;
819 interrupts = <AT91_PMC_PCKRDY(1)>;
820 };
821
822 prog2: prog2 {
823 #clock-cells = <0>;
824 reg = <2>;
825 interrupts = <AT91_PMC_PCKRDY(2)>;
826 };
827 };
828
829 smd: smdclk {
830 compatible = "atmel,at91sam9x5-clk-smd";
831 #clock-cells = <0>;
832 clocks = <&plladiv>, <&utmi>;
833 };
834
835 systemck {
836 compatible = "atmel,at91rm9200-clk-system";
837 #address-cells = <1>;
838 #size-cells = <0>;
839
840 ddrck: ddrck {
841 #clock-cells = <0>;
842 reg = <2>;
843 clocks = <&mck>;
844 };
845
846 smdck: smdck {
847 #clock-cells = <0>;
848 reg = <4>;
849 clocks = <&smd>;
850 };
851
852 uhpck: uhpck {
853 #clock-cells = <0>;
854 reg = <6>;
855 clocks = <&usb>;
856 };
857
858 udpck: udpck {
859 #clock-cells = <0>;
860 reg = <7>;
861 clocks = <&usb>;
862 };
863
864 pck0: pck0 {
865 #clock-cells = <0>;
866 reg = <8>;
867 clocks = <&prog0>;
868 };
869
870 pck1: pck1 {
871 #clock-cells = <0>;
872 reg = <9>;
873 clocks = <&prog1>;
874 };
875
876 pck2: pck2 {
877 #clock-cells = <0>;
878 reg = <10>;
879 clocks = <&prog2>;
880 };
881 };
882
883 periphck {
884 compatible = "atmel,at91sam9x5-clk-peripheral";
885 #address-cells = <1>;
886 #size-cells = <0>;
887 clocks = <&mck>;
888
889 dbgu_clk: dbgu_clk {
890 #clock-cells = <0>;
891 reg = <2>;
892 };
893
894 pioA_clk: pioA_clk {
895 #clock-cells = <0>;
896 reg = <6>;
897 };
898
899 pioB_clk: pioB_clk {
900 #clock-cells = <0>;
901 reg = <7>;
902 };
903
904 pioC_clk: pioC_clk {
905 #clock-cells = <0>;
906 reg = <8>;
907 };
908
909 pioD_clk: pioD_clk {
910 #clock-cells = <0>;
911 reg = <9>;
912 };
913
914 pioE_clk: pioE_clk {
915 #clock-cells = <0>;
916 reg = <10>;
917 };
918
919 usart0_clk: usart0_clk {
920 #clock-cells = <0>;
921 reg = <12>;
922 atmel,clk-output-range = <0 66000000>;
923 };
924
925 usart1_clk: usart1_clk {
926 #clock-cells = <0>;
927 reg = <13>;
928 atmel,clk-output-range = <0 66000000>;
929 };
930
931 usart2_clk: usart2_clk {
932 #clock-cells = <0>;
933 reg = <14>;
934 atmel,clk-output-range = <0 66000000>;
935 };
936
937 usart3_clk: usart3_clk {
938 #clock-cells = <0>;
939 reg = <15>;
940 atmel,clk-output-range = <0 66000000>;
941 };
942
943 twi0_clk: twi0_clk {
944 reg = <18>;
945 #clock-cells = <0>;
946 atmel,clk-output-range = <0 16625000>;
947 };
948
949 twi1_clk: twi1_clk {
950 #clock-cells = <0>;
951 reg = <19>;
952 atmel,clk-output-range = <0 16625000>;
953 };
954
955 twi2_clk: twi2_clk {
956 #clock-cells = <0>;
957 reg = <20>;
958 atmel,clk-output-range = <0 16625000>;
959 };
960
961 mci0_clk: mci0_clk {
962 #clock-cells = <0>;
963 reg = <21>;
964 };
965
966 mci1_clk: mci1_clk {
967 #clock-cells = <0>;
968 reg = <22>;
969 };
970
971 spi0_clk: spi0_clk {
972 #clock-cells = <0>;
973 reg = <24>;
974 atmel,clk-output-range = <0 133000000>;
975 };
976
977 spi1_clk: spi1_clk {
978 #clock-cells = <0>;
979 reg = <25>;
980 atmel,clk-output-range = <0 133000000>;
981 };
982
983 tcb0_clk: tcb0_clk {
984 #clock-cells = <0>;
985 reg = <26>;
986 atmel,clk-output-range = <0 133000000>;
987 };
988
989 pwm_clk: pwm_clk {
990 #clock-cells = <0>;
991 reg = <28>;
992 };
993
994 adc_clk: adc_clk {
995 #clock-cells = <0>;
996 reg = <29>;
997 atmel,clk-output-range = <0 66000000>;
998 };
999
1000 dma0_clk: dma0_clk {
1001 #clock-cells = <0>;
1002 reg = <30>;
1003 };
1004
1005 dma1_clk: dma1_clk {
1006 #clock-cells = <0>;
1007 reg = <31>;
1008 };
1009
1010 uhphs_clk: uhphs_clk {
1011 #clock-cells = <0>;
1012 reg = <32>;
1013 };
1014
1015 udphs_clk: udphs_clk {
1016 #clock-cells = <0>;
1017 reg = <33>;
1018 };
1019
1020 isi_clk: isi_clk {
1021 #clock-cells = <0>;
1022 reg = <37>;
1023 };
1024
1025 ssc0_clk: ssc0_clk {
1026 #clock-cells = <0>;
1027 reg = <38>;
1028 atmel,clk-output-range = <0 66000000>;
1029 };
1030
1031 ssc1_clk: ssc1_clk {
1032 #clock-cells = <0>;
1033 reg = <39>;
1034 atmel,clk-output-range = <0 66000000>;
1035 };
1036
1037 sha_clk: sha_clk {
1038 #clock-cells = <0>;
1039 reg = <42>;
1040 };
1041
1042 aes_clk: aes_clk {
1043 #clock-cells = <0>;
1044 reg = <43>;
1045 };
1046
1047 tdes_clk: tdes_clk {
1048 #clock-cells = <0>;
1049 reg = <44>;
1050 };
1051
1052 trng_clk: trng_clk {
1053 #clock-cells = <0>;
1054 reg = <45>;
1055 };
1056
1057 fuse_clk: fuse_clk {
1058 #clock-cells = <0>;
1059 reg = <48>;
1060 };
1061 };
675 }; 1062 };
676 1063
677 rstc@fffffe00 { 1064 rstc@fffffe00 {
@@ -683,6 +1070,7 @@
683 compatible = "atmel,at91sam9260-pit"; 1070 compatible = "atmel,at91sam9260-pit";
684 reg = <0xfffffe30 0xf>; 1071 reg = <0xfffffe30 0xf>;
685 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 1072 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1073 clocks = <&mck>;
686 }; 1074 };
687 1075
688 watchdog@fffffe40 { 1076 watchdog@fffffe40 {
@@ -705,6 +1093,8 @@
705 reg = <0x00500000 0x100000 1093 reg = <0x00500000 0x100000
706 0xf8030000 0x4000>; 1094 0xf8030000 0x4000>;
707 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; 1095 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
1096 clocks = <&udphs_clk>, <&utmi>;
1097 clock-names = "pclk", "hclk";
708 status = "disabled"; 1098 status = "disabled";
709 1099
710 ep0 { 1100 ep0 {
@@ -817,6 +1207,9 @@
817 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 1207 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
818 reg = <0x00600000 0x100000>; 1208 reg = <0x00600000 0x100000>;
819 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; 1209 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1210 clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
1211 <&uhpck>;
1212 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
820 status = "disabled"; 1213 status = "disabled";
821 }; 1214 };
822 1215
@@ -824,6 +1217,8 @@
824 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1217 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
825 reg = <0x00700000 0x100000>; 1218 reg = <0x00700000 0x100000>;
826 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; 1219 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1220 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
1221 clock-names = "usb_clk", "ehci_clk", "uhpck";
827 status = "disabled"; 1222 status = "disabled";
828 }; 1223 };
829 1224
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi
index 8ed3260cef66..a0775851cce5 100644
--- a/arch/arm/boot/dts/sama5d3_can.dtsi
+++ b/arch/arm/boot/dts/sama5d3_can.dtsi
@@ -32,12 +32,30 @@
32 32
33 }; 33 };
34 34
35 pmc: pmc@fffffc00 {
36 periphck {
37 can0_clk: can0_clk {
38 #clock-cells = <0>;
39 reg = <40>;
40 atmel,clk-output-range = <0 66000000>;
41 };
42
43 can1_clk: can0_clk {
44 #clock-cells = <0>;
45 reg = <41>;
46 atmel,clk-output-range = <0 66000000>;
47 };
48 };
49 };
50
35 can0: can@f000c000 { 51 can0: can@f000c000 {
36 compatible = "atmel,at91sam9x5-can"; 52 compatible = "atmel,at91sam9x5-can";
37 reg = <0xf000c000 0x300>; 53 reg = <0xf000c000 0x300>;
38 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; 54 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
39 pinctrl-names = "default"; 55 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_can0_rx_tx>; 56 pinctrl-0 = <&pinctrl_can0_rx_tx>;
57 clocks = <&can0_clk>;
58 clock-names = "can_clk";
41 status = "disabled"; 59 status = "disabled";
42 }; 60 };
43 61
@@ -47,6 +65,8 @@
47 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; 65 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
48 pinctrl-names = "default"; 66 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_can1_rx_tx>; 67 pinctrl-0 = <&pinctrl_can1_rx_tx>;
68 clocks = <&can1_clk>;
69 clock-names = "can_clk";
50 status = "disabled"; 70 status = "disabled";
51 }; 71 };
52 }; 72 };
diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi
index 4d4f351f1f9f..fe2af9276312 100644
--- a/arch/arm/boot/dts/sama5d3_emac.dtsi
+++ b/arch/arm/boot/dts/sama5d3_emac.dtsi
@@ -31,12 +31,23 @@
31 }; 31 };
32 }; 32 };
33 33
34 pmc: pmc@fffffc00 {
35 periphck {
36 macb1_clk: macb1_clk {
37 #clock-cells = <0>;
38 reg = <35>;
39 };
40 };
41 };
42
34 macb1: ethernet@f802c000 { 43 macb1: ethernet@f802c000 {
35 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 44 compatible = "cdns,at32ap7000-macb", "cdns,macb";
36 reg = <0xf802c000 0x100>; 45 reg = <0xf802c000 0x100>;
37 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; 46 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
38 pinctrl-names = "default"; 47 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_macb1_rmii>; 48 pinctrl-0 = <&pinctrl_macb1_rmii>;
49 clocks = <&macb1_clk>, <&macb1_clk>;
50 clock-names = "hclk", "pclk";
40 status = "disabled"; 51 status = "disabled";
41 }; 52 };
42 }; 53 };
diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi
index 0ba8be30ccd8..a6cb0508762f 100644
--- a/arch/arm/boot/dts/sama5d3_gmac.dtsi
+++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi
@@ -64,12 +64,23 @@
64 }; 64 };
65 }; 65 };
66 66
67 pmc: pmc@fffffc00 {
68 periphck {
69 macb0_clk: macb0_clk {
70 #clock-cells = <0>;
71 reg = <34>;
72 };
73 };
74 };
75
67 macb0: ethernet@f0028000 { 76 macb0: ethernet@f0028000 {
68 compatible = "cdns,pc302-gem", "cdns,gem"; 77 compatible = "cdns,pc302-gem", "cdns,gem";
69 reg = <0xf0028000 0x100>; 78 reg = <0xf0028000 0x100>;
70 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; 79 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
71 pinctrl-names = "default"; 80 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; 81 pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
82 clocks = <&macb0_clk>, <&macb0_clk>;
83 clock-names = "hclk", "pclk";
73 status = "disabled"; 84 status = "disabled";
74 }; 85 };
75 }; 86 };
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi
index 01f52a79f8ba..85d302701565 100644
--- a/arch/arm/boot/dts/sama5d3_lcd.dtsi
+++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi
@@ -50,6 +50,23 @@
50 }; 50 };
51 }; 51 };
52 }; 52 };
53
54 pmc: pmc@fffffc00 {
55 periphck {
56 lcdc_clk: lcdc_clk {
57 #clock-cells = <0>;
58 reg = <36>;
59 };
60 };
61
62 systemck {
63 lcdck: lcdck {
64 #clock-cells = <0>;
65 reg = <3>;
66 clocks = <&mck>;
67 };
68 };
69 };
53 }; 70 };
54 }; 71 };
55}; 72};
diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi
index 38e88e39e551..b029fe7ef17a 100644
--- a/arch/arm/boot/dts/sama5d3_mci2.dtsi
+++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi
@@ -9,6 +9,7 @@
9 9
10#include <dt-bindings/pinctrl/at91.h> 10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/clk/at91.h>
12 13
13/ { 14/ {
14 ahb { 15 ahb {
@@ -30,6 +31,15 @@
30 }; 31 };
31 }; 32 };
32 33
34 pmc: pmc@fffffc00 {
35 periphck {
36 mci2_clk: mci2_clk {
37 #clock-cells = <0>;
38 reg = <23>;
39 };
40 };
41 };
42
33 mmc2: mmc@f8004000 { 43 mmc2: mmc@f8004000 {
34 compatible = "atmel,hsmci"; 44 compatible = "atmel,hsmci";
35 reg = <0xf8004000 0x600>; 45 reg = <0xf8004000 0x600>;
@@ -38,6 +48,8 @@
38 dma-names = "rxtx"; 48 dma-names = "rxtx";
39 pinctrl-names = "default"; 49 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; 50 pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
51 clocks = <&mci2_clk>;
52 clock-names = "mci_clk";
41 status = "disabled"; 53 status = "disabled";
42 #address-cells = <1>; 54 #address-cells = <1>;
43 #size-cells = <0>; 55 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
index 5264bb4a6998..382b04431f66 100644
--- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi
+++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
@@ -9,6 +9,7 @@
9 9
10#include <dt-bindings/pinctrl/at91.h> 10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/clk/at91.h>
12 13
13/ { 14/ {
14 aliases { 15 aliases {
@@ -17,10 +18,21 @@
17 18
18 ahb { 19 ahb {
19 apb { 20 apb {
21 pmc: pmc@fffffc00 {
22 periphck {
23 tcb1_clk: tcb1_clk {
24 #clock-cells = <0>;
25 reg = <27>;
26 };
27 };
28 };
29
20 tcb1: timer@f8014000 { 30 tcb1: timer@f8014000 {
21 compatible = "atmel,at91sam9x5-tcb"; 31 compatible = "atmel,at91sam9x5-tcb";
22 reg = <0xf8014000 0x100>; 32 reg = <0xf8014000 0x100>;
23 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; 33 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
34 clocks = <&tcb1_clk>;
35 clock-names = "t0_clk";
24 }; 36 };
25 }; 37 };
26 }; 38 };
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
index 98fcb2d57446..a9fa75e41652 100644
--- a/arch/arm/boot/dts/sama5d3_uart.dtsi
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -9,8 +9,14 @@
9 9
10#include <dt-bindings/pinctrl/at91.h> 10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/clk/at91.h>
12 13
13/ { 14/ {
15 aliases {
16 serial5 = &uart0;
17 serial6 = &uart1;
18 };
19
14 ahb { 20 ahb {
15 apb { 21 apb {
16 pinctrl@fffff200 { 22 pinctrl@fffff200 {
@@ -31,12 +37,30 @@
31 }; 37 };
32 }; 38 };
33 39
40 pmc: pmc@fffffc00 {
41 periphck {
42 uart0_clk: uart0_clk {
43 #clock-cells = <0>;
44 reg = <16>;
45 atmel,clk-output-range = <0 66000000>;
46 };
47
48 uart1_clk: uart1_clk {
49 #clock-cells = <0>;
50 reg = <17>;
51 atmel,clk-output-range = <0 66000000>;
52 };
53 };
54 };
55
34 uart0: serial@f0024000 { 56 uart0: serial@f0024000 {
35 compatible = "atmel,at91sam9260-usart"; 57 compatible = "atmel,at91sam9260-usart";
36 reg = <0xf0024000 0x200>; 58 reg = <0xf0024000 0x200>;
37 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 59 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
38 pinctrl-names = "default"; 60 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_uart0>; 61 pinctrl-0 = <&pinctrl_uart0>;
62 clocks = <&uart0_clk>;
63 clock-names = "usart";
40 status = "disabled"; 64 status = "disabled";
41 }; 65 };
42 66
@@ -46,6 +70,8 @@
46 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; 70 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
47 pinctrl-names = "default"; 71 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_uart1>; 72 pinctrl-0 = <&pinctrl_uart1>;
73 clocks = <&uart1_clk>;
74 clock-names = "usart";
49 status = "disabled"; 75 status = "disabled";
50 }; 76 };
51 }; 77 };
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 726a0f35100c..f55ed072c8e6 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -18,17 +18,6 @@
18 reg = <0x20000000 0x20000000>; 18 reg = <0x20000000 0x20000000>;
19 }; 19 };
20 20
21 clocks {
22 #address-cells = <1>;
23 #size-cells = <1>;
24 ranges;
25
26 main_clock: clock@0 {
27 compatible = "atmel,osc", "fixed-clock";
28 clock-frequency = <12000000>;
29 };
30 };
31
32 ahb { 21 ahb {
33 apb { 22 apb {
34 spi0: spi@f0004000 { 23 spi0: spi@f0004000 {
@@ -38,6 +27,12 @@
38 macb0: ethernet@f0028000 { 27 macb0: ethernet@f0028000 {
39 phy-mode = "rgmii"; 28 phy-mode = "rgmii";
40 }; 29 };
30
31 pmc: pmc@fffffc00 {
32 main: mainck {
33 clock-frequency = <12000000>;
34 };
35 };
41 }; 36 };
42 37
43 nand0: nand@60000000 { 38 nand0: nand@60000000 {
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi
index 1c296d6b2f2a..f9bdde542ced 100644
--- a/arch/arm/boot/dts/sama5d3xdm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xdm.dtsi
@@ -18,6 +18,7 @@
18 interrupts = <31 0x0>; 18 interrupts = <31 0x0>;
19 pinctrl-names = "default"; 19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_qt1070_irq>; 20 pinctrl-0 = <&pinctrl_qt1070_irq>;
21 wakeup-source;
21 }; 22 };
22 }; 23 };
23 24
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 699b71e7f7ec..b4f7d6ffa30b 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,15 +1,33 @@
1if ARCH_AT91 1if ARCH_AT91
2 2
3config HAVE_AT91_UTMI
4 bool
5
6config HAVE_AT91_USB_CLK
7 bool
8
3config HAVE_AT91_DBGU0 9config HAVE_AT91_DBGU0
4 bool 10 bool
5 11
6config HAVE_AT91_DBGU1 12config HAVE_AT91_DBGU1
7 bool 13 bool
8 14
15config AT91_USE_OLD_CLK
16 bool
17
9config AT91_PMC_UNIT 18config AT91_PMC_UNIT
10 bool 19 bool
11 default !ARCH_AT91X40 20 default !ARCH_AT91X40
12 21
22config COMMON_CLK_AT91
23 bool
24 default AT91_PMC_UNIT && USE_OF && !AT91_USE_OLD_CLK
25 select COMMON_CLK
26
27config OLD_CLK_AT91
28 bool
29 default AT91_PMC_UNIT && AT91_USE_OLD_CLK
30
13config AT91_SAM9_ALT_RESET 31config AT91_SAM9_ALT_RESET
14 bool 32 bool
15 default !ARCH_AT91X40 33 default !ARCH_AT91X40
@@ -21,6 +39,9 @@ config AT91_SAM9G45_RESET
21config AT91_SAM9_TIME 39config AT91_SAM9_TIME
22 bool 40 bool
23 41
42config HAVE_AT91_SMD
43 bool
44
24config SOC_AT91SAM9 45config SOC_AT91SAM9
25 bool 46 bool
26 select AT91_SAM9_TIME 47 select AT91_SAM9_TIME
@@ -65,6 +86,9 @@ config SOC_SAMA5D3
65 select SOC_SAMA5 86 select SOC_SAMA5
66 select HAVE_FB_ATMEL 87 select HAVE_FB_ATMEL
67 select HAVE_AT91_DBGU1 88 select HAVE_AT91_DBGU1
89 select HAVE_AT91_UTMI
90 select HAVE_AT91_SMD
91 select HAVE_AT91_USB_CLK
68 help 92 help
69 Select this if you are using one of Atmel's SAMA5D3 family SoC. 93 Select this if you are using one of Atmel's SAMA5D3 family SoC.
70 This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35. 94 This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35.
@@ -78,11 +102,15 @@ config SOC_AT91RM9200
78 select HAVE_AT91_DBGU0 102 select HAVE_AT91_DBGU0
79 select MULTI_IRQ_HANDLER 103 select MULTI_IRQ_HANDLER
80 select SPARSE_IRQ 104 select SPARSE_IRQ
105 select AT91_USE_OLD_CLK
106 select HAVE_AT91_USB_CLK
81 107
82config SOC_AT91SAM9260 108config SOC_AT91SAM9260
83 bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" 109 bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20"
84 select HAVE_AT91_DBGU0 110 select HAVE_AT91_DBGU0
85 select SOC_AT91SAM9 111 select SOC_AT91SAM9
112 select AT91_USE_OLD_CLK
113 select HAVE_AT91_USB_CLK
86 help 114 help
87 Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE 115 Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
88 or AT91SAM9G20 SoC. 116 or AT91SAM9G20 SoC.
@@ -92,6 +120,8 @@ config SOC_AT91SAM9261
92 select HAVE_AT91_DBGU0 120 select HAVE_AT91_DBGU0
93 select HAVE_FB_ATMEL 121 select HAVE_FB_ATMEL
94 select SOC_AT91SAM9 122 select SOC_AT91SAM9
123 select AT91_USE_OLD_CLK
124 select HAVE_AT91_USB_CLK
95 help 125 help
96 Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. 126 Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC.
97 127
@@ -100,18 +130,25 @@ config SOC_AT91SAM9263
100 select HAVE_AT91_DBGU1 130 select HAVE_AT91_DBGU1
101 select HAVE_FB_ATMEL 131 select HAVE_FB_ATMEL
102 select SOC_AT91SAM9 132 select SOC_AT91SAM9
133 select AT91_USE_OLD_CLK
134 select HAVE_AT91_USB_CLK
103 135
104config SOC_AT91SAM9RL 136config SOC_AT91SAM9RL
105 bool "AT91SAM9RL" 137 bool "AT91SAM9RL"
106 select HAVE_AT91_DBGU0 138 select HAVE_AT91_DBGU0
107 select HAVE_FB_ATMEL 139 select HAVE_FB_ATMEL
108 select SOC_AT91SAM9 140 select SOC_AT91SAM9
141 select AT91_USE_OLD_CLK
142 select HAVE_AT91_UTMI
109 143
110config SOC_AT91SAM9G45 144config SOC_AT91SAM9G45
111 bool "AT91SAM9G45 or AT91SAM9M10 families" 145 bool "AT91SAM9G45 or AT91SAM9M10 families"
112 select HAVE_AT91_DBGU1 146 select HAVE_AT91_DBGU1
113 select HAVE_FB_ATMEL 147 select HAVE_FB_ATMEL
114 select SOC_AT91SAM9 148 select SOC_AT91SAM9
149 select AT91_USE_OLD_CLK
150 select HAVE_AT91_UTMI
151 select HAVE_AT91_USB_CLK
115 help 152 help
116 Select this if you are using one of Atmel's AT91SAM9G45 family SoC. 153 Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
117 This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. 154 This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
@@ -121,6 +158,10 @@ config SOC_AT91SAM9X5
121 select HAVE_AT91_DBGU0 158 select HAVE_AT91_DBGU0
122 select HAVE_FB_ATMEL 159 select HAVE_FB_ATMEL
123 select SOC_AT91SAM9 160 select SOC_AT91SAM9
161 select AT91_USE_OLD_CLK
162 select HAVE_AT91_UTMI
163 select HAVE_AT91_SMD
164 select HAVE_AT91_USB_CLK
124 help 165 help
125 Select this if you are using one of Atmel's AT91SAM9x5 family SoC. 166 Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
126 This means that your SAM9 name finishes with a '5' (except if it is 167 This means that your SAM9 name finishes with a '5' (except if it is
@@ -133,6 +174,8 @@ config SOC_AT91SAM9N12
133 select HAVE_AT91_DBGU0 174 select HAVE_AT91_DBGU0
134 select HAVE_FB_ATMEL 175 select HAVE_FB_ATMEL
135 select SOC_AT91SAM9 176 select SOC_AT91SAM9
177 select AT91_USE_OLD_CLK
178 select HAVE_AT91_USB_CLK
136 help 179 help
137 Select this if you are using Atmel's AT91SAM9N12 SoC. 180 Select this if you are using Atmel's AT91SAM9N12 SoC.
138 181
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index ca900be144ce..b736b571e882 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -12,26 +12,32 @@ config ARCH_AT91_NONE
12config ARCH_AT91RM9200 12config ARCH_AT91RM9200
13 bool "AT91RM9200" 13 bool "AT91RM9200"
14 select SOC_AT91RM9200 14 select SOC_AT91RM9200
15 select AT91_USE_OLD_CLK
15 16
16config ARCH_AT91SAM9260 17config ARCH_AT91SAM9260
17 bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20" 18 bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20"
18 select SOC_AT91SAM9260 19 select SOC_AT91SAM9260
20 select AT91_USE_OLD_CLK
19 21
20config ARCH_AT91SAM9261 22config ARCH_AT91SAM9261
21 bool "AT91SAM9261 or AT91SAM9G10" 23 bool "AT91SAM9261 or AT91SAM9G10"
22 select SOC_AT91SAM9261 24 select SOC_AT91SAM9261
25 select AT91_USE_OLD_CLK
23 26
24config ARCH_AT91SAM9263 27config ARCH_AT91SAM9263
25 bool "AT91SAM9263" 28 bool "AT91SAM9263"
26 select SOC_AT91SAM9263 29 select SOC_AT91SAM9263
30 select AT91_USE_OLD_CLK
27 31
28config ARCH_AT91SAM9RL 32config ARCH_AT91SAM9RL
29 bool "AT91SAM9RL" 33 bool "AT91SAM9RL"
30 select SOC_AT91SAM9RL 34 select SOC_AT91SAM9RL
35 select AT91_USE_OLD_CLK
31 36
32config ARCH_AT91SAM9G45 37config ARCH_AT91SAM9G45
33 bool "AT91SAM9G45" 38 bool "AT91SAM9G45"
34 select SOC_AT91SAM9G45 39 select SOC_AT91SAM9G45
40 select AT91_USE_OLD_CLK
35 41
36config ARCH_AT91X40 42config ARCH_AT91X40
37 bool "AT91x40" 43 bool "AT91x40"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 90aab2d5a07f..705b38a179ec 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -7,7 +7,7 @@ obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
9 9
10obj-$(CONFIG_AT91_PMC_UNIT) += clock.o 10obj-$(CONFIG_OLD_CLK_AT91) += clock.o
11obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o 11obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
12obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o 12obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
13obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o 13obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 25805f2f6010..e47f5fd232f5 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -12,13 +12,13 @@
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/reboot.h> 14#include <linux/reboot.h>
15#include <linux/clk/at91_pmc.h>
15 16
16#include <asm/irq.h> 17#include <asm/irq.h>
17#include <asm/mach/arch.h> 18#include <asm/mach/arch.h>
18#include <asm/mach/map.h> 19#include <asm/mach/map.h>
19#include <asm/system_misc.h> 20#include <asm/system_misc.h>
20#include <mach/at91rm9200.h> 21#include <mach/at91rm9200.h>
21#include <mach/at91_pmc.h>
22#include <mach/at91_st.h> 22#include <mach/at91_st.h>
23#include <mach/cpu.h> 23#include <mach/cpu.h>
24 24
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index d6a1fa85371d..6c821e562159 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/clk/at91_pmc.h>
14 15
15#include <asm/proc-fns.h> 16#include <asm/proc-fns.h>
16#include <asm/irq.h> 17#include <asm/irq.h>
@@ -20,7 +21,6 @@
20#include <mach/cpu.h> 21#include <mach/cpu.h>
21#include <mach/at91_dbgu.h> 22#include <mach/at91_dbgu.h>
22#include <mach/at91sam9260.h> 23#include <mach/at91sam9260.h>
23#include <mach/at91_pmc.h>
24 24
25#include "at91_aic.h" 25#include "at91_aic.h"
26#include "at91_rstc.h" 26#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 23ba1d8a1531..6276b4c1acfe 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/clk/at91_pmc.h>
14 15
15#include <asm/proc-fns.h> 16#include <asm/proc-fns.h>
16#include <asm/irq.h> 17#include <asm/irq.h>
@@ -19,7 +20,6 @@
19#include <asm/system_misc.h> 20#include <asm/system_misc.h>
20#include <mach/cpu.h> 21#include <mach/cpu.h>
21#include <mach/at91sam9261.h> 22#include <mach/at91sam9261.h>
22#include <mach/at91_pmc.h>
23 23
24#include "at91_aic.h" 24#include "at91_aic.h"
25#include "at91_rstc.h" 25#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 7eccb0fc57bc..37b90f4b990c 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/clk/at91_pmc.h>
14 15
15#include <asm/proc-fns.h> 16#include <asm/proc-fns.h>
16#include <asm/irq.h> 17#include <asm/irq.h>
@@ -18,7 +19,6 @@
18#include <asm/mach/map.h> 19#include <asm/mach/map.h>
19#include <asm/system_misc.h> 20#include <asm/system_misc.h>
20#include <mach/at91sam9263.h> 21#include <mach/at91sam9263.h>
21#include <mach/at91_pmc.h>
22 22
23#include "at91_aic.h" 23#include "at91_aic.h"
24#include "at91_rstc.h" 24#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index bb392320a0dd..0f04ffe9c5a8 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -39,6 +39,7 @@
39static u32 pit_cycle; /* write-once */ 39static u32 pit_cycle; /* write-once */
40static u32 pit_cnt; /* access only w/system irq blocked */ 40static u32 pit_cnt; /* access only w/system irq blocked */
41static void __iomem *pit_base_addr __read_mostly; 41static void __iomem *pit_base_addr __read_mostly;
42static struct clk *mck;
42 43
43static inline unsigned int pit_read(unsigned int reg_offset) 44static inline unsigned int pit_read(unsigned int reg_offset)
44{ 45{
@@ -195,10 +196,14 @@ static int __init of_at91sam926x_pit_init(void)
195 if (!pit_base_addr) 196 if (!pit_base_addr)
196 goto node_err; 197 goto node_err;
197 198
199 mck = of_clk_get(np, 0);
200
198 /* Get the interrupts property */ 201 /* Get the interrupts property */
199 ret = irq_of_parse_and_map(np, 0); 202 ret = irq_of_parse_and_map(np, 0);
200 if (!ret) { 203 if (!ret) {
201 pr_crit("AT91: PIT: Unable to get IRQ from DT\n"); 204 pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
205 if (!IS_ERR(mck))
206 clk_put(mck);
202 goto ioremap_err; 207 goto ioremap_err;
203 } 208 }
204 at91sam926x_pit_irq.irq = ret; 209 at91sam926x_pit_irq.irq = ret;
@@ -230,6 +235,8 @@ void __init at91sam926x_pit_init(void)
230 unsigned bits; 235 unsigned bits;
231 int ret; 236 int ret;
232 237
238 mck = ERR_PTR(-ENOENT);
239
233 /* For device tree enabled device: initialize here */ 240 /* For device tree enabled device: initialize here */
234 of_at91sam926x_pit_init(); 241 of_at91sam926x_pit_init();
235 242
@@ -237,7 +244,12 @@ void __init at91sam926x_pit_init(void)
237 * Use our actual MCK to figure out how many MCK/16 ticks per 244 * Use our actual MCK to figure out how many MCK/16 ticks per
238 * 1/HZ period (instead of a compile-time constant LATCH). 245 * 1/HZ period (instead of a compile-time constant LATCH).
239 */ 246 */
240 pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16; 247 if (IS_ERR(mck))
248 mck = clk_get(NULL, "mck");
249
250 if (IS_ERR(mck))
251 panic("AT91: PIT: Unable to get mck clk\n");
252 pit_rate = clk_get_rate(mck) / 16;
241 pit_cycle = (pit_rate + HZ/2) / HZ; 253 pit_cycle = (pit_rate + HZ/2) / HZ;
242 WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0); 254 WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
243 255
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 9405aa08b104..2f455ce35268 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -12,13 +12,13 @@
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
15#include <linux/clk/at91_pmc.h>
15 16
16#include <asm/irq.h> 17#include <asm/irq.h>
17#include <asm/mach/arch.h> 18#include <asm/mach/arch.h>
18#include <asm/mach/map.h> 19#include <asm/mach/map.h>
19#include <asm/system_misc.h> 20#include <asm/system_misc.h>
20#include <mach/at91sam9g45.h> 21#include <mach/at91sam9g45.h>
21#include <mach/at91_pmc.h>
22#include <mach/cpu.h> 22#include <mach/cpu.h>
23 23
24#include "at91_aic.h" 24#include "at91_aic.h"
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 388ec3aec4b9..4ef088c62eab 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -8,12 +8,12 @@
8 8
9#include <linux/module.h> 9#include <linux/module.h>
10#include <linux/dma-mapping.h> 10#include <linux/dma-mapping.h>
11#include <linux/clk/at91_pmc.h>
11 12
12#include <asm/irq.h> 13#include <asm/irq.h>
13#include <asm/mach/arch.h> 14#include <asm/mach/arch.h>
14#include <asm/mach/map.h> 15#include <asm/mach/map.h>
15#include <mach/at91sam9n12.h> 16#include <mach/at91sam9n12.h>
16#include <mach/at91_pmc.h>
17#include <mach/cpu.h> 17#include <mach/cpu.h>
18 18
19#include "board.h" 19#include "board.h"
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 0750ffb7e6b1..3651517abedf 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/clk/at91_pmc.h>
13 14
14#include <asm/proc-fns.h> 15#include <asm/proc-fns.h>
15#include <asm/irq.h> 16#include <asm/irq.h>
@@ -19,7 +20,6 @@
19#include <mach/cpu.h> 20#include <mach/cpu.h>
20#include <mach/at91_dbgu.h> 21#include <mach/at91_dbgu.h>
21#include <mach/at91sam9rl.h> 22#include <mach/at91sam9rl.h>
22#include <mach/at91_pmc.h>
23 23
24#include "at91_aic.h" 24#include "at91_aic.h"
25#include "at91_rstc.h" 25#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index e8a2e075a1b8..3e8ec26e39dc 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -8,12 +8,12 @@
8 8
9#include <linux/module.h> 9#include <linux/module.h>
10#include <linux/dma-mapping.h> 10#include <linux/dma-mapping.h>
11#include <linux/clk/at91_pmc.h>
11 12
12#include <asm/irq.h> 13#include <asm/irq.h>
13#include <asm/mach/arch.h> 14#include <asm/mach/arch.h>
14#include <asm/mach/map.h> 15#include <asm/mach/map.h>
15#include <mach/at91sam9x5.h> 16#include <mach/at91sam9x5.h>
16#include <mach/at91_pmc.h>
17#include <mach/cpu.h> 17#include <mach/cpu.h>
18 18
19#include "board.h" 19#include "board.h"
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index bf00d15d954d..075ec0576ada 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -16,6 +16,7 @@
16#include <linux/of_irq.h> 16#include <linux/of_irq.h>
17#include <linux/of_platform.h> 17#include <linux/of_platform.h>
18#include <linux/phy.h> 18#include <linux/phy.h>
19#include <linux/clk-provider.h>
19 20
20#include <asm/setup.h> 21#include <asm/setup.h>
21#include <asm/irq.h> 22#include <asm/irq.h>
@@ -26,6 +27,13 @@
26#include "at91_aic.h" 27#include "at91_aic.h"
27#include "generic.h" 28#include "generic.h"
28 29
30static void __init sama5_dt_timer_init(void)
31{
32#if defined(CONFIG_COMMON_CLK)
33 of_clk_init(NULL);
34#endif
35 at91sam926x_pit_init();
36}
29 37
30static const struct of_device_id irq_of_match[] __initconst = { 38static const struct of_device_id irq_of_match[] __initconst = {
31 39
@@ -72,7 +80,7 @@ static const char *sama5_dt_board_compat[] __initdata = {
72 80
73DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)") 81DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
74 /* Maintainer: Atmel */ 82 /* Maintainer: Atmel */
75 .init_time = at91sam926x_pit_init, 83 .init_time = sama5_dt_timer_init,
76 .map_io = at91_map_io, 84 .map_io = at91_map_io,
77 .handle_irq = at91_aic5_handle_irq, 85 .handle_irq = at91_aic5_handle_irq,
78 .init_early = at91_dt_initialize, 86 .init_early = at91_dt_initialize,
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 6b2630a92f71..72b257944733 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -24,9 +24,9 @@
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <linux/io.h> 25#include <linux/io.h>
26#include <linux/of_address.h> 26#include <linux/of_address.h>
27#include <linux/clk/at91_pmc.h>
27 28
28#include <mach/hardware.h> 29#include <mach/hardware.h>
29#include <mach/at91_pmc.h>
30#include <mach/cpu.h> 30#include <mach/cpu.h>
31 31
32#include <asm/proc-fns.h> 32#include <asm/proc-fns.h>
@@ -884,6 +884,11 @@ static int __init at91_pmc_init(unsigned long main_clock)
884#if defined(CONFIG_OF) 884#if defined(CONFIG_OF)
885static struct of_device_id pmc_ids[] = { 885static struct of_device_id pmc_ids[] = {
886 { .compatible = "atmel,at91rm9200-pmc" }, 886 { .compatible = "atmel,at91rm9200-pmc" },
887 { .compatible = "atmel,at91sam9260-pmc" },
888 { .compatible = "atmel,at91sam9g45-pmc" },
889 { .compatible = "atmel,at91sam9n12-pmc" },
890 { .compatible = "atmel,at91sam9x5-pmc" },
891 { .compatible = "atmel,sama5d3-pmc" },
887 { /*sentinel*/ } 892 { /*sentinel*/ }
888}; 893};
889 894
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 26dee3ce9397..631fa3b8c16d 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -46,11 +46,12 @@ extern void at91sam926x_pit_init(void);
46extern void at91x40_timer_init(void); 46extern void at91x40_timer_init(void);
47 47
48 /* Clocks */ 48 /* Clocks */
49#ifdef CONFIG_AT91_PMC_UNIT 49#ifdef CONFIG_OLD_CLK_AT91
50extern int __init at91_clock_init(unsigned long main_clock); 50extern int __init at91_clock_init(unsigned long main_clock);
51extern int __init at91_dt_clock_init(void); 51extern int __init at91_dt_clock_init(void);
52#else 52#else
53static int inline at91_clock_init(unsigned long main_clock) { return 0; } 53static int inline at91_clock_init(unsigned long main_clock) { return 0; }
54static int inline at91_dt_clock_init(void) { return 0; }
54#endif 55#endif
55struct device; 56struct device;
56 57
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 9986542e8060..d43b79f56e94 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -19,13 +19,13 @@
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/clk/at91_pmc.h>
22 23
23#include <asm/irq.h> 24#include <asm/irq.h>
24#include <linux/atomic.h> 25#include <linux/atomic.h>
25#include <asm/mach/time.h> 26#include <asm/mach/time.h>
26#include <asm/mach/irq.h> 27#include <asm/mach/irq.h>
27 28
28#include <mach/at91_pmc.h>
29#include <mach/cpu.h> 29#include <mach/cpu.h>
30 30
31#include "at91_aic.h" 31#include "at91_aic.h"
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 098c28ddf025..20018779bae7 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -13,8 +13,8 @@
13 */ 13 */
14 14
15#include <linux/linkage.h> 15#include <linux/linkage.h>
16#include <linux/clk/at91_pmc.h>
16#include <mach/hardware.h> 17#include <mach/hardware.h>
17#include <mach/at91_pmc.h>
18#include <mach/at91_ramc.h> 18#include <mach/at91_ramc.h>
19 19
20 20
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index 3ea86428ee09..3d775d08de08 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -9,360 +9,19 @@
9 9
10#include <linux/module.h> 10#include <linux/module.h>
11#include <linux/dma-mapping.h> 11#include <linux/dma-mapping.h>
12#include <linux/clk/at91_pmc.h>
12 13
13#include <asm/irq.h> 14#include <asm/irq.h>
14#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
15#include <asm/mach/map.h> 16#include <asm/mach/map.h>
16#include <mach/sama5d3.h> 17#include <mach/sama5d3.h>
17#include <mach/at91_pmc.h>
18#include <mach/cpu.h> 18#include <mach/cpu.h>
19 19
20#include "soc.h" 20#include "soc.h"
21#include "generic.h" 21#include "generic.h"
22#include "clock.h"
23#include "sam9_smc.h" 22#include "sam9_smc.h"
24 23
25/* -------------------------------------------------------------------- 24/* --------------------------------------------------------------------
26 * Clocks
27 * -------------------------------------------------------------------- */
28
29/*
30 * The peripheral clocks.
31 */
32
33static struct clk pioA_clk = {
34 .name = "pioA_clk",
35 .pid = SAMA5D3_ID_PIOA,
36 .type = CLK_TYPE_PERIPHERAL,
37};
38static struct clk pioB_clk = {
39 .name = "pioB_clk",
40 .pid = SAMA5D3_ID_PIOB,
41 .type = CLK_TYPE_PERIPHERAL,
42};
43static struct clk pioC_clk = {
44 .name = "pioC_clk",
45 .pid = SAMA5D3_ID_PIOC,
46 .type = CLK_TYPE_PERIPHERAL,
47};
48static struct clk pioD_clk = {
49 .name = "pioD_clk",
50 .pid = SAMA5D3_ID_PIOD,
51 .type = CLK_TYPE_PERIPHERAL,
52};
53static struct clk pioE_clk = {
54 .name = "pioE_clk",
55 .pid = SAMA5D3_ID_PIOE,
56 .type = CLK_TYPE_PERIPHERAL,
57};
58static struct clk usart0_clk = {
59 .name = "usart0_clk",
60 .pid = SAMA5D3_ID_USART0,
61 .type = CLK_TYPE_PERIPHERAL,
62 .div = AT91_PMC_PCR_DIV2,
63};
64static struct clk usart1_clk = {
65 .name = "usart1_clk",
66 .pid = SAMA5D3_ID_USART1,
67 .type = CLK_TYPE_PERIPHERAL,
68 .div = AT91_PMC_PCR_DIV2,
69};
70static struct clk usart2_clk = {
71 .name = "usart2_clk",
72 .pid = SAMA5D3_ID_USART2,
73 .type = CLK_TYPE_PERIPHERAL,
74 .div = AT91_PMC_PCR_DIV2,
75};
76static struct clk usart3_clk = {
77 .name = "usart3_clk",
78 .pid = SAMA5D3_ID_USART3,
79 .type = CLK_TYPE_PERIPHERAL,
80 .div = AT91_PMC_PCR_DIV2,
81};
82static struct clk uart0_clk = {
83 .name = "uart0_clk",
84 .pid = SAMA5D3_ID_UART0,
85 .type = CLK_TYPE_PERIPHERAL,
86 .div = AT91_PMC_PCR_DIV2,
87};
88static struct clk uart1_clk = {
89 .name = "uart1_clk",
90 .pid = SAMA5D3_ID_UART1,
91 .type = CLK_TYPE_PERIPHERAL,
92 .div = AT91_PMC_PCR_DIV2,
93};
94static struct clk twi0_clk = {
95 .name = "twi0_clk",
96 .pid = SAMA5D3_ID_TWI0,
97 .type = CLK_TYPE_PERIPHERAL,
98 .div = AT91_PMC_PCR_DIV2,
99};
100static struct clk twi1_clk = {
101 .name = "twi1_clk",
102 .pid = SAMA5D3_ID_TWI1,
103 .type = CLK_TYPE_PERIPHERAL,
104 .div = AT91_PMC_PCR_DIV2,
105};
106static struct clk twi2_clk = {
107 .name = "twi2_clk",
108 .pid = SAMA5D3_ID_TWI2,
109 .type = CLK_TYPE_PERIPHERAL,
110 .div = AT91_PMC_PCR_DIV2,
111};
112static struct clk mmc0_clk = {
113 .name = "mci0_clk",
114 .pid = SAMA5D3_ID_HSMCI0,
115 .type = CLK_TYPE_PERIPHERAL,
116};
117static struct clk mmc1_clk = {
118 .name = "mci1_clk",
119 .pid = SAMA5D3_ID_HSMCI1,
120 .type = CLK_TYPE_PERIPHERAL,
121};
122static struct clk mmc2_clk = {
123 .name = "mci2_clk",
124 .pid = SAMA5D3_ID_HSMCI2,
125 .type = CLK_TYPE_PERIPHERAL,
126};
127static struct clk spi0_clk = {
128 .name = "spi0_clk",
129 .pid = SAMA5D3_ID_SPI0,
130 .type = CLK_TYPE_PERIPHERAL,
131};
132static struct clk spi1_clk = {
133 .name = "spi1_clk",
134 .pid = SAMA5D3_ID_SPI1,
135 .type = CLK_TYPE_PERIPHERAL,
136};
137static struct clk tcb0_clk = {
138 .name = "tcb0_clk",
139 .pid = SAMA5D3_ID_TC0,
140 .type = CLK_TYPE_PERIPHERAL,
141 .div = AT91_PMC_PCR_DIV2,
142};
143static struct clk tcb1_clk = {
144 .name = "tcb1_clk",
145 .pid = SAMA5D3_ID_TC1,
146 .type = CLK_TYPE_PERIPHERAL,
147 .div = AT91_PMC_PCR_DIV2,
148};
149static struct clk adc_clk = {
150 .name = "adc_clk",
151 .pid = SAMA5D3_ID_ADC,
152 .type = CLK_TYPE_PERIPHERAL,
153 .div = AT91_PMC_PCR_DIV2,
154};
155static struct clk adc_op_clk = {
156 .name = "adc_op_clk",
157 .type = CLK_TYPE_PERIPHERAL,
158 .rate_hz = 5000000,
159};
160static struct clk dma0_clk = {
161 .name = "dma0_clk",
162 .pid = SAMA5D3_ID_DMA0,
163 .type = CLK_TYPE_PERIPHERAL,
164};
165static struct clk dma1_clk = {
166 .name = "dma1_clk",
167 .pid = SAMA5D3_ID_DMA1,
168 .type = CLK_TYPE_PERIPHERAL,
169};
170static struct clk uhphs_clk = {
171 .name = "uhphs",
172 .pid = SAMA5D3_ID_UHPHS,
173 .type = CLK_TYPE_PERIPHERAL,
174};
175static struct clk udphs_clk = {
176 .name = "udphs_clk",
177 .pid = SAMA5D3_ID_UDPHS,
178 .type = CLK_TYPE_PERIPHERAL,
179};
180/* gmac only for sama5d33, sama5d34, sama5d35 */
181static struct clk macb0_clk = {
182 .name = "macb0_clk",
183 .pid = SAMA5D3_ID_GMAC,
184 .type = CLK_TYPE_PERIPHERAL,
185};
186/* emac only for sama5d31, sama5d35 */
187static struct clk macb1_clk = {
188 .name = "macb1_clk",
189 .pid = SAMA5D3_ID_EMAC,
190 .type = CLK_TYPE_PERIPHERAL,
191};
192/* lcd only for sama5d31, sama5d33, sama5d34 */
193static struct clk lcdc_clk = {
194 .name = "lcdc_clk",
195 .pid = SAMA5D3_ID_LCDC,
196 .type = CLK_TYPE_PERIPHERAL,
197};
198/* isi only for sama5d33, sama5d35 */
199static struct clk isi_clk = {
200 .name = "isi_clk",
201 .pid = SAMA5D3_ID_ISI,
202 .type = CLK_TYPE_PERIPHERAL,
203};
204static struct clk can0_clk = {
205 .name = "can0_clk",
206 .pid = SAMA5D3_ID_CAN0,
207 .type = CLK_TYPE_PERIPHERAL,
208 .div = AT91_PMC_PCR_DIV2,
209};
210static struct clk can1_clk = {
211 .name = "can1_clk",
212 .pid = SAMA5D3_ID_CAN1,
213 .type = CLK_TYPE_PERIPHERAL,
214 .div = AT91_PMC_PCR_DIV2,
215};
216static struct clk ssc0_clk = {
217 .name = "ssc0_clk",
218 .pid = SAMA5D3_ID_SSC0,
219 .type = CLK_TYPE_PERIPHERAL,
220 .div = AT91_PMC_PCR_DIV2,
221};
222static struct clk ssc1_clk = {
223 .name = "ssc1_clk",
224 .pid = SAMA5D3_ID_SSC1,
225 .type = CLK_TYPE_PERIPHERAL,
226 .div = AT91_PMC_PCR_DIV2,
227};
228static struct clk sha_clk = {
229 .name = "sha_clk",
230 .pid = SAMA5D3_ID_SHA,
231 .type = CLK_TYPE_PERIPHERAL,
232 .div = AT91_PMC_PCR_DIV8,
233};
234static struct clk aes_clk = {
235 .name = "aes_clk",
236 .pid = SAMA5D3_ID_AES,
237 .type = CLK_TYPE_PERIPHERAL,
238};
239static struct clk tdes_clk = {
240 .name = "tdes_clk",
241 .pid = SAMA5D3_ID_TDES,
242 .type = CLK_TYPE_PERIPHERAL,
243};
244
245static struct clk *periph_clocks[] __initdata = {
246 &pioA_clk,
247 &pioB_clk,
248 &pioC_clk,
249 &pioD_clk,
250 &pioE_clk,
251 &usart0_clk,
252 &usart1_clk,
253 &usart2_clk,
254 &usart3_clk,
255 &uart0_clk,
256 &uart1_clk,
257 &twi0_clk,
258 &twi1_clk,
259 &twi2_clk,
260 &mmc0_clk,
261 &mmc1_clk,
262 &mmc2_clk,
263 &spi0_clk,
264 &spi1_clk,
265 &tcb0_clk,
266 &tcb1_clk,
267 &adc_clk,
268 &adc_op_clk,
269 &dma0_clk,
270 &dma1_clk,
271 &uhphs_clk,
272 &udphs_clk,
273 &macb0_clk,
274 &macb1_clk,
275 &lcdc_clk,
276 &isi_clk,
277 &can0_clk,
278 &can1_clk,
279 &ssc0_clk,
280 &ssc1_clk,
281 &sha_clk,
282 &aes_clk,
283 &tdes_clk,
284};
285
286static struct clk pck0 = {
287 .name = "pck0",
288 .pmc_mask = AT91_PMC_PCK0,
289 .type = CLK_TYPE_PROGRAMMABLE,
290 .id = 0,
291};
292
293static struct clk pck1 = {
294 .name = "pck1",
295 .pmc_mask = AT91_PMC_PCK1,
296 .type = CLK_TYPE_PROGRAMMABLE,
297 .id = 1,
298};
299
300static struct clk pck2 = {
301 .name = "pck2",
302 .pmc_mask = AT91_PMC_PCK2,
303 .type = CLK_TYPE_PROGRAMMABLE,
304 .id = 2,
305};
306
307static struct clk_lookup periph_clocks_lookups[] = {
308 /* lookup table for DT entries */
309 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
310 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
311 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
312 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
313 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk),
314 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk),
315 CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk),
316 CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk),
317 CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk),
318 CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk),
319 CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk),
320 CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk),
321 CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk),
322 CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk),
323 CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk),
324 CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk),
325 CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk),
326 CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk),
327 CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk),
328 CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk),
329 CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk),
330 CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk),
331 CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk),
332 CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
333 CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
334 CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
335 CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
336 CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
337 CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk),
338 CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk),
339 CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk),
340 CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk),
341 CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk),
342 CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk),
343 CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk),
344 CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk),
345 CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk),
346 CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk),
347 CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk),
348};
349
350static void __init sama5d3_register_clocks(void)
351{
352 int i;
353
354 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
355 clk_register(periph_clocks[i]);
356
357 clkdev_add_table(periph_clocks_lookups,
358 ARRAY_SIZE(periph_clocks_lookups));
359
360 clk_register(&pck0);
361 clk_register(&pck1);
362 clk_register(&pck2);
363}
364
365/* --------------------------------------------------------------------
366 * AT91SAM9x5 processor initialization 25 * AT91SAM9x5 processor initialization
367 * -------------------------------------------------------------------- */ 26 * -------------------------------------------------------------------- */
368 27
@@ -378,6 +37,5 @@ static void __init sama5d3_initialize(void)
378 37
379AT91_SOC_START(sama5d3) 38AT91_SOC_START(sama5d3)
380 .map_io = sama5d3_map_io, 39 .map_io = sama5d3_map_io,
381 .register_clocks = sama5d3_register_clocks,
382 .init = sama5d3_initialize, 40 .init = sama5d3_initialize,
383AT91_SOC_END 41AT91_SOC_END
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 094b3459c288..7d3f7cc61081 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -11,6 +11,7 @@
11#include <linux/pm.h> 11#include <linux/pm.h>
12#include <linux/of_address.h> 12#include <linux/of_address.h>
13#include <linux/pinctrl/machine.h> 13#include <linux/pinctrl/machine.h>
14#include <linux/clk/at91_pmc.h>
14 15
15#include <asm/system_misc.h> 16#include <asm/system_misc.h>
16#include <asm/mach/map.h> 17#include <asm/mach/map.h>
@@ -18,7 +19,6 @@
18#include <mach/hardware.h> 19#include <mach/hardware.h>
19#include <mach/cpu.h> 20#include <mach/cpu.h>
20#include <mach/at91_dbgu.h> 21#include <mach/at91_dbgu.h>
21#include <mach/at91_pmc.h>
22 22
23#include "at91_shdwc.h" 23#include "at91_shdwc.h"
24#include "soc.h" 24#include "soc.h"
@@ -491,7 +491,8 @@ void __init at91rm9200_dt_initialize(void)
491 at91_dt_clock_init(); 491 at91_dt_clock_init();
492 492
493 /* Register the processor-specific clocks */ 493 /* Register the processor-specific clocks */
494 at91_boot_soc.register_clocks(); 494 if (at91_boot_soc.register_clocks)
495 at91_boot_soc.register_clocks();
495 496
496 at91_boot_soc.init(); 497 at91_boot_soc.init();
497} 498}
@@ -506,7 +507,8 @@ void __init at91_dt_initialize(void)
506 at91_dt_clock_init(); 507 at91_dt_clock_init();
507 508
508 /* Register the processor-specific clocks */ 509 /* Register the processor-specific clocks */
509 at91_boot_soc.register_clocks(); 510 if (at91_boot_soc.register_clocks)
511 at91_boot_soc.register_clocks();
510 512
511 if (at91_boot_soc.init) 513 if (at91_boot_soc.init)
512 at91_boot_soc.init(); 514 at91_boot_soc.init();
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 7a10bc9a23e7..ace7309c4369 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/
35obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ 35obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
36obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o 36obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
37obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ 37obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
38obj-$(CONFIG_COMMON_CLK_AT91) += at91/
38 39
39obj-$(CONFIG_X86) += x86/ 40obj-$(CONFIG_X86) += x86/
40 41
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
new file mode 100644
index 000000000000..0e92b716f934
--- /dev/null
+++ b/drivers/clk/at91/Makefile
@@ -0,0 +1,12 @@
1#
2# Makefile for at91 specific clk
3#
4
5obj-y += pmc.o
6obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
7obj-y += clk-system.o clk-peripheral.o
8
9obj-$(CONFIG_AT91_PROGRAMMABLE_CLOCKS) += clk-programmable.o
10obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
11obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
12obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
new file mode 100644
index 000000000000..8e9e8cc0412d
--- /dev/null
+++ b/drivers/clk/at91/clk-main.c
@@ -0,0 +1,187 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/delay.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/of_irq.h>
18#include <linux/io.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/sched.h>
22#include <linux/wait.h>
23
24#include "pmc.h"
25
26#define SLOW_CLOCK_FREQ 32768
27#define MAINF_DIV 16
28#define MAINFRDY_TIMEOUT (((MAINF_DIV + 1) * USEC_PER_SEC) / \
29 SLOW_CLOCK_FREQ)
30#define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ)
31#define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT
32
33struct clk_main {
34 struct clk_hw hw;
35 struct at91_pmc *pmc;
36 unsigned long rate;
37 unsigned int irq;
38 wait_queue_head_t wait;
39};
40
41#define to_clk_main(hw) container_of(hw, struct clk_main, hw)
42
43static irqreturn_t clk_main_irq_handler(int irq, void *dev_id)
44{
45 struct clk_main *clkmain = (struct clk_main *)dev_id;
46
47 wake_up(&clkmain->wait);
48 disable_irq_nosync(clkmain->irq);
49
50 return IRQ_HANDLED;
51}
52
53static int clk_main_prepare(struct clk_hw *hw)
54{
55 struct clk_main *clkmain = to_clk_main(hw);
56 struct at91_pmc *pmc = clkmain->pmc;
57 unsigned long halt_time, timeout;
58 u32 tmp;
59
60 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS)) {
61 enable_irq(clkmain->irq);
62 wait_event(clkmain->wait,
63 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS);
64 }
65
66 if (clkmain->rate)
67 return 0;
68
69 timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
70 do {
71 halt_time = jiffies;
72 tmp = pmc_read(pmc, AT91_CKGR_MCFR);
73 if (tmp & AT91_PMC_MAINRDY)
74 return 0;
75 usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
76 } while (time_before(halt_time, timeout));
77
78 return 0;
79}
80
81static int clk_main_is_prepared(struct clk_hw *hw)
82{
83 struct clk_main *clkmain = to_clk_main(hw);
84
85 return !!(pmc_read(clkmain->pmc, AT91_PMC_SR) & AT91_PMC_MOSCS);
86}
87
88static unsigned long clk_main_recalc_rate(struct clk_hw *hw,
89 unsigned long parent_rate)
90{
91 u32 tmp;
92 struct clk_main *clkmain = to_clk_main(hw);
93 struct at91_pmc *pmc = clkmain->pmc;
94
95 if (clkmain->rate)
96 return clkmain->rate;
97
98 tmp = pmc_read(pmc, AT91_CKGR_MCFR) & AT91_PMC_MAINF;
99 clkmain->rate = (tmp * parent_rate) / MAINF_DIV;
100
101 return clkmain->rate;
102}
103
104static const struct clk_ops main_ops = {
105 .prepare = clk_main_prepare,
106 .is_prepared = clk_main_is_prepared,
107 .recalc_rate = clk_main_recalc_rate,
108};
109
110static struct clk * __init
111at91_clk_register_main(struct at91_pmc *pmc,
112 unsigned int irq,
113 const char *name,
114 const char *parent_name,
115 unsigned long rate)
116{
117 int ret;
118 struct clk_main *clkmain;
119 struct clk *clk = NULL;
120 struct clk_init_data init;
121
122 if (!pmc || !irq || !name)
123 return ERR_PTR(-EINVAL);
124
125 if (!rate && !parent_name)
126 return ERR_PTR(-EINVAL);
127
128 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
129 if (!clkmain)
130 return ERR_PTR(-ENOMEM);
131
132 init.name = name;
133 init.ops = &main_ops;
134 init.parent_names = parent_name ? &parent_name : NULL;
135 init.num_parents = parent_name ? 1 : 0;
136 init.flags = parent_name ? 0 : CLK_IS_ROOT;
137
138 clkmain->hw.init = &init;
139 clkmain->rate = rate;
140 clkmain->pmc = pmc;
141 clkmain->irq = irq;
142 init_waitqueue_head(&clkmain->wait);
143 irq_set_status_flags(clkmain->irq, IRQ_NOAUTOEN);
144 ret = request_irq(clkmain->irq, clk_main_irq_handler,
145 IRQF_TRIGGER_HIGH, "clk-main", clkmain);
146 if (ret)
147 return ERR_PTR(ret);
148
149 clk = clk_register(NULL, &clkmain->hw);
150 if (IS_ERR(clk)) {
151 free_irq(clkmain->irq, clkmain);
152 kfree(clkmain);
153 }
154
155 return clk;
156}
157
158
159
160static void __init
161of_at91_clk_main_setup(struct device_node *np, struct at91_pmc *pmc)
162{
163 struct clk *clk;
164 unsigned int irq;
165 const char *parent_name;
166 const char *name = np->name;
167 u32 rate = 0;
168
169 parent_name = of_clk_get_parent_name(np, 0);
170 of_property_read_string(np, "clock-output-names", &name);
171 of_property_read_u32(np, "clock-frequency", &rate);
172 irq = irq_of_parse_and_map(np, 0);
173 if (!irq)
174 return;
175
176 clk = at91_clk_register_main(pmc, irq, name, parent_name, rate);
177 if (IS_ERR(clk))
178 return;
179
180 of_clk_add_provider(np, of_clk_src_simple_get, clk);
181}
182
183void __init of_at91rm9200_clk_main_setup(struct device_node *np,
184 struct at91_pmc *pmc)
185{
186 of_at91_clk_main_setup(np, pmc);
187}
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
new file mode 100644
index 000000000000..bd313f7816a8
--- /dev/null
+++ b/drivers/clk/at91/clk-master.c
@@ -0,0 +1,270 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/io.h>
18#include <linux/wait.h>
19#include <linux/sched.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22
23#include "pmc.h"
24
25#define MASTER_SOURCE_MAX 4
26
27#define MASTER_PRES_MASK 0x7
28#define MASTER_PRES_MAX MASTER_PRES_MASK
29#define MASTER_DIV_SHIFT 8
30#define MASTER_DIV_MASK 0x3
31
32struct clk_master_characteristics {
33 struct clk_range output;
34 u32 divisors[4];
35 u8 have_div3_pres;
36};
37
38struct clk_master_layout {
39 u32 mask;
40 u8 pres_shift;
41};
42
43#define to_clk_master(hw) container_of(hw, struct clk_master, hw)
44
45struct clk_master {
46 struct clk_hw hw;
47 struct at91_pmc *pmc;
48 unsigned int irq;
49 wait_queue_head_t wait;
50 const struct clk_master_layout *layout;
51 const struct clk_master_characteristics *characteristics;
52};
53
54static irqreturn_t clk_master_irq_handler(int irq, void *dev_id)
55{
56 struct clk_master *master = (struct clk_master *)dev_id;
57
58 wake_up(&master->wait);
59 disable_irq_nosync(master->irq);
60
61 return IRQ_HANDLED;
62}
63static int clk_master_prepare(struct clk_hw *hw)
64{
65 struct clk_master *master = to_clk_master(hw);
66 struct at91_pmc *pmc = master->pmc;
67
68 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY)) {
69 enable_irq(master->irq);
70 wait_event(master->wait,
71 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY);
72 }
73
74 return 0;
75}
76
77static int clk_master_is_prepared(struct clk_hw *hw)
78{
79 struct clk_master *master = to_clk_master(hw);
80
81 return !!(pmc_read(master->pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY);
82}
83
84static unsigned long clk_master_recalc_rate(struct clk_hw *hw,
85 unsigned long parent_rate)
86{
87 u8 pres;
88 u8 div;
89 unsigned long rate = parent_rate;
90 struct clk_master *master = to_clk_master(hw);
91 struct at91_pmc *pmc = master->pmc;
92 const struct clk_master_layout *layout = master->layout;
93 const struct clk_master_characteristics *characteristics =
94 master->characteristics;
95 u32 tmp;
96
97 pmc_lock(pmc);
98 tmp = pmc_read(pmc, AT91_PMC_MCKR) & layout->mask;
99 pmc_unlock(pmc);
100
101 pres = (tmp >> layout->pres_shift) & MASTER_PRES_MASK;
102 div = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
103
104 if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX)
105 rate /= 3;
106 else
107 rate >>= pres;
108
109 rate /= characteristics->divisors[div];
110
111 if (rate < characteristics->output.min)
112 pr_warn("master clk is underclocked");
113 else if (rate > characteristics->output.max)
114 pr_warn("master clk is overclocked");
115
116 return rate;
117}
118
119static u8 clk_master_get_parent(struct clk_hw *hw)
120{
121 struct clk_master *master = to_clk_master(hw);
122 struct at91_pmc *pmc = master->pmc;
123
124 return pmc_read(pmc, AT91_PMC_MCKR) & AT91_PMC_CSS;
125}
126
127static const struct clk_ops master_ops = {
128 .prepare = clk_master_prepare,
129 .is_prepared = clk_master_is_prepared,
130 .recalc_rate = clk_master_recalc_rate,
131 .get_parent = clk_master_get_parent,
132};
133
134static struct clk * __init
135at91_clk_register_master(struct at91_pmc *pmc, unsigned int irq,
136 const char *name, int num_parents,
137 const char **parent_names,
138 const struct clk_master_layout *layout,
139 const struct clk_master_characteristics *characteristics)
140{
141 int ret;
142 struct clk_master *master;
143 struct clk *clk = NULL;
144 struct clk_init_data init;
145
146 if (!pmc || !irq || !name || !num_parents || !parent_names)
147 return ERR_PTR(-EINVAL);
148
149 master = kzalloc(sizeof(*master), GFP_KERNEL);
150 if (!master)
151 return ERR_PTR(-ENOMEM);
152
153 init.name = name;
154 init.ops = &master_ops;
155 init.parent_names = parent_names;
156 init.num_parents = num_parents;
157 init.flags = 0;
158
159 master->hw.init = &init;
160 master->layout = layout;
161 master->characteristics = characteristics;
162 master->pmc = pmc;
163 master->irq = irq;
164 init_waitqueue_head(&master->wait);
165 irq_set_status_flags(master->irq, IRQ_NOAUTOEN);
166 ret = request_irq(master->irq, clk_master_irq_handler,
167 IRQF_TRIGGER_HIGH, "clk-master", master);
168 if (ret)
169 return ERR_PTR(ret);
170
171 clk = clk_register(NULL, &master->hw);
172 if (IS_ERR(clk))
173 kfree(master);
174
175 return clk;
176}
177
178
179static const struct clk_master_layout at91rm9200_master_layout = {
180 .mask = 0x31F,
181 .pres_shift = 2,
182};
183
184static const struct clk_master_layout at91sam9x5_master_layout = {
185 .mask = 0x373,
186 .pres_shift = 4,
187};
188
189
190static struct clk_master_characteristics * __init
191of_at91_clk_master_get_characteristics(struct device_node *np)
192{
193 struct clk_master_characteristics *characteristics;
194
195 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
196 if (!characteristics)
197 return NULL;
198
199 if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output))
200 goto out_free_characteristics;
201
202 of_property_read_u32_array(np, "atmel,clk-divisors",
203 characteristics->divisors, 4);
204
205 characteristics->have_div3_pres =
206 of_property_read_bool(np, "atmel,master-clk-have-div3-pres");
207
208 return characteristics;
209
210out_free_characteristics:
211 kfree(characteristics);
212 return NULL;
213}
214
215static void __init
216of_at91_clk_master_setup(struct device_node *np, struct at91_pmc *pmc,
217 const struct clk_master_layout *layout)
218{
219 struct clk *clk;
220 int num_parents;
221 int i;
222 unsigned int irq;
223 const char *parent_names[MASTER_SOURCE_MAX];
224 const char *name = np->name;
225 struct clk_master_characteristics *characteristics;
226
227 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
228 if (num_parents <= 0 || num_parents > MASTER_SOURCE_MAX)
229 return;
230
231 for (i = 0; i < num_parents; ++i) {
232 parent_names[i] = of_clk_get_parent_name(np, i);
233 if (!parent_names[i])
234 return;
235 }
236
237 of_property_read_string(np, "clock-output-names", &name);
238
239 characteristics = of_at91_clk_master_get_characteristics(np);
240 if (!characteristics)
241 return;
242
243 irq = irq_of_parse_and_map(np, 0);
244 if (!irq)
245 return;
246
247 clk = at91_clk_register_master(pmc, irq, name, num_parents,
248 parent_names, layout,
249 characteristics);
250 if (IS_ERR(clk))
251 goto out_free_characteristics;
252
253 of_clk_add_provider(np, of_clk_src_simple_get, clk);
254 return;
255
256out_free_characteristics:
257 kfree(characteristics);
258}
259
260void __init of_at91rm9200_clk_master_setup(struct device_node *np,
261 struct at91_pmc *pmc)
262{
263 of_at91_clk_master_setup(np, pmc, &at91rm9200_master_layout);
264}
265
266void __init of_at91sam9x5_clk_master_setup(struct device_node *np,
267 struct at91_pmc *pmc)
268{
269 of_at91_clk_master_setup(np, pmc, &at91sam9x5_master_layout);
270}
diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c
new file mode 100644
index 000000000000..597fed423d7d
--- /dev/null
+++ b/drivers/clk/at91/clk-peripheral.c
@@ -0,0 +1,410 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17
18#include "pmc.h"
19
20#define PERIPHERAL_MAX 64
21
22#define PERIPHERAL_AT91RM9200 0
23#define PERIPHERAL_AT91SAM9X5 1
24
25#define PERIPHERAL_ID_MIN 2
26#define PERIPHERAL_ID_MAX 31
27#define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
28
29#define PERIPHERAL_RSHIFT_MASK 0x3
30#define PERIPHERAL_RSHIFT(val) (((val) >> 16) & PERIPHERAL_RSHIFT_MASK)
31
32#define PERIPHERAL_MAX_SHIFT 4
33
34struct clk_peripheral {
35 struct clk_hw hw;
36 struct at91_pmc *pmc;
37 u32 id;
38};
39
40#define to_clk_peripheral(hw) container_of(hw, struct clk_peripheral, hw)
41
42struct clk_sam9x5_peripheral {
43 struct clk_hw hw;
44 struct at91_pmc *pmc;
45 struct clk_range range;
46 u32 id;
47 u32 div;
48 bool auto_div;
49};
50
51#define to_clk_sam9x5_peripheral(hw) \
52 container_of(hw, struct clk_sam9x5_peripheral, hw)
53
54static int clk_peripheral_enable(struct clk_hw *hw)
55{
56 struct clk_peripheral *periph = to_clk_peripheral(hw);
57 struct at91_pmc *pmc = periph->pmc;
58 int offset = AT91_PMC_PCER;
59 u32 id = periph->id;
60
61 if (id < PERIPHERAL_ID_MIN)
62 return 0;
63 if (id > PERIPHERAL_ID_MAX)
64 offset = AT91_PMC_PCER1;
65 pmc_write(pmc, offset, PERIPHERAL_MASK(id));
66 return 0;
67}
68
69static void clk_peripheral_disable(struct clk_hw *hw)
70{
71 struct clk_peripheral *periph = to_clk_peripheral(hw);
72 struct at91_pmc *pmc = periph->pmc;
73 int offset = AT91_PMC_PCDR;
74 u32 id = periph->id;
75
76 if (id < PERIPHERAL_ID_MIN)
77 return;
78 if (id > PERIPHERAL_ID_MAX)
79 offset = AT91_PMC_PCDR1;
80 pmc_write(pmc, offset, PERIPHERAL_MASK(id));
81}
82
83static int clk_peripheral_is_enabled(struct clk_hw *hw)
84{
85 struct clk_peripheral *periph = to_clk_peripheral(hw);
86 struct at91_pmc *pmc = periph->pmc;
87 int offset = AT91_PMC_PCSR;
88 u32 id = periph->id;
89
90 if (id < PERIPHERAL_ID_MIN)
91 return 1;
92 if (id > PERIPHERAL_ID_MAX)
93 offset = AT91_PMC_PCSR1;
94 return !!(pmc_read(pmc, offset) & PERIPHERAL_MASK(id));
95}
96
97static const struct clk_ops peripheral_ops = {
98 .enable = clk_peripheral_enable,
99 .disable = clk_peripheral_disable,
100 .is_enabled = clk_peripheral_is_enabled,
101};
102
103static struct clk * __init
104at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name,
105 const char *parent_name, u32 id)
106{
107 struct clk_peripheral *periph;
108 struct clk *clk = NULL;
109 struct clk_init_data init;
110
111 if (!pmc || !name || !parent_name || id > PERIPHERAL_ID_MAX)
112 return ERR_PTR(-EINVAL);
113
114 periph = kzalloc(sizeof(*periph), GFP_KERNEL);
115 if (!periph)
116 return ERR_PTR(-ENOMEM);
117
118 init.name = name;
119 init.ops = &peripheral_ops;
120 init.parent_names = (parent_name ? &parent_name : NULL);
121 init.num_parents = (parent_name ? 1 : 0);
122 init.flags = 0;
123
124 periph->id = id;
125 periph->hw.init = &init;
126 periph->pmc = pmc;
127
128 clk = clk_register(NULL, &periph->hw);
129 if (IS_ERR(clk))
130 kfree(periph);
131
132 return clk;
133}
134
135static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph)
136{
137 struct clk *parent;
138 unsigned long parent_rate;
139 int shift = 0;
140
141 if (!periph->auto_div)
142 return;
143
144 if (periph->range.max) {
145 parent = clk_get_parent_by_index(periph->hw.clk, 0);
146 parent_rate = __clk_get_rate(parent);
147 if (!parent_rate)
148 return;
149
150 for (; shift < PERIPHERAL_MAX_SHIFT; shift++) {
151 if (parent_rate >> shift <= periph->range.max)
152 break;
153 }
154 }
155
156 periph->auto_div = false;
157 periph->div = shift;
158}
159
160static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)
161{
162 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
163 struct at91_pmc *pmc = periph->pmc;
164
165 if (periph->id < PERIPHERAL_ID_MIN)
166 return 0;
167
168 pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID) |
169 AT91_PMC_PCR_CMD |
170 AT91_PMC_PCR_DIV(periph->div) |
171 AT91_PMC_PCR_EN);
172 return 0;
173}
174
175static void clk_sam9x5_peripheral_disable(struct clk_hw *hw)
176{
177 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
178 struct at91_pmc *pmc = periph->pmc;
179
180 if (periph->id < PERIPHERAL_ID_MIN)
181 return;
182
183 pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID) |
184 AT91_PMC_PCR_CMD);
185}
186
187static int clk_sam9x5_peripheral_is_enabled(struct clk_hw *hw)
188{
189 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
190 struct at91_pmc *pmc = periph->pmc;
191 int ret;
192
193 if (periph->id < PERIPHERAL_ID_MIN)
194 return 1;
195
196 pmc_lock(pmc);
197 pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID));
198 ret = !!(pmc_read(pmc, AT91_PMC_PCR) & AT91_PMC_PCR_EN);
199 pmc_unlock(pmc);
200
201 return ret;
202}
203
204static unsigned long
205clk_sam9x5_peripheral_recalc_rate(struct clk_hw *hw,
206 unsigned long parent_rate)
207{
208 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
209 struct at91_pmc *pmc = periph->pmc;
210 u32 tmp;
211
212 if (periph->id < PERIPHERAL_ID_MIN)
213 return parent_rate;
214
215 pmc_lock(pmc);
216 pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID));
217 tmp = pmc_read(pmc, AT91_PMC_PCR);
218 pmc_unlock(pmc);
219
220 if (tmp & AT91_PMC_PCR_EN) {
221 periph->div = PERIPHERAL_RSHIFT(tmp);
222 periph->auto_div = false;
223 } else {
224 clk_sam9x5_peripheral_autodiv(periph);
225 }
226
227 return parent_rate >> periph->div;
228}
229
230static long clk_sam9x5_peripheral_round_rate(struct clk_hw *hw,
231 unsigned long rate,
232 unsigned long *parent_rate)
233{
234 int shift = 0;
235 unsigned long best_rate;
236 unsigned long best_diff;
237 unsigned long cur_rate = *parent_rate;
238 unsigned long cur_diff;
239 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
240
241 if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max)
242 return *parent_rate;
243
244 if (periph->range.max) {
245 for (; shift < PERIPHERAL_MAX_SHIFT; shift++) {
246 cur_rate = *parent_rate >> shift;
247 if (cur_rate <= periph->range.max)
248 break;
249 }
250 }
251
252 if (rate >= cur_rate)
253 return cur_rate;
254
255 best_diff = cur_rate - rate;
256 best_rate = cur_rate;
257 for (; shift < PERIPHERAL_MAX_SHIFT; shift++) {
258 cur_rate = *parent_rate >> shift;
259 if (cur_rate < rate)
260 cur_diff = rate - cur_rate;
261 else
262 cur_diff = cur_rate - rate;
263
264 if (cur_diff < best_diff) {
265 best_diff = cur_diff;
266 best_rate = cur_rate;
267 }
268
269 if (!best_diff || cur_rate < rate)
270 break;
271 }
272
273 return best_rate;
274}
275
276static int clk_sam9x5_peripheral_set_rate(struct clk_hw *hw,
277 unsigned long rate,
278 unsigned long parent_rate)
279{
280 int shift;
281 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
282 if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max) {
283 if (parent_rate == rate)
284 return 0;
285 else
286 return -EINVAL;
287 }
288
289 if (periph->range.max && rate > periph->range.max)
290 return -EINVAL;
291
292 for (shift = 0; shift < PERIPHERAL_MAX_SHIFT; shift++) {
293 if (parent_rate >> shift == rate) {
294 periph->auto_div = false;
295 periph->div = shift;
296 return 0;
297 }
298 }
299
300 return -EINVAL;
301}
302
303static const struct clk_ops sam9x5_peripheral_ops = {
304 .enable = clk_sam9x5_peripheral_enable,
305 .disable = clk_sam9x5_peripheral_disable,
306 .is_enabled = clk_sam9x5_peripheral_is_enabled,
307 .recalc_rate = clk_sam9x5_peripheral_recalc_rate,
308 .round_rate = clk_sam9x5_peripheral_round_rate,
309 .set_rate = clk_sam9x5_peripheral_set_rate,
310};
311
312static struct clk * __init
313at91_clk_register_sam9x5_peripheral(struct at91_pmc *pmc, const char *name,
314 const char *parent_name, u32 id,
315 const struct clk_range *range)
316{
317 struct clk_sam9x5_peripheral *periph;
318 struct clk *clk = NULL;
319 struct clk_init_data init;
320
321 if (!pmc || !name || !parent_name)
322 return ERR_PTR(-EINVAL);
323
324 periph = kzalloc(sizeof(*periph), GFP_KERNEL);
325 if (!periph)
326 return ERR_PTR(-ENOMEM);
327
328 init.name = name;
329 init.ops = &sam9x5_peripheral_ops;
330 init.parent_names = (parent_name ? &parent_name : NULL);
331 init.num_parents = (parent_name ? 1 : 0);
332 init.flags = 0;
333
334 periph->id = id;
335 periph->hw.init = &init;
336 periph->div = 0;
337 periph->pmc = pmc;
338 periph->auto_div = true;
339 periph->range = *range;
340
341 clk = clk_register(NULL, &periph->hw);
342 if (IS_ERR(clk))
343 kfree(periph);
344 else
345 clk_sam9x5_peripheral_autodiv(periph);
346
347 return clk;
348}
349
350static void __init
351of_at91_clk_periph_setup(struct device_node *np, struct at91_pmc *pmc, u8 type)
352{
353 int num;
354 u32 id;
355 struct clk *clk;
356 const char *parent_name;
357 const char *name;
358 struct device_node *periphclknp;
359
360 parent_name = of_clk_get_parent_name(np, 0);
361 if (!parent_name)
362 return;
363
364 num = of_get_child_count(np);
365 if (!num || num > PERIPHERAL_MAX)
366 return;
367
368 for_each_child_of_node(np, periphclknp) {
369 if (of_property_read_u32(periphclknp, "reg", &id))
370 continue;
371
372 if (id >= PERIPHERAL_MAX)
373 continue;
374
375 if (of_property_read_string(np, "clock-output-names", &name))
376 name = periphclknp->name;
377
378 if (type == PERIPHERAL_AT91RM9200) {
379 clk = at91_clk_register_peripheral(pmc, name,
380 parent_name, id);
381 } else {
382 struct clk_range range = CLK_RANGE(0, 0);
383
384 of_at91_get_clk_range(periphclknp,
385 "atmel,clk-output-range",
386 &range);
387
388 clk = at91_clk_register_sam9x5_peripheral(pmc, name,
389 parent_name,
390 id, &range);
391 }
392
393 if (IS_ERR(clk))
394 continue;
395
396 of_clk_add_provider(periphclknp, of_clk_src_simple_get, clk);
397 }
398}
399
400void __init of_at91rm9200_clk_periph_setup(struct device_node *np,
401 struct at91_pmc *pmc)
402{
403 of_at91_clk_periph_setup(np, pmc, PERIPHERAL_AT91RM9200);
404}
405
406void __init of_at91sam9x5_clk_periph_setup(struct device_node *np,
407 struct at91_pmc *pmc)
408{
409 of_at91_clk_periph_setup(np, pmc, PERIPHERAL_AT91SAM9X5);
410}
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
new file mode 100644
index 000000000000..cf6ed023504c
--- /dev/null
+++ b/drivers/clk/at91/clk-pll.c
@@ -0,0 +1,531 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/io.h>
18#include <linux/wait.h>
19#include <linux/sched.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22
23#include "pmc.h"
24
25#define PLL_STATUS_MASK(id) (1 << (1 + (id)))
26#define PLL_REG(id) (AT91_CKGR_PLLAR + ((id) * 4))
27#define PLL_DIV_MASK 0xff
28#define PLL_DIV_MAX PLL_DIV_MASK
29#define PLL_DIV(reg) ((reg) & PLL_DIV_MASK)
30#define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
31 (layout)->mul_mask)
32#define PLL_ICPR_SHIFT(id) ((id) * 16)
33#define PLL_ICPR_MASK(id) (0xffff << PLL_ICPR_SHIFT(id))
34#define PLL_MAX_COUNT 0x3ff
35#define PLL_COUNT_SHIFT 8
36#define PLL_OUT_SHIFT 14
37#define PLL_MAX_ID 1
38
39struct clk_pll_characteristics {
40 struct clk_range input;
41 int num_output;
42 struct clk_range *output;
43 u16 *icpll;
44 u8 *out;
45};
46
47struct clk_pll_layout {
48 u32 pllr_mask;
49 u16 mul_mask;
50 u8 mul_shift;
51};
52
53#define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
54
55struct clk_pll {
56 struct clk_hw hw;
57 struct at91_pmc *pmc;
58 unsigned int irq;
59 wait_queue_head_t wait;
60 u8 id;
61 u8 div;
62 u8 range;
63 u16 mul;
64 const struct clk_pll_layout *layout;
65 const struct clk_pll_characteristics *characteristics;
66};
67
68static irqreturn_t clk_pll_irq_handler(int irq, void *dev_id)
69{
70 struct clk_pll *pll = (struct clk_pll *)dev_id;
71
72 wake_up(&pll->wait);
73 disable_irq_nosync(pll->irq);
74
75 return IRQ_HANDLED;
76}
77
78static int clk_pll_prepare(struct clk_hw *hw)
79{
80 struct clk_pll *pll = to_clk_pll(hw);
81 struct at91_pmc *pmc = pll->pmc;
82 const struct clk_pll_layout *layout = pll->layout;
83 const struct clk_pll_characteristics *characteristics =
84 pll->characteristics;
85 u8 id = pll->id;
86 u32 mask = PLL_STATUS_MASK(id);
87 int offset = PLL_REG(id);
88 u8 out = 0;
89 u32 pllr, icpr;
90 u8 div;
91 u16 mul;
92
93 pllr = pmc_read(pmc, offset);
94 div = PLL_DIV(pllr);
95 mul = PLL_MUL(pllr, layout);
96
97 if ((pmc_read(pmc, AT91_PMC_SR) & mask) &&
98 (div == pll->div && mul == pll->mul))
99 return 0;
100
101 if (characteristics->out)
102 out = characteristics->out[pll->range];
103 if (characteristics->icpll) {
104 icpr = pmc_read(pmc, AT91_PMC_PLLICPR) & ~PLL_ICPR_MASK(id);
105 icpr |= (characteristics->icpll[pll->range] <<
106 PLL_ICPR_SHIFT(id));
107 pmc_write(pmc, AT91_PMC_PLLICPR, icpr);
108 }
109
110 pllr &= ~layout->pllr_mask;
111 pllr |= layout->pllr_mask &
112 (pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) |
113 (out << PLL_OUT_SHIFT) |
114 ((pll->mul & layout->mul_mask) << layout->mul_shift));
115 pmc_write(pmc, offset, pllr);
116
117 while (!(pmc_read(pmc, AT91_PMC_SR) & mask)) {
118 enable_irq(pll->irq);
119 wait_event(pll->wait,
120 pmc_read(pmc, AT91_PMC_SR) & mask);
121 }
122
123 return 0;
124}
125
126static int clk_pll_is_prepared(struct clk_hw *hw)
127{
128 struct clk_pll *pll = to_clk_pll(hw);
129 struct at91_pmc *pmc = pll->pmc;
130
131 return !!(pmc_read(pmc, AT91_PMC_SR) &
132 PLL_STATUS_MASK(pll->id));
133}
134
135static void clk_pll_unprepare(struct clk_hw *hw)
136{
137 struct clk_pll *pll = to_clk_pll(hw);
138 struct at91_pmc *pmc = pll->pmc;
139 const struct clk_pll_layout *layout = pll->layout;
140 int offset = PLL_REG(pll->id);
141 u32 tmp = pmc_read(pmc, offset) & ~(layout->pllr_mask);
142
143 pmc_write(pmc, offset, tmp);
144}
145
146static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
147 unsigned long parent_rate)
148{
149 struct clk_pll *pll = to_clk_pll(hw);
150 const struct clk_pll_layout *layout = pll->layout;
151 struct at91_pmc *pmc = pll->pmc;
152 int offset = PLL_REG(pll->id);
153 u32 tmp = pmc_read(pmc, offset) & layout->pllr_mask;
154 u8 div = PLL_DIV(tmp);
155 u16 mul = PLL_MUL(tmp, layout);
156 if (!div || !mul)
157 return 0;
158
159 return (parent_rate * (mul + 1)) / div;
160}
161
162static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
163 unsigned long parent_rate,
164 u32 *div, u32 *mul,
165 u32 *index) {
166 unsigned long maxrate;
167 unsigned long minrate;
168 unsigned long divrate;
169 unsigned long bestdiv = 1;
170 unsigned long bestmul;
171 unsigned long tmpdiv;
172 unsigned long roundup;
173 unsigned long rounddown;
174 unsigned long remainder;
175 unsigned long bestremainder;
176 unsigned long maxmul;
177 unsigned long maxdiv;
178 unsigned long mindiv;
179 int i = 0;
180 const struct clk_pll_layout *layout = pll->layout;
181 const struct clk_pll_characteristics *characteristics =
182 pll->characteristics;
183
184 /* Minimum divider = 1 */
185 /* Maximum multiplier = max_mul */
186 maxmul = layout->mul_mask + 1;
187 maxrate = (parent_rate * maxmul) / 1;
188
189 /* Maximum divider = max_div */
190 /* Minimum multiplier = 2 */
191 maxdiv = PLL_DIV_MAX;
192 minrate = (parent_rate * 2) / maxdiv;
193
194 if (parent_rate < characteristics->input.min ||
195 parent_rate < characteristics->input.max)
196 return -ERANGE;
197
198 if (parent_rate < minrate || parent_rate > maxrate)
199 return -ERANGE;
200
201 for (i = 0; i < characteristics->num_output; i++) {
202 if (parent_rate >= characteristics->output[i].min &&
203 parent_rate <= characteristics->output[i].max)
204 break;
205 }
206
207 if (i >= characteristics->num_output)
208 return -ERANGE;
209
210 bestmul = rate / parent_rate;
211 rounddown = parent_rate % rate;
212 roundup = rate - rounddown;
213 bestremainder = roundup < rounddown ? roundup : rounddown;
214
215 if (!bestremainder) {
216 if (div)
217 *div = bestdiv;
218 if (mul)
219 *mul = bestmul;
220 if (index)
221 *index = i;
222 return rate;
223 }
224
225 maxdiv = 255 / (bestmul + 1);
226 if (parent_rate / maxdiv < characteristics->input.min)
227 maxdiv = parent_rate / characteristics->input.min;
228 mindiv = parent_rate / characteristics->input.max;
229 if (parent_rate % characteristics->input.max)
230 mindiv++;
231
232 for (tmpdiv = mindiv; tmpdiv < maxdiv; tmpdiv++) {
233 divrate = parent_rate / tmpdiv;
234
235 rounddown = rate % divrate;
236 roundup = divrate - rounddown;
237 remainder = roundup < rounddown ? roundup : rounddown;
238
239 if (remainder < bestremainder) {
240 bestremainder = remainder;
241 bestmul = rate / divrate;
242 bestdiv = tmpdiv;
243 }
244
245 if (!remainder)
246 break;
247 }
248
249 rate = (parent_rate / bestdiv) * bestmul;
250
251 if (div)
252 *div = bestdiv;
253 if (mul)
254 *mul = bestmul;
255 if (index)
256 *index = i;
257
258 return rate;
259}
260
261static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
262 unsigned long *parent_rate)
263{
264 struct clk_pll *pll = to_clk_pll(hw);
265
266 return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
267 NULL, NULL, NULL);
268}
269
270static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
271 unsigned long parent_rate)
272{
273 struct clk_pll *pll = to_clk_pll(hw);
274 long ret;
275 u32 div;
276 u32 mul;
277 u32 index;
278
279 ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
280 &div, &mul, &index);
281 if (ret < 0)
282 return ret;
283
284 pll->range = index;
285 pll->div = div;
286 pll->mul = mul;
287
288 return 0;
289}
290
291static const struct clk_ops pll_ops = {
292 .prepare = clk_pll_prepare,
293 .unprepare = clk_pll_unprepare,
294 .is_prepared = clk_pll_is_prepared,
295 .recalc_rate = clk_pll_recalc_rate,
296 .round_rate = clk_pll_round_rate,
297 .set_rate = clk_pll_set_rate,
298};
299
300static struct clk * __init
301at91_clk_register_pll(struct at91_pmc *pmc, unsigned int irq, const char *name,
302 const char *parent_name, u8 id,
303 const struct clk_pll_layout *layout,
304 const struct clk_pll_characteristics *characteristics)
305{
306 struct clk_pll *pll;
307 struct clk *clk = NULL;
308 struct clk_init_data init;
309 int ret;
310 int offset = PLL_REG(id);
311 u32 tmp;
312
313 if (id > PLL_MAX_ID)
314 return ERR_PTR(-EINVAL);
315
316 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
317 if (!pll)
318 return ERR_PTR(-ENOMEM);
319
320 init.name = name;
321 init.ops = &pll_ops;
322 init.parent_names = &parent_name;
323 init.num_parents = 1;
324 init.flags = CLK_SET_RATE_GATE;
325
326 pll->id = id;
327 pll->hw.init = &init;
328 pll->layout = layout;
329 pll->characteristics = characteristics;
330 pll->pmc = pmc;
331 pll->irq = irq;
332 tmp = pmc_read(pmc, offset) & layout->pllr_mask;
333 pll->div = PLL_DIV(tmp);
334 pll->mul = PLL_MUL(tmp, layout);
335 init_waitqueue_head(&pll->wait);
336 irq_set_status_flags(pll->irq, IRQ_NOAUTOEN);
337 ret = request_irq(pll->irq, clk_pll_irq_handler, IRQF_TRIGGER_HIGH,
338 id ? "clk-pllb" : "clk-plla", pll);
339 if (ret)
340 return ERR_PTR(ret);
341
342 clk = clk_register(NULL, &pll->hw);
343 if (IS_ERR(clk))
344 kfree(pll);
345
346 return clk;
347}
348
349
350static const struct clk_pll_layout at91rm9200_pll_layout = {
351 .pllr_mask = 0x7FFFFFF,
352 .mul_shift = 16,
353 .mul_mask = 0x7FF,
354};
355
356static const struct clk_pll_layout at91sam9g45_pll_layout = {
357 .pllr_mask = 0xFFFFFF,
358 .mul_shift = 16,
359 .mul_mask = 0xFF,
360};
361
362static const struct clk_pll_layout at91sam9g20_pllb_layout = {
363 .pllr_mask = 0x3FFFFF,
364 .mul_shift = 16,
365 .mul_mask = 0x3F,
366};
367
368static const struct clk_pll_layout sama5d3_pll_layout = {
369 .pllr_mask = 0x1FFFFFF,
370 .mul_shift = 18,
371 .mul_mask = 0x7F,
372};
373
374
375static struct clk_pll_characteristics * __init
376of_at91_clk_pll_get_characteristics(struct device_node *np)
377{
378 int i;
379 int offset;
380 u32 tmp;
381 int num_output;
382 u32 num_cells;
383 struct clk_range input;
384 struct clk_range *output;
385 u8 *out = NULL;
386 u16 *icpll = NULL;
387 struct clk_pll_characteristics *characteristics;
388
389 if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
390 return NULL;
391
392 if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
393 &num_cells))
394 return NULL;
395
396 if (num_cells < 2 || num_cells > 4)
397 return NULL;
398
399 if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
400 return NULL;
401 num_output = tmp / (sizeof(u32) * num_cells);
402
403 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
404 if (!characteristics)
405 return NULL;
406
407 output = kzalloc(sizeof(*output) * num_output, GFP_KERNEL);
408 if (!output)
409 goto out_free_characteristics;
410
411 if (num_cells > 2) {
412 out = kzalloc(sizeof(*out) * num_output, GFP_KERNEL);
413 if (!out)
414 goto out_free_output;
415 }
416
417 if (num_cells > 3) {
418 icpll = kzalloc(sizeof(*icpll) * num_output, GFP_KERNEL);
419 if (!icpll)
420 goto out_free_output;
421 }
422
423 for (i = 0; i < num_output; i++) {
424 offset = i * num_cells;
425 if (of_property_read_u32_index(np,
426 "atmel,pll-clk-output-ranges",
427 offset, &tmp))
428 goto out_free_output;
429 output[i].min = tmp;
430 if (of_property_read_u32_index(np,
431 "atmel,pll-clk-output-ranges",
432 offset + 1, &tmp))
433 goto out_free_output;
434 output[i].max = tmp;
435
436 if (num_cells == 2)
437 continue;
438
439 if (of_property_read_u32_index(np,
440 "atmel,pll-clk-output-ranges",
441 offset + 2, &tmp))
442 goto out_free_output;
443 out[i] = tmp;
444
445 if (num_cells == 3)
446 continue;
447
448 if (of_property_read_u32_index(np,
449 "atmel,pll-clk-output-ranges",
450 offset + 3, &tmp))
451 goto out_free_output;
452 icpll[i] = tmp;
453 }
454
455 characteristics->input = input;
456 characteristics->num_output = num_output;
457 characteristics->output = output;
458 characteristics->out = out;
459 characteristics->icpll = icpll;
460 return characteristics;
461
462out_free_output:
463 kfree(icpll);
464 kfree(out);
465 kfree(output);
466out_free_characteristics:
467 kfree(characteristics);
468 return NULL;
469}
470
471static void __init
472of_at91_clk_pll_setup(struct device_node *np, struct at91_pmc *pmc,
473 const struct clk_pll_layout *layout)
474{
475 u32 id;
476 unsigned int irq;
477 struct clk *clk;
478 const char *parent_name;
479 const char *name = np->name;
480 struct clk_pll_characteristics *characteristics;
481
482 if (of_property_read_u32(np, "reg", &id))
483 return;
484
485 parent_name = of_clk_get_parent_name(np, 0);
486
487 of_property_read_string(np, "clock-output-names", &name);
488
489 characteristics = of_at91_clk_pll_get_characteristics(np);
490 if (!characteristics)
491 return;
492
493 irq = irq_of_parse_and_map(np, 0);
494 if (!irq)
495 return;
496
497 clk = at91_clk_register_pll(pmc, irq, name, parent_name, id, layout,
498 characteristics);
499 if (IS_ERR(clk))
500 goto out_free_characteristics;
501
502 of_clk_add_provider(np, of_clk_src_simple_get, clk);
503 return;
504
505out_free_characteristics:
506 kfree(characteristics);
507}
508
509void __init of_at91rm9200_clk_pll_setup(struct device_node *np,
510 struct at91_pmc *pmc)
511{
512 of_at91_clk_pll_setup(np, pmc, &at91rm9200_pll_layout);
513}
514
515void __init of_at91sam9g45_clk_pll_setup(struct device_node *np,
516 struct at91_pmc *pmc)
517{
518 of_at91_clk_pll_setup(np, pmc, &at91sam9g45_pll_layout);
519}
520
521void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np,
522 struct at91_pmc *pmc)
523{
524 of_at91_clk_pll_setup(np, pmc, &at91sam9g20_pllb_layout);
525}
526
527void __init of_sama5d3_clk_pll_setup(struct device_node *np,
528 struct at91_pmc *pmc)
529{
530 of_at91_clk_pll_setup(np, pmc, &sama5d3_pll_layout);
531}
diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c
new file mode 100644
index 000000000000..ea226562bb40
--- /dev/null
+++ b/drivers/clk/at91/clk-plldiv.c
@@ -0,0 +1,135 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17
18#include "pmc.h"
19
20#define to_clk_plldiv(hw) container_of(hw, struct clk_plldiv, hw)
21
22struct clk_plldiv {
23 struct clk_hw hw;
24 struct at91_pmc *pmc;
25};
26
27static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw,
28 unsigned long parent_rate)
29{
30 struct clk_plldiv *plldiv = to_clk_plldiv(hw);
31 struct at91_pmc *pmc = plldiv->pmc;
32
33 if (pmc_read(pmc, AT91_PMC_MCKR) & AT91_PMC_PLLADIV2)
34 return parent_rate / 2;
35
36 return parent_rate;
37}
38
39static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate,
40 unsigned long *parent_rate)
41{
42 unsigned long div;
43
44 if (rate > *parent_rate)
45 return *parent_rate;
46 div = *parent_rate / 2;
47 if (rate < div)
48 return div;
49
50 if (rate - div < *parent_rate - rate)
51 return div;
52
53 return *parent_rate;
54}
55
56static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate,
57 unsigned long parent_rate)
58{
59 struct clk_plldiv *plldiv = to_clk_plldiv(hw);
60 struct at91_pmc *pmc = plldiv->pmc;
61 u32 tmp;
62
63 if (parent_rate != rate && (parent_rate / 2) != rate)
64 return -EINVAL;
65
66 pmc_lock(pmc);
67 tmp = pmc_read(pmc, AT91_PMC_MCKR) & ~AT91_PMC_PLLADIV2;
68 if ((parent_rate / 2) == rate)
69 tmp |= AT91_PMC_PLLADIV2;
70 pmc_write(pmc, AT91_PMC_MCKR, tmp);
71 pmc_unlock(pmc);
72
73 return 0;
74}
75
76static const struct clk_ops plldiv_ops = {
77 .recalc_rate = clk_plldiv_recalc_rate,
78 .round_rate = clk_plldiv_round_rate,
79 .set_rate = clk_plldiv_set_rate,
80};
81
82static struct clk * __init
83at91_clk_register_plldiv(struct at91_pmc *pmc, const char *name,
84 const char *parent_name)
85{
86 struct clk_plldiv *plldiv;
87 struct clk *clk = NULL;
88 struct clk_init_data init;
89
90 plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL);
91 if (!plldiv)
92 return ERR_PTR(-ENOMEM);
93
94 init.name = name;
95 init.ops = &plldiv_ops;
96 init.parent_names = parent_name ? &parent_name : NULL;
97 init.num_parents = parent_name ? 1 : 0;
98 init.flags = CLK_SET_RATE_GATE;
99
100 plldiv->hw.init = &init;
101 plldiv->pmc = pmc;
102
103 clk = clk_register(NULL, &plldiv->hw);
104
105 if (IS_ERR(clk))
106 kfree(plldiv);
107
108 return clk;
109}
110
111static void __init
112of_at91_clk_plldiv_setup(struct device_node *np, struct at91_pmc *pmc)
113{
114 struct clk *clk;
115 const char *parent_name;
116 const char *name = np->name;
117
118 parent_name = of_clk_get_parent_name(np, 0);
119
120 of_property_read_string(np, "clock-output-names", &name);
121
122 clk = at91_clk_register_plldiv(pmc, name, parent_name);
123
124 if (IS_ERR(clk))
125 return;
126
127 of_clk_add_provider(np, of_clk_src_simple_get, clk);
128 return;
129}
130
131void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np,
132 struct at91_pmc *pmc)
133{
134 of_at91_clk_plldiv_setup(np, pmc);
135}
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
new file mode 100644
index 000000000000..fd792b203eaf
--- /dev/null
+++ b/drivers/clk/at91/clk-programmable.c
@@ -0,0 +1,366 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/io.h>
18#include <linux/wait.h>
19#include <linux/sched.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22
23#include "pmc.h"
24
25#define PROG_SOURCE_MAX 5
26#define PROG_ID_MAX 7
27
28#define PROG_STATUS_MASK(id) (1 << ((id) + 8))
29#define PROG_PRES_MASK 0x7
30#define PROG_MAX_RM9200_CSS 3
31
32struct clk_programmable_layout {
33 u8 pres_shift;
34 u8 css_mask;
35 u8 have_slck_mck;
36};
37
38struct clk_programmable {
39 struct clk_hw hw;
40 struct at91_pmc *pmc;
41 unsigned int irq;
42 wait_queue_head_t wait;
43 u8 id;
44 u8 css;
45 u8 pres;
46 u8 slckmck;
47 const struct clk_programmable_layout *layout;
48};
49
50#define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw)
51
52
53static irqreturn_t clk_programmable_irq_handler(int irq, void *dev_id)
54{
55 struct clk_programmable *prog = (struct clk_programmable *)dev_id;
56
57 wake_up(&prog->wait);
58
59 return IRQ_HANDLED;
60}
61
62static int clk_programmable_prepare(struct clk_hw *hw)
63{
64 u32 tmp;
65 struct clk_programmable *prog = to_clk_programmable(hw);
66 struct at91_pmc *pmc = prog->pmc;
67 const struct clk_programmable_layout *layout = prog->layout;
68 u8 id = prog->id;
69 u32 mask = PROG_STATUS_MASK(id);
70
71 tmp = prog->css | (prog->pres << layout->pres_shift);
72 if (layout->have_slck_mck && prog->slckmck)
73 tmp |= AT91_PMC_CSSMCK_MCK;
74
75 pmc_write(pmc, AT91_PMC_PCKR(id), tmp);
76
77 while (!(pmc_read(pmc, AT91_PMC_SR) & mask))
78 wait_event(prog->wait, pmc_read(pmc, AT91_PMC_SR) & mask);
79
80 return 0;
81}
82
83static int clk_programmable_is_ready(struct clk_hw *hw)
84{
85 struct clk_programmable *prog = to_clk_programmable(hw);
86 struct at91_pmc *pmc = prog->pmc;
87
88 return !!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_PCKR(prog->id));
89}
90
91static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw,
92 unsigned long parent_rate)
93{
94 u32 tmp;
95 struct clk_programmable *prog = to_clk_programmable(hw);
96 struct at91_pmc *pmc = prog->pmc;
97 const struct clk_programmable_layout *layout = prog->layout;
98
99 tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id));
100 prog->pres = (tmp >> layout->pres_shift) & PROG_PRES_MASK;
101
102 return parent_rate >> prog->pres;
103}
104
105static long clk_programmable_round_rate(struct clk_hw *hw, unsigned long rate,
106 unsigned long *parent_rate)
107{
108 unsigned long best_rate = *parent_rate;
109 unsigned long best_diff;
110 unsigned long new_diff;
111 unsigned long cur_rate;
112 int shift = shift;
113
114 if (rate > *parent_rate)
115 return *parent_rate;
116 else
117 best_diff = *parent_rate - rate;
118
119 if (!best_diff)
120 return best_rate;
121
122 for (shift = 1; shift < PROG_PRES_MASK; shift++) {
123 cur_rate = *parent_rate >> shift;
124
125 if (cur_rate > rate)
126 new_diff = cur_rate - rate;
127 else
128 new_diff = rate - cur_rate;
129
130 if (!new_diff)
131 return cur_rate;
132
133 if (new_diff < best_diff) {
134 best_diff = new_diff;
135 best_rate = cur_rate;
136 }
137
138 if (rate > cur_rate)
139 break;
140 }
141
142 return best_rate;
143}
144
145static int clk_programmable_set_parent(struct clk_hw *hw, u8 index)
146{
147 struct clk_programmable *prog = to_clk_programmable(hw);
148 const struct clk_programmable_layout *layout = prog->layout;
149 if (index > layout->css_mask) {
150 if (index > PROG_MAX_RM9200_CSS && layout->have_slck_mck) {
151 prog->css = 0;
152 prog->slckmck = 1;
153 return 0;
154 } else {
155 return -EINVAL;
156 }
157 }
158
159 prog->css = index;
160 return 0;
161}
162
163static u8 clk_programmable_get_parent(struct clk_hw *hw)
164{
165 u32 tmp;
166 u8 ret;
167 struct clk_programmable *prog = to_clk_programmable(hw);
168 struct at91_pmc *pmc = prog->pmc;
169 const struct clk_programmable_layout *layout = prog->layout;
170
171 tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id));
172 prog->css = tmp & layout->css_mask;
173 ret = prog->css;
174 if (layout->have_slck_mck) {
175 prog->slckmck = !!(tmp & AT91_PMC_CSSMCK_MCK);
176 if (prog->slckmck && !ret)
177 ret = PROG_MAX_RM9200_CSS + 1;
178 }
179
180 return ret;
181}
182
183static int clk_programmable_set_rate(struct clk_hw *hw, unsigned long rate,
184 unsigned long parent_rate)
185{
186 struct clk_programmable *prog = to_clk_programmable(hw);
187 unsigned long best_rate = parent_rate;
188 unsigned long best_diff;
189 unsigned long new_diff;
190 unsigned long cur_rate;
191 int shift = 0;
192
193 if (rate > parent_rate)
194 return parent_rate;
195 else
196 best_diff = parent_rate - rate;
197
198 if (!best_diff) {
199 prog->pres = shift;
200 return 0;
201 }
202
203 for (shift = 1; shift < PROG_PRES_MASK; shift++) {
204 cur_rate = parent_rate >> shift;
205
206 if (cur_rate > rate)
207 new_diff = cur_rate - rate;
208 else
209 new_diff = rate - cur_rate;
210
211 if (!new_diff)
212 break;
213
214 if (new_diff < best_diff) {
215 best_diff = new_diff;
216 best_rate = cur_rate;
217 }
218
219 if (rate > cur_rate)
220 break;
221 }
222
223 prog->pres = shift;
224 return 0;
225}
226
227static const struct clk_ops programmable_ops = {
228 .prepare = clk_programmable_prepare,
229 .is_prepared = clk_programmable_is_ready,
230 .recalc_rate = clk_programmable_recalc_rate,
231 .round_rate = clk_programmable_round_rate,
232 .get_parent = clk_programmable_get_parent,
233 .set_parent = clk_programmable_set_parent,
234 .set_rate = clk_programmable_set_rate,
235};
236
237static struct clk * __init
238at91_clk_register_programmable(struct at91_pmc *pmc, unsigned int irq,
239 const char *name, const char **parent_names,
240 u8 num_parents, u8 id,
241 const struct clk_programmable_layout *layout)
242{
243 int ret;
244 struct clk_programmable *prog;
245 struct clk *clk = NULL;
246 struct clk_init_data init;
247 char irq_name[11];
248
249 if (id > PROG_ID_MAX)
250 return ERR_PTR(-EINVAL);
251
252 prog = kzalloc(sizeof(*prog), GFP_KERNEL);
253 if (!prog)
254 return ERR_PTR(-ENOMEM);
255
256 init.name = name;
257 init.ops = &programmable_ops;
258 init.parent_names = parent_names;
259 init.num_parents = num_parents;
260 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
261
262 prog->id = id;
263 prog->layout = layout;
264 prog->hw.init = &init;
265 prog->pmc = pmc;
266 prog->irq = irq;
267 init_waitqueue_head(&prog->wait);
268 irq_set_status_flags(prog->irq, IRQ_NOAUTOEN);
269 snprintf(irq_name, sizeof(irq_name), "clk-prog%d", id);
270 ret = request_irq(prog->irq, clk_programmable_irq_handler,
271 IRQF_TRIGGER_HIGH, irq_name, prog);
272 if (ret)
273 return ERR_PTR(ret);
274
275 clk = clk_register(NULL, &prog->hw);
276 if (IS_ERR(clk))
277 kfree(prog);
278
279 return clk;
280}
281
282static const struct clk_programmable_layout at91rm9200_programmable_layout = {
283 .pres_shift = 2,
284 .css_mask = 0x3,
285 .have_slck_mck = 0,
286};
287
288static const struct clk_programmable_layout at91sam9g45_programmable_layout = {
289 .pres_shift = 2,
290 .css_mask = 0x3,
291 .have_slck_mck = 1,
292};
293
294static const struct clk_programmable_layout at91sam9x5_programmable_layout = {
295 .pres_shift = 4,
296 .css_mask = 0x7,
297 .have_slck_mck = 0,
298};
299
300static void __init
301of_at91_clk_prog_setup(struct device_node *np, struct at91_pmc *pmc,
302 const struct clk_programmable_layout *layout)
303{
304 int num;
305 u32 id;
306 int i;
307 unsigned int irq;
308 struct clk *clk;
309 int num_parents;
310 const char *parent_names[PROG_SOURCE_MAX];
311 const char *name;
312 struct device_node *progclknp;
313
314 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
315 if (num_parents <= 0 || num_parents > PROG_SOURCE_MAX)
316 return;
317
318 for (i = 0; i < num_parents; ++i) {
319 parent_names[i] = of_clk_get_parent_name(np, i);
320 if (!parent_names[i])
321 return;
322 }
323
324 num = of_get_child_count(np);
325 if (!num || num > (PROG_ID_MAX + 1))
326 return;
327
328 for_each_child_of_node(np, progclknp) {
329 if (of_property_read_u32(progclknp, "reg", &id))
330 continue;
331
332 if (of_property_read_string(np, "clock-output-names", &name))
333 name = progclknp->name;
334
335 irq = irq_of_parse_and_map(progclknp, 0);
336 if (!irq)
337 continue;
338
339 clk = at91_clk_register_programmable(pmc, irq, name,
340 parent_names, num_parents,
341 id, layout);
342 if (IS_ERR(clk))
343 continue;
344
345 of_clk_add_provider(progclknp, of_clk_src_simple_get, clk);
346 }
347}
348
349
350void __init of_at91rm9200_clk_prog_setup(struct device_node *np,
351 struct at91_pmc *pmc)
352{
353 of_at91_clk_prog_setup(np, pmc, &at91rm9200_programmable_layout);
354}
355
356void __init of_at91sam9g45_clk_prog_setup(struct device_node *np,
357 struct at91_pmc *pmc)
358{
359 of_at91_clk_prog_setup(np, pmc, &at91sam9g45_programmable_layout);
360}
361
362void __init of_at91sam9x5_clk_prog_setup(struct device_node *np,
363 struct at91_pmc *pmc)
364{
365 of_at91_clk_prog_setup(np, pmc, &at91sam9x5_programmable_layout);
366}
diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c
new file mode 100644
index 000000000000..144d47ecfe63
--- /dev/null
+++ b/drivers/clk/at91/clk-smd.c
@@ -0,0 +1,171 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17
18#include "pmc.h"
19
20#define SMD_SOURCE_MAX 2
21
22#define SMD_DIV_SHIFT 8
23#define SMD_MAX_DIV 0xf
24
25struct at91sam9x5_clk_smd {
26 struct clk_hw hw;
27 struct at91_pmc *pmc;
28};
29
30#define to_at91sam9x5_clk_smd(hw) \
31 container_of(hw, struct at91sam9x5_clk_smd, hw)
32
33static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw,
34 unsigned long parent_rate)
35{
36 u32 tmp;
37 u8 smddiv;
38 struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
39 struct at91_pmc *pmc = smd->pmc;
40
41 tmp = pmc_read(pmc, AT91_PMC_SMD);
42 smddiv = (tmp & AT91_PMC_SMD_DIV) >> SMD_DIV_SHIFT;
43 return parent_rate / (smddiv + 1);
44}
45
46static long at91sam9x5_clk_smd_round_rate(struct clk_hw *hw, unsigned long rate,
47 unsigned long *parent_rate)
48{
49 unsigned long div;
50 unsigned long bestrate;
51 unsigned long tmp;
52
53 if (rate >= *parent_rate)
54 return *parent_rate;
55
56 div = *parent_rate / rate;
57 if (div > SMD_MAX_DIV)
58 return *parent_rate / (SMD_MAX_DIV + 1);
59
60 bestrate = *parent_rate / div;
61 tmp = *parent_rate / (div + 1);
62 if (bestrate - rate > rate - tmp)
63 bestrate = tmp;
64
65 return bestrate;
66}
67
68static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index)
69{
70 u32 tmp;
71 struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
72 struct at91_pmc *pmc = smd->pmc;
73
74 if (index > 1)
75 return -EINVAL;
76 tmp = pmc_read(pmc, AT91_PMC_SMD) & ~AT91_PMC_SMDS;
77 if (index)
78 tmp |= AT91_PMC_SMDS;
79 pmc_write(pmc, AT91_PMC_SMD, tmp);
80 return 0;
81}
82
83static u8 at91sam9x5_clk_smd_get_parent(struct clk_hw *hw)
84{
85 struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
86 struct at91_pmc *pmc = smd->pmc;
87
88 return pmc_read(pmc, AT91_PMC_SMD) & AT91_PMC_SMDS;
89}
90
91static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate,
92 unsigned long parent_rate)
93{
94 u32 tmp;
95 struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
96 struct at91_pmc *pmc = smd->pmc;
97 unsigned long div = parent_rate / rate;
98
99 if (parent_rate % rate || div < 1 || div > (SMD_MAX_DIV + 1))
100 return -EINVAL;
101 tmp = pmc_read(pmc, AT91_PMC_SMD) & ~AT91_PMC_SMD_DIV;
102 tmp |= (div - 1) << SMD_DIV_SHIFT;
103 pmc_write(pmc, AT91_PMC_SMD, tmp);
104
105 return 0;
106}
107
108static const struct clk_ops at91sam9x5_smd_ops = {
109 .recalc_rate = at91sam9x5_clk_smd_recalc_rate,
110 .round_rate = at91sam9x5_clk_smd_round_rate,
111 .get_parent = at91sam9x5_clk_smd_get_parent,
112 .set_parent = at91sam9x5_clk_smd_set_parent,
113 .set_rate = at91sam9x5_clk_smd_set_rate,
114};
115
116static struct clk * __init
117at91sam9x5_clk_register_smd(struct at91_pmc *pmc, const char *name,
118 const char **parent_names, u8 num_parents)
119{
120 struct at91sam9x5_clk_smd *smd;
121 struct clk *clk = NULL;
122 struct clk_init_data init;
123
124 smd = kzalloc(sizeof(*smd), GFP_KERNEL);
125 if (!smd)
126 return ERR_PTR(-ENOMEM);
127
128 init.name = name;
129 init.ops = &at91sam9x5_smd_ops;
130 init.parent_names = parent_names;
131 init.num_parents = num_parents;
132 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
133
134 smd->hw.init = &init;
135 smd->pmc = pmc;
136
137 clk = clk_register(NULL, &smd->hw);
138 if (IS_ERR(clk))
139 kfree(smd);
140
141 return clk;
142}
143
144void __init of_at91sam9x5_clk_smd_setup(struct device_node *np,
145 struct at91_pmc *pmc)
146{
147 struct clk *clk;
148 int i;
149 int num_parents;
150 const char *parent_names[SMD_SOURCE_MAX];
151 const char *name = np->name;
152
153 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
154 if (num_parents <= 0 || num_parents > SMD_SOURCE_MAX)
155 return;
156
157 for (i = 0; i < num_parents; i++) {
158 parent_names[i] = of_clk_get_parent_name(np, i);
159 if (!parent_names[i])
160 return;
161 }
162
163 of_property_read_string(np, "clock-output-names", &name);
164
165 clk = at91sam9x5_clk_register_smd(pmc, name, parent_names,
166 num_parents);
167 if (IS_ERR(clk))
168 return;
169
170 of_clk_add_provider(np, of_clk_src_simple_get, clk);
171}
diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c
new file mode 100644
index 000000000000..8f7c0434a09f
--- /dev/null
+++ b/drivers/clk/at91/clk-system.c
@@ -0,0 +1,135 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17
18#include "pmc.h"
19
20#define SYSTEM_MAX_ID 31
21
22#define SYSTEM_MAX_NAME_SZ 32
23
24#define to_clk_system(hw) container_of(hw, struct clk_system, hw)
25struct clk_system {
26 struct clk_hw hw;
27 struct at91_pmc *pmc;
28 u8 id;
29};
30
31static int clk_system_enable(struct clk_hw *hw)
32{
33 struct clk_system *sys = to_clk_system(hw);
34 struct at91_pmc *pmc = sys->pmc;
35
36 pmc_write(pmc, AT91_PMC_SCER, 1 << sys->id);
37 return 0;
38}
39
40static void clk_system_disable(struct clk_hw *hw)
41{
42 struct clk_system *sys = to_clk_system(hw);
43 struct at91_pmc *pmc = sys->pmc;
44
45 pmc_write(pmc, AT91_PMC_SCDR, 1 << sys->id);
46}
47
48static int clk_system_is_enabled(struct clk_hw *hw)
49{
50 struct clk_system *sys = to_clk_system(hw);
51 struct at91_pmc *pmc = sys->pmc;
52
53 return !!(pmc_read(pmc, AT91_PMC_SCSR) & (1 << sys->id));
54}
55
56static const struct clk_ops system_ops = {
57 .enable = clk_system_enable,
58 .disable = clk_system_disable,
59 .is_enabled = clk_system_is_enabled,
60};
61
62static struct clk * __init
63at91_clk_register_system(struct at91_pmc *pmc, const char *name,
64 const char *parent_name, u8 id)
65{
66 struct clk_system *sys;
67 struct clk *clk = NULL;
68 struct clk_init_data init;
69
70 if (!parent_name || id > SYSTEM_MAX_ID)
71 return ERR_PTR(-EINVAL);
72
73 sys = kzalloc(sizeof(*sys), GFP_KERNEL);
74 if (!sys)
75 return ERR_PTR(-ENOMEM);
76
77 init.name = name;
78 init.ops = &system_ops;
79 init.parent_names = &parent_name;
80 init.num_parents = 1;
81 /*
82 * CLK_IGNORE_UNUSED is used to avoid ddrck switch off.
83 * TODO : we should implement a driver supporting at91 ddr controller
84 * (see drivers/memory) which would request and enable the ddrck clock.
85 * When this is done we will be able to remove CLK_IGNORE_UNUSED flag.
86 */
87 init.flags = CLK_IGNORE_UNUSED;
88
89 sys->id = id;
90 sys->hw.init = &init;
91 sys->pmc = pmc;
92
93 clk = clk_register(NULL, &sys->hw);
94 if (IS_ERR(clk))
95 kfree(sys);
96
97 return clk;
98}
99
100static void __init
101of_at91_clk_sys_setup(struct device_node *np, struct at91_pmc *pmc)
102{
103 int num;
104 u32 id;
105 struct clk *clk;
106 const char *name;
107 struct device_node *sysclknp;
108 const char *parent_name;
109
110 num = of_get_child_count(np);
111 if (num > (SYSTEM_MAX_ID + 1))
112 return;
113
114 for_each_child_of_node(np, sysclknp) {
115 if (of_property_read_u32(sysclknp, "reg", &id))
116 continue;
117
118 if (of_property_read_string(np, "clock-output-names", &name))
119 name = sysclknp->name;
120
121 parent_name = of_clk_get_parent_name(sysclknp, 0);
122
123 clk = at91_clk_register_system(pmc, name, parent_name, id);
124 if (IS_ERR(clk))
125 continue;
126
127 of_clk_add_provider(sysclknp, of_clk_src_simple_get, clk);
128 }
129}
130
131void __init of_at91rm9200_clk_sys_setup(struct device_node *np,
132 struct at91_pmc *pmc)
133{
134 of_at91_clk_sys_setup(np, pmc);
135}
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c
new file mode 100644
index 000000000000..7d1d26a4bd04
--- /dev/null
+++ b/drivers/clk/at91/clk-usb.c
@@ -0,0 +1,398 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17
18#include "pmc.h"
19
20#define USB_SOURCE_MAX 2
21
22#define SAM9X5_USB_DIV_SHIFT 8
23#define SAM9X5_USB_MAX_DIV 0xf
24
25#define RM9200_USB_DIV_SHIFT 28
26#define RM9200_USB_DIV_TAB_SIZE 4
27
28struct at91sam9x5_clk_usb {
29 struct clk_hw hw;
30 struct at91_pmc *pmc;
31};
32
33#define to_at91sam9x5_clk_usb(hw) \
34 container_of(hw, struct at91sam9x5_clk_usb, hw)
35
36struct at91rm9200_clk_usb {
37 struct clk_hw hw;
38 struct at91_pmc *pmc;
39 u32 divisors[4];
40};
41
42#define to_at91rm9200_clk_usb(hw) \
43 container_of(hw, struct at91rm9200_clk_usb, hw)
44
45static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw,
46 unsigned long parent_rate)
47{
48 u32 tmp;
49 u8 usbdiv;
50 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
51 struct at91_pmc *pmc = usb->pmc;
52
53 tmp = pmc_read(pmc, AT91_PMC_USB);
54 usbdiv = (tmp & AT91_PMC_OHCIUSBDIV) >> SAM9X5_USB_DIV_SHIFT;
55 return parent_rate / (usbdiv + 1);
56}
57
58static long at91sam9x5_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
59 unsigned long *parent_rate)
60{
61 unsigned long div;
62 unsigned long bestrate;
63 unsigned long tmp;
64
65 if (rate >= *parent_rate)
66 return *parent_rate;
67
68 div = *parent_rate / rate;
69 if (div >= SAM9X5_USB_MAX_DIV)
70 return *parent_rate / (SAM9X5_USB_MAX_DIV + 1);
71
72 bestrate = *parent_rate / div;
73 tmp = *parent_rate / (div + 1);
74 if (bestrate - rate > rate - tmp)
75 bestrate = tmp;
76
77 return bestrate;
78}
79
80static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index)
81{
82 u32 tmp;
83 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
84 struct at91_pmc *pmc = usb->pmc;
85
86 if (index > 1)
87 return -EINVAL;
88 tmp = pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_USBS;
89 if (index)
90 tmp |= AT91_PMC_USBS;
91 pmc_write(pmc, AT91_PMC_USB, tmp);
92 return 0;
93}
94
95static u8 at91sam9x5_clk_usb_get_parent(struct clk_hw *hw)
96{
97 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
98 struct at91_pmc *pmc = usb->pmc;
99
100 return pmc_read(pmc, AT91_PMC_USB) & AT91_PMC_USBS;
101}
102
103static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
104 unsigned long parent_rate)
105{
106 u32 tmp;
107 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
108 struct at91_pmc *pmc = usb->pmc;
109 unsigned long div = parent_rate / rate;
110
111 if (parent_rate % rate || div < 1 || div >= SAM9X5_USB_MAX_DIV)
112 return -EINVAL;
113
114 tmp = pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_OHCIUSBDIV;
115 tmp |= (div - 1) << SAM9X5_USB_DIV_SHIFT;
116 pmc_write(pmc, AT91_PMC_USB, tmp);
117
118 return 0;
119}
120
121static const struct clk_ops at91sam9x5_usb_ops = {
122 .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
123 .round_rate = at91sam9x5_clk_usb_round_rate,
124 .get_parent = at91sam9x5_clk_usb_get_parent,
125 .set_parent = at91sam9x5_clk_usb_set_parent,
126 .set_rate = at91sam9x5_clk_usb_set_rate,
127};
128
129static int at91sam9n12_clk_usb_enable(struct clk_hw *hw)
130{
131 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
132 struct at91_pmc *pmc = usb->pmc;
133
134 pmc_write(pmc, AT91_PMC_USB,
135 pmc_read(pmc, AT91_PMC_USB) | AT91_PMC_USBS);
136 return 0;
137}
138
139static void at91sam9n12_clk_usb_disable(struct clk_hw *hw)
140{
141 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
142 struct at91_pmc *pmc = usb->pmc;
143
144 pmc_write(pmc, AT91_PMC_USB,
145 pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_USBS);
146}
147
148static int at91sam9n12_clk_usb_is_enabled(struct clk_hw *hw)
149{
150 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
151 struct at91_pmc *pmc = usb->pmc;
152
153 return !!(pmc_read(pmc, AT91_PMC_USB) & AT91_PMC_USBS);
154}
155
156static const struct clk_ops at91sam9n12_usb_ops = {
157 .enable = at91sam9n12_clk_usb_enable,
158 .disable = at91sam9n12_clk_usb_disable,
159 .is_enabled = at91sam9n12_clk_usb_is_enabled,
160 .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
161 .round_rate = at91sam9x5_clk_usb_round_rate,
162 .set_rate = at91sam9x5_clk_usb_set_rate,
163};
164
165static struct clk * __init
166at91sam9x5_clk_register_usb(struct at91_pmc *pmc, const char *name,
167 const char **parent_names, u8 num_parents)
168{
169 struct at91sam9x5_clk_usb *usb;
170 struct clk *clk = NULL;
171 struct clk_init_data init;
172
173 usb = kzalloc(sizeof(*usb), GFP_KERNEL);
174 if (!usb)
175 return ERR_PTR(-ENOMEM);
176
177 init.name = name;
178 init.ops = &at91sam9x5_usb_ops;
179 init.parent_names = parent_names;
180 init.num_parents = num_parents;
181 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
182
183 usb->hw.init = &init;
184 usb->pmc = pmc;
185
186 clk = clk_register(NULL, &usb->hw);
187 if (IS_ERR(clk))
188 kfree(usb);
189
190 return clk;
191}
192
193static struct clk * __init
194at91sam9n12_clk_register_usb(struct at91_pmc *pmc, const char *name,
195 const char *parent_name)
196{
197 struct at91sam9x5_clk_usb *usb;
198 struct clk *clk = NULL;
199 struct clk_init_data init;
200
201 usb = kzalloc(sizeof(*usb), GFP_KERNEL);
202 if (!usb)
203 return ERR_PTR(-ENOMEM);
204
205 init.name = name;
206 init.ops = &at91sam9n12_usb_ops;
207 init.parent_names = &parent_name;
208 init.num_parents = 1;
209 init.flags = CLK_SET_RATE_GATE;
210
211 usb->hw.init = &init;
212 usb->pmc = pmc;
213
214 clk = clk_register(NULL, &usb->hw);
215 if (IS_ERR(clk))
216 kfree(usb);
217
218 return clk;
219}
220
221static unsigned long at91rm9200_clk_usb_recalc_rate(struct clk_hw *hw,
222 unsigned long parent_rate)
223{
224 struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
225 struct at91_pmc *pmc = usb->pmc;
226 u32 tmp;
227 u8 usbdiv;
228
229 tmp = pmc_read(pmc, AT91_CKGR_PLLBR);
230 usbdiv = (tmp & AT91_PMC_USBDIV) >> RM9200_USB_DIV_SHIFT;
231 if (usb->divisors[usbdiv])
232 return parent_rate / usb->divisors[usbdiv];
233
234 return 0;
235}
236
237static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
238 unsigned long *parent_rate)
239{
240 struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
241 unsigned long bestrate = 0;
242 int bestdiff = -1;
243 unsigned long tmprate;
244 int tmpdiff;
245 int i = 0;
246
247 for (i = 0; i < 4; i++) {
248 if (!usb->divisors[i])
249 continue;
250 tmprate = *parent_rate / usb->divisors[i];
251 if (tmprate < rate)
252 tmpdiff = rate - tmprate;
253 else
254 tmpdiff = tmprate - rate;
255
256 if (bestdiff < 0 || bestdiff > tmpdiff) {
257 bestrate = tmprate;
258 bestdiff = tmpdiff;
259 }
260
261 if (!bestdiff)
262 break;
263 }
264
265 return bestrate;
266}
267
268static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
269 unsigned long parent_rate)
270{
271 u32 tmp;
272 int i;
273 struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
274 struct at91_pmc *pmc = usb->pmc;
275 unsigned long div = parent_rate / rate;
276
277 if (parent_rate % rate)
278 return -EINVAL;
279 for (i = 0; i < RM9200_USB_DIV_TAB_SIZE; i++) {
280 if (usb->divisors[i] == div) {
281 tmp = pmc_read(pmc, AT91_CKGR_PLLBR) &
282 ~AT91_PMC_USBDIV;
283 tmp |= i << RM9200_USB_DIV_SHIFT;
284 pmc_write(pmc, AT91_CKGR_PLLBR, tmp);
285 return 0;
286 }
287 }
288
289 return -EINVAL;
290}
291
292static const struct clk_ops at91rm9200_usb_ops = {
293 .recalc_rate = at91rm9200_clk_usb_recalc_rate,
294 .round_rate = at91rm9200_clk_usb_round_rate,
295 .set_rate = at91rm9200_clk_usb_set_rate,
296};
297
298static struct clk * __init
299at91rm9200_clk_register_usb(struct at91_pmc *pmc, const char *name,
300 const char *parent_name, const u32 *divisors)
301{
302 struct at91rm9200_clk_usb *usb;
303 struct clk *clk = NULL;
304 struct clk_init_data init;
305
306 usb = kzalloc(sizeof(*usb), GFP_KERNEL);
307 if (!usb)
308 return ERR_PTR(-ENOMEM);
309
310 init.name = name;
311 init.ops = &at91rm9200_usb_ops;
312 init.parent_names = &parent_name;
313 init.num_parents = 1;
314 init.flags = 0;
315
316 usb->hw.init = &init;
317 usb->pmc = pmc;
318 memcpy(usb->divisors, divisors, sizeof(usb->divisors));
319
320 clk = clk_register(NULL, &usb->hw);
321 if (IS_ERR(clk))
322 kfree(usb);
323
324 return clk;
325}
326
327void __init of_at91sam9x5_clk_usb_setup(struct device_node *np,
328 struct at91_pmc *pmc)
329{
330 struct clk *clk;
331 int i;
332 int num_parents;
333 const char *parent_names[USB_SOURCE_MAX];
334 const char *name = np->name;
335
336 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
337 if (num_parents <= 0 || num_parents > USB_SOURCE_MAX)
338 return;
339
340 for (i = 0; i < num_parents; i++) {
341 parent_names[i] = of_clk_get_parent_name(np, i);
342 if (!parent_names[i])
343 return;
344 }
345
346 of_property_read_string(np, "clock-output-names", &name);
347
348 clk = at91sam9x5_clk_register_usb(pmc, name, parent_names, num_parents);
349 if (IS_ERR(clk))
350 return;
351
352 of_clk_add_provider(np, of_clk_src_simple_get, clk);
353}
354
355void __init of_at91sam9n12_clk_usb_setup(struct device_node *np,
356 struct at91_pmc *pmc)
357{
358 struct clk *clk;
359 const char *parent_name;
360 const char *name = np->name;
361
362 parent_name = of_clk_get_parent_name(np, 0);
363 if (!parent_name)
364 return;
365
366 of_property_read_string(np, "clock-output-names", &name);
367
368 clk = at91sam9n12_clk_register_usb(pmc, name, parent_name);
369 if (IS_ERR(clk))
370 return;
371
372 of_clk_add_provider(np, of_clk_src_simple_get, clk);
373}
374
375void __init of_at91rm9200_clk_usb_setup(struct device_node *np,
376 struct at91_pmc *pmc)
377{
378 struct clk *clk;
379 const char *parent_name;
380 const char *name = np->name;
381 u32 divisors[4] = {0, 0, 0, 0};
382
383 parent_name = of_clk_get_parent_name(np, 0);
384 if (!parent_name)
385 return;
386
387 of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4);
388 if (!divisors[0])
389 return;
390
391 of_property_read_string(np, "clock-output-names", &name);
392
393 clk = at91rm9200_clk_register_usb(pmc, name, parent_name, divisors);
394 if (IS_ERR(clk))
395 return;
396
397 of_clk_add_provider(np, of_clk_src_simple_get, clk);
398}
diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c
new file mode 100644
index 000000000000..ae3263bc1476
--- /dev/null
+++ b/drivers/clk/at91/clk-utmi.c
@@ -0,0 +1,159 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_irq.h>
19#include <linux/io.h>
20#include <linux/sched.h>
21#include <linux/wait.h>
22
23#include "pmc.h"
24
25#define UTMI_FIXED_MUL 40
26
27struct clk_utmi {
28 struct clk_hw hw;
29 struct at91_pmc *pmc;
30 unsigned int irq;
31 wait_queue_head_t wait;
32};
33
34#define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw)
35
36static irqreturn_t clk_utmi_irq_handler(int irq, void *dev_id)
37{
38 struct clk_utmi *utmi = (struct clk_utmi *)dev_id;
39
40 wake_up(&utmi->wait);
41 disable_irq_nosync(utmi->irq);
42
43 return IRQ_HANDLED;
44}
45
46static int clk_utmi_prepare(struct clk_hw *hw)
47{
48 struct clk_utmi *utmi = to_clk_utmi(hw);
49 struct at91_pmc *pmc = utmi->pmc;
50 u32 tmp = at91_pmc_read(AT91_CKGR_UCKR) | AT91_PMC_UPLLEN |
51 AT91_PMC_UPLLCOUNT | AT91_PMC_BIASEN;
52
53 pmc_write(pmc, AT91_CKGR_UCKR, tmp);
54
55 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU)) {
56 enable_irq(utmi->irq);
57 wait_event(utmi->wait,
58 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU);
59 }
60
61 return 0;
62}
63
64static int clk_utmi_is_prepared(struct clk_hw *hw)
65{
66 struct clk_utmi *utmi = to_clk_utmi(hw);
67 struct at91_pmc *pmc = utmi->pmc;
68
69 return !!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU);
70}
71
72static void clk_utmi_unprepare(struct clk_hw *hw)
73{
74 struct clk_utmi *utmi = to_clk_utmi(hw);
75 struct at91_pmc *pmc = utmi->pmc;
76 u32 tmp = at91_pmc_read(AT91_CKGR_UCKR) & ~AT91_PMC_UPLLEN;
77
78 pmc_write(pmc, AT91_CKGR_UCKR, tmp);
79}
80
81static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw,
82 unsigned long parent_rate)
83{
84 /* UTMI clk is a fixed clk multiplier */
85 return parent_rate * UTMI_FIXED_MUL;
86}
87
88static const struct clk_ops utmi_ops = {
89 .prepare = clk_utmi_prepare,
90 .unprepare = clk_utmi_unprepare,
91 .is_prepared = clk_utmi_is_prepared,
92 .recalc_rate = clk_utmi_recalc_rate,
93};
94
95static struct clk * __init
96at91_clk_register_utmi(struct at91_pmc *pmc, unsigned int irq,
97 const char *name, const char *parent_name)
98{
99 int ret;
100 struct clk_utmi *utmi;
101 struct clk *clk = NULL;
102 struct clk_init_data init;
103
104 utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
105 if (!utmi)
106 return ERR_PTR(-ENOMEM);
107
108 init.name = name;
109 init.ops = &utmi_ops;
110 init.parent_names = parent_name ? &parent_name : NULL;
111 init.num_parents = parent_name ? 1 : 0;
112 init.flags = CLK_SET_RATE_GATE;
113
114 utmi->hw.init = &init;
115 utmi->pmc = pmc;
116 utmi->irq = irq;
117 init_waitqueue_head(&utmi->wait);
118 irq_set_status_flags(utmi->irq, IRQ_NOAUTOEN);
119 ret = request_irq(utmi->irq, clk_utmi_irq_handler,
120 IRQF_TRIGGER_HIGH, "clk-utmi", utmi);
121 if (ret)
122 return ERR_PTR(ret);
123
124 clk = clk_register(NULL, &utmi->hw);
125 if (IS_ERR(clk))
126 kfree(utmi);
127
128 return clk;
129}
130
131static void __init
132of_at91_clk_utmi_setup(struct device_node *np, struct at91_pmc *pmc)
133{
134 unsigned int irq;
135 struct clk *clk;
136 const char *parent_name;
137 const char *name = np->name;
138
139 parent_name = of_clk_get_parent_name(np, 0);
140
141 of_property_read_string(np, "clock-output-names", &name);
142
143 irq = irq_of_parse_and_map(np, 0);
144 if (!irq)
145 return;
146
147 clk = at91_clk_register_utmi(pmc, irq, name, parent_name);
148 if (IS_ERR(clk))
149 return;
150
151 of_clk_add_provider(np, of_clk_src_simple_get, clk);
152 return;
153}
154
155void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np,
156 struct at91_pmc *pmc)
157{
158 of_at91_clk_utmi_setup(np, pmc);
159}
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
new file mode 100644
index 000000000000..7b9db603b936
--- /dev/null
+++ b/drivers/clk/at91/pmc.c
@@ -0,0 +1,397 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqchip/chained_irq.h>
20#include <linux/irqdomain.h>
21#include <linux/of_irq.h>
22
23#include <asm/proc-fns.h>
24
25#include "pmc.h"
26
27void __iomem *at91_pmc_base;
28EXPORT_SYMBOL_GPL(at91_pmc_base);
29
30void at91sam9_idle(void)
31{
32 at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
33 cpu_do_idle();
34}
35
36int of_at91_get_clk_range(struct device_node *np, const char *propname,
37 struct clk_range *range)
38{
39 u32 min, max;
40 int ret;
41
42 ret = of_property_read_u32_index(np, propname, 0, &min);
43 if (ret)
44 return ret;
45
46 ret = of_property_read_u32_index(np, propname, 1, &max);
47 if (ret)
48 return ret;
49
50 if (range) {
51 range->min = min;
52 range->max = max;
53 }
54
55 return 0;
56}
57EXPORT_SYMBOL_GPL(of_at91_get_clk_range);
58
59static void pmc_irq_mask(struct irq_data *d)
60{
61 struct at91_pmc *pmc = irq_data_get_irq_chip_data(d);
62
63 pmc_write(pmc, AT91_PMC_IDR, 1 << d->hwirq);
64}
65
66static void pmc_irq_unmask(struct irq_data *d)
67{
68 struct at91_pmc *pmc = irq_data_get_irq_chip_data(d);
69
70 pmc_write(pmc, AT91_PMC_IER, 1 << d->hwirq);
71}
72
73static int pmc_irq_set_type(struct irq_data *d, unsigned type)
74{
75 if (type != IRQ_TYPE_LEVEL_HIGH) {
76 pr_warn("PMC: type not supported (support only IRQ_TYPE_LEVEL_HIGH type)\n");
77 return -EINVAL;
78 }
79
80 return 0;
81}
82
83static struct irq_chip pmc_irq = {
84 .name = "PMC",
85 .irq_disable = pmc_irq_mask,
86 .irq_mask = pmc_irq_mask,
87 .irq_unmask = pmc_irq_unmask,
88 .irq_set_type = pmc_irq_set_type,
89};
90
91static struct lock_class_key pmc_lock_class;
92
93static int pmc_irq_map(struct irq_domain *h, unsigned int virq,
94 irq_hw_number_t hw)
95{
96 struct at91_pmc *pmc = h->host_data;
97
98 irq_set_lockdep_class(virq, &pmc_lock_class);
99
100 irq_set_chip_and_handler(virq, &pmc_irq,
101 handle_level_irq);
102 set_irq_flags(virq, IRQF_VALID);
103 irq_set_chip_data(virq, pmc);
104
105 return 0;
106}
107
108static int pmc_irq_domain_xlate(struct irq_domain *d,
109 struct device_node *ctrlr,
110 const u32 *intspec, unsigned int intsize,
111 irq_hw_number_t *out_hwirq,
112 unsigned int *out_type)
113{
114 struct at91_pmc *pmc = d->host_data;
115 const struct at91_pmc_caps *caps = pmc->caps;
116
117 if (WARN_ON(intsize < 1))
118 return -EINVAL;
119
120 *out_hwirq = intspec[0];
121
122 if (!(caps->available_irqs & (1 << *out_hwirq)))
123 return -EINVAL;
124
125 *out_type = IRQ_TYPE_LEVEL_HIGH;
126
127 return 0;
128}
129
130static struct irq_domain_ops pmc_irq_ops = {
131 .map = pmc_irq_map,
132 .xlate = pmc_irq_domain_xlate,
133};
134
135static irqreturn_t pmc_irq_handler(int irq, void *data)
136{
137 struct at91_pmc *pmc = (struct at91_pmc *)data;
138 unsigned long sr;
139 int n;
140
141 sr = pmc_read(pmc, AT91_PMC_SR) & pmc_read(pmc, AT91_PMC_IMR);
142 if (!sr)
143 return IRQ_NONE;
144
145 for_each_set_bit(n, &sr, BITS_PER_LONG)
146 generic_handle_irq(irq_find_mapping(pmc->irqdomain, n));
147
148 return IRQ_HANDLED;
149}
150
151static const struct at91_pmc_caps at91rm9200_caps = {
152 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB |
153 AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY |
154 AT91_PMC_PCK1RDY | AT91_PMC_PCK2RDY |
155 AT91_PMC_PCK3RDY,
156};
157
158static const struct at91_pmc_caps at91sam9260_caps = {
159 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB |
160 AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY |
161 AT91_PMC_PCK1RDY,
162};
163
164static const struct at91_pmc_caps at91sam9g45_caps = {
165 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY |
166 AT91_PMC_LOCKU | AT91_PMC_PCK0RDY |
167 AT91_PMC_PCK1RDY,
168};
169
170static const struct at91_pmc_caps at91sam9n12_caps = {
171 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB |
172 AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY |
173 AT91_PMC_PCK1RDY | AT91_PMC_MOSCSELS |
174 AT91_PMC_MOSCRCS | AT91_PMC_CFDEV,
175};
176
177static const struct at91_pmc_caps at91sam9x5_caps = {
178 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY |
179 AT91_PMC_LOCKU | AT91_PMC_PCK0RDY |
180 AT91_PMC_PCK1RDY | AT91_PMC_MOSCSELS |
181 AT91_PMC_MOSCRCS | AT91_PMC_CFDEV,
182};
183
184static const struct at91_pmc_caps sama5d3_caps = {
185 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY |
186 AT91_PMC_LOCKU | AT91_PMC_PCK0RDY |
187 AT91_PMC_PCK1RDY | AT91_PMC_PCK2RDY |
188 AT91_PMC_MOSCSELS | AT91_PMC_MOSCRCS |
189 AT91_PMC_CFDEV,
190};
191
192static struct at91_pmc *__init at91_pmc_init(struct device_node *np,
193 void __iomem *regbase, int virq,
194 const struct at91_pmc_caps *caps)
195{
196 struct at91_pmc *pmc;
197
198 if (!regbase || !virq || !caps)
199 return NULL;
200
201 at91_pmc_base = regbase;
202
203 pmc = kzalloc(sizeof(*pmc), GFP_KERNEL);
204 if (!pmc)
205 return NULL;
206
207 spin_lock_init(&pmc->lock);
208 pmc->regbase = regbase;
209 pmc->virq = virq;
210 pmc->caps = caps;
211
212 pmc->irqdomain = irq_domain_add_linear(np, 32, &pmc_irq_ops, pmc);
213
214 if (!pmc->irqdomain)
215 goto out_free_pmc;
216
217 pmc_write(pmc, AT91_PMC_IDR, 0xffffffff);
218 if (request_irq(pmc->virq, pmc_irq_handler, IRQF_SHARED, "pmc", pmc))
219 goto out_remove_irqdomain;
220
221 return pmc;
222
223out_remove_irqdomain:
224 irq_domain_remove(pmc->irqdomain);
225out_free_pmc:
226 kfree(pmc);
227
228 return NULL;
229}
230
231static const struct of_device_id pmc_clk_ids[] __initdata = {
232 /* Main clock */
233 {
234 .compatible = "atmel,at91rm9200-clk-main",
235 .data = of_at91rm9200_clk_main_setup,
236 },
237 /* PLL clocks */
238 {
239 .compatible = "atmel,at91rm9200-clk-pll",
240 .data = of_at91rm9200_clk_pll_setup,
241 },
242 {
243 .compatible = "atmel,at91sam9g45-clk-pll",
244 .data = of_at91sam9g45_clk_pll_setup,
245 },
246 {
247 .compatible = "atmel,at91sam9g20-clk-pllb",
248 .data = of_at91sam9g20_clk_pllb_setup,
249 },
250 {
251 .compatible = "atmel,sama5d3-clk-pll",
252 .data = of_sama5d3_clk_pll_setup,
253 },
254 {
255 .compatible = "atmel,at91sam9x5-clk-plldiv",
256 .data = of_at91sam9x5_clk_plldiv_setup,
257 },
258 /* Master clock */
259 {
260 .compatible = "atmel,at91rm9200-clk-master",
261 .data = of_at91rm9200_clk_master_setup,
262 },
263 {
264 .compatible = "atmel,at91sam9x5-clk-master",
265 .data = of_at91sam9x5_clk_master_setup,
266 },
267 /* System clocks */
268 {
269 .compatible = "atmel,at91rm9200-clk-system",
270 .data = of_at91rm9200_clk_sys_setup,
271 },
272 /* Peripheral clocks */
273 {
274 .compatible = "atmel,at91rm9200-clk-peripheral",
275 .data = of_at91rm9200_clk_periph_setup,
276 },
277 {
278 .compatible = "atmel,at91sam9x5-clk-peripheral",
279 .data = of_at91sam9x5_clk_periph_setup,
280 },
281 /* Programmable clocks */
282#if defined(CONFIG_AT91_PROGRAMMABLE_CLOCKS)
283 {
284 .compatible = "atmel,at91rm9200-clk-programmable",
285 .data = of_at91rm9200_clk_prog_setup,
286 },
287 {
288 .compatible = "atmel,at91sam9g45-clk-programmable",
289 .data = of_at91sam9g45_clk_prog_setup,
290 },
291 {
292 .compatible = "atmel,at91sam9x5-clk-programmable",
293 .data = of_at91sam9x5_clk_prog_setup,
294 },
295#endif
296 /* UTMI clock */
297#if defined(CONFIG_HAVE_AT91_UTMI)
298 {
299 .compatible = "atmel,at91sam9x5-clk-utmi",
300 .data = of_at91sam9x5_clk_utmi_setup,
301 },
302#endif
303 /* USB clock */
304#if defined(CONFIG_HAVE_AT91_USB_CLK)
305 {
306 .compatible = "atmel,at91rm9200-clk-usb",
307 .data = of_at91rm9200_clk_usb_setup,
308 },
309 {
310 .compatible = "atmel,at91sam9x5-clk-usb",
311 .data = of_at91sam9x5_clk_usb_setup,
312 },
313 {
314 .compatible = "atmel,at91sam9n12-clk-usb",
315 .data = of_at91sam9n12_clk_usb_setup,
316 },
317#endif
318 /* SMD clock */
319#if defined(CONFIG_HAVE_AT91_SMD)
320 {
321 .compatible = "atmel,at91sam9x5-clk-smd",
322 .data = of_at91sam9x5_clk_smd_setup,
323 },
324#endif
325 { /*sentinel*/ }
326};
327
328static void __init of_at91_pmc_setup(struct device_node *np,
329 const struct at91_pmc_caps *caps)
330{
331 struct at91_pmc *pmc;
332 struct device_node *childnp;
333 void (*clk_setup)(struct device_node *, struct at91_pmc *);
334 const struct of_device_id *clk_id;
335 void __iomem *regbase = of_iomap(np, 0);
336 int virq;
337
338 if (!regbase)
339 return;
340
341 virq = irq_of_parse_and_map(np, 0);
342 if (!virq)
343 return;
344
345 pmc = at91_pmc_init(np, regbase, virq, caps);
346 if (!pmc)
347 return;
348 for_each_child_of_node(np, childnp) {
349 clk_id = of_match_node(pmc_clk_ids, childnp);
350 if (!clk_id)
351 continue;
352 clk_setup = clk_id->data;
353 clk_setup(childnp, pmc);
354 }
355}
356
357static void __init of_at91rm9200_pmc_setup(struct device_node *np)
358{
359 of_at91_pmc_setup(np, &at91rm9200_caps);
360}
361CLK_OF_DECLARE(at91rm9200_clk_pmc, "atmel,at91rm9200-pmc",
362 of_at91rm9200_pmc_setup);
363
364static void __init of_at91sam9260_pmc_setup(struct device_node *np)
365{
366 of_at91_pmc_setup(np, &at91sam9260_caps);
367}
368CLK_OF_DECLARE(at91sam9260_clk_pmc, "atmel,at91sam9260-pmc",
369 of_at91sam9260_pmc_setup);
370
371static void __init of_at91sam9g45_pmc_setup(struct device_node *np)
372{
373 of_at91_pmc_setup(np, &at91sam9g45_caps);
374}
375CLK_OF_DECLARE(at91sam9g45_clk_pmc, "atmel,at91sam9g45-pmc",
376 of_at91sam9g45_pmc_setup);
377
378static void __init of_at91sam9n12_pmc_setup(struct device_node *np)
379{
380 of_at91_pmc_setup(np, &at91sam9n12_caps);
381}
382CLK_OF_DECLARE(at91sam9n12_clk_pmc, "atmel,at91sam9n12-pmc",
383 of_at91sam9n12_pmc_setup);
384
385static void __init of_at91sam9x5_pmc_setup(struct device_node *np)
386{
387 of_at91_pmc_setup(np, &at91sam9x5_caps);
388}
389CLK_OF_DECLARE(at91sam9x5_clk_pmc, "atmel,at91sam9x5-pmc",
390 of_at91sam9x5_pmc_setup);
391
392static void __init of_sama5d3_pmc_setup(struct device_node *np)
393{
394 of_at91_pmc_setup(np, &sama5d3_caps);
395}
396CLK_OF_DECLARE(sama5d3_clk_pmc, "atmel,sama5d3-pmc",
397 of_sama5d3_pmc_setup);
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
new file mode 100644
index 000000000000..ba8d14233f80
--- /dev/null
+++ b/drivers/clk/at91/pmc.h
@@ -0,0 +1,116 @@
1/*
2 * drivers/clk/at91/pmc.h
3 *
4 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef __PMC_H_
13#define __PMC_H_
14
15#include <linux/io.h>
16#include <linux/irqdomain.h>
17#include <linux/spinlock.h>
18
19struct clk_range {
20 unsigned long min;
21 unsigned long max;
22};
23
24#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
25
26struct at91_pmc_caps {
27 u32 available_irqs;
28};
29
30struct at91_pmc {
31 void __iomem *regbase;
32 int virq;
33 spinlock_t lock;
34 const struct at91_pmc_caps *caps;
35 struct irq_domain *irqdomain;
36};
37
38static inline void pmc_lock(struct at91_pmc *pmc)
39{
40 spin_lock(&pmc->lock);
41}
42
43static inline void pmc_unlock(struct at91_pmc *pmc)
44{
45 spin_unlock(&pmc->lock);
46}
47
48static inline u32 pmc_read(struct at91_pmc *pmc, int offset)
49{
50 return readl(pmc->regbase + offset);
51}
52
53static inline void pmc_write(struct at91_pmc *pmc, int offset, u32 value)
54{
55 writel(value, pmc->regbase + offset);
56}
57
58int of_at91_get_clk_range(struct device_node *np, const char *propname,
59 struct clk_range *range);
60
61extern void __init of_at91rm9200_clk_main_setup(struct device_node *np,
62 struct at91_pmc *pmc);
63
64extern void __init of_at91rm9200_clk_pll_setup(struct device_node *np,
65 struct at91_pmc *pmc);
66extern void __init of_at91sam9g45_clk_pll_setup(struct device_node *np,
67 struct at91_pmc *pmc);
68extern void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np,
69 struct at91_pmc *pmc);
70extern void __init of_sama5d3_clk_pll_setup(struct device_node *np,
71 struct at91_pmc *pmc);
72extern void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np,
73 struct at91_pmc *pmc);
74
75extern void __init of_at91rm9200_clk_master_setup(struct device_node *np,
76 struct at91_pmc *pmc);
77extern void __init of_at91sam9x5_clk_master_setup(struct device_node *np,
78 struct at91_pmc *pmc);
79
80extern void __init of_at91rm9200_clk_sys_setup(struct device_node *np,
81 struct at91_pmc *pmc);
82
83extern void __init of_at91rm9200_clk_periph_setup(struct device_node *np,
84 struct at91_pmc *pmc);
85extern void __init of_at91sam9x5_clk_periph_setup(struct device_node *np,
86 struct at91_pmc *pmc);
87
88#if defined(CONFIG_AT91_PROGRAMMABLE_CLOCKS)
89extern void __init of_at91rm9200_clk_prog_setup(struct device_node *np,
90 struct at91_pmc *pmc);
91extern void __init of_at91sam9g45_clk_prog_setup(struct device_node *np,
92 struct at91_pmc *pmc);
93extern void __init of_at91sam9x5_clk_prog_setup(struct device_node *np,
94 struct at91_pmc *pmc);
95#endif
96
97#if defined(CONFIG_HAVE_AT91_UTMI)
98extern void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np,
99 struct at91_pmc *pmc);
100#endif
101
102#if defined(CONFIG_HAVE_AT91_USB_CLK)
103extern void __init of_at91rm9200_clk_usb_setup(struct device_node *np,
104 struct at91_pmc *pmc);
105extern void __init of_at91sam9x5_clk_usb_setup(struct device_node *np,
106 struct at91_pmc *pmc);
107extern void __init of_at91sam9n12_clk_usb_setup(struct device_node *np,
108 struct at91_pmc *pmc);
109#endif
110
111#if defined(CONFIG_HAVE_AT91_SMD)
112extern void __init of_at91sam9x5_clk_smd_setup(struct device_node *np,
113 struct at91_pmc *pmc);
114#endif
115
116#endif /* __PMC_H_ */
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index 2cb52e0438df..9f71d9fdcc14 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -326,7 +326,7 @@ static int vbus_is_present(struct usba_udc *udc)
326 326
327#if defined(CONFIG_ARCH_AT91SAM9RL) 327#if defined(CONFIG_ARCH_AT91SAM9RL)
328 328
329#include <mach/at91_pmc.h> 329#include <linux/clk/at91_pmc.h>
330 330
331static void toggle_bias(int is_on) 331static void toggle_bias(int is_on)
332{ 332{
diff --git a/include/dt-bindings/clk/at91.h b/include/dt-bindings/clk/at91.h
new file mode 100644
index 000000000000..0b4cb999a3f7
--- /dev/null
+++ b/include/dt-bindings/clk/at91.h
@@ -0,0 +1,22 @@
1/*
2 * This header provides constants for AT91 pmc status.
3 *
4 * The constants defined in this header are being used in dts.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef _DT_BINDINGS_CLK_AT91_H
10#define _DT_BINDINGS_CLK_AT91_H
11
12#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
13#define AT91_PMC_LOCKA 1 /* PLLA Lock */
14#define AT91_PMC_LOCKB 2 /* PLLB Lock */
15#define AT91_PMC_MCKRDY 3 /* Master Clock */
16#define AT91_PMC_LOCKU 6 /* UPLL Lock */
17#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */
18#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */
19#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */
20#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
21
22#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/include/linux/clk/at91_pmc.h
index c604cc69acb5..a6911ebbd02a 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-at91/include/mach/at91_pmc.h 2 * include/linux/clk/at91_pmc.h
3 * 3 *
4 * Copyright (C) 2005 Ivan Kokshaysky 4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People 5 * Copyright (C) SAN People
@@ -164,6 +164,8 @@ extern void __iomem *at91_pmc_base;
164#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ 164#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
165#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ 165#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
166 166
167#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */
168
167#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ 169#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
168#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ 170#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
169#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ 171#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 17:31:18 -0500