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-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi249
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts45
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi319
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-smaug.dts314
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210.dtsi292
5 files changed, 1218 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
index 316c92c03821..5fda583351d7 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
@@ -1,3 +1,5 @@
1#include <dt-bindings/mfd/max77620.h>
2
1#include "tegra210.dtsi" 3#include "tegra210.dtsi"
2 4
3/ { 5/ {
@@ -5,10 +7,15 @@
5 compatible = "nvidia,p2180", "nvidia,tegra210"; 7 compatible = "nvidia,p2180", "nvidia,tegra210";
6 8
7 aliases { 9 aliases {
10 rtc0 = "/i2c@7000d000/pmic@3c";
8 rtc1 = "/rtc@7000e000"; 11 rtc1 = "/rtc@7000e000";
9 serial0 = &uarta; 12 serial0 = &uarta;
10 }; 13 };
11 14
15 chosen {
16 stdout-path = "serial0:115200n8";
17 };
18
12 memory { 19 memory {
13 device_type = "memory"; 20 device_type = "memory";
14 reg = <0x0 0x80000000 0x1 0x0>; 21 reg = <0x0 0x80000000 0x1 0x0>;
@@ -19,6 +26,248 @@
19 status = "okay"; 26 status = "okay";
20 }; 27 };
21 28
29 i2c@7000d000 {
30 status = "okay";
31 clock-frequency = <400000>;
32
33 pmic: pmic@3c {
34 compatible = "maxim,max77620";
35 reg = <0x3c>;
36 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
37
38 #interrupt-cells = <2>;
39 interrupt-controller;
40
41 #gpio-cells = <2>;
42 gpio-controller;
43
44 pinctrl-names = "default";
45 pinctrl-0 = <&max77620_default>;
46
47 max77620_default: pinmux {
48 gpio0 {
49 pins = "gpio0";
50 function = "gpio";
51 };
52
53 gpio1 {
54 pins = "gpio1";
55 function = "fps-out";
56 drive-push-pull = <1>;
57 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
58 maxim,active-fps-power-up-slot = <7>;
59 maxim,active-fps-power-down-slot = <0>;
60 };
61
62 gpio2_3 {
63 pins = "gpio2", "gpio3";
64 function = "fps-out";
65 drive-open-drain = <1>;
66 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
67 };
68
69 gpio4 {
70 pins = "gpio4";
71 function = "32k-out1";
72 };
73
74 gpio5_6_7 {
75 pins = "gpio5", "gpio6", "gpio7";
76 function = "gpio";
77 drive-push-pull = <1>;
78 };
79 };
80
81 fps {
82 fps0 {
83 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
84 maxim,suspend-fps-time-period-us = <1280>;
85 };
86
87 fps1 {
88 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
89 maxim,suspend-fps-time-period-us = <1280>;
90 };
91
92 fps2 {
93 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
94 };
95 };
96
97 regulators {
98 in-ldo0-1-supply = <&vdd_pre>;
99 in-ldo7-8-supply = <&vdd_pre>;
100 in-sd3-supply = <&vdd_5v0_sys>;
101
102 vdd_soc: sd0 {
103 regulator-name = "VDD_SOC";
104 regulator-min-microvolt = <600000>;
105 regulator-max-microvolt = <1400000>;
106 regulator-always-on;
107 regulator-boot-on;
108
109 regulator-enable-ramp-delay = <146>;
110 regulator-ramp-delay = <27500>;
111
112 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
113 };
114
115 vdd_ddr: sd1 {
116 regulator-name = "VDD_DDR_1V1_PMIC";
117 regulator-always-on;
118 regulator-boot-on;
119
120 regulator-enable-ramp-delay = <130>;
121 regulator-ramp-delay = <27500>;
122
123 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
124 };
125
126 vdd_pre: sd2 {
127 regulator-name = "VDD_PRE_REG_1V35";
128 regulator-min-microvolt = <1350000>;
129 regulator-max-microvolt = <1350000>;
130
131 regulator-enable-ramp-delay = <176>;
132 regulator-ramp-delay = <27500>;
133
134 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
135 };
136
137 vdd_1v8: sd3 {
138 regulator-name = "VDD_1V8";
139 regulator-min-microvolt = <1800000>;
140 regulator-max-microvolt = <1800000>;
141 regulator-always-on;
142 regulator-boot-on;
143
144 regulator-enable-ramp-delay = <242>;
145 regulator-ramp-delay = <27500>;
146
147 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
148 };
149
150 vdd_sys_1v2: ldo0 {
151 regulator-name = "AVDD_SYS_1V2";
152 regulator-min-microvolt = <1200000>;
153 regulator-max-microvolt = <1200000>;
154 regulator-always-on;
155 regulator-boot-on;
156
157 regulator-enable-ramp-delay = <26>;
158 regulator-ramp-delay = <100000>;
159
160 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
161 };
162
163 vdd_pex_1v05: ldo1 {
164 regulator-name = "VDD_PEX_1V05";
165 regulator-min-microvolt = <1050000>;
166 regulator-max-microvolt = <1050000>;
167
168 regulator-enable-ramp-delay = <22>;
169 regulator-ramp-delay = <100000>;
170
171 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
172 };
173
174 vddio_sdmmc: ldo2 {
175 regulator-name = "VDDIO_SDMMC";
176 /*
177 * Technically this supply should have
178 * a supported range from 1.8 - 3.3 V.
179 * However, that would cause the SDHCI
180 * driver to request 2.7 V upon access
181 * and that in turn will cause traffic
182 * to be broken. Leave it at 3.3 V for
183 * now.
184 */
185 regulator-min-microvolt = <3300000>;
186 regulator-max-microvolt = <3300000>;
187 regulator-always-on;
188 regulator-boot-on;
189
190 regulator-enable-ramp-delay = <62>;
191 regulator-ramp-delay = <100000>;
192
193 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
194 };
195
196 vdd_cam_hv: ldo3 {
197 regulator-name = "VDD_CAM_HV";
198 regulator-min-microvolt = <2800000>;
199 regulator-max-microvolt = <2800000>;
200
201 regulator-enable-ramp-delay = <50>;
202 regulator-ramp-delay = <100000>;
203
204 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
205 };
206
207 vdd_rtc: ldo4 {
208 regulator-name = "VDD_RTC";
209 regulator-min-microvolt = <850000>;
210 regulator-max-microvolt = <850000>;
211 regulator-always-on;
212 regulator-boot-on;
213
214 regulator-enable-ramp-delay = <22>;
215 regulator-ramp-delay = <100000>;
216
217 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
218 };
219
220 vdd_ts_hv: ldo5 {
221 regulator-name = "VDD_TS_HV";
222 regulator-min-microvolt = <3300000>;
223 regulator-max-microvolt = <3300000>;
224
225 regulator-enable-ramp-delay = <62>;
226 regulator-ramp-delay = <100000>;
227
228 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
229 };
230
231 vdd_ts: ldo6 {
232 regulator-name = "VDD_TS_1V8";
233 regulator-min-microvolt = <1800000>;
234 regulator-max-microvolt = <1800000>;
235
236 regulator-enable-ramp-delay = <36>;
237 regulator-ramp-delay = <100000>;
238
239 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
240 maxim,active-fps-power-up-slot = <7>;
241 maxim,active-fps-power-down-slot = <0>;
242 };
243
244 avdd_1v05_pll: ldo7 {
245 regulator-name = "AVDD_1V05_PLL";
246 regulator-min-microvolt = <1050000>;
247 regulator-max-microvolt = <1050000>;
248 regulator-always-on;
249 regulator-boot-on;
250
251 regulator-enable-ramp-delay = <24>;
252 regulator-ramp-delay = <100000>;
253
254 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
255 };
256
257 avdd_1v05: ldo8 {
258 regulator-name = "AVDD_SATA_HDMI_DP_1V05";
259 regulator-min-microvolt = <1050000>;
260 regulator-max-microvolt = <1050000>;
261
262 regulator-enable-ramp-delay = <22>;
263 regulator-ramp-delay = <100000>;
264
265 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
266 };
267 };
268 };
269 };
270
22 pmc@7000e400 { 271 pmc@7000e400 {
23 nvidia,invert-interrupt; 272 nvidia,invert-interrupt;
24 }; 273 };
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
index 683b339a980c..983775e637a4 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -6,4 +6,49 @@
6/ { 6/ {
7 model = "NVIDIA Jetson TX1 Developer Kit"; 7 model = "NVIDIA Jetson TX1 Developer Kit";
8 compatible = "nvidia,p2371-2180", "nvidia,tegra210"; 8 compatible = "nvidia,p2371-2180", "nvidia,tegra210";
9
10 host1x@50000000 {
11 dsi@54300000 {
12 status = "okay";
13
14 avdd-dsi-csi-supply = <&vdd_dsi_csi>;
15
16 panel@0 {
17 compatible = "auo,b080uan01";
18 reg = <0>;
19
20 enable-gpios = <&gpio TEGRA_GPIO(V, 2)
21 GPIO_ACTIVE_HIGH>;
22 power-supply = <&vdd_5v0_io>;
23 backlight = <&backlight>;
24 };
25 };
26 };
27
28 i2c@7000c400 {
29 backlight: backlight@2c {
30 compatible = "ti,lp8557";
31 reg = <0x2c>;
32
33 dev-ctrl = /bits/ 8 <0x80>;
34 init-brt = /bits/ 8 <0xff>;
35
36 pwm-period = <29334>;
37
38 pwms = <&pwm 0 29334>;
39 pwm-names = "lp8557";
40
41 /* 3 LED string */
42 rom_14h {
43 rom-addr = /bits/ 8 <0x14>;
44 rom-val = /bits/ 8 <0x87>;
45 };
46
47 /* boost frequency 1 MHz */
48 rom_13h {
49 rom-addr = /bits/ 8 <0x13>;
50 rom-val = /bits/ 8 <0x01>;
51 };
52 };
53 };
9}; 54};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
index a2480c0c7e72..e5fc67bf46c2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
@@ -4,6 +4,24 @@
4 model = "NVIDIA Tegra210 P2597 I/O board"; 4 model = "NVIDIA Tegra210 P2597 I/O board";
5 compatible = "nvidia,p2597", "nvidia,tegra210"; 5 compatible = "nvidia,p2597", "nvidia,tegra210";
6 6
7 host1x@50000000 {
8 dpaux@54040000 {
9 status = "okay";
10 };
11
12 sor@54580000 {
13 status = "okay";
14
15 avdd-io-supply = <&avdd_1v05>;
16 vdd-pll-supply = <&vdd_1v8>;
17 hdmi-supply = <&vdd_hdmi>;
18
19 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
20 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
21 GPIO_ACTIVE_LOW>;
22 };
23 };
24
7 pinmux: pinmux@700008d4 { 25 pinmux: pinmux@700008d4 {
8 pinctrl-names = "boot"; 26 pinctrl-names = "boot";
9 pinctrl-0 = <&state_boot>; 27 pinctrl-0 = <&state_boot>;
@@ -1261,6 +1279,169 @@
1261 }; 1279 };
1262 }; 1280 };
1263 1281
1282 pwm@7000a000 {
1283 status = "okay";
1284 };
1285
1286 i2c@7000c400 {
1287 status = "okay";
1288 clock-frequency = <100000>;
1289
1290 exp1: gpio@74 {
1291 compatible = "ti,tca9539";
1292 reg = <0x74>;
1293
1294 #gpio-cells = <2>;
1295 gpio-controller;
1296 };
1297 };
1298
1299 /* HDMI DDC */
1300 hdmi_ddc: i2c@7000c700 {
1301 status = "okay";
1302 clock-frequency = <100000>;
1303 };
1304
1305 usb@70090000 {
1306 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
1307 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
1308 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
1309 <&{/padctl@7009f000/pads/usb2/lanes/usb2-3}>,
1310 <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>,
1311 <&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>;
1312 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0",
1313 "usb3-1";
1314
1315 dvddio-pex-supply = <&vdd_pex_1v05>;
1316 hvddio-pex-supply = <&vdd_1v8>;
1317 avdd-usb-supply = <&vdd_3v3_sys>;
1318 /* XXX what are these? */
1319 avdd-pll-utmip-supply = <&vdd_1v8>;
1320 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
1321 dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
1322 hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;
1323
1324 status = "okay";
1325 };
1326
1327 padctl@7009f000 {
1328 status = "okay";
1329
1330 pads {
1331 usb2 {
1332 status = "okay";
1333
1334 lanes {
1335 usb2-0 {
1336 nvidia,function = "xusb";
1337 status = "okay";
1338 };
1339
1340 usb2-1 {
1341 nvidia,function = "xusb";
1342 status = "okay";
1343 };
1344
1345 usb2-2 {
1346 nvidia,function = "xusb";
1347 status = "okay";
1348 };
1349
1350 usb2-3 {
1351 nvidia,function = "xusb";
1352 status = "okay";
1353 };
1354 };
1355 };
1356
1357 pcie {
1358 status = "okay";
1359
1360 lanes {
1361 pcie-0 {
1362 nvidia,function = "pcie-x1";
1363 status = "okay";
1364 };
1365
1366 pcie-1 {
1367 nvidia,function = "pcie-x4";
1368 status = "okay";
1369 };
1370
1371 pcie-2 {
1372 nvidia,function = "pcie-x4";
1373 status = "okay";
1374 };
1375
1376 pcie-3 {
1377 nvidia,function = "pcie-x4";
1378 status = "okay";
1379 };
1380
1381 pcie-4 {
1382 nvidia,function = "pcie-x4";
1383 status = "okay";
1384 };
1385
1386 pcie-5 {
1387 nvidia,function = "usb3-ss";
1388 status = "okay";
1389 };
1390
1391 pcie-6 {
1392 nvidia,function = "usb3-ss";
1393 status = "okay";
1394 };
1395 };
1396 };
1397
1398 sata {
1399 status = "okay";
1400
1401 lanes {
1402 sata-0 {
1403 nvidia,function = "sata";
1404 status = "okay";
1405 };
1406 };
1407 };
1408 };
1409
1410 ports {
1411 usb2-0 {
1412 status = "okay";
1413 mode = "otg";
1414 };
1415
1416 usb2-1 {
1417 status = "okay";
1418 vbus-supply = <&vdd_5v0_rtl>;
1419 mode = "host";
1420 };
1421
1422 usb2-2 {
1423 status = "okay";
1424 vbus-supply = <&vdd_usb_vbus>;
1425 mode = "host";
1426 };
1427
1428 usb2-3 {
1429 status = "okay";
1430 mode = "host";
1431 };
1432
1433 usb3-0 {
1434 nvidia,usb2-companion = <1>;
1435 status = "okay";
1436 };
1437
1438 usb3-1 {
1439 nvidia,usb2-companion = <2>;
1440 status = "okay";
1441 };
1442 };
1443 };
1444
1264 /* MMC/SD */ 1445 /* MMC/SD */
1265 sdhci@700b0000 { 1446 sdhci@700b0000 {
1266 status = "okay"; 1447 status = "okay";
@@ -1268,6 +1449,144 @@
1268 no-1-8-v; 1449 no-1-8-v;
1269 1450
1270 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; 1451 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
1452
1453 vqmmc-supply = <&vddio_sdmmc>;
1454 vmmc-supply = <&vdd_3v3_sd>;
1455 };
1456
1457 regulators {
1458 compatible = "simple-bus";
1459 #address-cells = <1>;
1460 #size-cells = <0>;
1461
1462 vdd_sys_mux: regulator@0 {
1463 compatible = "regulator-fixed";
1464 reg = <0>;
1465 regulator-name = "VDD_SYS_MUX";
1466 regulator-min-microvolt = <5000000>;
1467 regulator-max-microvolt = <5000000>;
1468 regulator-always-on;
1469 regulator-boot-on;
1470 };
1471
1472 vdd_5v0_sys: regulator@1 {
1473 compatible = "regulator-fixed";
1474 reg = <1>;
1475 regulator-name = "VDD_5V0_SYS";
1476 regulator-min-microvolt = <5000000>;
1477 regulator-max-microvolt = <5000000>;
1478 regulator-always-on;
1479 regulator-boot-on;
1480 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
1481 enable-active-high;
1482 vin-supply = <&vdd_sys_mux>;
1483 };
1484
1485 vdd_3v3_sys: regulator@2 {
1486 compatible = "regulator-fixed";
1487 reg = <2>;
1488 regulator-name = "VDD_3V3_SYS";
1489 regulator-min-microvolt = <3300000>;
1490 regulator-max-microvolt = <3300000>;
1491 regulator-always-on;
1492 regulator-boot-on;
1493 gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
1494 enable-active-high;
1495 vin-supply = <&vdd_sys_mux>;
1496
1497 regulator-enable-ramp-delay = <160>;
1498 regulator-disable-ramp-delay = <10000>;
1499 };
1500
1501 vdd_5v0_io: regulator@3 {
1502 compatible = "regulator-fixed";
1503 reg = <3>;
1504 regulator-name = "VDD_5V0_IO_SYS";
1505 regulator-min-microvolt = <5000000>;
1506 regulator-max-microvolt = <5000000>;
1507 regulator-always-on;
1508 regulator-boot-on;
1509 };
1510
1511 vdd_3v3_sd: regulator@4 {
1512 compatible = "regulator-fixed";
1513 reg = <4>;
1514 regulator-name = "VDD_3V3_SD";
1515 regulator-min-microvolt = <3300000>;
1516 regulator-max-microvolt = <3300000>;
1517 gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
1518 enable-active-high;
1519 vin-supply = <&vdd_3v3_sys>;
1520
1521 regulator-enable-ramp-delay = <472>;
1522 regulator-disable-ramp-delay = <4880>;
1523 };
1524
1525 vdd_dsi_csi: regulator@5 {
1526 compatible = "regulator-fixed";
1527 reg = <5>;
1528 regulator-name = "AVDD_DSI_CSI_1V2";
1529 regulator-min-microvolt = <1200000>;
1530 regulator-max-microvolt = <1200000>;
1531 vin-supply = <&vdd_sys_1v2>;
1532 };
1533
1534 vdd_3v3_dis: regulator@6 {
1535 compatible = "regulator-fixed";
1536 reg = <6>;
1537 regulator-name = "VDD_DIS_3V3_LCD";
1538 regulator-min-microvolt = <3300000>;
1539 regulator-max-microvolt = <3300000>;
1540 regulator-always-on;
1541 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
1542 enable-active-high;
1543 vin-supply = <&vdd_3v3_sys>;
1544 };
1545
1546 vdd_1v8_dis: regulator@7 {
1547 compatible = "regulator-fixed";
1548 reg = <7>;
1549 regulator-name = "VDD_LCD_1V8_DIS";
1550 regulator-min-microvolt = <1800000>;
1551 regulator-max-microvolt = <1800000>;
1552 regulator-always-on;
1553 gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
1554 enable-active-high;
1555 vin-supply = <&vdd_1v8>;
1556 };
1557
1558 vdd_5v0_rtl: regulator@8 {
1559 compatible = "regulator-fixed";
1560 reg = <8>;
1561 regulator-name = "RTL_5V";
1562 regulator-min-microvolt = <5000000>;
1563 regulator-max-microvolt = <5000000>;
1564 gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
1565 enable-active-high;
1566 vin-supply = <&vdd_5v0_sys>;
1567 };
1568
1569 vdd_usb_vbus: regulator@9 {
1570 compatible = "regulator-fixed";
1571 reg = <9>;
1572 regulator-name = "USB_VBUS_EN1";
1573 regulator-min-microvolt = <5000000>;
1574 regulator-max-microvolt = <5000000>;
1575 gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
1576 enable-active-high;
1577 vin-supply = <&vdd_5v0_sys>;
1578 };
1579
1580 vdd_hdmi: regulator@10 {
1581 compatible = "regulator-fixed";
1582 reg = <10>;
1583 regulator-name = "VDD_HDMI_5V0";
1584 regulator-min-microvolt = <5000000>;
1585 regulator-max-microvolt = <5000000>;
1586 gpio = <&exp1 12 GPIO_ACTIVE_LOW>;
1587 enable-active-high;
1588 vin-supply = <&vdd_5v0_sys>;
1589 };
1271 }; 1590 };
1272 1591
1273 gpio-keys { 1592 gpio-keys {
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index 4d89f4e02d98..431266a48e9c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/input.h> 3#include <dt-bindings/input/input.h>
4#include <dt-bindings/mfd/max77620.h>
4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 6
6#include "tegra210.dtsi" 7#include "tegra210.dtsi"
@@ -1327,6 +1328,234 @@
1327 }; 1328 };
1328 }; 1329 };
1329 1330
1331 i2c@7000d000 {
1332 status = "okay";
1333 clock-frequency = <1000000>;
1334
1335 max77620: max77620@3c {
1336 compatible = "maxim,max77620";
1337 reg = <0x3c>;
1338 interrupts = <0 86 IRQ_TYPE_NONE>;
1339
1340 #interrupt-cells = <2>;
1341 interrupt-controller;
1342
1343 gpio-controller;
1344 #gpio-cells = <2>;
1345
1346 pinctrl-names = "default";
1347 pinctrl-0 = <&max77620_default>;
1348
1349 max77620_default: pinmux@0 {
1350 pin_gpio {
1351 pins = "gpio0", "gpio1", "gpio2", "gpio7";
1352 function = "gpio";
1353 };
1354
1355 /*
1356 * GPIO3 is used to en_pp3300, and it is part of power
1357 * sequence, So it must be sequenced up (automatically
1358 * set by OTP) and down properly.
1359 */
1360 pin_gpio3 {
1361 pins = "gpio3";
1362 function = "fps-out";
1363 drive-open-drain = <1>;
1364 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1365 maxim,active-fps-power-up-slot = <4>;
1366 maxim,active-fps-power-down-slot = <2>;
1367 };
1368
1369 pin_gpio5_6 {
1370 pins = "gpio5", "gpio6";
1371 function = "gpio";
1372 drive-push-pull = <1>;
1373 };
1374
1375 pin_32k {
1376 pins = "gpio4";
1377 function = "32k-out1";
1378 };
1379 };
1380
1381 fps {
1382 fps0 {
1383 maxim,shutdown-fps-time-period-us = <5120>;
1384 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
1385 };
1386
1387 fps1 {
1388 maxim,shutdown-fps-time-period-us = <5120>;
1389 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
1390 maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>;
1391 };
1392
1393 fps2 {
1394 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
1395 };
1396 };
1397
1398 regulators {
1399 in-ldo0-1-supply = <&pp1350>;
1400 in-ldo2-supply = <&pp3300>;
1401 in-ldo3-5-supply = <&pp3300>;
1402 in-ldo7-8-supply = <&pp1350>;
1403
1404 ppvar_soc: sd0 {
1405 regulator-name = "PPVAR_SOC";
1406 regulator-min-microvolt = <825000>;
1407 regulator-max-microvolt = <1125000>;
1408 regulator-always-on;
1409 regulator-boot-on;
1410 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
1411 maxim,active-fps-power-up-slot = <1>;
1412 maxim,active-fps-power-down-slot = <7>;
1413 };
1414
1415 pp1100_sd1: sd1 {
1416 regulator-name = "PP1100";
1417 regulator-min-microvolt = <1125000>;
1418 regulator-max-microvolt = <1125000>;
1419 regulator-always-on;
1420 regulator-boot-on;
1421 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1422 maxim,active-fps-power-up-slot = <5>;
1423 maxim,active-fps-power-down-slot = <1>;
1424 };
1425
1426 pp1350: sd2 {
1427 regulator-name = "PP1350";
1428 regulator-min-microvolt = <1350000>;
1429 regulator-max-microvolt = <1350000>;
1430 regulator-always-on;
1431 regulator-boot-on;
1432 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1433 maxim,active-fps-power-up-slot = <2>;
1434 maxim,active-fps-power-down-slot = <5>;
1435 };
1436
1437 pp1800: sd3 {
1438 regulator-name = "PP1800";
1439 regulator-min-microvolt = <1800000>;
1440 regulator-max-microvolt = <1800000>;
1441 regulator-always-on;
1442 regulator-boot-on;
1443 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1444 maxim,active-fps-power-up-slot = <3>;
1445 maxim,active-fps-power-down-slot = <3>;
1446 };
1447
1448 pp1200_avdd: ldo0 {
1449 regulator-name = "PP1200_AVDD";
1450 regulator-min-microvolt = <1200000>;
1451 regulator-max-microvolt = <1200000>;
1452 regulator-enable-ramp-delay = <26>;
1453 regulator-ramp-delay = <100000>;
1454 regulator-boot-on;
1455 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1456 maxim,active-fps-power-up-slot = <0>;
1457 maxim,active-fps-power-down-slot = <7>;
1458 };
1459
1460 pp1200_rcam: ldo1 {
1461 regulator-name = "PP1200_RCAM";
1462 regulator-min-microvolt = <1200000>;
1463 regulator-max-microvolt = <1200000>;
1464 regulator-enable-ramp-delay = <22>;
1465 regulator-ramp-delay = <100000>;
1466 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1467 maxim,active-fps-power-up-slot = <0>;
1468 maxim,active-fps-power-down-slot = <7>;
1469 };
1470
1471 pp_ldo2: ldo2 {
1472 regulator-name = "PP_LDO2";
1473 regulator-min-microvolt = <1800000>;
1474 regulator-max-microvolt = <1800000>;
1475 regulator-enable-ramp-delay = <62>;
1476 regulator-ramp-delay = <11000>;
1477 regulator-always-on;
1478 regulator-boot-on;
1479 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1480 maxim,active-fps-power-up-slot = <0>;
1481 maxim,active-fps-power-down-slot = <7>;
1482 };
1483
1484 pp2800l_rcam: ldo3 {
1485 regulator-name = "PP2800L_RCAM";
1486 regulator-min-microvolt = <2800000>;
1487 regulator-max-microvolt = <2800000>;
1488 regulator-enable-ramp-delay = <50>;
1489 regulator-ramp-delay = <100000>;
1490 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1491 maxim,active-fps-power-up-slot = <0>;
1492 maxim,active-fps-power-down-slot = <7>;
1493 };
1494
1495 pp100_soc_rtc: ldo4 {
1496 regulator-name = "PP1100_SOC_RTC";
1497 regulator-min-microvolt = <850000>;
1498 regulator-max-microvolt = <850000>;
1499 regulator-enable-ramp-delay = <22>;
1500 regulator-ramp-delay = <100000>;
1501 regulator-always-on; /* Check this */
1502 regulator-boot-on;
1503 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1504 maxim,active-fps-power-up-slot = <1>;
1505 maxim,active-fps-power-down-slot = <7>;
1506 };
1507
1508 pp2800l_fcam: ldo5 {
1509 regulator-name = "PP2800L_FCAM";
1510 regulator-min-microvolt = <2800000>;
1511 regulator-max-microvolt = <2800000>;
1512 regulator-enable-ramp-delay = <62>;
1513 regulator-ramp-delay = <100000>;
1514 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1515 maxim,active-fps-power-up-slot = <0>;
1516 maxim,active-fps-power-down-slot = <7>;
1517 };
1518
1519 ldo6 {
1520 /* Unused. */
1521 regulator-name = "PP_LDO6";
1522 regulator-min-microvolt = <1800000>;
1523 regulator-max-microvolt = <1800000>;
1524 regulator-enable-ramp-delay = <36>;
1525 regulator-ramp-delay = <100000>;
1526 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1527 maxim,active-fps-power-up-slot = <0>;
1528 maxim,active-fps-power-down-slot = <7>;
1529 };
1530
1531 pp1050_avdd: ldo7 {
1532 regulator-name = "PP1050_AVDD";
1533 regulator-min-microvolt = <1050000>;
1534 regulator-max-microvolt = <1050000>;
1535 regulator-enable-ramp-delay = <24>;
1536 regulator-ramp-delay = <100000>;
1537 regulator-always-on;
1538 regulator-boot-on;
1539 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
1540 maxim,active-fps-power-up-slot = <3>;
1541 maxim,active-fps-power-down-slot = <4>;
1542 };
1543
1544 avddio_1v05: ldo8 {
1545 regulator-name = "AVDDIO_1V05";
1546 regulator-min-microvolt = <1050000>;
1547 regulator-max-microvolt = <1050000>;
1548 regulator-enable-ramp-delay = <22>;
1549 regulator-ramp-delay = <100000>;
1550 regulator-boot-on;
1551 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1552 maxim,active-fps-power-up-slot = <0>;
1553 maxim,active-fps-power-down-slot = <7>;
1554 };
1555 };
1556 };
1557 };
1558
1330 pmc@7000e400 { 1559 pmc@7000e400 {
1331 nvidia,invert-interrupt; 1560 nvidia,invert-interrupt;
1332 nvidia,suspend-mode = <0>; 1561 nvidia,suspend-mode = <0>;
@@ -1421,4 +1650,89 @@
1421 compatible = "arm,psci-1.0"; 1650 compatible = "arm,psci-1.0";
1422 method = "smc"; 1651 method = "smc";
1423 }; 1652 };
1653
1654 regulators {
1655 compatible = "simple-bus";
1656 device_type = "fixed-regulators";
1657 #address-cells = <1>;
1658 #size-cells = <0>;
1659
1660 ppvar_sys: regulator@0 {
1661 compatible = "regulator-fixed";
1662 reg = <0>;
1663 regulator-name = "PPVAR_SYS";
1664 regulator-min-microvolt = <4400000>;
1665 regulator-max-microvolt = <4400000>;
1666 regulator-always-on;
1667 };
1668
1669 pplcd_vdd: regulator@1 {
1670 compatible = "regulator-fixed";
1671 reg = <1>;
1672 regulator-name = "PPLCD_VDD";
1673 regulator-min-microvolt = <4400000>;
1674 regulator-max-microvolt = <4400000>;
1675 gpio = <&gpio TEGRA_GPIO(V, 4) 0>;
1676 enable-active-high;
1677 regulator-boot-on;
1678 };
1679
1680 pp3000_always: regulator@2 {
1681 compatible = "regulator-fixed";
1682 reg = <2>;
1683 regulator-name = "PP3000_ALWAYS";
1684 regulator-min-microvolt = <3000000>;
1685 regulator-max-microvolt = <3000000>;
1686 regulator-always-on;
1687 };
1688
1689 pp3300: regulator@3 {
1690 compatible = "regulator-fixed";
1691 reg = <3>;
1692 regulator-name = "PP3300";
1693 regulator-min-microvolt = <3300000>;
1694 regulator-max-microvolt = <3300000>;
1695 regulator-boot-on;
1696 regulator-always-on;
1697 enable-active-high;
1698 };
1699
1700 pp5000: regulator@4 {
1701 compatible = "regulator-fixed";
1702 reg = <4>;
1703 regulator-name = "PP5000";
1704 regulator-min-microvolt = <5000000>;
1705 regulator-max-microvolt = <5000000>;
1706 regulator-always-on;
1707 };
1708
1709 pp1800_lcdio: regulator@5 {
1710 compatible = "regulator-fixed";
1711 reg = <5>;
1712 regulator-name = "PP1800_LCDIO";
1713 regulator-min-microvolt = <1800000>;
1714 regulator-max-microvolt = <1800000>;
1715 gpio = <&gpio TEGRA_GPIO(V, 3) 0>;
1716 enable-active-high;
1717 regulator-boot-on;
1718 };
1719
1720 pp1800_cam: regulator@6 {
1721 compatible = "regulator-fixed";
1722 reg= <6>;
1723 regulator-name = "PP1800_CAM";
1724 regulator-min-microvolt = <1800000>;
1725 regulator-max-microvolt = <1800000>;
1726 gpio = <&gpio TEGRA_GPIO(K, 3) 0>;
1727 enable-active-high;
1728 };
1729
1730 usbc_vbus: regulator@7 {
1731 compatible = "regulator-fixed";
1732 reg = <7>;
1733 regulator-name = "USBC_VBUS";
1734 regulator-min-microvolt = <5000000>;
1735 regulator-max-microvolt = <5000000>;
1736 };
1737 };
1424}; 1738};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 76fe31faa1a5..c4cfdcf60d26 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -35,6 +35,26 @@
35 resets = <&tegra_car 207>; 35 resets = <&tegra_car 207>;
36 reset-names = "dpaux"; 36 reset-names = "dpaux";
37 status = "disabled"; 37 status = "disabled";
38
39 state_dpaux1_aux: pinmux-aux {
40 groups = "dpaux-io";
41 function = "aux";
42 };
43
44 state_dpaux1_i2c: pinmux-i2c {
45 groups = "dpaux-io";
46 function = "i2c";
47 };
48
49 state_dpaux1_off: pinmux-off {
50 groups = "dpaux-io";
51 function = "off";
52 };
53
54 i2c-bus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57 };
38 }; 58 };
39 59
40 vi@54080000 { 60 vi@54080000 {
@@ -154,6 +174,10 @@
154 clock-names = "sor", "parent", "dp", "safe"; 174 clock-names = "sor", "parent", "dp", "safe";
155 resets = <&tegra_car 182>; 175 resets = <&tegra_car 182>;
156 reset-names = "sor"; 176 reset-names = "sor";
177 pinctrl-0 = <&state_dpaux_aux>;
178 pinctrl-1 = <&state_dpaux_i2c>;
179 pinctrl-2 = <&state_dpaux_off>;
180 pinctrl-names = "aux", "i2c", "off";
157 status = "disabled"; 181 status = "disabled";
158 }; 182 };
159 183
@@ -162,12 +186,17 @@
162 reg = <0x0 0x54580000 0x0 0x00040000>; 186 reg = <0x0 0x54580000 0x0 0x00040000>;
163 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 187 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 188 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
189 <&tegra_car TEGRA210_CLK_SOR1_SRC>,
165 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 190 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
166 <&tegra_car TEGRA210_CLK_PLL_DP>, 191 <&tegra_car TEGRA210_CLK_PLL_DP>,
167 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 192 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
168 clock-names = "sor", "parent", "dp", "safe"; 193 clock-names = "sor", "source", "parent", "dp", "safe";
169 resets = <&tegra_car 183>; 194 resets = <&tegra_car 183>;
170 reset-names = "sor"; 195 reset-names = "sor";
196 pinctrl-0 = <&state_dpaux1_aux>;
197 pinctrl-1 = <&state_dpaux1_i2c>;
198 pinctrl-2 = <&state_dpaux1_off>;
199 pinctrl-names = "aux", "i2c", "off";
171 status = "disabled"; 200 status = "disabled";
172 }; 201 };
173 202
@@ -181,6 +210,26 @@
181 resets = <&tegra_car 181>; 210 resets = <&tegra_car 181>;
182 reset-names = "dpaux"; 211 reset-names = "dpaux";
183 status = "disabled"; 212 status = "disabled";
213
214 state_dpaux_aux: pinmux-aux {
215 groups = "dpaux-io";
216 function = "aux";
217 };
218
219 state_dpaux_i2c: pinmux-i2c {
220 groups = "dpaux-io";
221 function = "i2c";
222 };
223
224 state_dpaux_off: pinmux-off {
225 groups = "dpaux-io";
226 function = "off";
227 };
228
229 i2c-bus {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 };
184 }; 233 };
185 234
186 isp@54600000 { 235 isp@54600000 {
@@ -478,6 +527,9 @@
478 reset-names = "i2c"; 527 reset-names = "i2c";
479 dmas = <&apbdma 26>, <&apbdma 26>; 528 dmas = <&apbdma 26>, <&apbdma 26>;
480 dma-names = "rx", "tx"; 529 dma-names = "rx", "tx";
530 pinctrl-0 = <&state_dpaux1_i2c>;
531 pinctrl-1 = <&state_dpaux1_off>;
532 pinctrl-names = "default", "idle";
481 status = "disabled"; 533 status = "disabled";
482 }; 534 };
483 535
@@ -508,6 +560,9 @@
508 reset-names = "i2c"; 560 reset-names = "i2c";
509 dmas = <&apbdma 30>, <&apbdma 30>; 561 dmas = <&apbdma 30>, <&apbdma 30>;
510 dma-names = "rx", "tx"; 562 dma-names = "rx", "tx";
563 pinctrl-0 = <&state_dpaux_i2c>;
564 pinctrl-1 = <&state_dpaux_off>;
565 pinctrl-names = "default", "idle";
511 status = "disabled"; 566 status = "disabled";
512 }; 567 };
513 568
@@ -584,6 +639,39 @@
584 reg = <0x0 0x7000e400 0x0 0x400>; 639 reg = <0x0 0x7000e400 0x0 0x400>;
585 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 640 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
586 clock-names = "pclk", "clk32k_in"; 641 clock-names = "pclk", "clk32k_in";
642
643 powergates {
644 pd_audio: aud {
645 clocks = <&tegra_car TEGRA210_CLK_APE>,
646 <&tegra_car TEGRA210_CLK_APB2APE>;
647 resets = <&tegra_car 198>;
648 #power-domain-cells = <0>;
649 };
650
651 pd_xusbss: xusba {
652 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
653 clock-names = "xusb-ss";
654 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
655 reset-names = "xusb-ss";
656 #power-domain-cells = <0>;
657 };
658
659 pd_xusbdev: xusbb {
660 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
661 clock-names = "xusb-dev";
662 resets = <&tegra_car 95>;
663 reset-names = "xusb-dev";
664 #power-domain-cells = <0>;
665 };
666
667 pd_xusbhost: xusbc {
668 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
669 clock-names = "xusb-host";
670 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
671 reset-names = "xusb-host";
672 #power-domain-cells = <0>;
673 };
674 };
587 }; 675 };
588 676
589 fuse@7000f800 { 677 fuse@7000f800 {
@@ -621,6 +709,196 @@
621 status = "disabled"; 709 status = "disabled";
622 }; 710 };
623 711
712 usb@70090000 {
713 compatible = "nvidia,tegra210-xusb";
714 reg = <0x0 0x70090000 0x0 0x8000>,
715 <0x0 0x70098000 0x0 0x1000>,
716 <0x0 0x70099000 0x0 0x1000>;
717 reg-names = "hcd", "fpci", "ipfs";
718
719 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
721
722 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
723 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
724 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
725 <&tegra_car TEGRA210_CLK_XUSB_SS>,
726 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
727 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
728 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
729 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
730 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
731 <&tegra_car TEGRA210_CLK_CLK_M>,
732 <&tegra_car TEGRA210_CLK_PLL_E>;
733 clock-names = "xusb_host", "xusb_host_src",
734 "xusb_falcon_src", "xusb_ss",
735 "xusb_ss_div2", "xusb_ss_src",
736 "xusb_hs_src", "xusb_fs_src",
737 "pll_u_480m", "clk_m", "pll_e";
738 resets = <&tegra_car 89>, <&tegra_car 156>,
739 <&tegra_car 143>;
740 reset-names = "xusb_host", "xusb_ss", "xusb_src";
741
742 nvidia,xusb-padctl = <&padctl>;
743
744 status = "disabled";
745 };
746
747 padctl: padctl@7009f000 {
748 compatible = "nvidia,tegra210-xusb-padctl";
749 reg = <0x0 0x7009f000 0x0 0x1000>;
750 resets = <&tegra_car 142>;
751 reset-names = "padctl";
752
753 status = "disabled";
754
755 pads {
756 usb2 {
757 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
758 clock-names = "trk";
759 status = "disabled";
760
761 lanes {
762 usb2-0 {
763 status = "disabled";
764 #phy-cells = <0>;
765 };
766
767 usb2-1 {
768 status = "disabled";
769 #phy-cells = <0>;
770 };
771
772 usb2-2 {
773 status = "disabled";
774 #phy-cells = <0>;
775 };
776
777 usb2-3 {
778 status = "disabled";
779 #phy-cells = <0>;
780 };
781 };
782 };
783
784 hsic {
785 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
786 clock-names = "trk";
787 status = "disabled";
788
789 lanes {
790 hsic-0 {
791 status = "disabled";
792 #phy-cells = <0>;
793 };
794
795 hsic-1 {
796 status = "disabled";
797 #phy-cells = <0>;
798 };
799 };
800 };
801
802 pcie {
803 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
804 clock-names = "pll";
805 resets = <&tegra_car 205>;
806 reset-names = "phy";
807 status = "disabled";
808
809 lanes {
810 pcie-0 {
811 status = "disabled";
812 #phy-cells = <0>;
813 };
814
815 pcie-1 {
816 status = "disabled";
817 #phy-cells = <0>;
818 };
819
820 pcie-2 {
821 status = "disabled";
822 #phy-cells = <0>;
823 };
824
825 pcie-3 {
826 status = "disabled";
827 #phy-cells = <0>;
828 };
829
830 pcie-4 {
831 status = "disabled";
832 #phy-cells = <0>;
833 };
834
835 pcie-5 {
836 status = "disabled";
837 #phy-cells = <0>;
838 };
839
840 pcie-6 {
841 status = "disabled";
842 #phy-cells = <0>;
843 };
844 };
845 };
846
847 sata {
848 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
849 clock-names = "pll";
850 resets = <&tegra_car 204>;
851 reset-names = "phy";
852 status = "disabled";
853
854 lanes {
855 sata-0 {
856 status = "disabled";
857 #phy-cells = <0>;
858 };
859 };
860 };
861 };
862
863 ports {
864 usb2-0 {
865 status = "disabled";
866 };
867
868 usb2-1 {
869 status = "disabled";
870 };
871
872 usb2-2 {
873 status = "disabled";
874 };
875
876 usb2-3 {
877 status = "disabled";
878 };
879
880 hsic-0 {
881 status = "disabled";
882 };
883
884 usb3-0 {
885 status = "disabled";
886 };
887
888 usb3-1 {
889 status = "disabled";
890 };
891
892 usb3-2 {
893 status = "disabled";
894 };
895
896 usb3-3 {
897 status = "disabled";
898 };
899 };
900 };
901
624 sdhci@700b0000 { 902 sdhci@700b0000 {
625 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 903 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
626 reg = <0x0 0x700b0000 0x0 0x200>; 904 reg = <0x0 0x700b0000 0x0 0x200>;
@@ -673,6 +951,18 @@
673 #nvidia,mipi-calibrate-cells = <1>; 951 #nvidia,mipi-calibrate-cells = <1>;
674 }; 952 };
675 953
954 aconnect@702c0000 {
955 compatible = "nvidia,tegra210-aconnect";
956 clocks = <&tegra_car TEGRA210_CLK_APE>,
957 <&tegra_car TEGRA210_CLK_APB2APE>;
958 clock-names = "ape", "apb2ape";
959 power-domains = <&pd_audio>;
960 #address-cells = <1>;
961 #size-cells = <1>;
962 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
963 status = "disabled";
964 };
965
676 spi@70410000 { 966 spi@70410000 {
677 compatible = "nvidia,tegra210-qspi"; 967 compatible = "nvidia,tegra210-qspi";
678 reg = <0x0 0x70410000 0x0 0x1000>; 968 reg = <0x0 0x70410000 0x0 0x1000>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-25 18:00:08 -0400