diff options
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-exynos-arm.c | 56 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 14 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-s3c24xx.c | 28 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-s3c64xx.c | 7 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-samsung.c | 61 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-samsung.h | 40 |
6 files changed, 154 insertions, 52 deletions
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c index c32399faff57..90c274490181 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c | |||
| @@ -124,7 +124,7 @@ static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = { | |||
| 124 | EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c), | 124 | EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c), |
| 125 | }; | 125 | }; |
| 126 | 126 | ||
| 127 | const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = { | 127 | static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = { |
| 128 | { | 128 | { |
| 129 | /* pin-controller instance 0 data */ | 129 | /* pin-controller instance 0 data */ |
| 130 | .pin_banks = s5pv210_pin_bank, | 130 | .pin_banks = s5pv210_pin_bank, |
| @@ -137,6 +137,11 @@ const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = { | |||
| 137 | }, | 137 | }, |
| 138 | }; | 138 | }; |
| 139 | 139 | ||
| 140 | const struct samsung_pinctrl_of_match_data s5pv210_of_data __initconst = { | ||
| 141 | .ctrl = s5pv210_pin_ctrl, | ||
| 142 | .num_ctrl = ARRAY_SIZE(s5pv210_pin_ctrl), | ||
| 143 | }; | ||
| 144 | |||
| 140 | /* Pad retention control code for accessing PMU regmap */ | 145 | /* Pad retention control code for accessing PMU regmap */ |
| 141 | static atomic_t exynos_shared_retention_refcnt; | 146 | static atomic_t exynos_shared_retention_refcnt; |
| 142 | 147 | ||
| @@ -199,7 +204,7 @@ static const struct samsung_retention_data exynos3250_retention_data __initconst | |||
| 199 | * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes | 204 | * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes |
| 200 | * two gpio/pin-mux/pinconfig controllers. | 205 | * two gpio/pin-mux/pinconfig controllers. |
| 201 | */ | 206 | */ |
| 202 | const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = { | 207 | static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = { |
| 203 | { | 208 | { |
| 204 | /* pin-controller instance 0 data */ | 209 | /* pin-controller instance 0 data */ |
| 205 | .pin_banks = exynos3250_pin_banks0, | 210 | .pin_banks = exynos3250_pin_banks0, |
| @@ -220,6 +225,11 @@ const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = { | |||
| 220 | }, | 225 | }, |
| 221 | }; | 226 | }; |
| 222 | 227 | ||
| 228 | const struct samsung_pinctrl_of_match_data exynos3250_of_data __initconst = { | ||
| 229 | .ctrl = exynos3250_pin_ctrl, | ||
| 230 | .num_ctrl = ARRAY_SIZE(exynos3250_pin_ctrl), | ||
| 231 | }; | ||
| 232 | |||
| 223 | /* pin banks of exynos4210 pin-controller 0 */ | 233 | /* pin banks of exynos4210 pin-controller 0 */ |
| 224 | static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = { | 234 | static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = { |
| 225 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), | 235 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), |
| @@ -303,7 +313,7 @@ static const struct samsung_retention_data exynos4_audio_retention_data __initco | |||
| 303 | * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes | 313 | * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes |
| 304 | * three gpio/pin-mux/pinconfig controllers. | 314 | * three gpio/pin-mux/pinconfig controllers. |
| 305 | */ | 315 | */ |
| 306 | const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = { | 316 | static const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = { |
| 307 | { | 317 | { |
| 308 | /* pin-controller instance 0 data */ | 318 | /* pin-controller instance 0 data */ |
| 309 | .pin_banks = exynos4210_pin_banks0, | 319 | .pin_banks = exynos4210_pin_banks0, |
| @@ -329,6 +339,11 @@ const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = { | |||
| 329 | }, | 339 | }, |
| 330 | }; | 340 | }; |
| 331 | 341 | ||
| 342 | const struct samsung_pinctrl_of_match_data exynos4210_of_data __initconst = { | ||
| 343 | .ctrl = exynos4210_pin_ctrl, | ||
| 344 | .num_ctrl = ARRAY_SIZE(exynos4210_pin_ctrl), | ||
| 345 | }; | ||
| 346 | |||
| 332 | /* pin banks of exynos4x12 pin-controller 0 */ | 347 | /* pin banks of exynos4x12 pin-controller 0 */ |
| 333 | static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = { | 348 | static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = { |
| 334 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), | 349 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), |
| @@ -391,7 +406,7 @@ static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = | |||
| 391 | * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes | 406 | * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes |
| 392 | * four gpio/pin-mux/pinconfig controllers. | 407 | * four gpio/pin-mux/pinconfig controllers. |
| 393 | */ | 408 | */ |
| 394 | const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { | 409 | static const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { |
| 395 | { | 410 | { |
| 396 | /* pin-controller instance 0 data */ | 411 | /* pin-controller instance 0 data */ |
| 397 | .pin_banks = exynos4x12_pin_banks0, | 412 | .pin_banks = exynos4x12_pin_banks0, |
| @@ -427,6 +442,11 @@ const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { | |||
| 427 | }, | 442 | }, |
| 428 | }; | 443 | }; |
| 429 | 444 | ||
| 445 | const struct samsung_pinctrl_of_match_data exynos4x12_of_data __initconst = { | ||
| 446 | .ctrl = exynos4x12_pin_ctrl, | ||
| 447 | .num_ctrl = ARRAY_SIZE(exynos4x12_pin_ctrl), | ||
| 448 | }; | ||
| 449 | |||
| 430 | /* pin banks of exynos5250 pin-controller 0 */ | 450 | /* pin banks of exynos5250 pin-controller 0 */ |
| 431 | static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = { | 451 | static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = { |
| 432 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), | 452 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), |
| @@ -487,7 +507,7 @@ static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = | |||
| 487 | * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes | 507 | * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes |
| 488 | * four gpio/pin-mux/pinconfig controllers. | 508 | * four gpio/pin-mux/pinconfig controllers. |
| 489 | */ | 509 | */ |
| 490 | const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = { | 510 | static const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = { |
| 491 | { | 511 | { |
| 492 | /* pin-controller instance 0 data */ | 512 | /* pin-controller instance 0 data */ |
| 493 | .pin_banks = exynos5250_pin_banks0, | 513 | .pin_banks = exynos5250_pin_banks0, |
| @@ -523,6 +543,11 @@ const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = { | |||
| 523 | }, | 543 | }, |
| 524 | }; | 544 | }; |
| 525 | 545 | ||
| 546 | const struct samsung_pinctrl_of_match_data exynos5250_of_data __initconst = { | ||
| 547 | .ctrl = exynos5250_pin_ctrl, | ||
| 548 | .num_ctrl = ARRAY_SIZE(exynos5250_pin_ctrl), | ||
| 549 | }; | ||
| 550 | |||
| 526 | /* pin banks of exynos5260 pin-controller 0 */ | 551 | /* pin banks of exynos5260 pin-controller 0 */ |
| 527 | static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = { | 552 | static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = { |
| 528 | EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), | 553 | EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), |
| @@ -567,7 +592,7 @@ static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = | |||
| 567 | * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes | 592 | * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes |
| 568 | * three gpio/pin-mux/pinconfig controllers. | 593 | * three gpio/pin-mux/pinconfig controllers. |
| 569 | */ | 594 | */ |
| 570 | const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { | 595 | static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { |
| 571 | { | 596 | { |
| 572 | /* pin-controller instance 0 data */ | 597 | /* pin-controller instance 0 data */ |
| 573 | .pin_banks = exynos5260_pin_banks0, | 598 | .pin_banks = exynos5260_pin_banks0, |
| @@ -587,6 +612,11 @@ const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { | |||
| 587 | }, | 612 | }, |
| 588 | }; | 613 | }; |
| 589 | 614 | ||
| 615 | const struct samsung_pinctrl_of_match_data exynos5260_of_data __initconst = { | ||
| 616 | .ctrl = exynos5260_pin_ctrl, | ||
| 617 | .num_ctrl = ARRAY_SIZE(exynos5260_pin_ctrl), | ||
| 618 | }; | ||
| 619 | |||
| 590 | /* pin banks of exynos5410 pin-controller 0 */ | 620 | /* pin banks of exynos5410 pin-controller 0 */ |
| 591 | static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = { | 621 | static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = { |
| 592 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), | 622 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), |
| @@ -657,7 +687,7 @@ static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = | |||
| 657 | * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes | 687 | * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes |
| 658 | * four gpio/pin-mux/pinconfig controllers. | 688 | * four gpio/pin-mux/pinconfig controllers. |
| 659 | */ | 689 | */ |
| 660 | const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = { | 690 | static const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = { |
| 661 | { | 691 | { |
| 662 | /* pin-controller instance 0 data */ | 692 | /* pin-controller instance 0 data */ |
| 663 | .pin_banks = exynos5410_pin_banks0, | 693 | .pin_banks = exynos5410_pin_banks0, |
| @@ -690,6 +720,11 @@ const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = { | |||
| 690 | }, | 720 | }, |
| 691 | }; | 721 | }; |
| 692 | 722 | ||
| 723 | const struct samsung_pinctrl_of_match_data exynos5410_of_data __initconst = { | ||
| 724 | .ctrl = exynos5410_pin_ctrl, | ||
| 725 | .num_ctrl = ARRAY_SIZE(exynos5410_pin_ctrl), | ||
| 726 | }; | ||
| 727 | |||
| 693 | /* pin banks of exynos5420 pin-controller 0 */ | 728 | /* pin banks of exynos5420 pin-controller 0 */ |
| 694 | static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = { | 729 | static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = { |
| 695 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), | 730 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), |
| @@ -774,7 +809,7 @@ static const struct samsung_retention_data exynos5420_retention_data __initconst | |||
| 774 | * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes | 809 | * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes |
| 775 | * four gpio/pin-mux/pinconfig controllers. | 810 | * four gpio/pin-mux/pinconfig controllers. |
| 776 | */ | 811 | */ |
| 777 | const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = { | 812 | static const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = { |
| 778 | { | 813 | { |
| 779 | /* pin-controller instance 0 data */ | 814 | /* pin-controller instance 0 data */ |
| 780 | .pin_banks = exynos5420_pin_banks0, | 815 | .pin_banks = exynos5420_pin_banks0, |
| @@ -808,3 +843,8 @@ const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = { | |||
| 808 | .retention_data = &exynos4_audio_retention_data, | 843 | .retention_data = &exynos4_audio_retention_data, |
| 809 | }, | 844 | }, |
| 810 | }; | 845 | }; |
| 846 | |||
| 847 | const struct samsung_pinctrl_of_match_data exynos5420_of_data __initconst = { | ||
| 848 | .ctrl = exynos5420_pin_ctrl, | ||
| 849 | .num_ctrl = ARRAY_SIZE(exynos5420_pin_ctrl), | ||
| 850 | }; | ||
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index fc8f7833bec0..71c9d1d9f345 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | |||
| @@ -175,7 +175,7 @@ static const struct samsung_retention_data exynos5433_fsys_retention_data __init | |||
| 175 | * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes | 175 | * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes |
| 176 | * ten gpio/pin-mux/pinconfig controllers. | 176 | * ten gpio/pin-mux/pinconfig controllers. |
| 177 | */ | 177 | */ |
| 178 | const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = { | 178 | static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = { |
| 179 | { | 179 | { |
| 180 | /* pin-controller instance 0 data */ | 180 | /* pin-controller instance 0 data */ |
| 181 | .pin_banks = exynos5433_pin_banks0, | 181 | .pin_banks = exynos5433_pin_banks0, |
| @@ -260,6 +260,11 @@ const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = { | |||
| 260 | }, | 260 | }, |
| 261 | }; | 261 | }; |
| 262 | 262 | ||
| 263 | const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = { | ||
| 264 | .ctrl = exynos5433_pin_ctrl, | ||
| 265 | .num_ctrl = ARRAY_SIZE(exynos5433_pin_ctrl), | ||
| 266 | }; | ||
| 267 | |||
| 263 | /* pin banks of exynos7 pin-controller - ALIVE */ | 268 | /* pin banks of exynos7 pin-controller - ALIVE */ |
| 264 | static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { | 269 | static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { |
| 265 | EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), | 270 | EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), |
| @@ -339,7 +344,7 @@ static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = { | |||
| 339 | EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), | 344 | EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), |
| 340 | }; | 345 | }; |
| 341 | 346 | ||
| 342 | const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { | 347 | static const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { |
| 343 | { | 348 | { |
| 344 | /* pin-controller instance 0 Alive data */ | 349 | /* pin-controller instance 0 Alive data */ |
| 345 | .pin_banks = exynos7_pin_banks0, | 350 | .pin_banks = exynos7_pin_banks0, |
| @@ -392,3 +397,8 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { | |||
| 392 | .eint_gpio_init = exynos_eint_gpio_init, | 397 | .eint_gpio_init = exynos_eint_gpio_init, |
| 393 | }, | 398 | }, |
| 394 | }; | 399 | }; |
| 400 | |||
| 401 | const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { | ||
| 402 | .ctrl = exynos7_pin_ctrl, | ||
| 403 | .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), | ||
| 404 | }; | ||
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c index 10187cb0e9b9..7e824e4d20f4 100644 --- a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c +++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c | |||
| @@ -565,7 +565,7 @@ static const struct samsung_pin_bank_data s3c2412_pin_banks[] __initconst = { | |||
| 565 | PIN_BANK_2BIT(13, 0x080, "gpj"), | 565 | PIN_BANK_2BIT(13, 0x080, "gpj"), |
| 566 | }; | 566 | }; |
| 567 | 567 | ||
| 568 | const struct samsung_pin_ctrl s3c2412_pin_ctrl[] __initconst = { | 568 | static const struct samsung_pin_ctrl s3c2412_pin_ctrl[] __initconst = { |
| 569 | { | 569 | { |
| 570 | .pin_banks = s3c2412_pin_banks, | 570 | .pin_banks = s3c2412_pin_banks, |
| 571 | .nr_banks = ARRAY_SIZE(s3c2412_pin_banks), | 571 | .nr_banks = ARRAY_SIZE(s3c2412_pin_banks), |
| @@ -573,6 +573,11 @@ const struct samsung_pin_ctrl s3c2412_pin_ctrl[] __initconst = { | |||
| 573 | }, | 573 | }, |
| 574 | }; | 574 | }; |
| 575 | 575 | ||
| 576 | const struct samsung_pinctrl_of_match_data s3c2412_of_data __initconst = { | ||
| 577 | .ctrl = s3c2412_pin_ctrl, | ||
| 578 | .num_ctrl = ARRAY_SIZE(s3c2412_pin_ctrl), | ||
| 579 | }; | ||
| 580 | |||
| 576 | static const struct samsung_pin_bank_data s3c2416_pin_banks[] __initconst = { | 581 | static const struct samsung_pin_bank_data s3c2416_pin_banks[] __initconst = { |
| 577 | PIN_BANK_A(27, 0x000, "gpa"), | 582 | PIN_BANK_A(27, 0x000, "gpa"), |
| 578 | PIN_BANK_2BIT(11, 0x010, "gpb"), | 583 | PIN_BANK_2BIT(11, 0x010, "gpb"), |
| @@ -587,7 +592,7 @@ static const struct samsung_pin_bank_data s3c2416_pin_banks[] __initconst = { | |||
| 587 | PIN_BANK_2BIT(2, 0x100, "gpm"), | 592 | PIN_BANK_2BIT(2, 0x100, "gpm"), |
| 588 | }; | 593 | }; |
| 589 | 594 | ||
| 590 | const struct samsung_pin_ctrl s3c2416_pin_ctrl[] __initconst = { | 595 | static const struct samsung_pin_ctrl s3c2416_pin_ctrl[] __initconst = { |
| 591 | { | 596 | { |
| 592 | .pin_banks = s3c2416_pin_banks, | 597 | .pin_banks = s3c2416_pin_banks, |
| 593 | .nr_banks = ARRAY_SIZE(s3c2416_pin_banks), | 598 | .nr_banks = ARRAY_SIZE(s3c2416_pin_banks), |
| @@ -595,6 +600,11 @@ const struct samsung_pin_ctrl s3c2416_pin_ctrl[] __initconst = { | |||
| 595 | }, | 600 | }, |
| 596 | }; | 601 | }; |
| 597 | 602 | ||
| 603 | const struct samsung_pinctrl_of_match_data s3c2416_of_data __initconst = { | ||
| 604 | .ctrl = s3c2416_pin_ctrl, | ||
| 605 | .num_ctrl = ARRAY_SIZE(s3c2416_pin_ctrl), | ||
| 606 | }; | ||
| 607 | |||
| 598 | static const struct samsung_pin_bank_data s3c2440_pin_banks[] __initconst = { | 608 | static const struct samsung_pin_bank_data s3c2440_pin_banks[] __initconst = { |
| 599 | PIN_BANK_A(25, 0x000, "gpa"), | 609 | PIN_BANK_A(25, 0x000, "gpa"), |
| 600 | PIN_BANK_2BIT(11, 0x010, "gpb"), | 610 | PIN_BANK_2BIT(11, 0x010, "gpb"), |
| @@ -607,7 +617,7 @@ static const struct samsung_pin_bank_data s3c2440_pin_banks[] __initconst = { | |||
| 607 | PIN_BANK_2BIT(13, 0x0d0, "gpj"), | 617 | PIN_BANK_2BIT(13, 0x0d0, "gpj"), |
| 608 | }; | 618 | }; |
| 609 | 619 | ||
| 610 | const struct samsung_pin_ctrl s3c2440_pin_ctrl[] __initconst = { | 620 | static const struct samsung_pin_ctrl s3c2440_pin_ctrl[] __initconst = { |
| 611 | { | 621 | { |
| 612 | .pin_banks = s3c2440_pin_banks, | 622 | .pin_banks = s3c2440_pin_banks, |
| 613 | .nr_banks = ARRAY_SIZE(s3c2440_pin_banks), | 623 | .nr_banks = ARRAY_SIZE(s3c2440_pin_banks), |
| @@ -615,6 +625,11 @@ const struct samsung_pin_ctrl s3c2440_pin_ctrl[] __initconst = { | |||
| 615 | }, | 625 | }, |
| 616 | }; | 626 | }; |
| 617 | 627 | ||
| 628 | const struct samsung_pinctrl_of_match_data s3c2440_of_data __initconst = { | ||
| 629 | .ctrl = s3c2440_pin_ctrl, | ||
| 630 | .num_ctrl = ARRAY_SIZE(s3c2440_pin_ctrl), | ||
| 631 | }; | ||
| 632 | |||
| 618 | static const struct samsung_pin_bank_data s3c2450_pin_banks[] __initconst = { | 633 | static const struct samsung_pin_bank_data s3c2450_pin_banks[] __initconst = { |
| 619 | PIN_BANK_A(28, 0x000, "gpa"), | 634 | PIN_BANK_A(28, 0x000, "gpa"), |
| 620 | PIN_BANK_2BIT(11, 0x010, "gpb"), | 635 | PIN_BANK_2BIT(11, 0x010, "gpb"), |
| @@ -630,10 +645,15 @@ static const struct samsung_pin_bank_data s3c2450_pin_banks[] __initconst = { | |||
| 630 | PIN_BANK_2BIT(2, 0x100, "gpm"), | 645 | PIN_BANK_2BIT(2, 0x100, "gpm"), |
| 631 | }; | 646 | }; |
| 632 | 647 | ||
| 633 | const struct samsung_pin_ctrl s3c2450_pin_ctrl[] __initconst = { | 648 | static const struct samsung_pin_ctrl s3c2450_pin_ctrl[] __initconst = { |
| 634 | { | 649 | { |
| 635 | .pin_banks = s3c2450_pin_banks, | 650 | .pin_banks = s3c2450_pin_banks, |
| 636 | .nr_banks = ARRAY_SIZE(s3c2450_pin_banks), | 651 | .nr_banks = ARRAY_SIZE(s3c2450_pin_banks), |
| 637 | .eint_wkup_init = s3c24xx_eint_init, | 652 | .eint_wkup_init = s3c24xx_eint_init, |
| 638 | }, | 653 | }, |
| 639 | }; | 654 | }; |
| 655 | |||
| 656 | const struct samsung_pinctrl_of_match_data s3c2450_of_data __initconst = { | ||
| 657 | .ctrl = s3c2450_pin_ctrl, | ||
| 658 | .num_ctrl = ARRAY_SIZE(s3c2450_pin_ctrl), | ||
| 659 | }; | ||
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c index 679628ac4b31..288e6567ceb1 100644 --- a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c +++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c | |||
| @@ -789,7 +789,7 @@ static const struct samsung_pin_bank_data s3c64xx_pin_banks0[] __initconst = { | |||
| 789 | * Samsung pinctrl driver data for S3C64xx SoC. S3C64xx SoC includes | 789 | * Samsung pinctrl driver data for S3C64xx SoC. S3C64xx SoC includes |
| 790 | * one gpio/pin-mux/pinconfig controller. | 790 | * one gpio/pin-mux/pinconfig controller. |
| 791 | */ | 791 | */ |
| 792 | const struct samsung_pin_ctrl s3c64xx_pin_ctrl[] __initconst = { | 792 | static const struct samsung_pin_ctrl s3c64xx_pin_ctrl[] __initconst = { |
| 793 | { | 793 | { |
| 794 | /* pin-controller instance 1 data */ | 794 | /* pin-controller instance 1 data */ |
| 795 | .pin_banks = s3c64xx_pin_banks0, | 795 | .pin_banks = s3c64xx_pin_banks0, |
| @@ -798,3 +798,8 @@ const struct samsung_pin_ctrl s3c64xx_pin_ctrl[] __initconst = { | |||
| 798 | .eint_wkup_init = s3c64xx_eint_eint0_init, | 798 | .eint_wkup_init = s3c64xx_eint_eint0_init, |
| 799 | }, | 799 | }, |
| 800 | }; | 800 | }; |
| 801 | |||
| 802 | const struct samsung_pinctrl_of_match_data s3c64xx_of_data __initconst = { | ||
| 803 | .ctrl = s3c64xx_pin_ctrl, | ||
| 804 | .num_ctrl = ARRAY_SIZE(s3c64xx_pin_ctrl), | ||
| 805 | }; | ||
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index da58e4554137..336e88d7bdb9 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c | |||
| @@ -942,12 +942,33 @@ static int samsung_gpiolib_register(struct platform_device *pdev, | |||
| 942 | return 0; | 942 | return 0; |
| 943 | } | 943 | } |
| 944 | 944 | ||
| 945 | static const struct samsung_pin_ctrl * | ||
| 946 | samsung_pinctrl_get_soc_data_for_of_alias(struct platform_device *pdev) | ||
| 947 | { | ||
| 948 | struct device_node *node = pdev->dev.of_node; | ||
| 949 | const struct samsung_pinctrl_of_match_data *of_data; | ||
| 950 | int id; | ||
| 951 | |||
| 952 | id = of_alias_get_id(node, "pinctrl"); | ||
| 953 | if (id < 0) { | ||
| 954 | dev_err(&pdev->dev, "failed to get alias id\n"); | ||
| 955 | return NULL; | ||
| 956 | } | ||
| 957 | |||
| 958 | of_data = of_device_get_match_data(&pdev->dev); | ||
| 959 | if (id >= of_data->num_ctrl) { | ||
| 960 | dev_err(&pdev->dev, "invalid alias id %d\n", id); | ||
| 961 | return NULL; | ||
| 962 | } | ||
| 963 | |||
| 964 | return &(of_data->ctrl[id]); | ||
| 965 | } | ||
| 966 | |||
| 945 | /* retrieve the soc specific data */ | 967 | /* retrieve the soc specific data */ |
| 946 | static const struct samsung_pin_ctrl * | 968 | static const struct samsung_pin_ctrl * |
| 947 | samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, | 969 | samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, |
| 948 | struct platform_device *pdev) | 970 | struct platform_device *pdev) |
| 949 | { | 971 | { |
| 950 | int id; | ||
| 951 | struct device_node *node = pdev->dev.of_node; | 972 | struct device_node *node = pdev->dev.of_node; |
| 952 | struct device_node *np; | 973 | struct device_node *np; |
| 953 | const struct samsung_pin_bank_data *bdata; | 974 | const struct samsung_pin_bank_data *bdata; |
| @@ -957,13 +978,9 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, | |||
| 957 | void __iomem *virt_base[SAMSUNG_PINCTRL_NUM_RESOURCES]; | 978 | void __iomem *virt_base[SAMSUNG_PINCTRL_NUM_RESOURCES]; |
| 958 | unsigned int i; | 979 | unsigned int i; |
| 959 | 980 | ||
| 960 | id = of_alias_get_id(node, "pinctrl"); | 981 | ctrl = samsung_pinctrl_get_soc_data_for_of_alias(pdev); |
| 961 | if (id < 0) { | 982 | if (!ctrl) |
| 962 | dev_err(&pdev->dev, "failed to get alias id\n"); | ||
| 963 | return ERR_PTR(-ENOENT); | 983 | return ERR_PTR(-ENOENT); |
| 964 | } | ||
| 965 | ctrl = of_device_get_match_data(&pdev->dev); | ||
| 966 | ctrl += id; | ||
| 967 | 984 | ||
| 968 | d->suspend = ctrl->suspend; | 985 | d->suspend = ctrl->suspend; |
| 969 | d->resume = ctrl->resume; | 986 | d->resume = ctrl->resume; |
| @@ -1188,41 +1205,41 @@ static int __maybe_unused samsung_pinctrl_resume(struct device *dev) | |||
| 1188 | static const struct of_device_id samsung_pinctrl_dt_match[] = { | 1205 | static const struct of_device_id samsung_pinctrl_dt_match[] = { |
| 1189 | #ifdef CONFIG_PINCTRL_EXYNOS_ARM | 1206 | #ifdef CONFIG_PINCTRL_EXYNOS_ARM |
| 1190 | { .compatible = "samsung,exynos3250-pinctrl", | 1207 | { .compatible = "samsung,exynos3250-pinctrl", |
| 1191 | .data = exynos3250_pin_ctrl }, | 1208 | .data = &exynos3250_of_data }, |
| 1192 | { .compatible = "samsung,exynos4210-pinctrl", | 1209 | { .compatible = "samsung,exynos4210-pinctrl", |
| 1193 | .data = exynos4210_pin_ctrl }, | 1210 | .data = &exynos4210_of_data }, |
| 1194 | { .compatible = "samsung,exynos4x12-pinctrl", | 1211 | { .compatible = "samsung,exynos4x12-pinctrl", |
| 1195 | .data = exynos4x12_pin_ctrl }, | 1212 | .data = &exynos4x12_of_data }, |
| 1196 | { .compatible = "samsung,exynos5250-pinctrl", | 1213 | { .compatible = "samsung,exynos5250-pinctrl", |
| 1197 | .data = exynos5250_pin_ctrl }, | 1214 | .data = &exynos5250_of_data }, |
| 1198 | { .compatible = "samsung,exynos5260-pinctrl", | 1215 | { .compatible = "samsung,exynos5260-pinctrl", |
| 1199 | .data = exynos5260_pin_ctrl }, | 1216 | .data = &exynos5260_of_data }, |
| 1200 | { .compatible = "samsung,exynos5410-pinctrl", | 1217 | { .compatible = "samsung,exynos5410-pinctrl", |
| 1201 | .data = exynos5410_pin_ctrl }, | 1218 | .data = &exynos5410_of_data }, |
| 1202 | { .compatible = "samsung,exynos5420-pinctrl", | 1219 | { .compatible = "samsung,exynos5420-pinctrl", |
| 1203 | .data = exynos5420_pin_ctrl }, | 1220 | .data = &exynos5420_of_data }, |
| 1204 | { .compatible = "samsung,s5pv210-pinctrl", | 1221 | { .compatible = "samsung,s5pv210-pinctrl", |
| 1205 | .data = s5pv210_pin_ctrl }, | 1222 | .data = &s5pv210_of_data }, |
| 1206 | #endif | 1223 | #endif |
| 1207 | #ifdef CONFIG_PINCTRL_EXYNOS_ARM64 | 1224 | #ifdef CONFIG_PINCTRL_EXYNOS_ARM64 |
| 1208 | { .compatible = "samsung,exynos5433-pinctrl", | 1225 | { .compatible = "samsung,exynos5433-pinctrl", |
| 1209 | .data = exynos5433_pin_ctrl }, | 1226 | .data = &exynos5433_of_data }, |
| 1210 | { .compatible = "samsung,exynos7-pinctrl", | 1227 | { .compatible = "samsung,exynos7-pinctrl", |
| 1211 | .data = exynos7_pin_ctrl }, | 1228 | .data = &exynos7_of_data }, |
| 1212 | #endif | 1229 | #endif |
| 1213 | #ifdef CONFIG_PINCTRL_S3C64XX | 1230 | #ifdef CONFIG_PINCTRL_S3C64XX |
| 1214 | { .compatible = "samsung,s3c64xx-pinctrl", | 1231 | { .compatible = "samsung,s3c64xx-pinctrl", |
| 1215 | .data = s3c64xx_pin_ctrl }, | 1232 | .data = &s3c64xx_of_data }, |
| 1216 | #endif | 1233 | #endif |
| 1217 | #ifdef CONFIG_PINCTRL_S3C24XX | 1234 | #ifdef CONFIG_PINCTRL_S3C24XX |
| 1218 | { .compatible = "samsung,s3c2412-pinctrl", | 1235 | { .compatible = "samsung,s3c2412-pinctrl", |
| 1219 | .data = s3c2412_pin_ctrl }, | 1236 | .data = &s3c2412_of_data }, |
| 1220 | { .compatible = "samsung,s3c2416-pinctrl", | 1237 | { .compatible = "samsung,s3c2416-pinctrl", |
| 1221 | .data = s3c2416_pin_ctrl }, | 1238 | .data = &s3c2416_of_data }, |
| 1222 | { .compatible = "samsung,s3c2440-pinctrl", | 1239 | { .compatible = "samsung,s3c2440-pinctrl", |
| 1223 | .data = s3c2440_pin_ctrl }, | 1240 | .data = &s3c2440_of_data }, |
| 1224 | { .compatible = "samsung,s3c2450-pinctrl", | 1241 | { .compatible = "samsung,s3c2450-pinctrl", |
| 1225 | .data = s3c2450_pin_ctrl }, | 1242 | .data = &s3c2450_of_data }, |
| 1226 | #endif | 1243 | #endif |
| 1227 | {}, | 1244 | {}, |
| 1228 | }; | 1245 | }; |
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index e204f609823b..f0cda9424dfe 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h | |||
| @@ -282,6 +282,16 @@ struct samsung_pinctrl_drv_data { | |||
| 282 | }; | 282 | }; |
| 283 | 283 | ||
| 284 | /** | 284 | /** |
| 285 | * struct samsung_pinctrl_of_match_data: OF match device specific configuration data. | ||
| 286 | * @ctrl: array of pin controller data. | ||
| 287 | * @num_ctrl: size of array @ctrl. | ||
| 288 | */ | ||
| 289 | struct samsung_pinctrl_of_match_data { | ||
| 290 | const struct samsung_pin_ctrl *ctrl; | ||
| 291 | unsigned int num_ctrl; | ||
| 292 | }; | ||
| 293 | |||
| 294 | /** | ||
| 285 | * struct samsung_pin_group: represent group of pins of a pinmux function. | 295 | * struct samsung_pin_group: represent group of pins of a pinmux function. |
| 286 | * @name: name of the pin group, used to lookup the group. | 296 | * @name: name of the pin group, used to lookup the group. |
| 287 | * @pins: the pins included in this group. | 297 | * @pins: the pins included in this group. |
| @@ -309,20 +319,20 @@ struct samsung_pmx_func { | |||
| 309 | }; | 319 | }; |
| 310 | 320 | ||
| 311 | /* list of all exported SoC specific data */ | 321 | /* list of all exported SoC specific data */ |
| 312 | extern const struct samsung_pin_ctrl exynos3250_pin_ctrl[]; | 322 | extern const struct samsung_pinctrl_of_match_data exynos3250_of_data; |
| 313 | extern const struct samsung_pin_ctrl exynos4210_pin_ctrl[]; | 323 | extern const struct samsung_pinctrl_of_match_data exynos4210_of_data; |
| 314 | extern const struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; | 324 | extern const struct samsung_pinctrl_of_match_data exynos4x12_of_data; |
| 315 | extern const struct samsung_pin_ctrl exynos5250_pin_ctrl[]; | 325 | extern const struct samsung_pinctrl_of_match_data exynos5250_of_data; |
| 316 | extern const struct samsung_pin_ctrl exynos5260_pin_ctrl[]; | 326 | extern const struct samsung_pinctrl_of_match_data exynos5260_of_data; |
| 317 | extern const struct samsung_pin_ctrl exynos5410_pin_ctrl[]; | 327 | extern const struct samsung_pinctrl_of_match_data exynos5410_of_data; |
| 318 | extern const struct samsung_pin_ctrl exynos5420_pin_ctrl[]; | 328 | extern const struct samsung_pinctrl_of_match_data exynos5420_of_data; |
| 319 | extern const struct samsung_pin_ctrl exynos5433_pin_ctrl[]; | 329 | extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; |
| 320 | extern const struct samsung_pin_ctrl exynos7_pin_ctrl[]; | 330 | extern const struct samsung_pinctrl_of_match_data exynos7_of_data; |
| 321 | extern const struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; | 331 | extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; |
| 322 | extern const struct samsung_pin_ctrl s3c2412_pin_ctrl[]; | 332 | extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; |
| 323 | extern const struct samsung_pin_ctrl s3c2416_pin_ctrl[]; | 333 | extern const struct samsung_pinctrl_of_match_data s3c2416_of_data; |
| 324 | extern const struct samsung_pin_ctrl s3c2440_pin_ctrl[]; | 334 | extern const struct samsung_pinctrl_of_match_data s3c2440_of_data; |
| 325 | extern const struct samsung_pin_ctrl s3c2450_pin_ctrl[]; | 335 | extern const struct samsung_pinctrl_of_match_data s3c2450_of_data; |
| 326 | extern const struct samsung_pin_ctrl s5pv210_pin_ctrl[]; | 336 | extern const struct samsung_pinctrl_of_match_data s5pv210_of_data; |
| 327 | 337 | ||
| 328 | #endif /* __PINCTRL_SAMSUNG_H */ | 338 | #endif /* __PINCTRL_SAMSUNG_H */ |
