diff options
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/cmd.c | 4 | ||||
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en.h | 9 | ||||
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c | 10 | ||||
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c | 10 | ||||
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 63 | ||||
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/eq.c | 20 | ||||
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/fpga/sdk.c | 6 | ||||
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 16 | ||||
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/health.c | 2 | ||||
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c | 2 | ||||
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/main.c | 75 | ||||
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/qp.c | 4 | ||||
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/rl.c | 22 | ||||
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/vxlan.c | 64 | ||||
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/vxlan.h | 1 | ||||
| -rw-r--r-- | include/linux/mlx5/driver.h | 3 | ||||
| -rw-r--r-- | include/linux/mlx5/mlx5_ifc.h | 8 |
17 files changed, 215 insertions, 104 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/cmd.c index 1fffdebbc9e8..e9a1fbcc4adf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/cmd.c | |||
| @@ -362,7 +362,7 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op, | |||
| 362 | case MLX5_CMD_OP_QUERY_VPORT_COUNTER: | 362 | case MLX5_CMD_OP_QUERY_VPORT_COUNTER: |
| 363 | case MLX5_CMD_OP_ALLOC_Q_COUNTER: | 363 | case MLX5_CMD_OP_ALLOC_Q_COUNTER: |
| 364 | case MLX5_CMD_OP_QUERY_Q_COUNTER: | 364 | case MLX5_CMD_OP_QUERY_Q_COUNTER: |
| 365 | case MLX5_CMD_OP_SET_RATE_LIMIT: | 365 | case MLX5_CMD_OP_SET_PP_RATE_LIMIT: |
| 366 | case MLX5_CMD_OP_QUERY_RATE_LIMIT: | 366 | case MLX5_CMD_OP_QUERY_RATE_LIMIT: |
| 367 | case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT: | 367 | case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT: |
| 368 | case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT: | 368 | case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT: |
| @@ -505,7 +505,7 @@ const char *mlx5_command_str(int command) | |||
| 505 | MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER); | 505 | MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER); |
| 506 | MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER); | 506 | MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER); |
| 507 | MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER); | 507 | MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER); |
| 508 | MLX5_COMMAND_STR_CASE(SET_RATE_LIMIT); | 508 | MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT); |
| 509 | MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT); | 509 | MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT); |
| 510 | MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT); | 510 | MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT); |
| 511 | MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT); | 511 | MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT); |
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h index c0872b3284cb..543060c305a0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h | |||
| @@ -82,6 +82,9 @@ | |||
| 82 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) | 82 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) |
| 83 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6) | 83 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6) |
| 84 | #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8) | 84 | #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8) |
| 85 | #define MLX5E_MPWQE_STRIDE_SZ(mdev, cqe_cmprs) \ | ||
| 86 | (cqe_cmprs ? MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) : \ | ||
| 87 | MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev)) | ||
| 85 | 88 | ||
| 86 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 | 89 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
| 87 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ | 90 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
| @@ -590,6 +593,7 @@ struct mlx5e_channel { | |||
| 590 | struct mlx5_core_dev *mdev; | 593 | struct mlx5_core_dev *mdev; |
| 591 | struct hwtstamp_config *tstamp; | 594 | struct hwtstamp_config *tstamp; |
| 592 | int ix; | 595 | int ix; |
| 596 | int cpu; | ||
| 593 | }; | 597 | }; |
| 594 | 598 | ||
| 595 | struct mlx5e_channels { | 599 | struct mlx5e_channels { |
| @@ -935,8 +939,9 @@ void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, | |||
| 935 | u8 cq_period_mode); | 939 | u8 cq_period_mode); |
| 936 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, | 940 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
| 937 | u8 cq_period_mode); | 941 | u8 cq_period_mode); |
| 938 | void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev, | 942 | void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, |
| 939 | struct mlx5e_params *params, u8 rq_type); | 943 | struct mlx5e_params *params, |
| 944 | u8 rq_type); | ||
| 940 | 945 | ||
| 941 | static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev) | 946 | static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev) |
| 942 | { | 947 | { |
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c b/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c index c6d90b6dd80e..9bcf38f4123b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c | |||
| @@ -274,6 +274,7 @@ int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets) | |||
| 274 | static int mlx5e_dbcnl_validate_ets(struct net_device *netdev, | 274 | static int mlx5e_dbcnl_validate_ets(struct net_device *netdev, |
| 275 | struct ieee_ets *ets) | 275 | struct ieee_ets *ets) |
| 276 | { | 276 | { |
| 277 | bool have_ets_tc = false; | ||
| 277 | int bw_sum = 0; | 278 | int bw_sum = 0; |
| 278 | int i; | 279 | int i; |
| 279 | 280 | ||
| @@ -288,11 +289,14 @@ static int mlx5e_dbcnl_validate_ets(struct net_device *netdev, | |||
| 288 | } | 289 | } |
| 289 | 290 | ||
| 290 | /* Validate Bandwidth Sum */ | 291 | /* Validate Bandwidth Sum */ |
| 291 | for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) | 292 | for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { |
| 292 | if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) | 293 | if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) { |
| 294 | have_ets_tc = true; | ||
| 293 | bw_sum += ets->tc_tx_bw[i]; | 295 | bw_sum += ets->tc_tx_bw[i]; |
| 296 | } | ||
| 297 | } | ||
| 294 | 298 | ||
| 295 | if (bw_sum != 0 && bw_sum != 100) { | 299 | if (have_ets_tc && bw_sum != 100) { |
| 296 | netdev_err(netdev, | 300 | netdev_err(netdev, |
| 297 | "Failed to validate ETS: BW sum is illegal\n"); | 301 | "Failed to validate ETS: BW sum is illegal\n"); |
| 298 | return -EINVAL; | 302 | return -EINVAL; |
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index 23425f028405..8f05efa5c829 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c | |||
| @@ -1523,8 +1523,10 @@ int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val | |||
| 1523 | new_channels.params = priv->channels.params; | 1523 | new_channels.params = priv->channels.params; |
| 1524 | MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val); | 1524 | MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val); |
| 1525 | 1525 | ||
| 1526 | mlx5e_set_rq_type_params(priv->mdev, &new_channels.params, | 1526 | new_channels.params.mpwqe_log_stride_sz = |
| 1527 | new_channels.params.rq_wq_type); | 1527 | MLX5E_MPWQE_STRIDE_SZ(priv->mdev, new_val); |
| 1528 | new_channels.params.mpwqe_log_num_strides = | ||
| 1529 | MLX5_MPWRQ_LOG_WQE_SZ - new_channels.params.mpwqe_log_stride_sz; | ||
| 1528 | 1530 | ||
| 1529 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { | 1531 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { |
| 1530 | priv->channels.params = new_channels.params; | 1532 | priv->channels.params = new_channels.params; |
| @@ -1536,6 +1538,10 @@ int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val | |||
| 1536 | return err; | 1538 | return err; |
| 1537 | 1539 | ||
| 1538 | mlx5e_switch_priv_channels(priv, &new_channels, NULL); | 1540 | mlx5e_switch_priv_channels(priv, &new_channels, NULL); |
| 1541 | mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n", | ||
| 1542 | MLX5E_GET_PFLAG(&priv->channels.params, | ||
| 1543 | MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF"); | ||
| 1544 | |||
| 1539 | return 0; | 1545 | return 0; |
| 1540 | } | 1546 | } |
| 1541 | 1547 | ||
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index d2b057a3e512..d9d8227f195f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c | |||
| @@ -71,11 +71,6 @@ struct mlx5e_channel_param { | |||
| 71 | struct mlx5e_cq_param icosq_cq; | 71 | struct mlx5e_cq_param icosq_cq; |
| 72 | }; | 72 | }; |
| 73 | 73 | ||
| 74 | static int mlx5e_get_node(struct mlx5e_priv *priv, int ix) | ||
| 75 | { | ||
| 76 | return pci_irq_get_node(priv->mdev->pdev, MLX5_EQ_VEC_COMP_BASE + ix); | ||
| 77 | } | ||
| 78 | |||
| 79 | static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev) | 74 | static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev) |
| 80 | { | 75 | { |
| 81 | return MLX5_CAP_GEN(mdev, striding_rq) && | 76 | return MLX5_CAP_GEN(mdev, striding_rq) && |
| @@ -83,8 +78,8 @@ static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev) | |||
| 83 | MLX5_CAP_ETH(mdev, reg_umr_sq); | 78 | MLX5_CAP_ETH(mdev, reg_umr_sq); |
| 84 | } | 79 | } |
| 85 | 80 | ||
| 86 | void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev, | 81 | void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, |
| 87 | struct mlx5e_params *params, u8 rq_type) | 82 | struct mlx5e_params *params, u8 rq_type) |
| 88 | { | 83 | { |
| 89 | params->rq_wq_type = rq_type; | 84 | params->rq_wq_type = rq_type; |
| 90 | params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; | 85 | params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; |
| @@ -93,10 +88,8 @@ void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev, | |||
| 93 | params->log_rq_size = is_kdump_kernel() ? | 88 | params->log_rq_size = is_kdump_kernel() ? |
| 94 | MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW : | 89 | MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW : |
| 95 | MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW; | 90 | MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW; |
| 96 | params->mpwqe_log_stride_sz = | 91 | params->mpwqe_log_stride_sz = MLX5E_MPWQE_STRIDE_SZ(mdev, |
| 97 | MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ? | 92 | MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)); |
| 98 | MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) : | ||
| 99 | MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev); | ||
| 100 | params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - | 93 | params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - |
| 101 | params->mpwqe_log_stride_sz; | 94 | params->mpwqe_log_stride_sz; |
| 102 | break; | 95 | break; |
| @@ -120,13 +113,14 @@ void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev, | |||
| 120 | MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)); | 113 | MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)); |
| 121 | } | 114 | } |
| 122 | 115 | ||
| 123 | static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params) | 116 | static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, |
| 117 | struct mlx5e_params *params) | ||
| 124 | { | 118 | { |
| 125 | u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) && | 119 | u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) && |
| 126 | !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ? | 120 | !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ? |
| 127 | MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ : | 121 | MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ : |
| 128 | MLX5_WQ_TYPE_LINKED_LIST; | 122 | MLX5_WQ_TYPE_LINKED_LIST; |
| 129 | mlx5e_set_rq_type_params(mdev, params, rq_type); | 123 | mlx5e_init_rq_type_params(mdev, params, rq_type); |
| 130 | } | 124 | } |
| 131 | 125 | ||
| 132 | static void mlx5e_update_carrier(struct mlx5e_priv *priv) | 126 | static void mlx5e_update_carrier(struct mlx5e_priv *priv) |
| @@ -444,17 +438,16 @@ static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, | |||
| 444 | int wq_sz = mlx5_wq_ll_get_size(&rq->wq); | 438 | int wq_sz = mlx5_wq_ll_get_size(&rq->wq); |
| 445 | int mtt_sz = mlx5e_get_wqe_mtt_sz(); | 439 | int mtt_sz = mlx5e_get_wqe_mtt_sz(); |
| 446 | int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1; | 440 | int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1; |
| 447 | int node = mlx5e_get_node(c->priv, c->ix); | ||
| 448 | int i; | 441 | int i; |
| 449 | 442 | ||
| 450 | rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info), | 443 | rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info), |
| 451 | GFP_KERNEL, node); | 444 | GFP_KERNEL, cpu_to_node(c->cpu)); |
| 452 | if (!rq->mpwqe.info) | 445 | if (!rq->mpwqe.info) |
| 453 | goto err_out; | 446 | goto err_out; |
| 454 | 447 | ||
| 455 | /* We allocate more than mtt_sz as we will align the pointer */ | 448 | /* We allocate more than mtt_sz as we will align the pointer */ |
| 456 | rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, | 449 | rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL, |
| 457 | GFP_KERNEL, node); | 450 | cpu_to_node(c->cpu)); |
| 458 | if (unlikely(!rq->mpwqe.mtt_no_align)) | 451 | if (unlikely(!rq->mpwqe.mtt_no_align)) |
| 459 | goto err_free_wqe_info; | 452 | goto err_free_wqe_info; |
| 460 | 453 | ||
| @@ -562,7 +555,7 @@ static int mlx5e_alloc_rq(struct mlx5e_channel *c, | |||
| 562 | int err; | 555 | int err; |
| 563 | int i; | 556 | int i; |
| 564 | 557 | ||
| 565 | rqp->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix); | 558 | rqp->wq.db_numa_node = cpu_to_node(c->cpu); |
| 566 | 559 | ||
| 567 | err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq, | 560 | err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq, |
| 568 | &rq->wq_ctrl); | 561 | &rq->wq_ctrl); |
| @@ -629,8 +622,7 @@ static int mlx5e_alloc_rq(struct mlx5e_channel *c, | |||
| 629 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | 622 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ |
| 630 | rq->wqe.frag_info = | 623 | rq->wqe.frag_info = |
| 631 | kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info), | 624 | kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info), |
| 632 | GFP_KERNEL, | 625 | GFP_KERNEL, cpu_to_node(c->cpu)); |
| 633 | mlx5e_get_node(c->priv, c->ix)); | ||
| 634 | if (!rq->wqe.frag_info) { | 626 | if (!rq->wqe.frag_info) { |
| 635 | err = -ENOMEM; | 627 | err = -ENOMEM; |
| 636 | goto err_rq_wq_destroy; | 628 | goto err_rq_wq_destroy; |
| @@ -1000,13 +992,13 @@ static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c, | |||
| 1000 | sq->uar_map = mdev->mlx5e_res.bfreg.map; | 992 | sq->uar_map = mdev->mlx5e_res.bfreg.map; |
| 1001 | sq->min_inline_mode = params->tx_min_inline_mode; | 993 | sq->min_inline_mode = params->tx_min_inline_mode; |
| 1002 | 994 | ||
| 1003 | param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix); | 995 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
| 1004 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl); | 996 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl); |
| 1005 | if (err) | 997 | if (err) |
| 1006 | return err; | 998 | return err; |
| 1007 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; | 999 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; |
| 1008 | 1000 | ||
| 1009 | err = mlx5e_alloc_xdpsq_db(sq, mlx5e_get_node(c->priv, c->ix)); | 1001 | err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu)); |
| 1010 | if (err) | 1002 | if (err) |
| 1011 | goto err_sq_wq_destroy; | 1003 | goto err_sq_wq_destroy; |
| 1012 | 1004 | ||
| @@ -1053,13 +1045,13 @@ static int mlx5e_alloc_icosq(struct mlx5e_channel *c, | |||
| 1053 | sq->channel = c; | 1045 | sq->channel = c; |
| 1054 | sq->uar_map = mdev->mlx5e_res.bfreg.map; | 1046 | sq->uar_map = mdev->mlx5e_res.bfreg.map; |
| 1055 | 1047 | ||
| 1056 | param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix); | 1048 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
| 1057 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl); | 1049 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl); |
| 1058 | if (err) | 1050 | if (err) |
| 1059 | return err; | 1051 | return err; |
| 1060 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; | 1052 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; |
| 1061 | 1053 | ||
| 1062 | err = mlx5e_alloc_icosq_db(sq, mlx5e_get_node(c->priv, c->ix)); | 1054 | err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu)); |
| 1063 | if (err) | 1055 | if (err) |
| 1064 | goto err_sq_wq_destroy; | 1056 | goto err_sq_wq_destroy; |
| 1065 | 1057 | ||
| @@ -1126,13 +1118,13 @@ static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, | |||
| 1126 | if (MLX5_IPSEC_DEV(c->priv->mdev)) | 1118 | if (MLX5_IPSEC_DEV(c->priv->mdev)) |
| 1127 | set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state); | 1119 | set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state); |
| 1128 | 1120 | ||
| 1129 | param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix); | 1121 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
| 1130 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl); | 1122 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl); |
| 1131 | if (err) | 1123 | if (err) |
| 1132 | return err; | 1124 | return err; |
| 1133 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; | 1125 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; |
| 1134 | 1126 | ||
| 1135 | err = mlx5e_alloc_txqsq_db(sq, mlx5e_get_node(c->priv, c->ix)); | 1127 | err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu)); |
| 1136 | if (err) | 1128 | if (err) |
| 1137 | goto err_sq_wq_destroy; | 1129 | goto err_sq_wq_destroy; |
| 1138 | 1130 | ||
| @@ -1504,8 +1496,8 @@ static int mlx5e_alloc_cq(struct mlx5e_channel *c, | |||
| 1504 | struct mlx5_core_dev *mdev = c->priv->mdev; | 1496 | struct mlx5_core_dev *mdev = c->priv->mdev; |
| 1505 | int err; | 1497 | int err; |
| 1506 | 1498 | ||
| 1507 | param->wq.buf_numa_node = mlx5e_get_node(c->priv, c->ix); | 1499 | param->wq.buf_numa_node = cpu_to_node(c->cpu); |
| 1508 | param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix); | 1500 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
| 1509 | param->eq_ix = c->ix; | 1501 | param->eq_ix = c->ix; |
| 1510 | 1502 | ||
| 1511 | err = mlx5e_alloc_cq_common(mdev, param, cq); | 1503 | err = mlx5e_alloc_cq_common(mdev, param, cq); |
| @@ -1604,6 +1596,11 @@ static void mlx5e_close_cq(struct mlx5e_cq *cq) | |||
| 1604 | mlx5e_free_cq(cq); | 1596 | mlx5e_free_cq(cq); |
| 1605 | } | 1597 | } |
| 1606 | 1598 | ||
| 1599 | static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix) | ||
| 1600 | { | ||
| 1601 | return cpumask_first(priv->mdev->priv.irq_info[ix].mask); | ||
| 1602 | } | ||
| 1603 | |||
| 1607 | static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, | 1604 | static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, |
| 1608 | struct mlx5e_params *params, | 1605 | struct mlx5e_params *params, |
| 1609 | struct mlx5e_channel_param *cparam) | 1606 | struct mlx5e_channel_param *cparam) |
| @@ -1752,12 +1749,13 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, | |||
| 1752 | { | 1749 | { |
| 1753 | struct mlx5e_cq_moder icocq_moder = {0, 0}; | 1750 | struct mlx5e_cq_moder icocq_moder = {0, 0}; |
| 1754 | struct net_device *netdev = priv->netdev; | 1751 | struct net_device *netdev = priv->netdev; |
| 1752 | int cpu = mlx5e_get_cpu(priv, ix); | ||
| 1755 | struct mlx5e_channel *c; | 1753 | struct mlx5e_channel *c; |
| 1756 | unsigned int irq; | 1754 | unsigned int irq; |
| 1757 | int err; | 1755 | int err; |
| 1758 | int eqn; | 1756 | int eqn; |
| 1759 | 1757 | ||
| 1760 | c = kzalloc_node(sizeof(*c), GFP_KERNEL, mlx5e_get_node(priv, ix)); | 1758 | c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu)); |
| 1761 | if (!c) | 1759 | if (!c) |
| 1762 | return -ENOMEM; | 1760 | return -ENOMEM; |
| 1763 | 1761 | ||
| @@ -1765,6 +1763,7 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, | |||
| 1765 | c->mdev = priv->mdev; | 1763 | c->mdev = priv->mdev; |
| 1766 | c->tstamp = &priv->tstamp; | 1764 | c->tstamp = &priv->tstamp; |
| 1767 | c->ix = ix; | 1765 | c->ix = ix; |
| 1766 | c->cpu = cpu; | ||
| 1768 | c->pdev = &priv->mdev->pdev->dev; | 1767 | c->pdev = &priv->mdev->pdev->dev; |
| 1769 | c->netdev = priv->netdev; | 1768 | c->netdev = priv->netdev; |
| 1770 | c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key); | 1769 | c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key); |
| @@ -1853,8 +1852,7 @@ static void mlx5e_activate_channel(struct mlx5e_channel *c) | |||
| 1853 | for (tc = 0; tc < c->num_tc; tc++) | 1852 | for (tc = 0; tc < c->num_tc; tc++) |
| 1854 | mlx5e_activate_txqsq(&c->sq[tc]); | 1853 | mlx5e_activate_txqsq(&c->sq[tc]); |
| 1855 | mlx5e_activate_rq(&c->rq); | 1854 | mlx5e_activate_rq(&c->rq); |
| 1856 | netif_set_xps_queue(c->netdev, | 1855 | netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix); |
| 1857 | mlx5_get_vector_affinity(c->priv->mdev, c->ix), c->ix); | ||
| 1858 | } | 1856 | } |
| 1859 | 1857 | ||
| 1860 | static void mlx5e_deactivate_channel(struct mlx5e_channel *c) | 1858 | static void mlx5e_deactivate_channel(struct mlx5e_channel *c) |
| @@ -3679,6 +3677,7 @@ static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv, | |||
| 3679 | struct sk_buff *skb, | 3677 | struct sk_buff *skb, |
| 3680 | netdev_features_t features) | 3678 | netdev_features_t features) |
| 3681 | { | 3679 | { |
| 3680 | unsigned int offset = 0; | ||
| 3682 | struct udphdr *udph; | 3681 | struct udphdr *udph; |
| 3683 | u8 proto; | 3682 | u8 proto; |
| 3684 | u16 port; | 3683 | u16 port; |
| @@ -3688,7 +3687,7 @@ static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv, | |||
| 3688 | proto = ip_hdr(skb)->protocol; | 3687 | proto = ip_hdr(skb)->protocol; |
| 3689 | break; | 3688 | break; |
| 3690 | case htons(ETH_P_IPV6): | 3689 | case htons(ETH_P_IPV6): |
| 3691 | proto = ipv6_hdr(skb)->nexthdr; | 3690 | proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL); |
| 3692 | break; | 3691 | break; |
| 3693 | default: | 3692 | default: |
| 3694 | goto out; | 3693 | goto out; |
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c index 60771865c99c..e7e7cef2bde4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c | |||
| @@ -466,7 +466,7 @@ static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr) | |||
| 466 | break; | 466 | break; |
| 467 | case MLX5_EVENT_TYPE_CQ_ERROR: | 467 | case MLX5_EVENT_TYPE_CQ_ERROR: |
| 468 | cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; | 468 | cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; |
| 469 | mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n", | 469 | mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrome 0x%x\n", |
| 470 | cqn, eqe->data.cq_err.syndrome); | 470 | cqn, eqe->data.cq_err.syndrome); |
| 471 | mlx5_cq_event(dev, cqn, eqe->type); | 471 | mlx5_cq_event(dev, cqn, eqe->type); |
| 472 | break; | 472 | break; |
| @@ -775,7 +775,7 @@ err1: | |||
| 775 | return err; | 775 | return err; |
| 776 | } | 776 | } |
| 777 | 777 | ||
| 778 | int mlx5_stop_eqs(struct mlx5_core_dev *dev) | 778 | void mlx5_stop_eqs(struct mlx5_core_dev *dev) |
| 779 | { | 779 | { |
| 780 | struct mlx5_eq_table *table = &dev->priv.eq_table; | 780 | struct mlx5_eq_table *table = &dev->priv.eq_table; |
| 781 | int err; | 781 | int err; |
| @@ -784,22 +784,26 @@ int mlx5_stop_eqs(struct mlx5_core_dev *dev) | |||
| 784 | if (MLX5_CAP_GEN(dev, pg)) { | 784 | if (MLX5_CAP_GEN(dev, pg)) { |
| 785 | err = mlx5_destroy_unmap_eq(dev, &table->pfault_eq); | 785 | err = mlx5_destroy_unmap_eq(dev, &table->pfault_eq); |
| 786 | if (err) | 786 | if (err) |
| 787 | return err; | 787 | mlx5_core_err(dev, "failed to destroy page fault eq, err(%d)\n", |
| 788 | err); | ||
| 788 | } | 789 | } |
| 789 | #endif | 790 | #endif |
| 790 | 791 | ||
| 791 | err = mlx5_destroy_unmap_eq(dev, &table->pages_eq); | 792 | err = mlx5_destroy_unmap_eq(dev, &table->pages_eq); |
| 792 | if (err) | 793 | if (err) |
| 793 | return err; | 794 | mlx5_core_err(dev, "failed to destroy pages eq, err(%d)\n", |
| 795 | err); | ||
| 794 | 796 | ||
| 795 | mlx5_destroy_unmap_eq(dev, &table->async_eq); | 797 | err = mlx5_destroy_unmap_eq(dev, &table->async_eq); |
| 798 | if (err) | ||
| 799 | mlx5_core_err(dev, "failed to destroy async eq, err(%d)\n", | ||
| 800 | err); | ||
| 796 | mlx5_cmd_use_polling(dev); | 801 | mlx5_cmd_use_polling(dev); |
| 797 | 802 | ||
| 798 | err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq); | 803 | err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq); |
| 799 | if (err) | 804 | if (err) |
| 800 | mlx5_cmd_use_events(dev); | 805 | mlx5_core_err(dev, "failed to destroy command eq, err(%d)\n", |
| 801 | 806 | err); | |
| 802 | return err; | ||
| 803 | } | 807 | } |
| 804 | 808 | ||
| 805 | int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, | 809 | int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, |
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/sdk.c b/drivers/net/ethernet/mellanox/mlx5/core/fpga/sdk.c index 3c11d6e2160a..14962969c5ba 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/sdk.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/sdk.c | |||
| @@ -66,6 +66,9 @@ static int mlx5_fpga_mem_read_i2c(struct mlx5_fpga_device *fdev, size_t size, | |||
| 66 | u8 actual_size; | 66 | u8 actual_size; |
| 67 | int err; | 67 | int err; |
| 68 | 68 | ||
| 69 | if (!size) | ||
| 70 | return -EINVAL; | ||
| 71 | |||
| 69 | if (!fdev->mdev) | 72 | if (!fdev->mdev) |
| 70 | return -ENOTCONN; | 73 | return -ENOTCONN; |
| 71 | 74 | ||
| @@ -95,6 +98,9 @@ static int mlx5_fpga_mem_write_i2c(struct mlx5_fpga_device *fdev, size_t size, | |||
| 95 | u8 actual_size; | 98 | u8 actual_size; |
| 96 | int err; | 99 | int err; |
| 97 | 100 | ||
| 101 | if (!size) | ||
| 102 | return -EINVAL; | ||
| 103 | |||
| 98 | if (!fdev->mdev) | 104 | if (!fdev->mdev) |
| 99 | return -ENOTCONN; | 105 | return -ENOTCONN; |
| 100 | 106 | ||
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c index c70fd663a633..dfaad9ecb2b8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | |||
| @@ -174,6 +174,8 @@ static void del_hw_fte(struct fs_node *node); | |||
| 174 | static void del_sw_flow_table(struct fs_node *node); | 174 | static void del_sw_flow_table(struct fs_node *node); |
| 175 | static void del_sw_flow_group(struct fs_node *node); | 175 | static void del_sw_flow_group(struct fs_node *node); |
| 176 | static void del_sw_fte(struct fs_node *node); | 176 | static void del_sw_fte(struct fs_node *node); |
| 177 | static void del_sw_prio(struct fs_node *node); | ||
| 178 | static void del_sw_ns(struct fs_node *node); | ||
| 177 | /* Delete rule (destination) is special case that | 179 | /* Delete rule (destination) is special case that |
| 178 | * requires to lock the FTE for all the deletion process. | 180 | * requires to lock the FTE for all the deletion process. |
| 179 | */ | 181 | */ |
| @@ -408,6 +410,16 @@ static inline struct mlx5_core_dev *get_dev(struct fs_node *node) | |||
| 408 | return NULL; | 410 | return NULL; |
| 409 | } | 411 | } |
| 410 | 412 | ||
| 413 | static void del_sw_ns(struct fs_node *node) | ||
| 414 | { | ||
| 415 | kfree(node); | ||
| 416 | } | ||
| 417 | |||
| 418 | static void del_sw_prio(struct fs_node *node) | ||
| 419 | { | ||
| 420 | kfree(node); | ||
| 421 | } | ||
| 422 | |||
| 411 | static void del_hw_flow_table(struct fs_node *node) | 423 | static void del_hw_flow_table(struct fs_node *node) |
| 412 | { | 424 | { |
| 413 | struct mlx5_flow_table *ft; | 425 | struct mlx5_flow_table *ft; |
| @@ -2064,7 +2076,7 @@ static struct fs_prio *fs_create_prio(struct mlx5_flow_namespace *ns, | |||
| 2064 | return ERR_PTR(-ENOMEM); | 2076 | return ERR_PTR(-ENOMEM); |
| 2065 | 2077 | ||
| 2066 | fs_prio->node.type = FS_TYPE_PRIO; | 2078 | fs_prio->node.type = FS_TYPE_PRIO; |
| 2067 | tree_init_node(&fs_prio->node, NULL, NULL); | 2079 | tree_init_node(&fs_prio->node, NULL, del_sw_prio); |
| 2068 | tree_add_node(&fs_prio->node, &ns->node); | 2080 | tree_add_node(&fs_prio->node, &ns->node); |
| 2069 | fs_prio->num_levels = num_levels; | 2081 | fs_prio->num_levels = num_levels; |
| 2070 | fs_prio->prio = prio; | 2082 | fs_prio->prio = prio; |
| @@ -2090,7 +2102,7 @@ static struct mlx5_flow_namespace *fs_create_namespace(struct fs_prio *prio) | |||
| 2090 | return ERR_PTR(-ENOMEM); | 2102 | return ERR_PTR(-ENOMEM); |
| 2091 | 2103 | ||
| 2092 | fs_init_namespace(ns); | 2104 | fs_init_namespace(ns); |
| 2093 | tree_init_node(&ns->node, NULL, NULL); | 2105 | tree_init_node(&ns->node, NULL, del_sw_ns); |
| 2094 | tree_add_node(&ns->node, &prio->node); | 2106 | tree_add_node(&ns->node, &prio->node); |
| 2095 | list_add_tail(&ns->node.list, &prio->node.children); | 2107 | list_add_tail(&ns->node.list, &prio->node.children); |
| 2096 | 2108 | ||
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/health.c b/drivers/net/ethernet/mellanox/mlx5/core/health.c index 1a0e797ad001..21d29f7936f6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/health.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/health.c | |||
| @@ -241,7 +241,7 @@ static void print_health_info(struct mlx5_core_dev *dev) | |||
| 241 | u32 fw; | 241 | u32 fw; |
| 242 | int i; | 242 | int i; |
| 243 | 243 | ||
| 244 | /* If the syndrom is 0, the device is OK and no need to print buffer */ | 244 | /* If the syndrome is 0, the device is OK and no need to print buffer */ |
| 245 | if (!ioread8(&h->synd)) | 245 | if (!ioread8(&h->synd)) |
| 246 | return; | 246 | return; |
| 247 | 247 | ||
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c index d2a66dc4adc6..8812d7208e8f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c | |||
| @@ -57,7 +57,7 @@ static void mlx5i_build_nic_params(struct mlx5_core_dev *mdev, | |||
| 57 | struct mlx5e_params *params) | 57 | struct mlx5e_params *params) |
| 58 | { | 58 | { |
| 59 | /* Override RQ params as IPoIB supports only LINKED LIST RQ for now */ | 59 | /* Override RQ params as IPoIB supports only LINKED LIST RQ for now */ |
| 60 | mlx5e_set_rq_type_params(mdev, params, MLX5_WQ_TYPE_LINKED_LIST); | 60 | mlx5e_init_rq_type_params(mdev, params, MLX5_WQ_TYPE_LINKED_LIST); |
| 61 | 61 | ||
| 62 | /* RQ size in ipoib by default is 512 */ | 62 | /* RQ size in ipoib by default is 512 */ |
| 63 | params->log_rq_size = is_kdump_kernel() ? | 63 | params->log_rq_size = is_kdump_kernel() ? |
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index 5f323442cc5a..8a89c7e8cd63 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c | |||
| @@ -317,9 +317,6 @@ static int mlx5_alloc_irq_vectors(struct mlx5_core_dev *dev) | |||
| 317 | { | 317 | { |
| 318 | struct mlx5_priv *priv = &dev->priv; | 318 | struct mlx5_priv *priv = &dev->priv; |
| 319 | struct mlx5_eq_table *table = &priv->eq_table; | 319 | struct mlx5_eq_table *table = &priv->eq_table; |
| 320 | struct irq_affinity irqdesc = { | ||
| 321 | .pre_vectors = MLX5_EQ_VEC_COMP_BASE, | ||
| 322 | }; | ||
| 323 | int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); | 320 | int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); |
| 324 | int nvec; | 321 | int nvec; |
| 325 | 322 | ||
| @@ -333,10 +330,9 @@ static int mlx5_alloc_irq_vectors(struct mlx5_core_dev *dev) | |||
| 333 | if (!priv->irq_info) | 330 | if (!priv->irq_info) |
| 334 | goto err_free_msix; | 331 | goto err_free_msix; |
| 335 | 332 | ||
| 336 | nvec = pci_alloc_irq_vectors_affinity(dev->pdev, | 333 | nvec = pci_alloc_irq_vectors(dev->pdev, |
| 337 | MLX5_EQ_VEC_COMP_BASE + 1, nvec, | 334 | MLX5_EQ_VEC_COMP_BASE + 1, nvec, |
| 338 | PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, | 335 | PCI_IRQ_MSIX); |
| 339 | &irqdesc); | ||
| 340 | if (nvec < 0) | 336 | if (nvec < 0) |
| 341 | return nvec; | 337 | return nvec; |
| 342 | 338 | ||
| @@ -622,6 +618,63 @@ u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev) | |||
| 622 | return (u64)timer_l | (u64)timer_h1 << 32; | 618 | return (u64)timer_l | (u64)timer_h1 << 32; |
| 623 | } | 619 | } |
| 624 | 620 | ||
| 621 | static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i) | ||
| 622 | { | ||
| 623 | struct mlx5_priv *priv = &mdev->priv; | ||
| 624 | int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i); | ||
| 625 | |||
| 626 | if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) { | ||
| 627 | mlx5_core_warn(mdev, "zalloc_cpumask_var failed"); | ||
| 628 | return -ENOMEM; | ||
| 629 | } | ||
| 630 | |||
| 631 | cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node), | ||
| 632 | priv->irq_info[i].mask); | ||
| 633 | |||
| 634 | if (IS_ENABLED(CONFIG_SMP) && | ||
| 635 | irq_set_affinity_hint(irq, priv->irq_info[i].mask)) | ||
| 636 | mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq); | ||
| 637 | |||
| 638 | return 0; | ||
| 639 | } | ||
| 640 | |||
| 641 | static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i) | ||
| 642 | { | ||
| 643 | struct mlx5_priv *priv = &mdev->priv; | ||
| 644 | int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i); | ||
| 645 | |||
| 646 | irq_set_affinity_hint(irq, NULL); | ||
| 647 | free_cpumask_var(priv->irq_info[i].mask); | ||
| 648 | } | ||
| 649 | |||
| 650 | static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev) | ||
| 651 | { | ||
| 652 | int err; | ||
| 653 | int i; | ||
| 654 | |||
| 655 | for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) { | ||
| 656 | err = mlx5_irq_set_affinity_hint(mdev, i); | ||
| 657 | if (err) | ||
| 658 | goto err_out; | ||
| 659 | } | ||
| 660 | |||
| 661 | return 0; | ||
| 662 | |||
| 663 | err_out: | ||
| 664 | for (i--; i >= 0; i--) | ||
| 665 | mlx5_irq_clear_affinity_hint(mdev, i); | ||
| 666 | |||
| 667 | return err; | ||
| 668 | } | ||
| 669 | |||
| 670 | static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev) | ||
| 671 | { | ||
| 672 | int i; | ||
| 673 | |||
| 674 | for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) | ||
| 675 | mlx5_irq_clear_affinity_hint(mdev, i); | ||
| 676 | } | ||
| 677 | |||
| 625 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, | 678 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
| 626 | unsigned int *irqn) | 679 | unsigned int *irqn) |
| 627 | { | 680 | { |
| @@ -1097,6 +1150,12 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, | |||
| 1097 | goto err_stop_eqs; | 1150 | goto err_stop_eqs; |
| 1098 | } | 1151 | } |
| 1099 | 1152 | ||
| 1153 | err = mlx5_irq_set_affinity_hints(dev); | ||
| 1154 | if (err) { | ||
| 1155 | dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n"); | ||
| 1156 | goto err_affinity_hints; | ||
| 1157 | } | ||
| 1158 | |||
| 1100 | err = mlx5_init_fs(dev); | 1159 | err = mlx5_init_fs(dev); |
| 1101 | if (err) { | 1160 | if (err) { |
| 1102 | dev_err(&pdev->dev, "Failed to init flow steering\n"); | 1161 | dev_err(&pdev->dev, "Failed to init flow steering\n"); |
| @@ -1154,6 +1213,9 @@ err_sriov: | |||
| 1154 | mlx5_cleanup_fs(dev); | 1213 | mlx5_cleanup_fs(dev); |
| 1155 | 1214 | ||
| 1156 | err_fs: | 1215 | err_fs: |
| 1216 | mlx5_irq_clear_affinity_hints(dev); | ||
| 1217 | |||
| 1218 | err_affinity_hints: | ||
| 1157 | free_comp_eqs(dev); | 1219 | free_comp_eqs(dev); |
| 1158 | 1220 | ||
| 1159 | err_stop_eqs: | 1221 | err_stop_eqs: |
| @@ -1222,6 +1284,7 @@ static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, | |||
| 1222 | 1284 | ||
| 1223 | mlx5_sriov_detach(dev); | 1285 | mlx5_sriov_detach(dev); |
| 1224 | mlx5_cleanup_fs(dev); | 1286 | mlx5_cleanup_fs(dev); |
| 1287 | mlx5_irq_clear_affinity_hints(dev); | ||
| 1225 | free_comp_eqs(dev); | 1288 | free_comp_eqs(dev); |
| 1226 | mlx5_stop_eqs(dev); | 1289 | mlx5_stop_eqs(dev); |
| 1227 | mlx5_put_uars_page(dev, priv->uar); | 1290 | mlx5_put_uars_page(dev, priv->uar); |
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/qp.c b/drivers/net/ethernet/mellanox/mlx5/core/qp.c index db9e665ab104..889130edb715 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/qp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/qp.c | |||
| @@ -213,8 +213,8 @@ int mlx5_core_create_qp(struct mlx5_core_dev *dev, | |||
| 213 | err_cmd: | 213 | err_cmd: |
| 214 | memset(din, 0, sizeof(din)); | 214 | memset(din, 0, sizeof(din)); |
| 215 | memset(dout, 0, sizeof(dout)); | 215 | memset(dout, 0, sizeof(dout)); |
| 216 | MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP); | 216 | MLX5_SET(destroy_qp_in, din, opcode, MLX5_CMD_OP_DESTROY_QP); |
| 217 | MLX5_SET(destroy_qp_in, in, qpn, qp->qpn); | 217 | MLX5_SET(destroy_qp_in, din, qpn, qp->qpn); |
| 218 | mlx5_cmd_exec(dev, din, sizeof(din), dout, sizeof(dout)); | 218 | mlx5_cmd_exec(dev, din, sizeof(din), dout, sizeof(dout)); |
| 219 | return err; | 219 | return err; |
| 220 | } | 220 | } |
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/rl.c b/drivers/net/ethernet/mellanox/mlx5/core/rl.c index e651e4c02867..d3c33e9eea72 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/rl.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/rl.c | |||
| @@ -125,16 +125,16 @@ static struct mlx5_rl_entry *find_rl_entry(struct mlx5_rl_table *table, | |||
| 125 | return ret_entry; | 125 | return ret_entry; |
| 126 | } | 126 | } |
| 127 | 127 | ||
| 128 | static int mlx5_set_rate_limit_cmd(struct mlx5_core_dev *dev, | 128 | static int mlx5_set_pp_rate_limit_cmd(struct mlx5_core_dev *dev, |
| 129 | u32 rate, u16 index) | 129 | u32 rate, u16 index) |
| 130 | { | 130 | { |
| 131 | u32 in[MLX5_ST_SZ_DW(set_rate_limit_in)] = {0}; | 131 | u32 in[MLX5_ST_SZ_DW(set_pp_rate_limit_in)] = {0}; |
| 132 | u32 out[MLX5_ST_SZ_DW(set_rate_limit_out)] = {0}; | 132 | u32 out[MLX5_ST_SZ_DW(set_pp_rate_limit_out)] = {0}; |
| 133 | 133 | ||
| 134 | MLX5_SET(set_rate_limit_in, in, opcode, | 134 | MLX5_SET(set_pp_rate_limit_in, in, opcode, |
| 135 | MLX5_CMD_OP_SET_RATE_LIMIT); | 135 | MLX5_CMD_OP_SET_PP_RATE_LIMIT); |
| 136 | MLX5_SET(set_rate_limit_in, in, rate_limit_index, index); | 136 | MLX5_SET(set_pp_rate_limit_in, in, rate_limit_index, index); |
| 137 | MLX5_SET(set_rate_limit_in, in, rate_limit, rate); | 137 | MLX5_SET(set_pp_rate_limit_in, in, rate_limit, rate); |
| 138 | return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); | 138 | return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); |
| 139 | } | 139 | } |
| 140 | 140 | ||
| @@ -173,7 +173,7 @@ int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index) | |||
| 173 | entry->refcount++; | 173 | entry->refcount++; |
| 174 | } else { | 174 | } else { |
| 175 | /* new rate limit */ | 175 | /* new rate limit */ |
| 176 | err = mlx5_set_rate_limit_cmd(dev, rate, entry->index); | 176 | err = mlx5_set_pp_rate_limit_cmd(dev, rate, entry->index); |
| 177 | if (err) { | 177 | if (err) { |
| 178 | mlx5_core_err(dev, "Failed configuring rate: %u (%d)\n", | 178 | mlx5_core_err(dev, "Failed configuring rate: %u (%d)\n", |
| 179 | rate, err); | 179 | rate, err); |
| @@ -209,7 +209,7 @@ void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate) | |||
| 209 | entry->refcount--; | 209 | entry->refcount--; |
| 210 | if (!entry->refcount) { | 210 | if (!entry->refcount) { |
| 211 | /* need to remove rate */ | 211 | /* need to remove rate */ |
| 212 | mlx5_set_rate_limit_cmd(dev, 0, entry->index); | 212 | mlx5_set_pp_rate_limit_cmd(dev, 0, entry->index); |
| 213 | entry->rate = 0; | 213 | entry->rate = 0; |
| 214 | } | 214 | } |
| 215 | 215 | ||
| @@ -262,8 +262,8 @@ void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev) | |||
| 262 | /* Clear all configured rates */ | 262 | /* Clear all configured rates */ |
| 263 | for (i = 0; i < table->max_size; i++) | 263 | for (i = 0; i < table->max_size; i++) |
| 264 | if (table->rl_entry[i].rate) | 264 | if (table->rl_entry[i].rate) |
| 265 | mlx5_set_rate_limit_cmd(dev, 0, | 265 | mlx5_set_pp_rate_limit_cmd(dev, 0, |
| 266 | table->rl_entry[i].index); | 266 | table->rl_entry[i].index); |
| 267 | 267 | ||
| 268 | kfree(dev->priv.rl_table.rl_entry); | 268 | kfree(dev->priv.rl_table.rl_entry); |
| 269 | } | 269 | } |
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/vxlan.c b/drivers/net/ethernet/mellanox/mlx5/core/vxlan.c index 07a9ba6cfc70..2f74953e4561 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/vxlan.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/vxlan.c | |||
| @@ -71,9 +71,9 @@ struct mlx5e_vxlan *mlx5e_vxlan_lookup_port(struct mlx5e_priv *priv, u16 port) | |||
| 71 | struct mlx5e_vxlan_db *vxlan_db = &priv->vxlan; | 71 | struct mlx5e_vxlan_db *vxlan_db = &priv->vxlan; |
| 72 | struct mlx5e_vxlan *vxlan; | 72 | struct mlx5e_vxlan *vxlan; |
| 73 | 73 | ||
| 74 | spin_lock(&vxlan_db->lock); | 74 | spin_lock_bh(&vxlan_db->lock); |
| 75 | vxlan = radix_tree_lookup(&vxlan_db->tree, port); | 75 | vxlan = radix_tree_lookup(&vxlan_db->tree, port); |
| 76 | spin_unlock(&vxlan_db->lock); | 76 | spin_unlock_bh(&vxlan_db->lock); |
| 77 | 77 | ||
| 78 | return vxlan; | 78 | return vxlan; |
| 79 | } | 79 | } |
| @@ -88,8 +88,12 @@ static void mlx5e_vxlan_add_port(struct work_struct *work) | |||
| 88 | struct mlx5e_vxlan *vxlan; | 88 | struct mlx5e_vxlan *vxlan; |
| 89 | int err; | 89 | int err; |
| 90 | 90 | ||
| 91 | if (mlx5e_vxlan_lookup_port(priv, port)) | 91 | mutex_lock(&priv->state_lock); |
| 92 | vxlan = mlx5e_vxlan_lookup_port(priv, port); | ||
| 93 | if (vxlan) { | ||
| 94 | atomic_inc(&vxlan->refcount); | ||
| 92 | goto free_work; | 95 | goto free_work; |
| 96 | } | ||
| 93 | 97 | ||
| 94 | if (mlx5e_vxlan_core_add_port_cmd(priv->mdev, port)) | 98 | if (mlx5e_vxlan_core_add_port_cmd(priv->mdev, port)) |
| 95 | goto free_work; | 99 | goto free_work; |
| @@ -99,10 +103,11 @@ static void mlx5e_vxlan_add_port(struct work_struct *work) | |||
| 99 | goto err_delete_port; | 103 | goto err_delete_port; |
| 100 | 104 | ||
| 101 | vxlan->udp_port = port; | 105 | vxlan->udp_port = port; |
| 106 | atomic_set(&vxlan->refcount, 1); | ||
| 102 | 107 | ||
| 103 | spin_lock_irq(&vxlan_db->lock); | 108 | spin_lock_bh(&vxlan_db->lock); |
| 104 | err = radix_tree_insert(&vxlan_db->tree, vxlan->udp_port, vxlan); | 109 | err = radix_tree_insert(&vxlan_db->tree, vxlan->udp_port, vxlan); |
| 105 | spin_unlock_irq(&vxlan_db->lock); | 110 | spin_unlock_bh(&vxlan_db->lock); |
| 106 | if (err) | 111 | if (err) |
| 107 | goto err_free; | 112 | goto err_free; |
| 108 | 113 | ||
| @@ -113,35 +118,39 @@ err_free: | |||
| 113 | err_delete_port: | 118 | err_delete_port: |
| 114 | mlx5e_vxlan_core_del_port_cmd(priv->mdev, port); | 119 | mlx5e_vxlan_core_del_port_cmd(priv->mdev, port); |
| 115 | free_work: | 120 | free_work: |
| 121 | mutex_unlock(&priv->state_lock); | ||
| 116 | kfree(vxlan_work); | 122 | kfree(vxlan_work); |
| 117 | } | 123 | } |
| 118 | 124 | ||
| 119 | static void __mlx5e_vxlan_core_del_port(struct mlx5e_priv *priv, u16 port) | 125 | static void mlx5e_vxlan_del_port(struct work_struct *work) |
| 120 | { | 126 | { |
| 127 | struct mlx5e_vxlan_work *vxlan_work = | ||
| 128 | container_of(work, struct mlx5e_vxlan_work, work); | ||
| 129 | struct mlx5e_priv *priv = vxlan_work->priv; | ||
| 121 | struct mlx5e_vxlan_db *vxlan_db = &priv->vxlan; | 130 | struct mlx5e_vxlan_db *vxlan_db = &priv->vxlan; |
| 131 | u16 port = vxlan_work->port; | ||
| 122 | struct mlx5e_vxlan *vxlan; | 132 | struct mlx5e_vxlan *vxlan; |
| 133 | bool remove = false; | ||
| 123 | 134 | ||
| 124 | spin_lock_irq(&vxlan_db->lock); | 135 | mutex_lock(&priv->state_lock); |
| 125 | vxlan = radix_tree_delete(&vxlan_db->tree, port); | 136 | spin_lock_bh(&vxlan_db->lock); |
| 126 | spin_unlock_irq(&vxlan_db->lock); | 137 | vxlan = radix_tree_lookup(&vxlan_db->tree, port); |
| 127 | |||
| 128 | if (!vxlan) | 138 | if (!vxlan) |
| 129 | return; | 139 | goto out_unlock; |
| 130 | |||
| 131 | mlx5e_vxlan_core_del_port_cmd(priv->mdev, vxlan->udp_port); | ||
| 132 | |||
| 133 | kfree(vxlan); | ||
| 134 | } | ||
| 135 | 140 | ||
| 136 | static void mlx5e_vxlan_del_port(struct work_struct *work) | 141 | if (atomic_dec_and_test(&vxlan->refcount)) { |
| 137 | { | 142 | radix_tree_delete(&vxlan_db->tree, port); |
| 138 | struct mlx5e_vxlan_work *vxlan_work = | 143 | remove = true; |
| 139 | container_of(work, struct mlx5e_vxlan_work, work); | 144 | } |
| 140 | struct mlx5e_priv *priv = vxlan_work->priv; | ||
| 141 | u16 port = vxlan_work->port; | ||
| 142 | 145 | ||
| 143 | __mlx5e_vxlan_core_del_port(priv, port); | 146 | out_unlock: |
| 147 | spin_unlock_bh(&vxlan_db->lock); | ||
| 144 | 148 | ||
| 149 | if (remove) { | ||
| 150 | mlx5e_vxlan_core_del_port_cmd(priv->mdev, port); | ||
| 151 | kfree(vxlan); | ||
| 152 | } | ||
| 153 | mutex_unlock(&priv->state_lock); | ||
| 145 | kfree(vxlan_work); | 154 | kfree(vxlan_work); |
| 146 | } | 155 | } |
| 147 | 156 | ||
| @@ -171,12 +180,11 @@ void mlx5e_vxlan_cleanup(struct mlx5e_priv *priv) | |||
| 171 | struct mlx5e_vxlan *vxlan; | 180 | struct mlx5e_vxlan *vxlan; |
| 172 | unsigned int port = 0; | 181 | unsigned int port = 0; |
| 173 | 182 | ||
| 174 | spin_lock_irq(&vxlan_db->lock); | 183 | /* Lockless since we are the only radix-tree consumers, wq is disabled */ |
| 175 | while (radix_tree_gang_lookup(&vxlan_db->tree, (void **)&vxlan, port, 1)) { | 184 | while (radix_tree_gang_lookup(&vxlan_db->tree, (void **)&vxlan, port, 1)) { |
| 176 | port = vxlan->udp_port; | 185 | port = vxlan->udp_port; |
| 177 | spin_unlock_irq(&vxlan_db->lock); | 186 | radix_tree_delete(&vxlan_db->tree, port); |
| 178 | __mlx5e_vxlan_core_del_port(priv, (u16)port); | 187 | mlx5e_vxlan_core_del_port_cmd(priv->mdev, port); |
| 179 | spin_lock_irq(&vxlan_db->lock); | 188 | kfree(vxlan); |
| 180 | } | 189 | } |
| 181 | spin_unlock_irq(&vxlan_db->lock); | ||
| 182 | } | 190 | } |
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/vxlan.h b/drivers/net/ethernet/mellanox/mlx5/core/vxlan.h index 5def12c048e3..5ef6ae7d568a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/vxlan.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/vxlan.h | |||
| @@ -36,6 +36,7 @@ | |||
| 36 | #include "en.h" | 36 | #include "en.h" |
| 37 | 37 | ||
| 38 | struct mlx5e_vxlan { | 38 | struct mlx5e_vxlan { |
| 39 | atomic_t refcount; | ||
| 39 | u16 udp_port; | 40 | u16 udp_port; |
| 40 | }; | 41 | }; |
| 41 | 42 | ||
diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index a886b51511ab..57b109c6e422 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h | |||
| @@ -556,6 +556,7 @@ struct mlx5_core_sriov { | |||
| 556 | }; | 556 | }; |
| 557 | 557 | ||
| 558 | struct mlx5_irq_info { | 558 | struct mlx5_irq_info { |
| 559 | cpumask_var_t mask; | ||
| 559 | char name[MLX5_MAX_IRQ_NAME]; | 560 | char name[MLX5_MAX_IRQ_NAME]; |
| 560 | }; | 561 | }; |
| 561 | 562 | ||
| @@ -1048,7 +1049,7 @@ int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, | |||
| 1048 | enum mlx5_eq_type type); | 1049 | enum mlx5_eq_type type); |
| 1049 | int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | 1050 | int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
| 1050 | int mlx5_start_eqs(struct mlx5_core_dev *dev); | 1051 | int mlx5_start_eqs(struct mlx5_core_dev *dev); |
| 1051 | int mlx5_stop_eqs(struct mlx5_core_dev *dev); | 1052 | void mlx5_stop_eqs(struct mlx5_core_dev *dev); |
| 1052 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, | 1053 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
| 1053 | unsigned int *irqn); | 1054 | unsigned int *irqn); |
| 1054 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | 1055 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 38a7577a9ce7..d44ec5f41d4a 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h | |||
| @@ -147,7 +147,7 @@ enum { | |||
| 147 | MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, | 147 | MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, |
| 148 | MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, | 148 | MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, |
| 149 | MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, | 149 | MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, |
| 150 | MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, | 150 | MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, |
| 151 | MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, | 151 | MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, |
| 152 | MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, | 152 | MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, |
| 153 | MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, | 153 | MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, |
| @@ -7239,7 +7239,7 @@ struct mlx5_ifc_add_vxlan_udp_dport_in_bits { | |||
| 7239 | u8 vxlan_udp_port[0x10]; | 7239 | u8 vxlan_udp_port[0x10]; |
| 7240 | }; | 7240 | }; |
| 7241 | 7241 | ||
| 7242 | struct mlx5_ifc_set_rate_limit_out_bits { | 7242 | struct mlx5_ifc_set_pp_rate_limit_out_bits { |
| 7243 | u8 status[0x8]; | 7243 | u8 status[0x8]; |
| 7244 | u8 reserved_at_8[0x18]; | 7244 | u8 reserved_at_8[0x18]; |
| 7245 | 7245 | ||
| @@ -7248,7 +7248,7 @@ struct mlx5_ifc_set_rate_limit_out_bits { | |||
| 7248 | u8 reserved_at_40[0x40]; | 7248 | u8 reserved_at_40[0x40]; |
| 7249 | }; | 7249 | }; |
| 7250 | 7250 | ||
| 7251 | struct mlx5_ifc_set_rate_limit_in_bits { | 7251 | struct mlx5_ifc_set_pp_rate_limit_in_bits { |
| 7252 | u8 opcode[0x10]; | 7252 | u8 opcode[0x10]; |
| 7253 | u8 reserved_at_10[0x10]; | 7253 | u8 reserved_at_10[0x10]; |
| 7254 | 7254 | ||
| @@ -7261,6 +7261,8 @@ struct mlx5_ifc_set_rate_limit_in_bits { | |||
| 7261 | u8 reserved_at_60[0x20]; | 7261 | u8 reserved_at_60[0x20]; |
| 7262 | 7262 | ||
| 7263 | u8 rate_limit[0x20]; | 7263 | u8 rate_limit[0x20]; |
| 7264 | |||
| 7265 | u8 reserved_at_a0[0x160]; | ||
| 7264 | }; | 7266 | }; |
| 7265 | 7267 | ||
| 7266 | struct mlx5_ifc_access_register_out_bits { | 7268 | struct mlx5_ifc_access_register_out_bits { |
