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-rw-r--r--drivers/gpu/drm/bridge/synopsys/Kconfig1
-rw-r--r--drivers/gpu/drm/mgag200/mgag200_mode.c9
-rw-r--r--drivers/gpu/drm/mxsfb/mxsfb_crtc.c42
-rw-r--r--drivers/gpu/drm/tegra/drm.c22
-rw-r--r--drivers/gpu/host1x/dev.c2
5 files changed, 57 insertions, 19 deletions
diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/bridge/synopsys/Kconfig
index 40d2827a6d19..53e78d092d18 100644
--- a/drivers/gpu/drm/bridge/synopsys/Kconfig
+++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
@@ -1,6 +1,7 @@
1config DRM_DW_HDMI 1config DRM_DW_HDMI
2 tristate 2 tristate
3 select DRM_KMS_HELPER 3 select DRM_KMS_HELPER
4 select REGMAP_MMIO
4 5
5config DRM_DW_HDMI_AHB_AUDIO 6config DRM_DW_HDMI_AHB_AUDIO
6 tristate "Synopsys Designware AHB Audio interface" 7 tristate "Synopsys Designware AHB Audio interface"
diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c
index adb411a078e8..f4b53588e071 100644
--- a/drivers/gpu/drm/mgag200/mgag200_mode.c
+++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
@@ -1173,7 +1173,10 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
1173 1173
1174 1174
1175 if (IS_G200_SE(mdev)) { 1175 if (IS_G200_SE(mdev)) {
1176 if (mdev->unique_rev_id >= 0x02) { 1176 if (mdev->unique_rev_id >= 0x04) {
1177 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1178 WREG8(MGAREG_CRTCEXT_DATA, 0);
1179 } else if (mdev->unique_rev_id >= 0x02) {
1177 u8 hi_pri_lvl; 1180 u8 hi_pri_lvl;
1178 u32 bpp; 1181 u32 bpp;
1179 u32 mb; 1182 u32 mb;
@@ -1639,6 +1642,10 @@ static int mga_vga_mode_valid(struct drm_connector *connector,
1639 if (mga_vga_calculate_mode_bandwidth(mode, bpp) 1642 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1640 > (30100 * 1024)) 1643 > (30100 * 1024))
1641 return MODE_BANDWIDTH; 1644 return MODE_BANDWIDTH;
1645 } else {
1646 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1647 > (55000 * 1024))
1648 return MODE_BANDWIDTH;
1642 } 1649 }
1643 } else if (mdev->type == G200_WB) { 1650 } else if (mdev->type == G200_WB) {
1644 if (mode->hdisplay > 1280) 1651 if (mode->hdisplay > 1280)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
index 1144e0c9e894..0abe77675b76 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
@@ -35,6 +35,13 @@
35#include "mxsfb_drv.h" 35#include "mxsfb_drv.h"
36#include "mxsfb_regs.h" 36#include "mxsfb_regs.h"
37 37
38#define MXS_SET_ADDR 0x4
39#define MXS_CLR_ADDR 0x8
40#define MODULE_CLKGATE BIT(30)
41#define MODULE_SFTRST BIT(31)
42/* 1 second delay should be plenty of time for block reset */
43#define RESET_TIMEOUT 1000000
44
38static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val) 45static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val)
39{ 46{
40 return (val & mxsfb->devdata->hs_wdth_mask) << 47 return (val & mxsfb->devdata->hs_wdth_mask) <<
@@ -159,6 +166,36 @@ static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
159 clk_disable_unprepare(mxsfb->clk_disp_axi); 166 clk_disable_unprepare(mxsfb->clk_disp_axi);
160} 167}
161 168
169/*
170 * Clear the bit and poll it cleared. This is usually called with
171 * a reset address and mask being either SFTRST(bit 31) or CLKGATE
172 * (bit 30).
173 */
174static int clear_poll_bit(void __iomem *addr, u32 mask)
175{
176 u32 reg;
177
178 writel(mask, addr + MXS_CLR_ADDR);
179 return readl_poll_timeout(addr, reg, !(reg & mask), 0, RESET_TIMEOUT);
180}
181
182static int mxsfb_reset_block(void __iomem *reset_addr)
183{
184 int ret;
185
186 ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
187 if (ret)
188 return ret;
189
190 writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR);
191
192 ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
193 if (ret)
194 return ret;
195
196 return clear_poll_bit(reset_addr, MODULE_CLKGATE);
197}
198
162static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb) 199static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
163{ 200{
164 struct drm_display_mode *m = &mxsfb->pipe.crtc.state->adjusted_mode; 201 struct drm_display_mode *m = &mxsfb->pipe.crtc.state->adjusted_mode;
@@ -173,6 +210,11 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
173 */ 210 */
174 mxsfb_enable_axi_clk(mxsfb); 211 mxsfb_enable_axi_clk(mxsfb);
175 212
213 /* Mandatory eLCDIF reset as per the Reference Manual */
214 err = mxsfb_reset_block(mxsfb->base);
215 if (err)
216 return;
217
176 /* Clear the FIFOs */ 218 /* Clear the FIFOs */
177 writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET); 219 writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);
178 220
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 9a1e34e48f64..81f86a67c10d 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -451,18 +451,6 @@ fail:
451 451
452 452
453#ifdef CONFIG_DRM_TEGRA_STAGING 453#ifdef CONFIG_DRM_TEGRA_STAGING
454static struct tegra_drm_context *
455tegra_drm_file_get_context(struct tegra_drm_file *file, u32 id)
456{
457 struct tegra_drm_context *context;
458
459 mutex_lock(&file->lock);
460 context = idr_find(&file->contexts, id);
461 mutex_unlock(&file->lock);
462
463 return context;
464}
465
466static int tegra_gem_create(struct drm_device *drm, void *data, 454static int tegra_gem_create(struct drm_device *drm, void *data,
467 struct drm_file *file) 455 struct drm_file *file)
468{ 456{
@@ -551,7 +539,7 @@ static int tegra_client_open(struct tegra_drm_file *fpriv,
551 if (err < 0) 539 if (err < 0)
552 return err; 540 return err;
553 541
554 err = idr_alloc(&fpriv->contexts, context, 0, 0, GFP_KERNEL); 542 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
555 if (err < 0) { 543 if (err < 0) {
556 client->ops->close_channel(context); 544 client->ops->close_channel(context);
557 return err; 545 return err;
@@ -606,7 +594,7 @@ static int tegra_close_channel(struct drm_device *drm, void *data,
606 594
607 mutex_lock(&fpriv->lock); 595 mutex_lock(&fpriv->lock);
608 596
609 context = tegra_drm_file_get_context(fpriv, args->context); 597 context = idr_find(&fpriv->contexts, args->context);
610 if (!context) { 598 if (!context) {
611 err = -EINVAL; 599 err = -EINVAL;
612 goto unlock; 600 goto unlock;
@@ -631,7 +619,7 @@ static int tegra_get_syncpt(struct drm_device *drm, void *data,
631 619
632 mutex_lock(&fpriv->lock); 620 mutex_lock(&fpriv->lock);
633 621
634 context = tegra_drm_file_get_context(fpriv, args->context); 622 context = idr_find(&fpriv->contexts, args->context);
635 if (!context) { 623 if (!context) {
636 err = -ENODEV; 624 err = -ENODEV;
637 goto unlock; 625 goto unlock;
@@ -660,7 +648,7 @@ static int tegra_submit(struct drm_device *drm, void *data,
660 648
661 mutex_lock(&fpriv->lock); 649 mutex_lock(&fpriv->lock);
662 650
663 context = tegra_drm_file_get_context(fpriv, args->context); 651 context = idr_find(&fpriv->contexts, args->context);
664 if (!context) { 652 if (!context) {
665 err = -ENODEV; 653 err = -ENODEV;
666 goto unlock; 654 goto unlock;
@@ -685,7 +673,7 @@ static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
685 673
686 mutex_lock(&fpriv->lock); 674 mutex_lock(&fpriv->lock);
687 675
688 context = tegra_drm_file_get_context(fpriv, args->context); 676 context = idr_find(&fpriv->contexts, args->context);
689 if (!context) { 677 if (!context) {
690 err = -ENODEV; 678 err = -ENODEV;
691 goto unlock; 679 goto unlock;
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index f05ebb14fa63..ac65f52850a6 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -172,7 +172,7 @@ static int host1x_probe(struct platform_device *pdev)
172 172
173 host->rst = devm_reset_control_get(&pdev->dev, "host1x"); 173 host->rst = devm_reset_control_get(&pdev->dev, "host1x");
174 if (IS_ERR(host->rst)) { 174 if (IS_ERR(host->rst)) {
175 err = PTR_ERR(host->clk); 175 err = PTR_ERR(host->rst);
176 dev_err(&pdev->dev, "failed to get reset: %d\n", err); 176 dev_err(&pdev->dev, "failed to get reset: %d\n", err);
177 return err; 177 return err;
178 } 178 }