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-rw-r--r--drivers/net/ethernet/intel/e1000e/80003es2lan.c12
-rw-r--r--drivers/net/ethernet/intel/e1000e/82571.c30
-rw-r--r--drivers/net/ethernet/intel/e1000e/e1000.h109
-rw-r--r--drivers/net/ethernet/intel/e1000e/ethtool.c57
-rw-r--r--drivers/net/ethernet/intel/e1000e/ich8lan.c44
-rw-r--r--drivers/net/ethernet/intel/e1000e/ich8lan.h8
-rw-r--r--drivers/net/ethernet/intel/e1000e/mac.c2
-rw-r--r--drivers/net/ethernet/intel/e1000e/netdev.c149
-rw-r--r--drivers/net/ethernet/intel/e1000e/nvm.c2
-rw-r--r--drivers/net/ethernet/intel/e1000e/phy.c4
-rw-r--r--drivers/net/ethernet/intel/e1000e/phy.h10
-rw-r--r--drivers/net/ethernet/intel/e1000e/ptp.c2
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_82575.c8
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_82575.h30
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_defines.h108
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_mac.c10
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_mbx.c4
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_nvm.c2
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_phy.h6
-rw-r--r--drivers/net/ethernet/intel/igb/igb.h40
-rw-r--r--drivers/net/ethernet/intel/igb/igb_ethtool.c18
-rw-r--r--drivers/net/ethernet/intel/igb/igb_main.c187
-rw-r--r--drivers/net/ethernet/intel/igb/igb_ptp.c42
-rw-r--r--drivers/net/ethernet/intel/igbvf/defines.h2
-rw-r--r--drivers/net/ethernet/intel/igbvf/ethtool.c3
-rw-r--r--drivers/net/ethernet/intel/igbvf/igbvf.h4
-rw-r--r--drivers/net/ethernet/intel/igbvf/netdev.c196
-rw-r--r--drivers/net/ethernet/intel/igbvf/vf.c2
28 files changed, 635 insertions, 456 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/80003es2lan.c b/drivers/net/ethernet/intel/e1000e/80003es2lan.c
index 2af603f3e418..cd391376036c 100644
--- a/drivers/net/ethernet/intel/e1000e/80003es2lan.c
+++ b/drivers/net/ethernet/intel/e1000e/80003es2lan.c
@@ -121,7 +121,7 @@ static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
121 /* EEPROM access above 16k is unsupported */ 121 /* EEPROM access above 16k is unsupported */
122 if (size > 14) 122 if (size > 14)
123 size = 14; 123 size = 14;
124 nvm->word_size = 1 << size; 124 nvm->word_size = BIT(size);
125 125
126 return 0; 126 return 0;
127} 127}
@@ -845,27 +845,27 @@ static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
845 845
846 /* Transmit Descriptor Control 0 */ 846 /* Transmit Descriptor Control 0 */
847 reg = er32(TXDCTL(0)); 847 reg = er32(TXDCTL(0));
848 reg |= (1 << 22); 848 reg |= BIT(22);
849 ew32(TXDCTL(0), reg); 849 ew32(TXDCTL(0), reg);
850 850
851 /* Transmit Descriptor Control 1 */ 851 /* Transmit Descriptor Control 1 */
852 reg = er32(TXDCTL(1)); 852 reg = er32(TXDCTL(1));
853 reg |= (1 << 22); 853 reg |= BIT(22);
854 ew32(TXDCTL(1), reg); 854 ew32(TXDCTL(1), reg);
855 855
856 /* Transmit Arbitration Control 0 */ 856 /* Transmit Arbitration Control 0 */
857 reg = er32(TARC(0)); 857 reg = er32(TARC(0));
858 reg &= ~(0xF << 27); /* 30:27 */ 858 reg &= ~(0xF << 27); /* 30:27 */
859 if (hw->phy.media_type != e1000_media_type_copper) 859 if (hw->phy.media_type != e1000_media_type_copper)
860 reg &= ~(1 << 20); 860 reg &= ~BIT(20);
861 ew32(TARC(0), reg); 861 ew32(TARC(0), reg);
862 862
863 /* Transmit Arbitration Control 1 */ 863 /* Transmit Arbitration Control 1 */
864 reg = er32(TARC(1)); 864 reg = er32(TARC(1));
865 if (er32(TCTL) & E1000_TCTL_MULR) 865 if (er32(TCTL) & E1000_TCTL_MULR)
866 reg &= ~(1 << 28); 866 reg &= ~BIT(28);
867 else 867 else
868 reg |= (1 << 28); 868 reg |= BIT(28);
869 ew32(TARC(1), reg); 869 ew32(TARC(1), reg);
870 870
871 /* Disable IPv6 extension header parsing because some malformed 871 /* Disable IPv6 extension header parsing because some malformed
diff --git a/drivers/net/ethernet/intel/e1000e/82571.c b/drivers/net/ethernet/intel/e1000e/82571.c
index 5f7016442ec4..7fd4d54599e4 100644
--- a/drivers/net/ethernet/intel/e1000e/82571.c
+++ b/drivers/net/ethernet/intel/e1000e/82571.c
@@ -185,7 +185,7 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
185 /* EEPROM access above 16k is unsupported */ 185 /* EEPROM access above 16k is unsupported */
186 if (size > 14) 186 if (size > 14)
187 size = 14; 187 size = 14;
188 nvm->word_size = 1 << size; 188 nvm->word_size = BIT(size);
189 break; 189 break;
190 } 190 }
191 191
@@ -1163,12 +1163,12 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1163 1163
1164 /* Transmit Descriptor Control 0 */ 1164 /* Transmit Descriptor Control 0 */
1165 reg = er32(TXDCTL(0)); 1165 reg = er32(TXDCTL(0));
1166 reg |= (1 << 22); 1166 reg |= BIT(22);
1167 ew32(TXDCTL(0), reg); 1167 ew32(TXDCTL(0), reg);
1168 1168
1169 /* Transmit Descriptor Control 1 */ 1169 /* Transmit Descriptor Control 1 */
1170 reg = er32(TXDCTL(1)); 1170 reg = er32(TXDCTL(1));
1171 reg |= (1 << 22); 1171 reg |= BIT(22);
1172 ew32(TXDCTL(1), reg); 1172 ew32(TXDCTL(1), reg);
1173 1173
1174 /* Transmit Arbitration Control 0 */ 1174 /* Transmit Arbitration Control 0 */
@@ -1177,11 +1177,11 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1177 switch (hw->mac.type) { 1177 switch (hw->mac.type) {
1178 case e1000_82571: 1178 case e1000_82571:
1179 case e1000_82572: 1179 case e1000_82572:
1180 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1180 reg |= BIT(23) | BIT(24) | BIT(25) | BIT(26);
1181 break; 1181 break;
1182 case e1000_82574: 1182 case e1000_82574:
1183 case e1000_82583: 1183 case e1000_82583:
1184 reg |= (1 << 26); 1184 reg |= BIT(26);
1185 break; 1185 break;
1186 default: 1186 default:
1187 break; 1187 break;
@@ -1193,12 +1193,12 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1193 switch (hw->mac.type) { 1193 switch (hw->mac.type) {
1194 case e1000_82571: 1194 case e1000_82571:
1195 case e1000_82572: 1195 case e1000_82572:
1196 reg &= ~((1 << 29) | (1 << 30)); 1196 reg &= ~(BIT(29) | BIT(30));
1197 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1197 reg |= BIT(22) | BIT(24) | BIT(25) | BIT(26);
1198 if (er32(TCTL) & E1000_TCTL_MULR) 1198 if (er32(TCTL) & E1000_TCTL_MULR)
1199 reg &= ~(1 << 28); 1199 reg &= ~BIT(28);
1200 else 1200 else
1201 reg |= (1 << 28); 1201 reg |= BIT(28);
1202 ew32(TARC(1), reg); 1202 ew32(TARC(1), reg);
1203 break; 1203 break;
1204 default: 1204 default:
@@ -1211,7 +1211,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1211 case e1000_82574: 1211 case e1000_82574:
1212 case e1000_82583: 1212 case e1000_82583:
1213 reg = er32(CTRL); 1213 reg = er32(CTRL);
1214 reg &= ~(1 << 29); 1214 reg &= ~BIT(29);
1215 ew32(CTRL, reg); 1215 ew32(CTRL, reg);
1216 break; 1216 break;
1217 default: 1217 default:
@@ -1224,8 +1224,8 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1224 case e1000_82574: 1224 case e1000_82574:
1225 case e1000_82583: 1225 case e1000_82583:
1226 reg = er32(CTRL_EXT); 1226 reg = er32(CTRL_EXT);
1227 reg &= ~(1 << 23); 1227 reg &= ~BIT(23);
1228 reg |= (1 << 22); 1228 reg |= BIT(22);
1229 ew32(CTRL_EXT, reg); 1229 ew32(CTRL_EXT, reg);
1230 break; 1230 break;
1231 default: 1231 default:
@@ -1261,7 +1261,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1261 case e1000_82574: 1261 case e1000_82574:
1262 case e1000_82583: 1262 case e1000_82583:
1263 reg = er32(GCR); 1263 reg = er32(GCR);
1264 reg |= (1 << 22); 1264 reg |= BIT(22);
1265 ew32(GCR, reg); 1265 ew32(GCR, reg);
1266 1266
1267 /* Workaround for hardware errata. 1267 /* Workaround for hardware errata.
@@ -1308,8 +1308,8 @@ static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1308 E1000_VFTA_ENTRY_SHIFT) & 1308 E1000_VFTA_ENTRY_SHIFT) &
1309 E1000_VFTA_ENTRY_MASK; 1309 E1000_VFTA_ENTRY_MASK;
1310 vfta_bit_in_reg = 1310 vfta_bit_in_reg =
1311 1 << (hw->mng_cookie.vlan_id & 1311 BIT(hw->mng_cookie.vlan_id &
1312 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1312 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1313 } 1313 }
1314 break; 1314 break;
1315 default: 1315 default:
diff --git a/drivers/net/ethernet/intel/e1000e/e1000.h b/drivers/net/ethernet/intel/e1000e/e1000.h
index 52eb641fc9dc..ef96cd11d6d2 100644
--- a/drivers/net/ethernet/intel/e1000e/e1000.h
+++ b/drivers/net/ethernet/intel/e1000e/e1000.h
@@ -109,18 +109,18 @@ struct e1000_info;
109#define E1000_TXDCTL_DMA_BURST_ENABLE \ 109#define E1000_TXDCTL_DMA_BURST_ENABLE \
110 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ 110 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
111 E1000_TXDCTL_COUNT_DESC | \ 111 E1000_TXDCTL_COUNT_DESC | \
112 (1 << 16) | /* wthresh must be +1 more than desired */\ 112 (1u << 16) | /* wthresh must be +1 more than desired */\
113 (1 << 8) | /* hthresh */ \ 113 (1u << 8) | /* hthresh */ \
114 0x1f) /* pthresh */ 114 0x1f) /* pthresh */
115 115
116#define E1000_RXDCTL_DMA_BURST_ENABLE \ 116#define E1000_RXDCTL_DMA_BURST_ENABLE \
117 (0x01000000 | /* set descriptor granularity */ \ 117 (0x01000000 | /* set descriptor granularity */ \
118 (4 << 16) | /* set writeback threshold */ \ 118 (4u << 16) | /* set writeback threshold */ \
119 (4 << 8) | /* set prefetch threshold */ \ 119 (4u << 8) | /* set prefetch threshold */ \
120 0x20) /* set hthresh */ 120 0x20) /* set hthresh */
121 121
122#define E1000_TIDV_FPD (1 << 31) 122#define E1000_TIDV_FPD BIT(31)
123#define E1000_RDTR_FPD (1 << 31) 123#define E1000_RDTR_FPD BIT(31)
124 124
125enum e1000_boards { 125enum e1000_boards {
126 board_82571, 126 board_82571,
@@ -347,6 +347,7 @@ struct e1000_adapter {
347 struct ptp_clock *ptp_clock; 347 struct ptp_clock *ptp_clock;
348 struct ptp_clock_info ptp_clock_info; 348 struct ptp_clock_info ptp_clock_info;
349 struct pm_qos_request pm_qos_req; 349 struct pm_qos_request pm_qos_req;
350 s32 ptp_delta;
350 351
351 u16 eee_advert; 352 u16 eee_advert;
352}; 353};
@@ -404,53 +405,53 @@ s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
404#define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL) 405#define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL)
405 406
406/* hardware capability, feature, and workaround flags */ 407/* hardware capability, feature, and workaround flags */
407#define FLAG_HAS_AMT (1 << 0) 408#define FLAG_HAS_AMT BIT(0)
408#define FLAG_HAS_FLASH (1 << 1) 409#define FLAG_HAS_FLASH BIT(1)
409#define FLAG_HAS_HW_VLAN_FILTER (1 << 2) 410#define FLAG_HAS_HW_VLAN_FILTER BIT(2)
410#define FLAG_HAS_WOL (1 << 3) 411#define FLAG_HAS_WOL BIT(3)
411/* reserved bit4 */ 412/* reserved BIT(4) */
412#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) 413#define FLAG_HAS_CTRLEXT_ON_LOAD BIT(5)
413#define FLAG_HAS_SWSM_ON_LOAD (1 << 6) 414#define FLAG_HAS_SWSM_ON_LOAD BIT(6)
414#define FLAG_HAS_JUMBO_FRAMES (1 << 7) 415#define FLAG_HAS_JUMBO_FRAMES BIT(7)
415#define FLAG_READ_ONLY_NVM (1 << 8) 416#define FLAG_READ_ONLY_NVM BIT(8)
416#define FLAG_IS_ICH (1 << 9) 417#define FLAG_IS_ICH BIT(9)
417#define FLAG_HAS_MSIX (1 << 10) 418#define FLAG_HAS_MSIX BIT(10)
418#define FLAG_HAS_SMART_POWER_DOWN (1 << 11) 419#define FLAG_HAS_SMART_POWER_DOWN BIT(11)
419#define FLAG_IS_QUAD_PORT_A (1 << 12) 420#define FLAG_IS_QUAD_PORT_A BIT(12)
420#define FLAG_IS_QUAD_PORT (1 << 13) 421#define FLAG_IS_QUAD_PORT BIT(13)
421#define FLAG_HAS_HW_TIMESTAMP (1 << 14) 422#define FLAG_HAS_HW_TIMESTAMP BIT(14)
422#define FLAG_APME_IN_WUC (1 << 15) 423#define FLAG_APME_IN_WUC BIT(15)
423#define FLAG_APME_IN_CTRL3 (1 << 16) 424#define FLAG_APME_IN_CTRL3 BIT(16)
424#define FLAG_APME_CHECK_PORT_B (1 << 17) 425#define FLAG_APME_CHECK_PORT_B BIT(17)
425#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18) 426#define FLAG_DISABLE_FC_PAUSE_TIME BIT(18)
426#define FLAG_NO_WAKE_UCAST (1 << 19) 427#define FLAG_NO_WAKE_UCAST BIT(19)
427#define FLAG_MNG_PT_ENABLED (1 << 20) 428#define FLAG_MNG_PT_ENABLED BIT(20)
428#define FLAG_RESET_OVERWRITES_LAA (1 << 21) 429#define FLAG_RESET_OVERWRITES_LAA BIT(21)
429#define FLAG_TARC_SPEED_MODE_BIT (1 << 22) 430#define FLAG_TARC_SPEED_MODE_BIT BIT(22)
430#define FLAG_TARC_SET_BIT_ZERO (1 << 23) 431#define FLAG_TARC_SET_BIT_ZERO BIT(23)
431#define FLAG_RX_NEEDS_RESTART (1 << 24) 432#define FLAG_RX_NEEDS_RESTART BIT(24)
432#define FLAG_LSC_GIG_SPEED_DROP (1 << 25) 433#define FLAG_LSC_GIG_SPEED_DROP BIT(25)
433#define FLAG_SMART_POWER_DOWN (1 << 26) 434#define FLAG_SMART_POWER_DOWN BIT(26)
434#define FLAG_MSI_ENABLED (1 << 27) 435#define FLAG_MSI_ENABLED BIT(27)
435/* reserved (1 << 28) */ 436/* reserved BIT(28) */
436#define FLAG_TSO_FORCE (1 << 29) 437#define FLAG_TSO_FORCE BIT(29)
437#define FLAG_RESTART_NOW (1 << 30) 438#define FLAG_RESTART_NOW BIT(30)
438#define FLAG_MSI_TEST_FAILED (1 << 31) 439#define FLAG_MSI_TEST_FAILED BIT(31)
439 440
440#define FLAG2_CRC_STRIPPING (1 << 0) 441#define FLAG2_CRC_STRIPPING BIT(0)
441#define FLAG2_HAS_PHY_WAKEUP (1 << 1) 442#define FLAG2_HAS_PHY_WAKEUP BIT(1)
442#define FLAG2_IS_DISCARDING (1 << 2) 443#define FLAG2_IS_DISCARDING BIT(2)
443#define FLAG2_DISABLE_ASPM_L1 (1 << 3) 444#define FLAG2_DISABLE_ASPM_L1 BIT(3)
444#define FLAG2_HAS_PHY_STATS (1 << 4) 445#define FLAG2_HAS_PHY_STATS BIT(4)
445#define FLAG2_HAS_EEE (1 << 5) 446#define FLAG2_HAS_EEE BIT(5)
446#define FLAG2_DMA_BURST (1 << 6) 447#define FLAG2_DMA_BURST BIT(6)
447#define FLAG2_DISABLE_ASPM_L0S (1 << 7) 448#define FLAG2_DISABLE_ASPM_L0S BIT(7)
448#define FLAG2_DISABLE_AIM (1 << 8) 449#define FLAG2_DISABLE_AIM BIT(8)
449#define FLAG2_CHECK_PHY_HANG (1 << 9) 450#define FLAG2_CHECK_PHY_HANG BIT(9)
450#define FLAG2_NO_DISABLE_RX (1 << 10) 451#define FLAG2_NO_DISABLE_RX BIT(10)
451#define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11) 452#define FLAG2_PCIM2PCI_ARBITER_WA BIT(11)
452#define FLAG2_DFLT_CRC_STRIPPING (1 << 12) 453#define FLAG2_DFLT_CRC_STRIPPING BIT(12)
453#define FLAG2_CHECK_RX_HWTSTAMP (1 << 13) 454#define FLAG2_CHECK_RX_HWTSTAMP BIT(13)
454 455
455#define E1000_RX_DESC_PS(R, i) \ 456#define E1000_RX_DESC_PS(R, i) \
456 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) 457 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
diff --git a/drivers/net/ethernet/intel/e1000e/ethtool.c b/drivers/net/ethernet/intel/e1000e/ethtool.c
index 1e3973aa707c..7aff68a4a4df 100644
--- a/drivers/net/ethernet/intel/e1000e/ethtool.c
+++ b/drivers/net/ethernet/intel/e1000e/ethtool.c
@@ -201,6 +201,9 @@ static int e1000_get_settings(struct net_device *netdev,
201 else 201 else
202 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix; 202 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix;
203 203
204 if (hw->phy.media_type != e1000_media_type_copper)
205 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_INVALID;
206
204 return 0; 207 return 0;
205} 208}
206 209
@@ -236,8 +239,13 @@ static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u32 spd, u8 dplx)
236 mac->forced_speed_duplex = ADVERTISE_100_FULL; 239 mac->forced_speed_duplex = ADVERTISE_100_FULL;
237 break; 240 break;
238 case SPEED_1000 + DUPLEX_FULL: 241 case SPEED_1000 + DUPLEX_FULL:
239 mac->autoneg = 1; 242 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
240 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 243 mac->autoneg = 1;
244 adapter->hw.phy.autoneg_advertised =
245 ADVERTISE_1000_FULL;
246 } else {
247 mac->forced_speed_duplex = ADVERTISE_1000_FULL;
248 }
241 break; 249 break;
242 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 250 case SPEED_1000 + DUPLEX_HALF: /* not supported */
243 default: 251 default:
@@ -439,8 +447,9 @@ static void e1000_get_regs(struct net_device *netdev,
439 447
440 memset(p, 0, E1000_REGS_LEN * sizeof(u32)); 448 memset(p, 0, E1000_REGS_LEN * sizeof(u32));
441 449
442 regs->version = (1 << 24) | (adapter->pdev->revision << 16) | 450 regs->version = (1u << 24) |
443 adapter->pdev->device; 451 (adapter->pdev->revision << 16) |
452 adapter->pdev->device;
444 453
445 regs_buff[0] = er32(CTRL); 454 regs_buff[0] = er32(CTRL);
446 regs_buff[1] = er32(STATUS); 455 regs_buff[1] = er32(STATUS);
@@ -895,7 +904,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
895 case e1000_pch2lan: 904 case e1000_pch2lan:
896 case e1000_pch_lpt: 905 case e1000_pch_lpt:
897 case e1000_pch_spt: 906 case e1000_pch_spt:
898 mask |= (1 << 18); 907 mask |= BIT(18);
899 break; 908 break;
900 default: 909 default:
901 break; 910 break;
@@ -914,9 +923,9 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
914 923
915 /* SHRAH[9] different than the others */ 924 /* SHRAH[9] different than the others */
916 if (i == 10) 925 if (i == 10)
917 mask |= (1 << 30); 926 mask |= BIT(30);
918 else 927 else
919 mask &= ~(1 << 30); 928 mask &= ~BIT(30);
920 } 929 }
921 if (mac->type == e1000_pch2lan) { 930 if (mac->type == e1000_pch2lan) {
922 /* SHRAH[0,1,2] different than previous */ 931 /* SHRAH[0,1,2] different than previous */
@@ -924,7 +933,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
924 mask &= 0xFFF4FFFF; 933 mask &= 0xFFF4FFFF;
925 /* SHRAH[3] different than SHRAH[0,1,2] */ 934 /* SHRAH[3] different than SHRAH[0,1,2] */
926 if (i == 4) 935 if (i == 4)
927 mask |= (1 << 30); 936 mask |= BIT(30);
928 /* RAR[1-6] owned by management engine - skipping */ 937 /* RAR[1-6] owned by management engine - skipping */
929 if (i > 0) 938 if (i > 0)
930 i += 6; 939 i += 6;
@@ -1019,7 +1028,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
1019 /* Test each interrupt */ 1028 /* Test each interrupt */
1020 for (i = 0; i < 10; i++) { 1029 for (i = 0; i < 10; i++) {
1021 /* Interrupt to test */ 1030 /* Interrupt to test */
1022 mask = 1 << i; 1031 mask = BIT(i);
1023 1032
1024 if (adapter->flags & FLAG_IS_ICH) { 1033 if (adapter->flags & FLAG_IS_ICH) {
1025 switch (mask) { 1034 switch (mask) {
@@ -1387,7 +1396,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1387 case e1000_phy_82579: 1396 case e1000_phy_82579:
1388 /* Disable PHY energy detect power down */ 1397 /* Disable PHY energy detect power down */
1389 e1e_rphy(hw, PHY_REG(0, 21), &phy_reg); 1398 e1e_rphy(hw, PHY_REG(0, 21), &phy_reg);
1390 e1e_wphy(hw, PHY_REG(0, 21), phy_reg & ~(1 << 3)); 1399 e1e_wphy(hw, PHY_REG(0, 21), phy_reg & ~BIT(3));
1391 /* Disable full chip energy detect */ 1400 /* Disable full chip energy detect */
1392 e1e_rphy(hw, PHY_REG(776, 18), &phy_reg); 1401 e1e_rphy(hw, PHY_REG(776, 18), &phy_reg);
1393 e1e_wphy(hw, PHY_REG(776, 18), phy_reg | 1); 1402 e1e_wphy(hw, PHY_REG(776, 18), phy_reg | 1);
@@ -1453,7 +1462,7 @@ static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter)
1453 1462
1454 /* disable autoneg */ 1463 /* disable autoneg */
1455 ctrl = er32(TXCW); 1464 ctrl = er32(TXCW);
1456 ctrl &= ~(1 << 31); 1465 ctrl &= ~BIT(31);
1457 ew32(TXCW, ctrl); 1466 ew32(TXCW, ctrl);
1458 1467
1459 link = (er32(STATUS) & E1000_STATUS_LU); 1468 link = (er32(STATUS) & E1000_STATUS_LU);
@@ -2283,19 +2292,19 @@ static int e1000e_get_ts_info(struct net_device *netdev,
2283 SOF_TIMESTAMPING_RX_HARDWARE | 2292 SOF_TIMESTAMPING_RX_HARDWARE |
2284 SOF_TIMESTAMPING_RAW_HARDWARE); 2293 SOF_TIMESTAMPING_RAW_HARDWARE);
2285 2294
2286 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 2295 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
2287 2296
2288 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) | 2297 info->rx_filters = (BIT(HWTSTAMP_FILTER_NONE) |
2289 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 2298 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2290 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 2299 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2291 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 2300 BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2292 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 2301 BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
2293 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 2302 BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2294 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | 2303 BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2295 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 2304 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
2296 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 2305 BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) |
2297 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 2306 BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
2298 (1 << HWTSTAMP_FILTER_ALL)); 2307 BIT(HWTSTAMP_FILTER_ALL));
2299 2308
2300 if (adapter->ptp_clock) 2309 if (adapter->ptp_clock)
2301 info->phc_index = ptp_clock_index(adapter->ptp_clock); 2310 info->phc_index = ptp_clock_index(adapter->ptp_clock);
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c b/drivers/net/ethernet/intel/e1000e/ich8lan.c
index c0f4887ea44d..3e11322d8d58 100644
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.c
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c
@@ -1048,7 +1048,7 @@ static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1048 1048
1049 while (value > PCI_LTR_VALUE_MASK) { 1049 while (value > PCI_LTR_VALUE_MASK) {
1050 scale++; 1050 scale++;
1051 value = DIV_ROUND_UP(value, (1 << 5)); 1051 value = DIV_ROUND_UP(value, BIT(5));
1052 } 1052 }
1053 if (scale > E1000_LTRV_SCALE_MAX) { 1053 if (scale > E1000_LTRV_SCALE_MAX) {
1054 e_dbg("Invalid LTR latency scale %d\n", scale); 1054 e_dbg("Invalid LTR latency scale %d\n", scale);
@@ -1573,7 +1573,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1573 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1573 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1574 1574
1575 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) 1575 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1576 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1576 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1577 1577
1578 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1578 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1579 break; 1579 break;
@@ -2044,9 +2044,9 @@ static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2044 /* Restore SMBus frequency */ 2044 /* Restore SMBus frequency */
2045 if (freq--) { 2045 if (freq--) {
2046 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 2046 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2047 phy_data |= (freq & (1 << 0)) << 2047 phy_data |= (freq & BIT(0)) <<
2048 HV_SMB_ADDR_FREQ_LOW_SHIFT; 2048 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2049 phy_data |= (freq & (1 << 1)) << 2049 phy_data |= (freq & BIT(1)) <<
2050 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 2050 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2051 } else { 2051 } else {
2052 e_dbg("Unsupported SMB frequency in PHY\n"); 2052 e_dbg("Unsupported SMB frequency in PHY\n");
@@ -2530,7 +2530,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2530 2530
2531 /* disable Rx path while enabling/disabling workaround */ 2531 /* disable Rx path while enabling/disabling workaround */
2532 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); 2532 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2533 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14)); 2533 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2534 if (ret_val) 2534 if (ret_val)
2535 return ret_val; 2535 return ret_val;
2536 2536
@@ -2561,7 +2561,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2561 2561
2562 /* Enable jumbo frame workaround in the MAC */ 2562 /* Enable jumbo frame workaround in the MAC */
2563 mac_reg = er32(FFLT_DBG); 2563 mac_reg = er32(FFLT_DBG);
2564 mac_reg &= ~(1 << 14); 2564 mac_reg &= ~BIT(14);
2565 mac_reg |= (7 << 15); 2565 mac_reg |= (7 << 15);
2566 ew32(FFLT_DBG, mac_reg); 2566 ew32(FFLT_DBG, mac_reg);
2567 2567
@@ -2576,7 +2576,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2576 return ret_val; 2576 return ret_val;
2577 ret_val = e1000e_write_kmrn_reg(hw, 2577 ret_val = e1000e_write_kmrn_reg(hw,
2578 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2578 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2579 data | (1 << 0)); 2579 data | BIT(0));
2580 if (ret_val) 2580 if (ret_val)
2581 return ret_val; 2581 return ret_val;
2582 ret_val = e1000e_read_kmrn_reg(hw, 2582 ret_val = e1000e_read_kmrn_reg(hw,
@@ -2600,7 +2600,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2600 if (ret_val) 2600 if (ret_val)
2601 return ret_val; 2601 return ret_val;
2602 e1e_rphy(hw, PHY_REG(769, 16), &data); 2602 e1e_rphy(hw, PHY_REG(769, 16), &data);
2603 data &= ~(1 << 13); 2603 data &= ~BIT(13);
2604 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2604 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2605 if (ret_val) 2605 if (ret_val)
2606 return ret_val; 2606 return ret_val;
@@ -2614,7 +2614,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2614 if (ret_val) 2614 if (ret_val)
2615 return ret_val; 2615 return ret_val;
2616 e1e_rphy(hw, HV_PM_CTRL, &data); 2616 e1e_rphy(hw, HV_PM_CTRL, &data);
2617 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10)); 2617 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2618 if (ret_val) 2618 if (ret_val)
2619 return ret_val; 2619 return ret_val;
2620 } else { 2620 } else {
@@ -2634,7 +2634,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2634 return ret_val; 2634 return ret_val;
2635 ret_val = e1000e_write_kmrn_reg(hw, 2635 ret_val = e1000e_write_kmrn_reg(hw,
2636 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2636 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2637 data & ~(1 << 0)); 2637 data & ~BIT(0));
2638 if (ret_val) 2638 if (ret_val)
2639 return ret_val; 2639 return ret_val;
2640 ret_val = e1000e_read_kmrn_reg(hw, 2640 ret_val = e1000e_read_kmrn_reg(hw,
@@ -2657,7 +2657,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2657 if (ret_val) 2657 if (ret_val)
2658 return ret_val; 2658 return ret_val;
2659 e1e_rphy(hw, PHY_REG(769, 16), &data); 2659 e1e_rphy(hw, PHY_REG(769, 16), &data);
2660 data |= (1 << 13); 2660 data |= BIT(13);
2661 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2661 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2662 if (ret_val) 2662 if (ret_val)
2663 return ret_val; 2663 return ret_val;
@@ -2671,13 +2671,13 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2671 if (ret_val) 2671 if (ret_val)
2672 return ret_val; 2672 return ret_val;
2673 e1e_rphy(hw, HV_PM_CTRL, &data); 2673 e1e_rphy(hw, HV_PM_CTRL, &data);
2674 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10)); 2674 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2675 if (ret_val) 2675 if (ret_val)
2676 return ret_val; 2676 return ret_val;
2677 } 2677 }
2678 2678
2679 /* re-enable Rx path after enabling/disabling workaround */ 2679 /* re-enable Rx path after enabling/disabling workaround */
2680 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14)); 2680 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2681} 2681}
2682 2682
2683/** 2683/**
@@ -4841,7 +4841,7 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4841 4841
4842 /* Extended Device Control */ 4842 /* Extended Device Control */
4843 reg = er32(CTRL_EXT); 4843 reg = er32(CTRL_EXT);
4844 reg |= (1 << 22); 4844 reg |= BIT(22);
4845 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 4845 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4846 if (hw->mac.type >= e1000_pchlan) 4846 if (hw->mac.type >= e1000_pchlan)
4847 reg |= E1000_CTRL_EXT_PHYPDEN; 4847 reg |= E1000_CTRL_EXT_PHYPDEN;
@@ -4849,34 +4849,34 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4849 4849
4850 /* Transmit Descriptor Control 0 */ 4850 /* Transmit Descriptor Control 0 */
4851 reg = er32(TXDCTL(0)); 4851 reg = er32(TXDCTL(0));
4852 reg |= (1 << 22); 4852 reg |= BIT(22);
4853 ew32(TXDCTL(0), reg); 4853 ew32(TXDCTL(0), reg);
4854 4854
4855 /* Transmit Descriptor Control 1 */ 4855 /* Transmit Descriptor Control 1 */
4856 reg = er32(TXDCTL(1)); 4856 reg = er32(TXDCTL(1));
4857 reg |= (1 << 22); 4857 reg |= BIT(22);
4858 ew32(TXDCTL(1), reg); 4858 ew32(TXDCTL(1), reg);
4859 4859
4860 /* Transmit Arbitration Control 0 */ 4860 /* Transmit Arbitration Control 0 */
4861 reg = er32(TARC(0)); 4861 reg = er32(TARC(0));
4862 if (hw->mac.type == e1000_ich8lan) 4862 if (hw->mac.type == e1000_ich8lan)
4863 reg |= (1 << 28) | (1 << 29); 4863 reg |= BIT(28) | BIT(29);
4864 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 4864 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4865 ew32(TARC(0), reg); 4865 ew32(TARC(0), reg);
4866 4866
4867 /* Transmit Arbitration Control 1 */ 4867 /* Transmit Arbitration Control 1 */
4868 reg = er32(TARC(1)); 4868 reg = er32(TARC(1));
4869 if (er32(TCTL) & E1000_TCTL_MULR) 4869 if (er32(TCTL) & E1000_TCTL_MULR)
4870 reg &= ~(1 << 28); 4870 reg &= ~BIT(28);
4871 else 4871 else
4872 reg |= (1 << 28); 4872 reg |= BIT(28);
4873 reg |= (1 << 24) | (1 << 26) | (1 << 30); 4873 reg |= BIT(24) | BIT(26) | BIT(30);
4874 ew32(TARC(1), reg); 4874 ew32(TARC(1), reg);
4875 4875
4876 /* Device Status */ 4876 /* Device Status */
4877 if (hw->mac.type == e1000_ich8lan) { 4877 if (hw->mac.type == e1000_ich8lan) {
4878 reg = er32(STATUS); 4878 reg = er32(STATUS);
4879 reg &= ~(1 << 31); 4879 reg &= ~BIT(31);
4880 ew32(STATUS, reg); 4880 ew32(STATUS, reg);
4881 } 4881 }
4882 4882
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.h b/drivers/net/ethernet/intel/e1000e/ich8lan.h
index 2311f6003f58..67163ca898ba 100644
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.h
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.h
@@ -73,10 +73,10 @@
73 (ID_LED_OFF1_ON2 << 4) | \ 73 (ID_LED_OFF1_ON2 << 4) | \
74 (ID_LED_DEF1_DEF2)) 74 (ID_LED_DEF1_DEF2))
75 75
76#define E1000_ICH_NVM_SIG_WORD 0x13 76#define E1000_ICH_NVM_SIG_WORD 0x13u
77#define E1000_ICH_NVM_SIG_MASK 0xC000 77#define E1000_ICH_NVM_SIG_MASK 0xC000u
78#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 78#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0u
79#define E1000_ICH_NVM_SIG_VALUE 0x80 79#define E1000_ICH_NVM_SIG_VALUE 0x80u
80 80
81#define E1000_ICH8_LAN_INIT_TIMEOUT 1500 81#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
82 82
diff --git a/drivers/net/ethernet/intel/e1000e/mac.c b/drivers/net/ethernet/intel/e1000e/mac.c
index e59d7c283cd4..b322011ec282 100644
--- a/drivers/net/ethernet/intel/e1000e/mac.c
+++ b/drivers/net/ethernet/intel/e1000e/mac.c
@@ -346,7 +346,7 @@ void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
346 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 346 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
347 hash_bit = hash_value & 0x1F; 347 hash_bit = hash_value & 0x1F;
348 348
349 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 349 hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit);
350 mc_addr_list += (ETH_ALEN); 350 mc_addr_list += (ETH_ALEN);
351 } 351 }
352 352
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index 269087cb7b96..75e60897b7e7 100644
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -317,8 +317,8 @@ static void e1000e_dump(struct e1000_adapter *adapter)
317 else 317 else
318 next_desc = ""; 318 next_desc = "";
319 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 319 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
320 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' : 320 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
321 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')), 321 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
322 i, 322 i,
323 (unsigned long long)le64_to_cpu(u0->a), 323 (unsigned long long)le64_to_cpu(u0->a),
324 (unsigned long long)le64_to_cpu(u0->b), 324 (unsigned long long)le64_to_cpu(u0->b),
@@ -2018,7 +2018,7 @@ static void e1000_configure_msix(struct e1000_adapter *adapter)
2018 adapter->eiac_mask |= E1000_IMS_OTHER; 2018 adapter->eiac_mask |= E1000_IMS_OTHER;
2019 2019
2020 /* Cause Tx interrupts on every write back */ 2020 /* Cause Tx interrupts on every write back */
2021 ivar |= (1 << 31); 2021 ivar |= BIT(31);
2022 2022
2023 ew32(IVAR, ivar); 2023 ew32(IVAR, ivar);
2024 2024
@@ -2709,7 +2709,7 @@ static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2709 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2709 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2710 index = (vid >> 5) & 0x7F; 2710 index = (vid >> 5) & 0x7F;
2711 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2711 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2712 vfta |= (1 << (vid & 0x1F)); 2712 vfta |= BIT((vid & 0x1F));
2713 hw->mac.ops.write_vfta(hw, index, vfta); 2713 hw->mac.ops.write_vfta(hw, index, vfta);
2714 } 2714 }
2715 2715
@@ -2737,7 +2737,7 @@ static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2737 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2737 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2738 index = (vid >> 5) & 0x7F; 2738 index = (vid >> 5) & 0x7F;
2739 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2739 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2740 vfta &= ~(1 << (vid & 0x1F)); 2740 vfta &= ~BIT((vid & 0x1F));
2741 hw->mac.ops.write_vfta(hw, index, vfta); 2741 hw->mac.ops.write_vfta(hw, index, vfta);
2742 } 2742 }
2743 2743
@@ -2878,7 +2878,7 @@ static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2878 2878
2879 /* Enable this decision filter in MANC2H */ 2879 /* Enable this decision filter in MANC2H */
2880 if (mdef) 2880 if (mdef)
2881 manc2h |= (1 << i); 2881 manc2h |= BIT(i);
2882 2882
2883 j |= mdef; 2883 j |= mdef;
2884 } 2884 }
@@ -2891,7 +2891,7 @@ static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2891 if (er32(MDEF(i)) == 0) { 2891 if (er32(MDEF(i)) == 0) {
2892 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2892 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2893 E1000_MDEF_PORT_664)); 2893 E1000_MDEF_PORT_664));
2894 manc2h |= (1 << 1); 2894 manc2h |= BIT(1);
2895 j++; 2895 j++;
2896 break; 2896 break;
2897 } 2897 }
@@ -2971,7 +2971,7 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
2971 /* set the speed mode bit, we'll clear it if we're not at 2971 /* set the speed mode bit, we'll clear it if we're not at
2972 * gigabit link later 2972 * gigabit link later
2973 */ 2973 */
2974#define SPEED_MODE_BIT (1 << 21) 2974#define SPEED_MODE_BIT BIT(21)
2975 tarc |= SPEED_MODE_BIT; 2975 tarc |= SPEED_MODE_BIT;
2976 ew32(TARC(0), tarc); 2976 ew32(TARC(0), tarc);
2977 } 2977 }
@@ -3071,12 +3071,12 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter)
3071 3071
3072 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3072 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3073 phy_data &= 0xfff8; 3073 phy_data &= 0xfff8;
3074 phy_data |= (1 << 2); 3074 phy_data |= BIT(2);
3075 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3075 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3076 3076
3077 e1e_rphy(hw, 22, &phy_data); 3077 e1e_rphy(hw, 22, &phy_data);
3078 phy_data &= 0x0fff; 3078 phy_data &= 0x0fff;
3079 phy_data |= (1 << 14); 3079 phy_data |= BIT(14);
3080 e1e_wphy(hw, 0x10, 0x2823); 3080 e1e_wphy(hw, 0x10, 0x2823);
3081 e1e_wphy(hw, 0x11, 0x0003); 3081 e1e_wphy(hw, 0x11, 0x0003);
3082 e1e_wphy(hw, 22, phy_data); 3082 e1e_wphy(hw, 22, phy_data);
@@ -3368,12 +3368,12 @@ static int e1000e_write_uc_addr_list(struct net_device *netdev)
3368 * combining 3368 * combining
3369 */ 3369 */
3370 netdev_for_each_uc_addr(ha, netdev) { 3370 netdev_for_each_uc_addr(ha, netdev) {
3371 int rval; 3371 int ret_val;
3372 3372
3373 if (!rar_entries) 3373 if (!rar_entries)
3374 break; 3374 break;
3375 rval = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3375 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3376 if (rval < 0) 3376 if (ret_val < 0)
3377 return -ENOMEM; 3377 return -ENOMEM;
3378 count++; 3378 count++;
3379 } 3379 }
@@ -3503,8 +3503,8 @@ s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3503 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3503 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3504 u32 fextnvm7 = er32(FEXTNVM7); 3504 u32 fextnvm7 = er32(FEXTNVM7);
3505 3505
3506 if (!(fextnvm7 & (1 << 0))) { 3506 if (!(fextnvm7 & BIT(0))) {
3507 ew32(FEXTNVM7, fextnvm7 | (1 << 0)); 3507 ew32(FEXTNVM7, fextnvm7 | BIT(0));
3508 e1e_flush(); 3508 e1e_flush();
3509 } 3509 }
3510 } 3510 }
@@ -3580,7 +3580,6 @@ static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3580 bool is_l4 = false; 3580 bool is_l4 = false;
3581 bool is_l2 = false; 3581 bool is_l2 = false;
3582 u32 regval; 3582 u32 regval;
3583 s32 ret_val;
3584 3583
3585 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3584 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3586 return -EINVAL; 3585 return -EINVAL;
@@ -3719,16 +3718,6 @@ static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3719 er32(RXSTMPH); 3718 er32(RXSTMPH);
3720 er32(TXSTMPH); 3719 er32(TXSTMPH);
3721 3720
3722 /* Get and set the System Time Register SYSTIM base frequency */
3723 ret_val = e1000e_get_base_timinca(adapter, &regval);
3724 if (ret_val)
3725 return ret_val;
3726 ew32(TIMINCA, regval);
3727
3728 /* reset the ns time counter */
3729 timecounter_init(&adapter->tc, &adapter->cc,
3730 ktime_to_ns(ktime_get_real()));
3731
3732 return 0; 3721 return 0;
3733} 3722}
3734 3723
@@ -3839,7 +3828,7 @@ static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3839 /* update thresholds: prefetch threshold to 31, host threshold to 1 3828 /* update thresholds: prefetch threshold to 31, host threshold to 1
3840 * and make sure the granularity is "descriptors" and not "cache lines" 3829 * and make sure the granularity is "descriptors" and not "cache lines"
3841 */ 3830 */
3842 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3831 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3843 3832
3844 ew32(RXDCTL(0), rxdctl); 3833 ew32(RXDCTL(0), rxdctl);
3845 /* momentarily enable the RX ring for the changes to take effect */ 3834 /* momentarily enable the RX ring for the changes to take effect */
@@ -3885,6 +3874,53 @@ static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3885} 3874}
3886 3875
3887/** 3876/**
3877 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3878 * @adapter: board private structure
3879 *
3880 * When the MAC is reset, all hardware bits for timesync will be reset to the
3881 * default values. This function will restore the settings last in place.
3882 * Since the clock SYSTIME registers are reset, we will simply restore the
3883 * cyclecounter to the kernel real clock time.
3884 **/
3885static void e1000e_systim_reset(struct e1000_adapter *adapter)
3886{
3887 struct ptp_clock_info *info = &adapter->ptp_clock_info;
3888 struct e1000_hw *hw = &adapter->hw;
3889 unsigned long flags;
3890 u32 timinca;
3891 s32 ret_val;
3892
3893 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3894 return;
3895
3896 if (info->adjfreq) {
3897 /* restore the previous ptp frequency delta */
3898 ret_val = info->adjfreq(info, adapter->ptp_delta);
3899 } else {
3900 /* set the default base frequency if no adjustment possible */
3901 ret_val = e1000e_get_base_timinca(adapter, &timinca);
3902 if (!ret_val)
3903 ew32(TIMINCA, timinca);
3904 }
3905
3906 if (ret_val) {
3907 dev_warn(&adapter->pdev->dev,
3908 "Failed to restore TIMINCA clock rate delta: %d\n",
3909 ret_val);
3910 return;
3911 }
3912
3913 /* reset the systim ns time counter */
3914 spin_lock_irqsave(&adapter->systim_lock, flags);
3915 timecounter_init(&adapter->tc, &adapter->cc,
3916 ktime_to_ns(ktime_get_real()));
3917 spin_unlock_irqrestore(&adapter->systim_lock, flags);
3918
3919 /* restore the previous hwtstamp configuration settings */
3920 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
3921}
3922
3923/**
3888 * e1000e_reset - bring the hardware into a known good state 3924 * e1000e_reset - bring the hardware into a known good state
3889 * 3925 *
3890 * This function boots the hardware and enables some settings that 3926 * This function boots the hardware and enables some settings that
@@ -4063,8 +4099,8 @@ void e1000e_reset(struct e1000_adapter *adapter)
4063 4099
4064 e1000e_reset_adaptive(hw); 4100 e1000e_reset_adaptive(hw);
4065 4101
4066 /* initialize systim and reset the ns time counter */ 4102 /* restore systim and hwtstamp settings */
4067 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config); 4103 e1000e_systim_reset(adapter);
4068 4104
4069 /* Set EEE advertisement as appropriate */ 4105 /* Set EEE advertisement as appropriate */
4070 if (adapter->flags2 & FLAG2_HAS_EEE) { 4106 if (adapter->flags2 & FLAG2_HAS_EEE) {
@@ -4275,7 +4311,7 @@ static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4275 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4311 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4276 cc); 4312 cc);
4277 struct e1000_hw *hw = &adapter->hw; 4313 struct e1000_hw *hw = &adapter->hw;
4278 u32 systimel_1, systimel_2, systimeh; 4314 u32 systimel, systimeh;
4279 cycle_t systim, systim_next; 4315 cycle_t systim, systim_next;
4280 /* SYSTIMH latching upon SYSTIML read does not work well. 4316 /* SYSTIMH latching upon SYSTIML read does not work well.
4281 * This means that if SYSTIML overflows after we read it but before 4317 * This means that if SYSTIML overflows after we read it but before
@@ -4283,24 +4319,25 @@ static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4283 * will experience a huge non linear increment in the systime value 4319 * will experience a huge non linear increment in the systime value
4284 * to fix that we test for overflow and if true, we re-read systime. 4320 * to fix that we test for overflow and if true, we re-read systime.
4285 */ 4321 */
4286 systimel_1 = er32(SYSTIML); 4322 systimel = er32(SYSTIML);
4287 systimeh = er32(SYSTIMH); 4323 systimeh = er32(SYSTIMH);
4288 systimel_2 = er32(SYSTIML); 4324 /* Is systimel is so large that overflow is possible? */
4289 /* Check for overflow. If there was no overflow, use the values */ 4325 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
4290 if (systimel_1 < systimel_2) { 4326 u32 systimel_2 = er32(SYSTIML);
4291 systim = (cycle_t)systimel_1; 4327 if (systimel > systimel_2) {
4292 systim |= (cycle_t)systimeh << 32; 4328 /* There was an overflow, read again SYSTIMH, and use
4293 } else { 4329 * systimel_2
4294 /* There was an overflow, read again SYSTIMH, and use 4330 */
4295 * systimel_2 4331 systimeh = er32(SYSTIMH);
4296 */ 4332 systimel = systimel_2;
4297 systimeh = er32(SYSTIMH); 4333 }
4298 systim = (cycle_t)systimel_2;
4299 systim |= (cycle_t)systimeh << 32;
4300 } 4334 }
4335 systim = (cycle_t)systimel;
4336 systim |= (cycle_t)systimeh << 32;
4301 4337
4302 if ((hw->mac.type == e1000_82574) || (hw->mac.type == e1000_82583)) { 4338 if ((hw->mac.type == e1000_82574) || (hw->mac.type == e1000_82583)) {
4303 u64 incvalue, time_delta, rem, temp; 4339 u64 time_delta, rem, temp;
4340 u32 incvalue;
4304 int i; 4341 int i;
4305 4342
4306 /* errata for 82574/82583 possible bad bits read from SYSTIMH/L 4343 /* errata for 82574/82583 possible bad bits read from SYSTIMH/L
@@ -6861,7 +6898,7 @@ static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6861 6898
6862 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 6899 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
6863 le16_to_cpus(&buf); 6900 le16_to_cpus(&buf);
6864 if (!ret_val && (!(buf & (1 << 0)))) { 6901 if (!ret_val && (!(buf & BIT(0)))) {
6865 /* Deep Smart Power Down (DSPD) */ 6902 /* Deep Smart Power Down (DSPD) */
6866 dev_warn(&adapter->pdev->dev, 6903 dev_warn(&adapter->pdev->dev,
6867 "Warning: detected DSPD enabled in EEPROM\n"); 6904 "Warning: detected DSPD enabled in EEPROM\n");
@@ -6965,7 +7002,7 @@ static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
6965 int bars, i, err, pci_using_dac; 7002 int bars, i, err, pci_using_dac;
6966 u16 eeprom_data = 0; 7003 u16 eeprom_data = 0;
6967 u16 eeprom_apme_mask = E1000_EEPROM_APME; 7004 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6968 s32 rval = 0; 7005 s32 ret_val = 0;
6969 7006
6970 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 7007 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6971 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7008 aspm_disable_flag = PCIE_LINK_STATE_L0S;
@@ -7200,18 +7237,18 @@ static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7200 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 7237 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7201 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 7238 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7202 (adapter->hw.bus.func == 1)) 7239 (adapter->hw.bus.func == 1))
7203 rval = e1000_read_nvm(&adapter->hw, 7240 ret_val = e1000_read_nvm(&adapter->hw,
7204 NVM_INIT_CONTROL3_PORT_B, 7241 NVM_INIT_CONTROL3_PORT_B,
7205 1, &eeprom_data); 7242 1, &eeprom_data);
7206 else 7243 else
7207 rval = e1000_read_nvm(&adapter->hw, 7244 ret_val = e1000_read_nvm(&adapter->hw,
7208 NVM_INIT_CONTROL3_PORT_A, 7245 NVM_INIT_CONTROL3_PORT_A,
7209 1, &eeprom_data); 7246 1, &eeprom_data);
7210 } 7247 }
7211 7248
7212 /* fetch WoL from EEPROM */ 7249 /* fetch WoL from EEPROM */
7213 if (rval) 7250 if (ret_val)
7214 e_dbg("NVM read error getting WoL initial values: %d\n", rval); 7251 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
7215 else if (eeprom_data & eeprom_apme_mask) 7252 else if (eeprom_data & eeprom_apme_mask)
7216 adapter->eeprom_wol |= E1000_WUFC_MAG; 7253 adapter->eeprom_wol |= E1000_WUFC_MAG;
7217 7254
@@ -7231,13 +7268,16 @@ static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7231 device_wakeup_enable(&pdev->dev); 7268 device_wakeup_enable(&pdev->dev);
7232 7269
7233 /* save off EEPROM version number */ 7270 /* save off EEPROM version number */
7234 rval = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 7271 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7235 7272
7236 if (rval) { 7273 if (ret_val) {
7237 e_dbg("NVM read error getting EEPROM version: %d\n", rval); 7274 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
7238 adapter->eeprom_vers = 0; 7275 adapter->eeprom_vers = 0;
7239 } 7276 }
7240 7277
7278 /* init PTP hardware clock */
7279 e1000e_ptp_init(adapter);
7280
7241 /* reset the hardware with the new settings */ 7281 /* reset the hardware with the new settings */
7242 e1000e_reset(adapter); 7282 e1000e_reset(adapter);
7243 7283
@@ -7256,9 +7296,6 @@ static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7256 /* carrier off reporting is important to ethtool even BEFORE open */ 7296 /* carrier off reporting is important to ethtool even BEFORE open */
7257 netif_carrier_off(netdev); 7297 netif_carrier_off(netdev);
7258 7298
7259 /* init PTP hardware clock */
7260 e1000e_ptp_init(adapter);
7261
7262 e1000_print_device_info(adapter); 7299 e1000_print_device_info(adapter);
7263 7300
7264 if (pci_dev_run_wake(pdev)) 7301 if (pci_dev_run_wake(pdev))
diff --git a/drivers/net/ethernet/intel/e1000e/nvm.c b/drivers/net/ethernet/intel/e1000e/nvm.c
index 49f205c023bf..2efd80dfd88e 100644
--- a/drivers/net/ethernet/intel/e1000e/nvm.c
+++ b/drivers/net/ethernet/intel/e1000e/nvm.c
@@ -67,7 +67,7 @@ static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
67 u32 eecd = er32(EECD); 67 u32 eecd = er32(EECD);
68 u32 mask; 68 u32 mask;
69 69
70 mask = 0x01 << (count - 1); 70 mask = BIT(count - 1);
71 if (nvm->type == e1000_nvm_eeprom_spi) 71 if (nvm->type == e1000_nvm_eeprom_spi)
72 eecd |= E1000_EECD_DO; 72 eecd |= E1000_EECD_DO;
73 73
diff --git a/drivers/net/ethernet/intel/e1000e/phy.c b/drivers/net/ethernet/intel/e1000e/phy.c
index de13aeacae97..d78d47b41a71 100644
--- a/drivers/net/ethernet/intel/e1000e/phy.c
+++ b/drivers/net/ethernet/intel/e1000e/phy.c
@@ -2894,11 +2894,11 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2894 if ((hw->phy.type == e1000_phy_82578) && 2894 if ((hw->phy.type == e1000_phy_82578) &&
2895 (hw->phy.revision >= 1) && 2895 (hw->phy.revision >= 1) &&
2896 (hw->phy.addr == 2) && 2896 (hw->phy.addr == 2) &&
2897 !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) { 2897 !(MAX_PHY_REG_ADDRESS & reg) && (data & BIT(11))) {
2898 u16 data2 = 0x7EFF; 2898 u16 data2 = 0x7EFF;
2899 2899
2900 ret_val = e1000_access_phy_debug_regs_hv(hw, 2900 ret_val = e1000_access_phy_debug_regs_hv(hw,
2901 (1 << 6) | 0x3, 2901 BIT(6) | 0x3,
2902 &data2, false); 2902 &data2, false);
2903 if (ret_val) 2903 if (ret_val)
2904 goto out; 2904 goto out;
diff --git a/drivers/net/ethernet/intel/e1000e/phy.h b/drivers/net/ethernet/intel/e1000e/phy.h
index 55bfe473514d..3027f63ee793 100644
--- a/drivers/net/ethernet/intel/e1000e/phy.h
+++ b/drivers/net/ethernet/intel/e1000e/phy.h
@@ -104,9 +104,9 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
104#define BM_WUC_DATA_OPCODE 0x12 104#define BM_WUC_DATA_OPCODE 0x12
105#define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE 105#define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE
106#define BM_WUC_ENABLE_REG 17 106#define BM_WUC_ENABLE_REG 17
107#define BM_WUC_ENABLE_BIT (1 << 2) 107#define BM_WUC_ENABLE_BIT BIT(2)
108#define BM_WUC_HOST_WU_BIT (1 << 4) 108#define BM_WUC_HOST_WU_BIT BIT(4)
109#define BM_WUC_ME_WU_BIT (1 << 5) 109#define BM_WUC_ME_WU_BIT BIT(5)
110 110
111#define PHY_UPPER_SHIFT 21 111#define PHY_UPPER_SHIFT 21
112#define BM_PHY_REG(page, reg) \ 112#define BM_PHY_REG(page, reg) \
@@ -124,8 +124,8 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
124#define I82578_ADDR_REG 29 124#define I82578_ADDR_REG 29
125#define I82577_ADDR_REG 16 125#define I82577_ADDR_REG 16
126#define I82577_CFG_REG 22 126#define I82577_CFG_REG 22
127#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) 127#define I82577_CFG_ASSERT_CRS_ON_TX BIT(15)
128#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift */ 128#define I82577_CFG_ENABLE_DOWNSHIFT (3u << 10) /* auto downshift */
129#define I82577_CTRL_REG 23 129#define I82577_CTRL_REG 23
130 130
131/* 82577 specific PHY registers */ 131/* 82577 specific PHY registers */
diff --git a/drivers/net/ethernet/intel/e1000e/ptp.c b/drivers/net/ethernet/intel/e1000e/ptp.c
index e2ff3ef75d5d..2e1b17ad52a3 100644
--- a/drivers/net/ethernet/intel/e1000e/ptp.c
+++ b/drivers/net/ethernet/intel/e1000e/ptp.c
@@ -79,6 +79,8 @@ static int e1000e_phc_adjfreq(struct ptp_clock_info *ptp, s32 delta)
79 79
80 ew32(TIMINCA, timinca); 80 ew32(TIMINCA, timinca);
81 81
82 adapter->ptp_delta = delta;
83
82 spin_unlock_irqrestore(&adapter->systim_lock, flags); 84 spin_unlock_irqrestore(&adapter->systim_lock, flags);
83 85
84 return 0; 86 return 0;
diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c
index a23aa6704394..a61447fd778e 100644
--- a/drivers/net/ethernet/intel/igb/e1000_82575.c
+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
@@ -361,7 +361,7 @@ static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
361 if (size > 15) 361 if (size > 15)
362 size = 15; 362 size = 15;
363 363
364 nvm->word_size = 1 << size; 364 nvm->word_size = BIT(size);
365 nvm->opcode_bits = 8; 365 nvm->opcode_bits = 8;
366 nvm->delay_usec = 1; 366 nvm->delay_usec = 1;
367 367
@@ -380,7 +380,7 @@ static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
380 16 : 8; 380 16 : 8;
381 break; 381 break;
382 } 382 }
383 if (nvm->word_size == (1 << 15)) 383 if (nvm->word_size == BIT(15))
384 nvm->page_size = 128; 384 nvm->page_size = 128;
385 385
386 nvm->type = e1000_nvm_eeprom_spi; 386 nvm->type = e1000_nvm_eeprom_spi;
@@ -391,7 +391,7 @@ static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
391 nvm->ops.write = igb_write_nvm_spi; 391 nvm->ops.write = igb_write_nvm_spi;
392 nvm->ops.validate = igb_validate_nvm_checksum; 392 nvm->ops.validate = igb_validate_nvm_checksum;
393 nvm->ops.update = igb_update_nvm_checksum; 393 nvm->ops.update = igb_update_nvm_checksum;
394 if (nvm->word_size < (1 << 15)) 394 if (nvm->word_size < BIT(15))
395 nvm->ops.read = igb_read_nvm_eerd; 395 nvm->ops.read = igb_read_nvm_eerd;
396 else 396 else
397 nvm->ops.read = igb_read_nvm_spi; 397 nvm->ops.read = igb_read_nvm_spi;
@@ -2107,7 +2107,7 @@ void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2107 /* The PF can spoof - it has to in order to 2107 /* The PF can spoof - it has to in order to
2108 * support emulation mode NICs 2108 * support emulation mode NICs
2109 */ 2109 */
2110 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); 2110 reg_val ^= (BIT(pf) | BIT(pf + MAX_NUM_VFS));
2111 } else { 2111 } else {
2112 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2112 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2113 E1000_DTXSWC_VLAN_SPOOF_MASK); 2113 E1000_DTXSWC_VLAN_SPOOF_MASK);
diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.h b/drivers/net/ethernet/intel/igb/e1000_82575.h
index de8805a2a2fe..199ff98209cf 100644
--- a/drivers/net/ethernet/intel/igb/e1000_82575.h
+++ b/drivers/net/ethernet/intel/igb/e1000_82575.h
@@ -168,16 +168,16 @@ struct e1000_adv_tx_context_desc {
168#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 168#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
169 169
170#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 170#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
171#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 171#define E1000_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
172#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ 172#define E1000_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */
173#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ 173#define E1000_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */
174#define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */ 174#define E1000_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */
175 175
176#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 176#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
177#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 177#define E1000_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
178#define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 178#define E1000_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */
179#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 179#define E1000_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */
180#define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 180#define E1000_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */
181 181
182/* Additional DCA related definitions, note change in position of CPUID */ 182/* Additional DCA related definitions, note change in position of CPUID */
183#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ 183#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
@@ -186,8 +186,8 @@ struct e1000_adv_tx_context_desc {
186#define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */ 186#define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
187 187
188/* ETQF register bit definitions */ 188/* ETQF register bit definitions */
189#define E1000_ETQF_FILTER_ENABLE (1 << 26) 189#define E1000_ETQF_FILTER_ENABLE BIT(26)
190#define E1000_ETQF_1588 (1 << 30) 190#define E1000_ETQF_1588 BIT(30)
191 191
192/* FTQF register bit definitions */ 192/* FTQF register bit definitions */
193#define E1000_FTQF_VF_BP 0x00008000 193#define E1000_FTQF_VF_BP 0x00008000
@@ -203,16 +203,16 @@ struct e1000_adv_tx_context_desc {
203#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */ 203#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */
204#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ 204#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
205#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 205#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
206#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */ 206#define E1000_DTXSWC_VMDQ_LOOPBACK_EN BIT(31) /* global VF LB enable */
207 207
208/* Easy defines for setting default pool, would normally be left a zero */ 208/* Easy defines for setting default pool, would normally be left a zero */
209#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 209#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
210#define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT) 210#define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
211 211
212/* Other useful VMD_CTL register defines */ 212/* Other useful VMD_CTL register defines */
213#define E1000_VT_CTL_IGNORE_MAC (1 << 28) 213#define E1000_VT_CTL_IGNORE_MAC BIT(28)
214#define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29) 214#define E1000_VT_CTL_DISABLE_DEF_POOL BIT(29)
215#define E1000_VT_CTL_VM_REPL_EN (1 << 30) 215#define E1000_VT_CTL_VM_REPL_EN BIT(30)
216 216
217/* Per VM Offload register setup */ 217/* Per VM Offload register setup */
218#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */ 218#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
@@ -252,7 +252,7 @@ struct e1000_adv_tx_context_desc {
252#define E1000_DTXCTL_MDP_EN 0x0020 252#define E1000_DTXCTL_MDP_EN 0x0020
253#define E1000_DTXCTL_SPOOF_INT 0x0040 253#define E1000_DTXCTL_SPOOF_INT 0x0040
254 254
255#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14) 255#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT BIT(14)
256 256
257#define ALL_QUEUES 0xFFFF 257#define ALL_QUEUES 0xFFFF
258 258
diff --git a/drivers/net/ethernet/intel/igb/e1000_defines.h b/drivers/net/ethernet/intel/igb/e1000_defines.h
index e9f23ee8f15e..2997c443c5dc 100644
--- a/drivers/net/ethernet/intel/igb/e1000_defines.h
+++ b/drivers/net/ethernet/intel/igb/e1000_defines.h
@@ -530,65 +530,65 @@
530 530
531/* Time Sync Interrupt Cause/Mask Register Bits */ 531/* Time Sync Interrupt Cause/Mask Register Bits */
532 532
533#define TSINTR_SYS_WRAP (1 << 0) /* SYSTIM Wrap around. */ 533#define TSINTR_SYS_WRAP BIT(0) /* SYSTIM Wrap around. */
534#define TSINTR_TXTS (1 << 1) /* Transmit Timestamp. */ 534#define TSINTR_TXTS BIT(1) /* Transmit Timestamp. */
535#define TSINTR_RXTS (1 << 2) /* Receive Timestamp. */ 535#define TSINTR_RXTS BIT(2) /* Receive Timestamp. */
536#define TSINTR_TT0 (1 << 3) /* Target Time 0 Trigger. */ 536#define TSINTR_TT0 BIT(3) /* Target Time 0 Trigger. */
537#define TSINTR_TT1 (1 << 4) /* Target Time 1 Trigger. */ 537#define TSINTR_TT1 BIT(4) /* Target Time 1 Trigger. */
538#define TSINTR_AUTT0 (1 << 5) /* Auxiliary Timestamp 0 Taken. */ 538#define TSINTR_AUTT0 BIT(5) /* Auxiliary Timestamp 0 Taken. */
539#define TSINTR_AUTT1 (1 << 6) /* Auxiliary Timestamp 1 Taken. */ 539#define TSINTR_AUTT1 BIT(6) /* Auxiliary Timestamp 1 Taken. */
540#define TSINTR_TADJ (1 << 7) /* Time Adjust Done. */ 540#define TSINTR_TADJ BIT(7) /* Time Adjust Done. */
541 541
542#define TSYNC_INTERRUPTS TSINTR_TXTS 542#define TSYNC_INTERRUPTS TSINTR_TXTS
543#define E1000_TSICR_TXTS TSINTR_TXTS 543#define E1000_TSICR_TXTS TSINTR_TXTS
544 544
545/* TSAUXC Configuration Bits */ 545/* TSAUXC Configuration Bits */
546#define TSAUXC_EN_TT0 (1 << 0) /* Enable target time 0. */ 546#define TSAUXC_EN_TT0 BIT(0) /* Enable target time 0. */
547#define TSAUXC_EN_TT1 (1 << 1) /* Enable target time 1. */ 547#define TSAUXC_EN_TT1 BIT(1) /* Enable target time 1. */
548#define TSAUXC_EN_CLK0 (1 << 2) /* Enable Configurable Frequency Clock 0. */ 548#define TSAUXC_EN_CLK0 BIT(2) /* Enable Configurable Frequency Clock 0. */
549#define TSAUXC_SAMP_AUT0 (1 << 3) /* Latch SYSTIML/H into AUXSTMPL/0. */ 549#define TSAUXC_SAMP_AUT0 BIT(3) /* Latch SYSTIML/H into AUXSTMPL/0. */
550#define TSAUXC_ST0 (1 << 4) /* Start Clock 0 Toggle on Target Time 0. */ 550#define TSAUXC_ST0 BIT(4) /* Start Clock 0 Toggle on Target Time 0. */
551#define TSAUXC_EN_CLK1 (1 << 5) /* Enable Configurable Frequency Clock 1. */ 551#define TSAUXC_EN_CLK1 BIT(5) /* Enable Configurable Frequency Clock 1. */
552#define TSAUXC_SAMP_AUT1 (1 << 6) /* Latch SYSTIML/H into AUXSTMPL/1. */ 552#define TSAUXC_SAMP_AUT1 BIT(6) /* Latch SYSTIML/H into AUXSTMPL/1. */
553#define TSAUXC_ST1 (1 << 7) /* Start Clock 1 Toggle on Target Time 1. */ 553#define TSAUXC_ST1 BIT(7) /* Start Clock 1 Toggle on Target Time 1. */
554#define TSAUXC_EN_TS0 (1 << 8) /* Enable hardware timestamp 0. */ 554#define TSAUXC_EN_TS0 BIT(8) /* Enable hardware timestamp 0. */
555#define TSAUXC_AUTT0 (1 << 9) /* Auxiliary Timestamp Taken. */ 555#define TSAUXC_AUTT0 BIT(9) /* Auxiliary Timestamp Taken. */
556#define TSAUXC_EN_TS1 (1 << 10) /* Enable hardware timestamp 0. */ 556#define TSAUXC_EN_TS1 BIT(10) /* Enable hardware timestamp 0. */
557#define TSAUXC_AUTT1 (1 << 11) /* Auxiliary Timestamp Taken. */ 557#define TSAUXC_AUTT1 BIT(11) /* Auxiliary Timestamp Taken. */
558#define TSAUXC_PLSG (1 << 17) /* Generate a pulse. */ 558#define TSAUXC_PLSG BIT(17) /* Generate a pulse. */
559#define TSAUXC_DISABLE (1 << 31) /* Disable SYSTIM Count Operation. */ 559#define TSAUXC_DISABLE BIT(31) /* Disable SYSTIM Count Operation. */
560 560
561/* SDP Configuration Bits */ 561/* SDP Configuration Bits */
562#define AUX0_SEL_SDP0 (0 << 0) /* Assign SDP0 to auxiliary time stamp 0. */ 562#define AUX0_SEL_SDP0 (0u << 0) /* Assign SDP0 to auxiliary time stamp 0. */
563#define AUX0_SEL_SDP1 (1 << 0) /* Assign SDP1 to auxiliary time stamp 0. */ 563#define AUX0_SEL_SDP1 (1u << 0) /* Assign SDP1 to auxiliary time stamp 0. */
564#define AUX0_SEL_SDP2 (2 << 0) /* Assign SDP2 to auxiliary time stamp 0. */ 564#define AUX0_SEL_SDP2 (2u << 0) /* Assign SDP2 to auxiliary time stamp 0. */
565#define AUX0_SEL_SDP3 (3 << 0) /* Assign SDP3 to auxiliary time stamp 0. */ 565#define AUX0_SEL_SDP3 (3u << 0) /* Assign SDP3 to auxiliary time stamp 0. */
566#define AUX0_TS_SDP_EN (1 << 2) /* Enable auxiliary time stamp trigger 0. */ 566#define AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */
567#define AUX1_SEL_SDP0 (0 << 3) /* Assign SDP0 to auxiliary time stamp 1. */ 567#define AUX1_SEL_SDP0 (0u << 3) /* Assign SDP0 to auxiliary time stamp 1. */
568#define AUX1_SEL_SDP1 (1 << 3) /* Assign SDP1 to auxiliary time stamp 1. */ 568#define AUX1_SEL_SDP1 (1u << 3) /* Assign SDP1 to auxiliary time stamp 1. */
569#define AUX1_SEL_SDP2 (2 << 3) /* Assign SDP2 to auxiliary time stamp 1. */ 569#define AUX1_SEL_SDP2 (2u << 3) /* Assign SDP2 to auxiliary time stamp 1. */
570#define AUX1_SEL_SDP3 (3 << 3) /* Assign SDP3 to auxiliary time stamp 1. */ 570#define AUX1_SEL_SDP3 (3u << 3) /* Assign SDP3 to auxiliary time stamp 1. */
571#define AUX1_TS_SDP_EN (1 << 5) /* Enable auxiliary time stamp trigger 1. */ 571#define AUX1_TS_SDP_EN (1u << 5) /* Enable auxiliary time stamp trigger 1. */
572#define TS_SDP0_SEL_TT0 (0 << 6) /* Target time 0 is output on SDP0. */ 572#define TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0. */
573#define TS_SDP0_SEL_TT1 (1 << 6) /* Target time 1 is output on SDP0. */ 573#define TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */
574#define TS_SDP0_SEL_FC0 (2 << 6) /* Freq clock 0 is output on SDP0. */ 574#define TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */
575#define TS_SDP0_SEL_FC1 (3 << 6) /* Freq clock 1 is output on SDP0. */ 575#define TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */
576#define TS_SDP0_EN (1 << 8) /* SDP0 is assigned to Tsync. */ 576#define TS_SDP0_EN (1u << 8) /* SDP0 is assigned to Tsync. */
577#define TS_SDP1_SEL_TT0 (0 << 9) /* Target time 0 is output on SDP1. */ 577#define TS_SDP1_SEL_TT0 (0u << 9) /* Target time 0 is output on SDP1. */
578#define TS_SDP1_SEL_TT1 (1 << 9) /* Target time 1 is output on SDP1. */ 578#define TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1. */
579#define TS_SDP1_SEL_FC0 (2 << 9) /* Freq clock 0 is output on SDP1. */ 579#define TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */
580#define TS_SDP1_SEL_FC1 (3 << 9) /* Freq clock 1 is output on SDP1. */ 580#define TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */
581#define TS_SDP1_EN (1 << 11) /* SDP1 is assigned to Tsync. */ 581#define TS_SDP1_EN (1u << 11) /* SDP1 is assigned to Tsync. */
582#define TS_SDP2_SEL_TT0 (0 << 12) /* Target time 0 is output on SDP2. */ 582#define TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2. */
583#define TS_SDP2_SEL_TT1 (1 << 12) /* Target time 1 is output on SDP2. */ 583#define TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */
584#define TS_SDP2_SEL_FC0 (2 << 12) /* Freq clock 0 is output on SDP2. */ 584#define TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */
585#define TS_SDP2_SEL_FC1 (3 << 12) /* Freq clock 1 is output on SDP2. */ 585#define TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */
586#define TS_SDP2_EN (1 << 14) /* SDP2 is assigned to Tsync. */ 586#define TS_SDP2_EN (1u << 14) /* SDP2 is assigned to Tsync. */
587#define TS_SDP3_SEL_TT0 (0 << 15) /* Target time 0 is output on SDP3. */ 587#define TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3. */
588#define TS_SDP3_SEL_TT1 (1 << 15) /* Target time 1 is output on SDP3. */ 588#define TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */
589#define TS_SDP3_SEL_FC0 (2 << 15) /* Freq clock 0 is output on SDP3. */ 589#define TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */
590#define TS_SDP3_SEL_FC1 (3 << 15) /* Freq clock 1 is output on SDP3. */ 590#define TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */
591#define TS_SDP3_EN (1 << 17) /* SDP3 is assigned to Tsync. */ 591#define TS_SDP3_EN (1u << 17) /* SDP3 is assigned to Tsync. */
592 592
593#define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ 593#define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */
594#define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ 594#define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */
@@ -997,8 +997,8 @@
997#define E1000_M88E1543_FIBER_CTRL 0x0 997#define E1000_M88E1543_FIBER_CTRL 0x0
998#define E1000_EEE_ADV_DEV_I354 7 998#define E1000_EEE_ADV_DEV_I354 7
999#define E1000_EEE_ADV_ADDR_I354 60 999#define E1000_EEE_ADV_ADDR_I354 60
1000#define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */ 1000#define E1000_EEE_ADV_100_SUPPORTED BIT(1) /* 100BaseTx EEE Supported */
1001#define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */ 1001#define E1000_EEE_ADV_1000_SUPPORTED BIT(2) /* 1000BaseT EEE Supported */
1002#define E1000_PCS_STATUS_DEV_I354 3 1002#define E1000_PCS_STATUS_DEV_I354 3
1003#define E1000_PCS_STATUS_ADDR_I354 1 1003#define E1000_PCS_STATUS_ADDR_I354 1
1004#define E1000_PCS_STATUS_TX_LPI_IND 0x0200 /* Tx in LPI state */ 1004#define E1000_PCS_STATUS_TX_LPI_IND 0x0200 /* Tx in LPI state */
diff --git a/drivers/net/ethernet/intel/igb/e1000_mac.c b/drivers/net/ethernet/intel/igb/e1000_mac.c
index 07cf4fe58338..5010e2232c50 100644
--- a/drivers/net/ethernet/intel/igb/e1000_mac.c
+++ b/drivers/net/ethernet/intel/igb/e1000_mac.c
@@ -212,7 +212,7 @@ s32 igb_vfta_set(struct e1000_hw *hw, u32 vlan, u32 vind,
212 * bits[4-0]: which bit in the register 212 * bits[4-0]: which bit in the register
213 */ 213 */
214 regidx = vlan / 32; 214 regidx = vlan / 32;
215 vfta_delta = 1 << (vlan % 32); 215 vfta_delta = BIT(vlan % 32);
216 vfta = adapter->shadow_vfta[regidx]; 216 vfta = adapter->shadow_vfta[regidx];
217 217
218 /* vfta_delta represents the difference between the current value 218 /* vfta_delta represents the difference between the current value
@@ -243,12 +243,12 @@ s32 igb_vfta_set(struct e1000_hw *hw, u32 vlan, u32 vind,
243 bits = rd32(E1000_VLVF(vlvf_index)); 243 bits = rd32(E1000_VLVF(vlvf_index));
244 244
245 /* set the pool bit */ 245 /* set the pool bit */
246 bits |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vind); 246 bits |= BIT(E1000_VLVF_POOLSEL_SHIFT + vind);
247 if (vlan_on) 247 if (vlan_on)
248 goto vlvf_update; 248 goto vlvf_update;
249 249
250 /* clear the pool bit */ 250 /* clear the pool bit */
251 bits ^= 1 << (E1000_VLVF_POOLSEL_SHIFT + vind); 251 bits ^= BIT(E1000_VLVF_POOLSEL_SHIFT + vind);
252 252
253 if (!(bits & E1000_VLVF_POOLSEL_MASK)) { 253 if (!(bits & E1000_VLVF_POOLSEL_MASK)) {
254 /* Clear VFTA first, then disable VLVF. Otherwise 254 /* Clear VFTA first, then disable VLVF. Otherwise
@@ -427,7 +427,7 @@ void igb_mta_set(struct e1000_hw *hw, u32 hash_value)
427 427
428 mta = array_rd32(E1000_MTA, hash_reg); 428 mta = array_rd32(E1000_MTA, hash_reg);
429 429
430 mta |= (1 << hash_bit); 430 mta |= BIT(hash_bit);
431 431
432 array_wr32(E1000_MTA, hash_reg, mta); 432 array_wr32(E1000_MTA, hash_reg, mta);
433 wrfl(); 433 wrfl();
@@ -527,7 +527,7 @@ void igb_update_mc_addr_list(struct e1000_hw *hw,
527 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 527 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
528 hash_bit = hash_value & 0x1F; 528 hash_bit = hash_value & 0x1F;
529 529
530 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 530 hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit);
531 mc_addr_list += (ETH_ALEN); 531 mc_addr_list += (ETH_ALEN);
532 } 532 }
533 533
diff --git a/drivers/net/ethernet/intel/igb/e1000_mbx.c b/drivers/net/ethernet/intel/igb/e1000_mbx.c
index 10f5c9e016a9..00e263f0c030 100644
--- a/drivers/net/ethernet/intel/igb/e1000_mbx.c
+++ b/drivers/net/ethernet/intel/igb/e1000_mbx.c
@@ -302,9 +302,9 @@ static s32 igb_check_for_rst_pf(struct e1000_hw *hw, u16 vf_number)
302 u32 vflre = rd32(E1000_VFLRE); 302 u32 vflre = rd32(E1000_VFLRE);
303 s32 ret_val = -E1000_ERR_MBX; 303 s32 ret_val = -E1000_ERR_MBX;
304 304
305 if (vflre & (1 << vf_number)) { 305 if (vflre & BIT(vf_number)) {
306 ret_val = 0; 306 ret_val = 0;
307 wr32(E1000_VFLRE, (1 << vf_number)); 307 wr32(E1000_VFLRE, BIT(vf_number));
308 hw->mbx.stats.rsts++; 308 hw->mbx.stats.rsts++;
309 } 309 }
310 310
diff --git a/drivers/net/ethernet/intel/igb/e1000_nvm.c b/drivers/net/ethernet/intel/igb/e1000_nvm.c
index e8280d0d7f02..3582c5cf8843 100644
--- a/drivers/net/ethernet/intel/igb/e1000_nvm.c
+++ b/drivers/net/ethernet/intel/igb/e1000_nvm.c
@@ -72,7 +72,7 @@ static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
72 u32 eecd = rd32(E1000_EECD); 72 u32 eecd = rd32(E1000_EECD);
73 u32 mask; 73 u32 mask;
74 74
75 mask = 0x01 << (count - 1); 75 mask = 1u << (count - 1);
76 if (nvm->type == e1000_nvm_eeprom_spi) 76 if (nvm->type == e1000_nvm_eeprom_spi)
77 eecd |= E1000_EECD_DO; 77 eecd |= E1000_EECD_DO;
78 78
diff --git a/drivers/net/ethernet/intel/igb/e1000_phy.h b/drivers/net/ethernet/intel/igb/e1000_phy.h
index 969a6ddafa3b..9b622b33bb5a 100644
--- a/drivers/net/ethernet/intel/igb/e1000_phy.h
+++ b/drivers/net/ethernet/intel/igb/e1000_phy.h
@@ -91,10 +91,10 @@ s32 igb_check_polarity_m88(struct e1000_hw *hw);
91 91
92#define I82580_ADDR_REG 16 92#define I82580_ADDR_REG 16
93#define I82580_CFG_REG 22 93#define I82580_CFG_REG 22
94#define I82580_CFG_ASSERT_CRS_ON_TX (1 << 15) 94#define I82580_CFG_ASSERT_CRS_ON_TX BIT(15)
95#define I82580_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ 95#define I82580_CFG_ENABLE_DOWNSHIFT (3u << 10) /* auto downshift 100/10 */
96#define I82580_CTRL_REG 23 96#define I82580_CTRL_REG 23
97#define I82580_CTRL_DOWNSHIFT_MASK (7 << 10) 97#define I82580_CTRL_DOWNSHIFT_MASK (7u << 10)
98 98
99/* 82580 specific PHY registers */ 99/* 82580 specific PHY registers */
100#define I82580_PHY_CTRL_2 18 100#define I82580_PHY_CTRL_2 18
diff --git a/drivers/net/ethernet/intel/igb/igb.h b/drivers/net/ethernet/intel/igb/igb.h
index 9413fa61392f..b9609afa5ca3 100644
--- a/drivers/net/ethernet/intel/igb/igb.h
+++ b/drivers/net/ethernet/intel/igb/igb.h
@@ -91,6 +91,14 @@ struct igb_adapter;
91#define NVM_COMB_VER_OFF 0x0083 91#define NVM_COMB_VER_OFF 0x0083
92#define NVM_COMB_VER_PTR 0x003d 92#define NVM_COMB_VER_PTR 0x003d
93 93
94/* Transmit and receive latency (for PTP timestamps) */
95#define IGB_I210_TX_LATENCY_10 9542
96#define IGB_I210_TX_LATENCY_100 1024
97#define IGB_I210_TX_LATENCY_1000 178
98#define IGB_I210_RX_LATENCY_10 20662
99#define IGB_I210_RX_LATENCY_100 2213
100#define IGB_I210_RX_LATENCY_1000 448
101
94struct vf_data_storage { 102struct vf_data_storage {
95 unsigned char vf_mac_addresses[ETH_ALEN]; 103 unsigned char vf_mac_addresses[ETH_ALEN];
96 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; 104 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
@@ -169,7 +177,7 @@ enum igb_tx_flags {
169 * maintain a power of two alignment we have to limit ourselves to 32K. 177 * maintain a power of two alignment we have to limit ourselves to 32K.
170 */ 178 */
171#define IGB_MAX_TXD_PWR 15 179#define IGB_MAX_TXD_PWR 15
172#define IGB_MAX_DATA_PER_TXD (1 << IGB_MAX_TXD_PWR) 180#define IGB_MAX_DATA_PER_TXD (1u << IGB_MAX_TXD_PWR)
173 181
174/* Tx Descriptors needed, worst case */ 182/* Tx Descriptors needed, worst case */
175#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD) 183#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
@@ -466,21 +474,21 @@ struct igb_adapter {
466 u16 eee_advert; 474 u16 eee_advert;
467}; 475};
468 476
469#define IGB_FLAG_HAS_MSI (1 << 0) 477#define IGB_FLAG_HAS_MSI BIT(0)
470#define IGB_FLAG_DCA_ENABLED (1 << 1) 478#define IGB_FLAG_DCA_ENABLED BIT(1)
471#define IGB_FLAG_QUAD_PORT_A (1 << 2) 479#define IGB_FLAG_QUAD_PORT_A BIT(2)
472#define IGB_FLAG_QUEUE_PAIRS (1 << 3) 480#define IGB_FLAG_QUEUE_PAIRS BIT(3)
473#define IGB_FLAG_DMAC (1 << 4) 481#define IGB_FLAG_DMAC BIT(4)
474#define IGB_FLAG_PTP (1 << 5) 482#define IGB_FLAG_PTP BIT(5)
475#define IGB_FLAG_RSS_FIELD_IPV4_UDP (1 << 6) 483#define IGB_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
476#define IGB_FLAG_RSS_FIELD_IPV6_UDP (1 << 7) 484#define IGB_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
477#define IGB_FLAG_WOL_SUPPORTED (1 << 8) 485#define IGB_FLAG_WOL_SUPPORTED BIT(8)
478#define IGB_FLAG_NEED_LINK_UPDATE (1 << 9) 486#define IGB_FLAG_NEED_LINK_UPDATE BIT(9)
479#define IGB_FLAG_MEDIA_RESET (1 << 10) 487#define IGB_FLAG_MEDIA_RESET BIT(10)
480#define IGB_FLAG_MAS_CAPABLE (1 << 11) 488#define IGB_FLAG_MAS_CAPABLE BIT(11)
481#define IGB_FLAG_MAS_ENABLE (1 << 12) 489#define IGB_FLAG_MAS_ENABLE BIT(12)
482#define IGB_FLAG_HAS_MSIX (1 << 13) 490#define IGB_FLAG_HAS_MSIX BIT(13)
483#define IGB_FLAG_EEE (1 << 14) 491#define IGB_FLAG_EEE BIT(14)
484#define IGB_FLAG_VLAN_PROMISC BIT(15) 492#define IGB_FLAG_VLAN_PROMISC BIT(15)
485 493
486/* Media Auto Sense */ 494/* Media Auto Sense */
diff --git a/drivers/net/ethernet/intel/igb/igb_ethtool.c b/drivers/net/ethernet/intel/igb/igb_ethtool.c
index bb4d6cdcd0b8..64e91c575a39 100644
--- a/drivers/net/ethernet/intel/igb/igb_ethtool.c
+++ b/drivers/net/ethernet/intel/igb/igb_ethtool.c
@@ -466,7 +466,7 @@ static void igb_get_regs(struct net_device *netdev,
466 466
467 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); 467 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
468 468
469 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; 469 regs->version = (1u << 24) | (hw->revision_id << 16) | hw->device_id;
470 470
471 /* General Registers */ 471 /* General Registers */
472 regs_buff[0] = rd32(E1000_CTRL); 472 regs_buff[0] = rd32(E1000_CTRL);
@@ -1448,7 +1448,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1448 /* Test each interrupt */ 1448 /* Test each interrupt */
1449 for (; i < 31; i++) { 1449 for (; i < 31; i++) {
1450 /* Interrupt to test */ 1450 /* Interrupt to test */
1451 mask = 1 << i; 1451 mask = BIT(i);
1452 1452
1453 if (!(mask & ics_mask)) 1453 if (!(mask & ics_mask))
1454 continue; 1454 continue;
@@ -2411,19 +2411,19 @@ static int igb_get_ts_info(struct net_device *dev,
2411 SOF_TIMESTAMPING_RAW_HARDWARE; 2411 SOF_TIMESTAMPING_RAW_HARDWARE;
2412 2412
2413 info->tx_types = 2413 info->tx_types =
2414 (1 << HWTSTAMP_TX_OFF) | 2414 BIT(HWTSTAMP_TX_OFF) |
2415 (1 << HWTSTAMP_TX_ON); 2415 BIT(HWTSTAMP_TX_ON);
2416 2416
2417 info->rx_filters = 1 << HWTSTAMP_FILTER_NONE; 2417 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE);
2418 2418
2419 /* 82576 does not support timestamping all packets. */ 2419 /* 82576 does not support timestamping all packets. */
2420 if (adapter->hw.mac.type >= e1000_82580) 2420 if (adapter->hw.mac.type >= e1000_82580)
2421 info->rx_filters |= 1 << HWTSTAMP_FILTER_ALL; 2421 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL);
2422 else 2422 else
2423 info->rx_filters |= 2423 info->rx_filters |=
2424 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 2424 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2425 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 2425 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2426 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 2426 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);
2427 2427
2428 return 0; 2428 return 0;
2429 default: 2429 default:
diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c
index 7460bdbe2e49..21727692bef6 100644
--- a/drivers/net/ethernet/intel/igb/igb_main.c
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
@@ -836,7 +836,7 @@ static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
836 igb_write_ivar(hw, msix_vector, 836 igb_write_ivar(hw, msix_vector,
837 tx_queue & 0x7, 837 tx_queue & 0x7,
838 ((tx_queue & 0x8) << 1) + 8); 838 ((tx_queue & 0x8) << 1) + 8);
839 q_vector->eims_value = 1 << msix_vector; 839 q_vector->eims_value = BIT(msix_vector);
840 break; 840 break;
841 case e1000_82580: 841 case e1000_82580:
842 case e1000_i350: 842 case e1000_i350:
@@ -857,7 +857,7 @@ static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
857 igb_write_ivar(hw, msix_vector, 857 igb_write_ivar(hw, msix_vector,
858 tx_queue >> 1, 858 tx_queue >> 1,
859 ((tx_queue & 0x1) << 4) + 8); 859 ((tx_queue & 0x1) << 4) + 8);
860 q_vector->eims_value = 1 << msix_vector; 860 q_vector->eims_value = BIT(msix_vector);
861 break; 861 break;
862 default: 862 default:
863 BUG(); 863 BUG();
@@ -919,7 +919,7 @@ static void igb_configure_msix(struct igb_adapter *adapter)
919 E1000_GPIE_NSICR); 919 E1000_GPIE_NSICR);
920 920
921 /* enable msix_other interrupt */ 921 /* enable msix_other interrupt */
922 adapter->eims_other = 1 << vector; 922 adapter->eims_other = BIT(vector);
923 tmp = (vector++ | E1000_IVAR_VALID) << 8; 923 tmp = (vector++ | E1000_IVAR_VALID) << 8;
924 924
925 wr32(E1000_IVAR_MISC, tmp); 925 wr32(E1000_IVAR_MISC, tmp);
@@ -2087,6 +2087,40 @@ static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2087 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2087 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2088} 2088}
2089 2089
2090#define IGB_MAX_MAC_HDR_LEN 127
2091#define IGB_MAX_NETWORK_HDR_LEN 511
2092
2093static netdev_features_t
2094igb_features_check(struct sk_buff *skb, struct net_device *dev,
2095 netdev_features_t features)
2096{
2097 unsigned int network_hdr_len, mac_hdr_len;
2098
2099 /* Make certain the headers can be described by a context descriptor */
2100 mac_hdr_len = skb_network_header(skb) - skb->data;
2101 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2102 return features & ~(NETIF_F_HW_CSUM |
2103 NETIF_F_SCTP_CRC |
2104 NETIF_F_HW_VLAN_CTAG_TX |
2105 NETIF_F_TSO |
2106 NETIF_F_TSO6);
2107
2108 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2109 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN))
2110 return features & ~(NETIF_F_HW_CSUM |
2111 NETIF_F_SCTP_CRC |
2112 NETIF_F_TSO |
2113 NETIF_F_TSO6);
2114
2115 /* We can only support IPV4 TSO in tunnels if we can mangle the
2116 * inner IP ID field, so strip TSO if MANGLEID is not supported.
2117 */
2118 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2119 features &= ~NETIF_F_TSO;
2120
2121 return features;
2122}
2123
2090static const struct net_device_ops igb_netdev_ops = { 2124static const struct net_device_ops igb_netdev_ops = {
2091 .ndo_open = igb_open, 2125 .ndo_open = igb_open,
2092 .ndo_stop = igb_close, 2126 .ndo_stop = igb_close,
@@ -2111,7 +2145,7 @@ static const struct net_device_ops igb_netdev_ops = {
2111 .ndo_fix_features = igb_fix_features, 2145 .ndo_fix_features = igb_fix_features,
2112 .ndo_set_features = igb_set_features, 2146 .ndo_set_features = igb_set_features,
2113 .ndo_fdb_add = igb_ndo_fdb_add, 2147 .ndo_fdb_add = igb_ndo_fdb_add,
2114 .ndo_features_check = passthru_features_check, 2148 .ndo_features_check = igb_features_check,
2115}; 2149};
2116 2150
2117/** 2151/**
@@ -2377,38 +2411,43 @@ static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2377 NETIF_F_TSO6 | 2411 NETIF_F_TSO6 |
2378 NETIF_F_RXHASH | 2412 NETIF_F_RXHASH |
2379 NETIF_F_RXCSUM | 2413 NETIF_F_RXCSUM |
2380 NETIF_F_HW_CSUM | 2414 NETIF_F_HW_CSUM;
2381 NETIF_F_HW_VLAN_CTAG_RX |
2382 NETIF_F_HW_VLAN_CTAG_TX;
2383 2415
2384 if (hw->mac.type >= e1000_82576) 2416 if (hw->mac.type >= e1000_82576)
2385 netdev->features |= NETIF_F_SCTP_CRC; 2417 netdev->features |= NETIF_F_SCTP_CRC;
2386 2418
2419#define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
2420 NETIF_F_GSO_GRE_CSUM | \
2421 NETIF_F_GSO_IPIP | \
2422 NETIF_F_GSO_SIT | \
2423 NETIF_F_GSO_UDP_TUNNEL | \
2424 NETIF_F_GSO_UDP_TUNNEL_CSUM)
2425
2426 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
2427 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
2428
2387 /* copy netdev features into list of user selectable features */ 2429 /* copy netdev features into list of user selectable features */
2388 netdev->hw_features |= netdev->features; 2430 netdev->hw_features |= netdev->features |
2389 netdev->hw_features |= NETIF_F_RXALL; 2431 NETIF_F_HW_VLAN_CTAG_RX |
2432 NETIF_F_HW_VLAN_CTAG_TX |
2433 NETIF_F_RXALL;
2390 2434
2391 if (hw->mac.type >= e1000_i350) 2435 if (hw->mac.type >= e1000_i350)
2392 netdev->hw_features |= NETIF_F_NTUPLE; 2436 netdev->hw_features |= NETIF_F_NTUPLE;
2393 2437
2394 /* set this bit last since it cannot be part of hw_features */ 2438 if (pci_using_dac)
2395 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2439 netdev->features |= NETIF_F_HIGHDMA;
2396
2397 netdev->vlan_features |= NETIF_F_SG |
2398 NETIF_F_TSO |
2399 NETIF_F_TSO6 |
2400 NETIF_F_HW_CSUM |
2401 NETIF_F_SCTP_CRC;
2402 2440
2441 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
2403 netdev->mpls_features |= NETIF_F_HW_CSUM; 2442 netdev->mpls_features |= NETIF_F_HW_CSUM;
2404 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 2443 netdev->hw_enc_features |= netdev->vlan_features;
2405 2444
2406 netdev->priv_flags |= IFF_SUPP_NOFCS; 2445 /* set this bit last since it cannot be part of vlan_features */
2446 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
2447 NETIF_F_HW_VLAN_CTAG_RX |
2448 NETIF_F_HW_VLAN_CTAG_TX;
2407 2449
2408 if (pci_using_dac) { 2450 netdev->priv_flags |= IFF_SUPP_NOFCS;
2409 netdev->features |= NETIF_F_HIGHDMA;
2410 netdev->vlan_features |= NETIF_F_HIGHDMA;
2411 }
2412 2451
2413 netdev->priv_flags |= IFF_UNICAST_FLT; 2452 netdev->priv_flags |= IFF_UNICAST_FLT;
2414 2453
@@ -4064,7 +4103,7 @@ static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
4064 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4103 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4065 u32 vlvf = rd32(E1000_VLVF(i)); 4104 u32 vlvf = rd32(E1000_VLVF(i));
4066 4105
4067 vlvf |= 1 << pf_id; 4106 vlvf |= BIT(pf_id);
4068 wr32(E1000_VLVF(i), vlvf); 4107 wr32(E1000_VLVF(i), vlvf);
4069 } 4108 }
4070 4109
@@ -4091,7 +4130,7 @@ static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
4091 /* guarantee that we don't scrub out management VLAN */ 4130 /* guarantee that we don't scrub out management VLAN */
4092 vid = adapter->mng_vlan_id; 4131 vid = adapter->mng_vlan_id;
4093 if (vid >= vid_start && vid < vid_end) 4132 if (vid >= vid_start && vid < vid_end)
4094 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32); 4133 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4095 4134
4096 if (!adapter->vfs_allocated_count) 4135 if (!adapter->vfs_allocated_count)
4097 goto set_vfta; 4136 goto set_vfta;
@@ -4110,7 +4149,7 @@ static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
4110 4149
4111 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 4150 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
4112 /* record VLAN ID in VFTA */ 4151 /* record VLAN ID in VFTA */
4113 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32); 4152 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4114 4153
4115 /* if PF is part of this then continue */ 4154 /* if PF is part of this then continue */
4116 if (test_bit(vid, adapter->active_vlans)) 4155 if (test_bit(vid, adapter->active_vlans))
@@ -4118,7 +4157,7 @@ static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
4118 } 4157 }
4119 4158
4120 /* remove PF from the pool */ 4159 /* remove PF from the pool */
4121 bits = ~(1 << pf_id); 4160 bits = ~BIT(pf_id);
4122 bits &= rd32(E1000_VLVF(i)); 4161 bits &= rd32(E1000_VLVF(i));
4123 wr32(E1000_VLVF(i), bits); 4162 wr32(E1000_VLVF(i), bits);
4124 } 4163 }
@@ -4276,13 +4315,13 @@ static void igb_spoof_check(struct igb_adapter *adapter)
4276 return; 4315 return;
4277 4316
4278 for (j = 0; j < adapter->vfs_allocated_count; j++) { 4317 for (j = 0; j < adapter->vfs_allocated_count; j++) {
4279 if (adapter->wvbr & (1 << j) || 4318 if (adapter->wvbr & BIT(j) ||
4280 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 4319 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) {
4281 dev_warn(&adapter->pdev->dev, 4320 dev_warn(&adapter->pdev->dev,
4282 "Spoof event(s) detected on VF %d\n", j); 4321 "Spoof event(s) detected on VF %d\n", j);
4283 adapter->wvbr &= 4322 adapter->wvbr &=
4284 ~((1 << j) | 4323 ~(BIT(j) |
4285 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 4324 BIT(j + IGB_STAGGERED_QUEUE_OFFSET));
4286 } 4325 }
4287 } 4326 }
4288} 4327}
@@ -4842,9 +4881,18 @@ static int igb_tso(struct igb_ring *tx_ring,
4842 struct igb_tx_buffer *first, 4881 struct igb_tx_buffer *first,
4843 u8 *hdr_len) 4882 u8 *hdr_len)
4844{ 4883{
4884 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
4845 struct sk_buff *skb = first->skb; 4885 struct sk_buff *skb = first->skb;
4846 u32 vlan_macip_lens, type_tucmd; 4886 union {
4847 u32 mss_l4len_idx, l4len; 4887 struct iphdr *v4;
4888 struct ipv6hdr *v6;
4889 unsigned char *hdr;
4890 } ip;
4891 union {
4892 struct tcphdr *tcp;
4893 unsigned char *hdr;
4894 } l4;
4895 u32 paylen, l4_offset;
4848 int err; 4896 int err;
4849 4897
4850 if (skb->ip_summed != CHECKSUM_PARTIAL) 4898 if (skb->ip_summed != CHECKSUM_PARTIAL)
@@ -4857,45 +4905,52 @@ static int igb_tso(struct igb_ring *tx_ring,
4857 if (err < 0) 4905 if (err < 0)
4858 return err; 4906 return err;
4859 4907
4908 ip.hdr = skb_network_header(skb);
4909 l4.hdr = skb_checksum_start(skb);
4910
4860 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4911 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4861 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4912 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4862 4913
4863 if (first->protocol == htons(ETH_P_IP)) { 4914 /* initialize outer IP header fields */
4864 struct iphdr *iph = ip_hdr(skb); 4915 if (ip.v4->version == 4) {
4865 iph->tot_len = 0; 4916 /* IP header will have to cancel out any data that
4866 iph->check = 0; 4917 * is not a part of the outer IP header
4867 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4918 */
4868 iph->daddr, 0, 4919 ip.v4->check = csum_fold(csum_add(lco_csum(skb),
4869 IPPROTO_TCP, 4920 csum_unfold(l4.tcp->check)));
4870 0);
4871 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4921 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4922
4923 ip.v4->tot_len = 0;
4872 first->tx_flags |= IGB_TX_FLAGS_TSO | 4924 first->tx_flags |= IGB_TX_FLAGS_TSO |
4873 IGB_TX_FLAGS_CSUM | 4925 IGB_TX_FLAGS_CSUM |
4874 IGB_TX_FLAGS_IPV4; 4926 IGB_TX_FLAGS_IPV4;
4875 } else if (skb_is_gso_v6(skb)) { 4927 } else {
4876 ipv6_hdr(skb)->payload_len = 0; 4928 ip.v6->payload_len = 0;
4877 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4878 &ipv6_hdr(skb)->daddr,
4879 0, IPPROTO_TCP, 0);
4880 first->tx_flags |= IGB_TX_FLAGS_TSO | 4929 first->tx_flags |= IGB_TX_FLAGS_TSO |
4881 IGB_TX_FLAGS_CSUM; 4930 IGB_TX_FLAGS_CSUM;
4882 } 4931 }
4883 4932
4884 /* compute header lengths */ 4933 /* determine offset of inner transport header */
4885 l4len = tcp_hdrlen(skb); 4934 l4_offset = l4.hdr - skb->data;
4886 *hdr_len = skb_transport_offset(skb) + l4len; 4935
4936 /* compute length of segmentation header */
4937 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
4938
4939 /* remove payload length from inner checksum */
4940 paylen = skb->len - l4_offset;
4941 csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
4887 4942
4888 /* update gso size and bytecount with header size */ 4943 /* update gso size and bytecount with header size */
4889 first->gso_segs = skb_shinfo(skb)->gso_segs; 4944 first->gso_segs = skb_shinfo(skb)->gso_segs;
4890 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4945 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4891 4946
4892 /* MSS L4LEN IDX */ 4947 /* MSS L4LEN IDX */
4893 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4948 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
4894 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4949 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4895 4950
4896 /* VLAN MACLEN IPLEN */ 4951 /* VLAN MACLEN IPLEN */
4897 vlan_macip_lens = skb_network_header_len(skb); 4952 vlan_macip_lens = l4.hdr - ip.hdr;
4898 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4953 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
4899 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4954 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4900 4955
4901 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4956 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
@@ -5963,11 +6018,11 @@ static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5963 6018
5964 /* create mask for VF and other pools */ 6019 /* create mask for VF and other pools */
5965 pool_mask = E1000_VLVF_POOLSEL_MASK; 6020 pool_mask = E1000_VLVF_POOLSEL_MASK;
5966 vlvf_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 6021 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
5967 6022
5968 /* drop PF from pool bits */ 6023 /* drop PF from pool bits */
5969 pool_mask &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + 6024 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
5970 adapter->vfs_allocated_count)); 6025 adapter->vfs_allocated_count);
5971 6026
5972 /* Find the vlan filter for this id */ 6027 /* Find the vlan filter for this id */
5973 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 6028 for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
@@ -5990,7 +6045,7 @@ static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5990 goto update_vlvf; 6045 goto update_vlvf;
5991 6046
5992 vid = vlvf & E1000_VLVF_VLANID_MASK; 6047 vid = vlvf & E1000_VLVF_VLANID_MASK;
5993 vfta_mask = 1 << (vid % 32); 6048 vfta_mask = BIT(vid % 32);
5994 6049
5995 /* clear bit from VFTA */ 6050 /* clear bit from VFTA */
5996 vfta = adapter->shadow_vfta[vid / 32]; 6051 vfta = adapter->shadow_vfta[vid / 32];
@@ -6027,7 +6082,7 @@ static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
6027 return idx; 6082 return idx;
6028} 6083}
6029 6084
6030void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 6085static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
6031{ 6086{
6032 struct e1000_hw *hw = &adapter->hw; 6087 struct e1000_hw *hw = &adapter->hw;
6033 u32 bits, pf_id; 6088 u32 bits, pf_id;
@@ -6041,13 +6096,13 @@ void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
6041 * entry other than the PF. 6096 * entry other than the PF.
6042 */ 6097 */
6043 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 6098 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
6044 bits = ~(1 << pf_id) & E1000_VLVF_POOLSEL_MASK; 6099 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
6045 bits &= rd32(E1000_VLVF(idx)); 6100 bits &= rd32(E1000_VLVF(idx));
6046 6101
6047 /* Disable the filter so this falls into the default pool. */ 6102 /* Disable the filter so this falls into the default pool. */
6048 if (!bits) { 6103 if (!bits) {
6049 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6104 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
6050 wr32(E1000_VLVF(idx), 1 << pf_id); 6105 wr32(E1000_VLVF(idx), BIT(pf_id));
6051 else 6106 else
6052 wr32(E1000_VLVF(idx), 0); 6107 wr32(E1000_VLVF(idx), 0);
6053 } 6108 }
@@ -6231,9 +6286,9 @@ static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
6231 6286
6232 /* enable transmit and receive for vf */ 6287 /* enable transmit and receive for vf */
6233 reg = rd32(E1000_VFTE); 6288 reg = rd32(E1000_VFTE);
6234 wr32(E1000_VFTE, reg | (1 << vf)); 6289 wr32(E1000_VFTE, reg | BIT(vf));
6235 reg = rd32(E1000_VFRE); 6290 reg = rd32(E1000_VFRE);
6236 wr32(E1000_VFRE, reg | (1 << vf)); 6291 wr32(E1000_VFRE, reg | BIT(vf));
6237 6292
6238 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 6293 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
6239 6294
@@ -7927,7 +7982,7 @@ static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7927 /* Calculate the rate factor values to set */ 7982 /* Calculate the rate factor values to set */
7928 rf_int = link_speed / tx_rate; 7983 rf_int = link_speed / tx_rate;
7929 rf_dec = (link_speed - (rf_int * tx_rate)); 7984 rf_dec = (link_speed - (rf_int * tx_rate));
7930 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) / 7985 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) /
7931 tx_rate; 7986 tx_rate;
7932 7987
7933 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7988 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
@@ -8017,11 +8072,11 @@ static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
8017 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 8072 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
8018 reg_val = rd32(reg_offset); 8073 reg_val = rd32(reg_offset);
8019 if (setting) 8074 if (setting)
8020 reg_val |= ((1 << vf) | 8075 reg_val |= (BIT(vf) |
8021 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 8076 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
8022 else 8077 else
8023 reg_val &= ~((1 << vf) | 8078 reg_val &= ~(BIT(vf) |
8024 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 8079 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
8025 wr32(reg_offset, reg_val); 8080 wr32(reg_offset, reg_val);
8026 8081
8027 adapter->vf_data[vf].spoofchk_enabled = setting; 8082 adapter->vf_data[vf].spoofchk_enabled = setting;
diff --git a/drivers/net/ethernet/intel/igb/igb_ptp.c b/drivers/net/ethernet/intel/igb/igb_ptp.c
index 22a8a29895b4..f097c5a8ab93 100644
--- a/drivers/net/ethernet/intel/igb/igb_ptp.c
+++ b/drivers/net/ethernet/intel/igb/igb_ptp.c
@@ -69,9 +69,9 @@
69 69
70#define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9) 70#define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
71#define IGB_PTP_TX_TIMEOUT (HZ * 15) 71#define IGB_PTP_TX_TIMEOUT (HZ * 15)
72#define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT) 72#define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT)
73#define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1) 73#define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
74#define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT) 74#define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT)
75#define IGB_NBITS_82580 40 75#define IGB_NBITS_82580 40
76 76
77static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); 77static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
@@ -722,11 +722,29 @@ static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
722 struct e1000_hw *hw = &adapter->hw; 722 struct e1000_hw *hw = &adapter->hw;
723 struct skb_shared_hwtstamps shhwtstamps; 723 struct skb_shared_hwtstamps shhwtstamps;
724 u64 regval; 724 u64 regval;
725 int adjust = 0;
725 726
726 regval = rd32(E1000_TXSTMPL); 727 regval = rd32(E1000_TXSTMPL);
727 regval |= (u64)rd32(E1000_TXSTMPH) << 32; 728 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
728 729
729 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); 730 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
731 /* adjust timestamp for the TX latency based on link speed */
732 if (adapter->hw.mac.type == e1000_i210) {
733 switch (adapter->link_speed) {
734 case SPEED_10:
735 adjust = IGB_I210_TX_LATENCY_10;
736 break;
737 case SPEED_100:
738 adjust = IGB_I210_TX_LATENCY_100;
739 break;
740 case SPEED_1000:
741 adjust = IGB_I210_TX_LATENCY_1000;
742 break;
743 }
744 }
745
746 shhwtstamps.hwtstamp = ktime_sub_ns(shhwtstamps.hwtstamp, adjust);
747
730 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps); 748 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
731 dev_kfree_skb_any(adapter->ptp_tx_skb); 749 dev_kfree_skb_any(adapter->ptp_tx_skb);
732 adapter->ptp_tx_skb = NULL; 750 adapter->ptp_tx_skb = NULL;
@@ -771,6 +789,7 @@ void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
771 struct igb_adapter *adapter = q_vector->adapter; 789 struct igb_adapter *adapter = q_vector->adapter;
772 struct e1000_hw *hw = &adapter->hw; 790 struct e1000_hw *hw = &adapter->hw;
773 u64 regval; 791 u64 regval;
792 int adjust = 0;
774 793
775 /* If this bit is set, then the RX registers contain the time stamp. No 794 /* If this bit is set, then the RX registers contain the time stamp. No
776 * other packet will be time stamped until we read these registers, so 795 * other packet will be time stamped until we read these registers, so
@@ -790,6 +809,23 @@ void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
790 809
791 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); 810 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
792 811
812 /* adjust timestamp for the RX latency based on link speed */
813 if (adapter->hw.mac.type == e1000_i210) {
814 switch (adapter->link_speed) {
815 case SPEED_10:
816 adjust = IGB_I210_RX_LATENCY_10;
817 break;
818 case SPEED_100:
819 adjust = IGB_I210_RX_LATENCY_100;
820 break;
821 case SPEED_1000:
822 adjust = IGB_I210_RX_LATENCY_1000;
823 break;
824 }
825 }
826 skb_hwtstamps(skb)->hwtstamp =
827 ktime_add_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
828
793 /* Update the last_rx_timestamp timer in order to enable watchdog check 829 /* Update the last_rx_timestamp timer in order to enable watchdog check
794 * for error case of latched timestamp on a dropped packet. 830 * for error case of latched timestamp on a dropped packet.
795 */ 831 */
diff --git a/drivers/net/ethernet/intel/igbvf/defines.h b/drivers/net/ethernet/intel/igbvf/defines.h
index ae3f28332fa0..ee1ef08d7fc4 100644
--- a/drivers/net/ethernet/intel/igbvf/defines.h
+++ b/drivers/net/ethernet/intel/igbvf/defines.h
@@ -113,7 +113,7 @@
113#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Que */ 113#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Que */
114 114
115/* Direct Cache Access (DCA) definitions */ 115/* Direct Cache Access (DCA) definitions */
116#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 116#define E1000_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */
117 117
118#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 118#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
119 119
diff --git a/drivers/net/ethernet/intel/igbvf/ethtool.c b/drivers/net/ethernet/intel/igbvf/ethtool.c
index b74ce53d7b52..8dea1b1367ef 100644
--- a/drivers/net/ethernet/intel/igbvf/ethtool.c
+++ b/drivers/net/ethernet/intel/igbvf/ethtool.c
@@ -154,7 +154,8 @@ static void igbvf_get_regs(struct net_device *netdev,
154 154
155 memset(p, 0, IGBVF_REGS_LEN * sizeof(u32)); 155 memset(p, 0, IGBVF_REGS_LEN * sizeof(u32));
156 156
157 regs->version = (1 << 24) | (adapter->pdev->revision << 16) | 157 regs->version = (1u << 24) |
158 (adapter->pdev->revision << 16) |
158 adapter->pdev->device; 159 adapter->pdev->device;
159 160
160 regs_buff[0] = er32(CTRL); 161 regs_buff[0] = er32(CTRL);
diff --git a/drivers/net/ethernet/intel/igbvf/igbvf.h b/drivers/net/ethernet/intel/igbvf/igbvf.h
index f166baab8d7e..6f4290d6dc9f 100644
--- a/drivers/net/ethernet/intel/igbvf/igbvf.h
+++ b/drivers/net/ethernet/intel/igbvf/igbvf.h
@@ -287,8 +287,8 @@ struct igbvf_info {
287}; 287};
288 288
289/* hardware capability, feature, and workaround flags */ 289/* hardware capability, feature, and workaround flags */
290#define IGBVF_FLAG_RX_CSUM_DISABLED (1 << 0) 290#define IGBVF_FLAG_RX_CSUM_DISABLED BIT(0)
291#define IGBVF_FLAG_RX_LB_VLAN_BSWAP (1 << 1) 291#define IGBVF_FLAG_RX_LB_VLAN_BSWAP BIT(1)
292#define IGBVF_RX_DESC_ADV(R, i) \ 292#define IGBVF_RX_DESC_ADV(R, i) \
293 (&((((R).desc))[i].rx_desc)) 293 (&((((R).desc))[i].rx_desc))
294#define IGBVF_TX_DESC_ADV(R, i) \ 294#define IGBVF_TX_DESC_ADV(R, i) \
diff --git a/drivers/net/ethernet/intel/igbvf/netdev.c b/drivers/net/ethernet/intel/igbvf/netdev.c
index c12442252adb..322a2d7828a5 100644
--- a/drivers/net/ethernet/intel/igbvf/netdev.c
+++ b/drivers/net/ethernet/intel/igbvf/netdev.c
@@ -964,7 +964,7 @@ static void igbvf_assign_vector(struct igbvf_adapter *adapter, int rx_queue,
964 ivar = ivar & 0xFFFFFF00; 964 ivar = ivar & 0xFFFFFF00;
965 ivar |= msix_vector | E1000_IVAR_VALID; 965 ivar |= msix_vector | E1000_IVAR_VALID;
966 } 966 }
967 adapter->rx_ring[rx_queue].eims_value = 1 << msix_vector; 967 adapter->rx_ring[rx_queue].eims_value = BIT(msix_vector);
968 array_ew32(IVAR0, index, ivar); 968 array_ew32(IVAR0, index, ivar);
969 } 969 }
970 if (tx_queue > IGBVF_NO_QUEUE) { 970 if (tx_queue > IGBVF_NO_QUEUE) {
@@ -979,7 +979,7 @@ static void igbvf_assign_vector(struct igbvf_adapter *adapter, int rx_queue,
979 ivar = ivar & 0xFFFF00FF; 979 ivar = ivar & 0xFFFF00FF;
980 ivar |= (msix_vector | E1000_IVAR_VALID) << 8; 980 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
981 } 981 }
982 adapter->tx_ring[tx_queue].eims_value = 1 << msix_vector; 982 adapter->tx_ring[tx_queue].eims_value = BIT(msix_vector);
983 array_ew32(IVAR0, index, ivar); 983 array_ew32(IVAR0, index, ivar);
984 } 984 }
985} 985}
@@ -1014,8 +1014,8 @@ static void igbvf_configure_msix(struct igbvf_adapter *adapter)
1014 1014
1015 ew32(IVAR_MISC, tmp); 1015 ew32(IVAR_MISC, tmp);
1016 1016
1017 adapter->eims_enable_mask = (1 << (vector)) - 1; 1017 adapter->eims_enable_mask = GENMASK(vector - 1, 0);
1018 adapter->eims_other = 1 << (vector - 1); 1018 adapter->eims_other = BIT(vector - 1);
1019 e1e_flush(); 1019 e1e_flush();
1020} 1020}
1021 1021
@@ -1367,7 +1367,7 @@ static void igbvf_configure_rx(struct igbvf_adapter *adapter)
1367 struct e1000_hw *hw = &adapter->hw; 1367 struct e1000_hw *hw = &adapter->hw;
1368 struct igbvf_ring *rx_ring = adapter->rx_ring; 1368 struct igbvf_ring *rx_ring = adapter->rx_ring;
1369 u64 rdba; 1369 u64 rdba;
1370 u32 rdlen, rxdctl; 1370 u32 rxdctl;
1371 1371
1372 /* disable receives */ 1372 /* disable receives */
1373 rxdctl = er32(RXDCTL(0)); 1373 rxdctl = er32(RXDCTL(0));
@@ -1375,8 +1375,6 @@ static void igbvf_configure_rx(struct igbvf_adapter *adapter)
1375 e1e_flush(); 1375 e1e_flush();
1376 msleep(10); 1376 msleep(10);
1377 1377
1378 rdlen = rx_ring->count * sizeof(union e1000_adv_rx_desc);
1379
1380 /* Setup the HW Rx Head and Tail Descriptor Pointers and 1378 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1381 * the Base and Length of the Rx Descriptor Ring 1379 * the Base and Length of the Rx Descriptor Ring
1382 */ 1380 */
@@ -1933,83 +1931,74 @@ static void igbvf_tx_ctxtdesc(struct igbvf_ring *tx_ring, u32 vlan_macip_lens,
1933 buffer_info->dma = 0; 1931 buffer_info->dma = 0;
1934} 1932}
1935 1933
1936static int igbvf_tso(struct igbvf_adapter *adapter, 1934static int igbvf_tso(struct igbvf_ring *tx_ring,
1937 struct igbvf_ring *tx_ring, 1935 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
1938 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len, 1936{
1939 __be16 protocol) 1937 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
1940{ 1938 union {
1941 struct e1000_adv_tx_context_desc *context_desc; 1939 struct iphdr *v4;
1942 struct igbvf_buffer *buffer_info; 1940 struct ipv6hdr *v6;
1943 u32 info = 0, tu_cmd = 0; 1941 unsigned char *hdr;
1944 u32 mss_l4len_idx, l4len; 1942 } ip;
1945 unsigned int i; 1943 union {
1944 struct tcphdr *tcp;
1945 unsigned char *hdr;
1946 } l4;
1947 u32 paylen, l4_offset;
1946 int err; 1948 int err;
1947 1949
1948 *hdr_len = 0; 1950 if (skb->ip_summed != CHECKSUM_PARTIAL)
1951 return 0;
1952
1953 if (!skb_is_gso(skb))
1954 return 0;
1949 1955
1950 err = skb_cow_head(skb, 0); 1956 err = skb_cow_head(skb, 0);
1951 if (err < 0) { 1957 if (err < 0)
1952 dev_err(&adapter->pdev->dev, "igbvf_tso returning an error\n");
1953 return err; 1958 return err;
1954 }
1955 1959
1956 l4len = tcp_hdrlen(skb); 1960 ip.hdr = skb_network_header(skb);
1957 *hdr_len += l4len; 1961 l4.hdr = skb_checksum_start(skb);
1958
1959 if (protocol == htons(ETH_P_IP)) {
1960 struct iphdr *iph = ip_hdr(skb);
1961
1962 iph->tot_len = 0;
1963 iph->check = 0;
1964 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1965 iph->daddr, 0,
1966 IPPROTO_TCP,
1967 0);
1968 } else if (skb_is_gso_v6(skb)) {
1969 ipv6_hdr(skb)->payload_len = 0;
1970 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1971 &ipv6_hdr(skb)->daddr,
1972 0, IPPROTO_TCP, 0);
1973 }
1974 1962
1975 i = tx_ring->next_to_use; 1963 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
1964 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
1976 1965
1977 buffer_info = &tx_ring->buffer_info[i]; 1966 /* initialize outer IP header fields */
1978 context_desc = IGBVF_TX_CTXTDESC_ADV(*tx_ring, i); 1967 if (ip.v4->version == 4) {
1979 /* VLAN MACLEN IPLEN */ 1968 /* IP header will have to cancel out any data that
1980 if (tx_flags & IGBVF_TX_FLAGS_VLAN) 1969 * is not a part of the outer IP header
1981 info |= (tx_flags & IGBVF_TX_FLAGS_VLAN_MASK); 1970 */
1982 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT); 1971 ip.v4->check = csum_fold(csum_add(lco_csum(skb),
1983 *hdr_len += skb_network_offset(skb); 1972 csum_unfold(l4.tcp->check)));
1984 info |= (skb_transport_header(skb) - skb_network_header(skb)); 1973 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
1985 *hdr_len += (skb_transport_header(skb) - skb_network_header(skb));
1986 context_desc->vlan_macip_lens = cpu_to_le32(info);
1987 1974
1988 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 1975 ip.v4->tot_len = 0;
1989 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT); 1976 } else {
1977 ip.v6->payload_len = 0;
1978 }
1990 1979
1991 if (protocol == htons(ETH_P_IP)) 1980 /* determine offset of inner transport header */
1992 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4; 1981 l4_offset = l4.hdr - skb->data;
1993 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
1994 1982
1995 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); 1983 /* compute length of segmentation header */
1984 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
1996 1985
1997 /* MSS L4LEN IDX */ 1986 /* remove payload length from inner checksum */
1998 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT); 1987 paylen = skb->len - l4_offset;
1999 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT); 1988 csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
2000 1989
2001 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 1990 /* MSS L4LEN IDX */
2002 context_desc->seqnum_seed = 0; 1991 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
1992 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
2003 1993
2004 buffer_info->time_stamp = jiffies; 1994 /* VLAN MACLEN IPLEN */
2005 buffer_info->dma = 0; 1995 vlan_macip_lens = l4.hdr - ip.hdr;
2006 i++; 1996 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
2007 if (i == tx_ring->count) 1997 vlan_macip_lens |= tx_flags & IGBVF_TX_FLAGS_VLAN_MASK;
2008 i = 0;
2009 1998
2010 tx_ring->next_to_use = i; 1999 igbvf_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
2011 2000
2012 return true; 2001 return 1;
2013} 2002}
2014 2003
2015static inline bool igbvf_ipv6_csum_is_sctp(struct sk_buff *skb) 2004static inline bool igbvf_ipv6_csum_is_sctp(struct sk_buff *skb)
@@ -2091,7 +2080,7 @@ static int igbvf_maybe_stop_tx(struct net_device *netdev, int size)
2091} 2080}
2092 2081
2093#define IGBVF_MAX_TXD_PWR 16 2082#define IGBVF_MAX_TXD_PWR 16
2094#define IGBVF_MAX_DATA_PER_TXD (1 << IGBVF_MAX_TXD_PWR) 2083#define IGBVF_MAX_DATA_PER_TXD (1u << IGBVF_MAX_TXD_PWR)
2095 2084
2096static inline int igbvf_tx_map_adv(struct igbvf_adapter *adapter, 2085static inline int igbvf_tx_map_adv(struct igbvf_adapter *adapter,
2097 struct igbvf_ring *tx_ring, 2086 struct igbvf_ring *tx_ring,
@@ -2271,8 +2260,7 @@ static netdev_tx_t igbvf_xmit_frame_ring_adv(struct sk_buff *skb,
2271 2260
2272 first = tx_ring->next_to_use; 2261 first = tx_ring->next_to_use;
2273 2262
2274 tso = skb_is_gso(skb) ? 2263 tso = igbvf_tso(tx_ring, skb, tx_flags, &hdr_len);
2275 igbvf_tso(adapter, tx_ring, skb, tx_flags, &hdr_len, protocol) : 0;
2276 if (unlikely(tso < 0)) { 2264 if (unlikely(tso < 0)) {
2277 dev_kfree_skb_any(skb); 2265 dev_kfree_skb_any(skb);
2278 return NETDEV_TX_OK; 2266 return NETDEV_TX_OK;
@@ -2615,6 +2603,40 @@ static int igbvf_set_features(struct net_device *netdev,
2615 return 0; 2603 return 0;
2616} 2604}
2617 2605
2606#define IGBVF_MAX_MAC_HDR_LEN 127
2607#define IGBVF_MAX_NETWORK_HDR_LEN 511
2608
2609static netdev_features_t
2610igbvf_features_check(struct sk_buff *skb, struct net_device *dev,
2611 netdev_features_t features)
2612{
2613 unsigned int network_hdr_len, mac_hdr_len;
2614
2615 /* Make certain the headers can be described by a context descriptor */
2616 mac_hdr_len = skb_network_header(skb) - skb->data;
2617 if (unlikely(mac_hdr_len > IGBVF_MAX_MAC_HDR_LEN))
2618 return features & ~(NETIF_F_HW_CSUM |
2619 NETIF_F_SCTP_CRC |
2620 NETIF_F_HW_VLAN_CTAG_TX |
2621 NETIF_F_TSO |
2622 NETIF_F_TSO6);
2623
2624 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2625 if (unlikely(network_hdr_len > IGBVF_MAX_NETWORK_HDR_LEN))
2626 return features & ~(NETIF_F_HW_CSUM |
2627 NETIF_F_SCTP_CRC |
2628 NETIF_F_TSO |
2629 NETIF_F_TSO6);
2630
2631 /* We can only support IPV4 TSO in tunnels if we can mangle the
2632 * inner IP ID field, so strip TSO if MANGLEID is not supported.
2633 */
2634 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2635 features &= ~NETIF_F_TSO;
2636
2637 return features;
2638}
2639
2618static const struct net_device_ops igbvf_netdev_ops = { 2640static const struct net_device_ops igbvf_netdev_ops = {
2619 .ndo_open = igbvf_open, 2641 .ndo_open = igbvf_open,
2620 .ndo_stop = igbvf_close, 2642 .ndo_stop = igbvf_close,
@@ -2631,7 +2653,7 @@ static const struct net_device_ops igbvf_netdev_ops = {
2631 .ndo_poll_controller = igbvf_netpoll, 2653 .ndo_poll_controller = igbvf_netpoll,
2632#endif 2654#endif
2633 .ndo_set_features = igbvf_set_features, 2655 .ndo_set_features = igbvf_set_features,
2634 .ndo_features_check = passthru_features_check, 2656 .ndo_features_check = igbvf_features_check,
2635}; 2657};
2636 2658
2637/** 2659/**
@@ -2739,22 +2761,30 @@ static int igbvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2739 NETIF_F_HW_CSUM | 2761 NETIF_F_HW_CSUM |
2740 NETIF_F_SCTP_CRC; 2762 NETIF_F_SCTP_CRC;
2741 2763
2742 netdev->features = netdev->hw_features | 2764#define IGBVF_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
2743 NETIF_F_HW_VLAN_CTAG_TX | 2765 NETIF_F_GSO_GRE_CSUM | \
2744 NETIF_F_HW_VLAN_CTAG_RX | 2766 NETIF_F_GSO_IPIP | \
2745 NETIF_F_HW_VLAN_CTAG_FILTER; 2767 NETIF_F_GSO_SIT | \
2768 NETIF_F_GSO_UDP_TUNNEL | \
2769 NETIF_F_GSO_UDP_TUNNEL_CSUM)
2770
2771 netdev->gso_partial_features = IGBVF_GSO_PARTIAL_FEATURES;
2772 netdev->hw_features |= NETIF_F_GSO_PARTIAL |
2773 IGBVF_GSO_PARTIAL_FEATURES;
2774
2775 netdev->features = netdev->hw_features;
2746 2776
2747 if (pci_using_dac) 2777 if (pci_using_dac)
2748 netdev->features |= NETIF_F_HIGHDMA; 2778 netdev->features |= NETIF_F_HIGHDMA;
2749 2779
2750 netdev->vlan_features |= NETIF_F_SG | 2780 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
2751 NETIF_F_TSO |
2752 NETIF_F_TSO6 |
2753 NETIF_F_HW_CSUM |
2754 NETIF_F_SCTP_CRC;
2755
2756 netdev->mpls_features |= NETIF_F_HW_CSUM; 2781 netdev->mpls_features |= NETIF_F_HW_CSUM;
2757 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 2782 netdev->hw_enc_features |= netdev->vlan_features;
2783
2784 /* set this bit last since it cannot be part of vlan_features */
2785 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
2786 NETIF_F_HW_VLAN_CTAG_RX |
2787 NETIF_F_HW_VLAN_CTAG_TX;
2758 2788
2759 /*reset the controller to put the device in a known good state */ 2789 /*reset the controller to put the device in a known good state */
2760 err = hw->mac.ops.reset_hw(hw); 2790 err = hw->mac.ops.reset_hw(hw);
diff --git a/drivers/net/ethernet/intel/igbvf/vf.c b/drivers/net/ethernet/intel/igbvf/vf.c
index a13baa90ae20..335ba6642145 100644
--- a/drivers/net/ethernet/intel/igbvf/vf.c
+++ b/drivers/net/ethernet/intel/igbvf/vf.c
@@ -266,7 +266,7 @@ static s32 e1000_set_vfta_vf(struct e1000_hw *hw, u16 vid, bool set)
266 msgbuf[1] = vid; 266 msgbuf[1] = vid;
267 /* Setting the 8 bit field MSG INFO to true indicates "add" */ 267 /* Setting the 8 bit field MSG INFO to true indicates "add" */
268 if (set) 268 if (set)
269 msgbuf[0] |= 1 << E1000_VT_MSGINFO_SHIFT; 269 msgbuf[0] |= BIT(E1000_VT_MSGINFO_SHIFT);
270 270
271 mbx->ops.write_posted(hw, msgbuf, 2); 271 mbx->ops.write_posted(hw, msgbuf, 2);
272 272
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-05 22:05:53 -0500