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-rw-r--r--drivers/iommu/arm-smmu-v3.c1
-rw-r--r--drivers/iommu/intel-iommu.c17
-rw-r--r--drivers/iommu/rockchip-iommu.c2
3 files changed, 14 insertions, 6 deletions
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 94b68213c50d..5f6b3bcab078 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -1941,6 +1941,7 @@ static struct iommu_ops arm_smmu_ops = {
1941 .attach_dev = arm_smmu_attach_dev, 1941 .attach_dev = arm_smmu_attach_dev,
1942 .map = arm_smmu_map, 1942 .map = arm_smmu_map,
1943 .unmap = arm_smmu_unmap, 1943 .unmap = arm_smmu_unmap,
1944 .map_sg = default_iommu_map_sg,
1944 .iova_to_phys = arm_smmu_iova_to_phys, 1945 .iova_to_phys = arm_smmu_iova_to_phys,
1945 .add_device = arm_smmu_add_device, 1946 .add_device = arm_smmu_add_device,
1946 .remove_device = arm_smmu_remove_device, 1947 .remove_device = arm_smmu_remove_device,
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index a644d0cec2d8..10700945994e 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -3222,11 +3222,6 @@ static int __init init_dmars(void)
3222 } 3222 }
3223 } 3223 }
3224 3224
3225 iommu_flush_write_buffer(iommu);
3226 iommu_set_root_entry(iommu);
3227 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
3228 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
3229
3230 if (!ecap_pass_through(iommu->ecap)) 3225 if (!ecap_pass_through(iommu->ecap))
3231 hw_pass_through = 0; 3226 hw_pass_through = 0;
3232#ifdef CONFIG_INTEL_IOMMU_SVM 3227#ifdef CONFIG_INTEL_IOMMU_SVM
@@ -3235,6 +3230,18 @@ static int __init init_dmars(void)
3235#endif 3230#endif
3236 } 3231 }
3237 3232
3233 /*
3234 * Now that qi is enabled on all iommus, set the root entry and flush
3235 * caches. This is required on some Intel X58 chipsets, otherwise the
3236 * flush_context function will loop forever and the boot hangs.
3237 */
3238 for_each_active_iommu(iommu, drhd) {
3239 iommu_flush_write_buffer(iommu);
3240 iommu_set_root_entry(iommu);
3241 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
3242 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
3243 }
3244
3238 if (iommu_pass_through) 3245 if (iommu_pass_through)
3239 iommu_identity_mapping |= IDENTMAP_ALL; 3246 iommu_identity_mapping |= IDENTMAP_ALL;
3240 3247
diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c
index c7d6156ff536..25b4627cb57f 100644
--- a/drivers/iommu/rockchip-iommu.c
+++ b/drivers/iommu/rockchip-iommu.c
@@ -815,7 +815,7 @@ static int rk_iommu_attach_device(struct iommu_domain *domain,
815 dte_addr = virt_to_phys(rk_domain->dt); 815 dte_addr = virt_to_phys(rk_domain->dt);
816 for (i = 0; i < iommu->num_mmu; i++) { 816 for (i = 0; i < iommu->num_mmu; i++) {
817 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, dte_addr); 817 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, dte_addr);
818 rk_iommu_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); 818 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
819 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK); 819 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK);
820 } 820 }
821 821