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-rw-r--r--arch/arm/boot/dts/imx6q-gw5400-a.dts2
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw51xx.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw52xx.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw53xx.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw54xx.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabreauto.dtsi6
6 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index 58adf176425a..a51834e1dd27 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -154,7 +154,7 @@
154&fec { 154&fec {
155 pinctrl-names = "default"; 155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_enet>; 156 pinctrl-0 = <&pinctrl_enet>;
157 phy-mode = "rgmii"; 157 phy-mode = "rgmii-id";
158 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; 158 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
159 status = "okay"; 159 status = "okay";
160}; 160};
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index 7b31fdb79ced..dc0cebfe22d7 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -94,7 +94,7 @@
94&fec { 94&fec {
95 pinctrl-names = "default"; 95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_enet>; 96 pinctrl-0 = <&pinctrl_enet>;
97 phy-mode = "rgmii"; 97 phy-mode = "rgmii-id";
98 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 98 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
99 status = "okay"; 99 status = "okay";
100}; 100};
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 1b66328a8498..18cd4114a23e 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -154,7 +154,7 @@
154&fec { 154&fec {
155 pinctrl-names = "default"; 155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_enet>; 156 pinctrl-0 = <&pinctrl_enet>;
157 phy-mode = "rgmii"; 157 phy-mode = "rgmii-id";
158 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 158 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
159 status = "okay"; 159 status = "okay";
160}; 160};
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 7c51839ff934..eea90f37bbb8 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -155,7 +155,7 @@
155&fec { 155&fec {
156 pinctrl-names = "default"; 156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_enet>; 157 pinctrl-0 = <&pinctrl_enet>;
158 phy-mode = "rgmii"; 158 phy-mode = "rgmii-id";
159 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 159 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
160 status = "okay"; 160 status = "okay";
161}; 161};
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 929e0b37bd9e..6c11a2ae35ef 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -145,7 +145,7 @@
145&fec { 145&fec {
146 pinctrl-names = "default"; 146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_enet>; 147 pinctrl-0 = <&pinctrl_enet>;
148 phy-mode = "rgmii"; 148 phy-mode = "rgmii-id";
149 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 149 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
150 status = "okay"; 150 status = "okay";
151}; 151};
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 8263fc18a7d9..d354d406954d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -113,14 +113,14 @@
113&clks { 113&clks {
114 assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>, 114 assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
115 <&clks IMX6QDL_PLL4_BYPASS>, 115 <&clks IMX6QDL_PLL4_BYPASS>,
116 <&clks IMX6QDL_CLK_PLL4_POST_DIV>,
117 <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 116 <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
118 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 117 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
118 <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
119 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, 119 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
120 <&clks IMX6QDL_PLL4_BYPASS_SRC>, 120 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
121 <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 121 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
122 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 122 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
123 assigned-clock-rates = <0>, <0>, <24576000>; 123 assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
124}; 124};
125 125
126&ecspi1 { 126&ecspi1 {