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-rw-r--r--drivers/clk/clk.c95
-rw-r--r--drivers/clk/ti/Makefile9
-rw-r--r--drivers/clk/ti/clk-33xx-compat.c218
-rw-r--r--drivers/clk/ti/clk-33xx.c232
-rw-r--r--drivers/clk/ti/clk-43xx-compat.c225
-rw-r--r--drivers/clk/ti/clk-43xx.c249
-rw-r--r--drivers/clk/ti/clk-7xx-compat.c823
-rw-r--r--drivers/clk/ti/clk-7xx.c590
-rw-r--r--drivers/clk/ti/clk.c7
-rw-r--r--drivers/clk/ti/clkctrl.c99
-rw-r--r--drivers/clk/ti/clock.h11
-rw-r--r--drivers/clk/ti/divider.c36
-rw-r--r--drivers/clk/ti/dpll.c6
-rw-r--r--drivers/clk/ti/dpll3xxx.c124
-rw-r--r--drivers/clk/ti/gate.c3
-rw-r--r--drivers/clk/ti/mux.c29
-rw-r--r--include/dt-bindings/clock/am3.h119
-rw-r--r--include/dt-bindings/clock/am4.h132
-rw-r--r--include/dt-bindings/clock/dra7.h326
-rw-r--r--include/linux/clk-provider.h9
-rw-r--r--include/linux/clk.h25
-rw-r--r--include/linux/clk/ti.h7
22 files changed, 2826 insertions, 548 deletions
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index d31055ae6ec6..af011974d4ec 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -924,6 +924,101 @@ static int clk_core_enable_lock(struct clk_core *core)
924} 924}
925 925
926/** 926/**
927 * clk_gate_restore_context - restore context for poweroff
928 * @hw: the clk_hw pointer of clock whose state is to be restored
929 *
930 * The clock gate restore context function enables or disables
931 * the gate clocks based on the enable_count. This is done in cases
932 * where the clock context is lost and based on the enable_count
933 * the clock either needs to be enabled/disabled. This
934 * helps restore the state of gate clocks.
935 */
936void clk_gate_restore_context(struct clk_hw *hw)
937{
938 struct clk_core *core = hw->core;
939
940 if (core->enable_count)
941 core->ops->enable(hw);
942 else
943 core->ops->disable(hw);
944}
945EXPORT_SYMBOL_GPL(clk_gate_restore_context);
946
947static int clk_core_save_context(struct clk_core *core)
948{
949 struct clk_core *child;
950 int ret = 0;
951
952 hlist_for_each_entry(child, &core->children, child_node) {
953 ret = clk_core_save_context(child);
954 if (ret < 0)
955 return ret;
956 }
957
958 if (core->ops && core->ops->save_context)
959 ret = core->ops->save_context(core->hw);
960
961 return ret;
962}
963
964static void clk_core_restore_context(struct clk_core *core)
965{
966 struct clk_core *child;
967
968 if (core->ops && core->ops->restore_context)
969 core->ops->restore_context(core->hw);
970
971 hlist_for_each_entry(child, &core->children, child_node)
972 clk_core_restore_context(child);
973}
974
975/**
976 * clk_save_context - save clock context for poweroff
977 *
978 * Saves the context of the clock register for powerstates in which the
979 * contents of the registers will be lost. Occurs deep within the suspend
980 * code. Returns 0 on success.
981 */
982int clk_save_context(void)
983{
984 struct clk_core *clk;
985 int ret;
986
987 hlist_for_each_entry(clk, &clk_root_list, child_node) {
988 ret = clk_core_save_context(clk);
989 if (ret < 0)
990 return ret;
991 }
992
993 hlist_for_each_entry(clk, &clk_orphan_list, child_node) {
994 ret = clk_core_save_context(clk);
995 if (ret < 0)
996 return ret;
997 }
998
999 return 0;
1000}
1001EXPORT_SYMBOL_GPL(clk_save_context);
1002
1003/**
1004 * clk_restore_context - restore clock context after poweroff
1005 *
1006 * Restore the saved clock context upon resume.
1007 *
1008 */
1009void clk_restore_context(void)
1010{
1011 struct clk_core *core;
1012
1013 hlist_for_each_entry(core, &clk_root_list, child_node)
1014 clk_core_restore_context(core);
1015
1016 hlist_for_each_entry(core, &clk_orphan_list, child_node)
1017 clk_core_restore_context(core);
1018}
1019EXPORT_SYMBOL_GPL(clk_restore_context);
1020
1021/**
927 * clk_enable - ungate a clock 1022 * clk_enable - ungate a clock
928 * @clk: the clk being ungated 1023 * @clk: the clk being ungated
929 * 1024 *
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 5ab295d2a3cb..5ca1e39dd88a 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -6,7 +6,8 @@ clk-common = dpll.o composite.o divider.o gate.o \
6 fixed-factor.o mux.o apll.o \ 6 fixed-factor.o mux.o apll.o \
7 clkt_dpll.o clkt_iclk.o clkt_dflt.o \ 7 clkt_dpll.o clkt_iclk.o clkt_dflt.o \
8 clkctrl.o 8 clkctrl.o
9obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o 9obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o \
10 clk-33xx-compat.o
10obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o 11obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o
11obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o 12obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
12obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \ 13obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
@@ -16,8 +17,10 @@ obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o \
16obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o \ 17obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o \
17 dpll3xxx.o dpll44xx.o 18 dpll3xxx.o dpll44xx.o
18obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \ 19obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
19 clk-dra7-atl.o dpll3xxx.o dpll44xx.o 20 clk-dra7-atl.o dpll3xxx.o \
20obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o 21 dpll44xx.o clk-7xx-compat.o
22obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o \
23 clk-43xx-compat.o
21 24
22endif # CONFIG_ARCH_OMAP2PLUS 25endif # CONFIG_ARCH_OMAP2PLUS
23 26
diff --git a/drivers/clk/ti/clk-33xx-compat.c b/drivers/clk/ti/clk-33xx-compat.c
new file mode 100644
index 000000000000..3e07f127912a
--- /dev/null
+++ b/drivers/clk/ti/clk-33xx-compat.c
@@ -0,0 +1,218 @@
1/*
2 * AM33XX Clock init
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/clk.h>
20#include <linux/clk-provider.h>
21#include <linux/clk/ti.h>
22#include <dt-bindings/clock/am3.h>
23
24#include "clock.h"
25
26static const char * const am3_gpio1_dbclk_parents[] __initconst = {
27 "l4_per_cm:clk:0138:0",
28 NULL,
29};
30
31static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
32 { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
33 { 0 },
34};
35
36static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
37 { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
38 { 0 },
39};
40
41static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
42 { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
43 { 0 },
44};
45
46static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {
47 { AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
48 { AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" },
49 { AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" },
50 { AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
51 { AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },
52 { AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
53 { AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
54 { AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
55 { AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
56 { AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
57 { AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
58 { AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
59 { AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
60 { AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
61 { AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
62 { AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
63 { AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
64 { AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
65 { AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
66 { AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
67 { AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
68 { AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
69 { AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
70 { AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
71 { AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
72 { AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
73 { AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
74 { AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
75 { AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
76 { AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
77 { AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
78 { AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
79 { AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
80 { AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
81 { AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
82 { AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
83 { AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
84 { AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
85 { AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
86 { AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
87 { AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
88 { AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
89 { AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
90 { AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
91 { AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
92 { AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
93 { AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
94 { AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
95 { AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" },
96 { AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
97 { AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" },
98 { 0 },
99};
100
101static const char * const am3_gpio0_dbclk_parents[] __initconst = {
102 "gpio0_dbclk_mux_ck",
103 NULL,
104};
105
106static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
107 { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
108 { 0 },
109};
110
111static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
112 "sys_clkin_ck",
113 NULL,
114};
115
116static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
117 "l4_wkup_cm:clk:0010:19",
118 "l4_wkup_cm:clk:0010:30",
119 NULL,
120};
121
122static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
123 "l4_wkup_cm:clk:0010:20",
124 NULL,
125};
126
127static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
128 .max_div = 64,
129 .flags = CLK_DIVIDER_POWER_OF_TWO,
130};
131
132static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
133 "l4_wkup_cm:clk:0010:22",
134 NULL,
135};
136
137static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
138 .max_div = 64,
139 .flags = CLK_DIVIDER_POWER_OF_TWO,
140};
141
142static const char * const am3_dbg_clka_ck_parents[] __initconst = {
143 "dpll_core_m4_ck",
144 NULL,
145};
146
147static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
148 { 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
149 { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
150 { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
151 { 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
152 { 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
153 { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
154 { 0 },
155};
156
157static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
158 { AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
159 { AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
160 { AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
161 { AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" },
162 { AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" },
163 { AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
164 { AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
165 { AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
166 { AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
167 { AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
168 { AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
169 { AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
170 { 0 },
171};
172
173static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
174 { AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
175 { 0 },
176};
177
178static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
179 { AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
180 { 0 },
181};
182
183static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
184 { AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
185 { 0 },
186};
187
188static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
189 { AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
190 { 0 },
191};
192
193const struct omap_clkctrl_data am3_clkctrl_compat_data[] __initconst = {
194 { 0x44e00014, am3_l4_per_clkctrl_regs },
195 { 0x44e00404, am3_l4_wkup_clkctrl_regs },
196 { 0x44e00604, am3_mpu_clkctrl_regs },
197 { 0x44e00800, am3_l4_rtc_clkctrl_regs },
198 { 0x44e00904, am3_gfx_l3_clkctrl_regs },
199 { 0x44e00a20, am3_l4_cefuse_clkctrl_regs },
200 { 0 },
201};
202
203struct ti_dt_clk am33xx_compat_clks[] = {
204 DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"),
205 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
206 DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"),
207 DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"),
208 DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"),
209 DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"),
210 DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"),
211 DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"),
212 DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"),
213 DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"),
214 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"),
215 DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"),
216 DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"),
217 { .node_name = NULL },
218};
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index 12e0a2d19911..a360d3109555 100644
--- a/drivers/clk/ti/clk-33xx.c
+++ b/drivers/clk/ti/clk-33xx.c
@@ -24,7 +24,7 @@
24#include "clock.h" 24#include "clock.h"
25 25
26static const char * const am3_gpio1_dbclk_parents[] __initconst = { 26static const char * const am3_gpio1_dbclk_parents[] __initconst = {
27 "l4_per_cm:clk:0138:0", 27 "clk-24mhz-clkctrl:0000:0",
28 NULL, 28 NULL,
29}; 29};
30 30
@@ -43,58 +43,86 @@ static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
43 { 0 }, 43 { 0 },
44}; 44};
45 45
46static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = { 46static const struct omap_clkctrl_reg_data am3_l4ls_clkctrl_regs[] __initconst = {
47 { AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" }, 47 { AM3_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
48 { AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" }, 48 { AM3_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
49 { AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" }, 49 { AM3_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
50 { AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 50 { AM3_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
51 { AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" }, 51 { AM3_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
52 { AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 52 { AM3_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
53 { AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, 53 { AM3_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
54 { AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" }, 54 { AM3_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
55 { AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 55 { AM3_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
56 { AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 56 { AM3_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
57 { AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 57 { AM3_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
58 { AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 58 { AM3_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
59 { AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 59 { AM3_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
60 { AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 60 { AM3_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
61 { AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 61 { AM3_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
62 { AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 62 { AM3_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
63 { AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" }, 63 { AM3_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
64 { AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 64 { AM3_L4LS_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
65 { AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 65 { AM3_L4LS_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
66 { AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 66 { AM3_L4LS_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
67 { AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 67 { AM3_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
68 { AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" }, 68 { AM3_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
69 { AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" }, 69 { AM3_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
70 { AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" }, 70 { AM3_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
71 { AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" }, 71 { AM3_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
72 { AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" }, 72 { AM3_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
73 { AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" }, 73 { AM3_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
74 { AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 74 { AM3_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
75 { AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 75 { AM3_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
76 { AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 76 { AM3_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
77 { AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 77 { AM3_L4LS_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
78 { AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 78 { 0 },
79 { AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" }, 79};
80 { AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" }, 80
81 { AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 81static const struct omap_clkctrl_reg_data am3_l3s_clkctrl_regs[] __initconst = {
82 { AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 82 { AM3_L3S_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck" },
83 { AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 83 { AM3_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
84 { AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 84 { AM3_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
85 { AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 85 { AM3_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
86 { AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" }, 86 { AM3_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
87 { AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" }, 87 { 0 },
88 { AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" }, 88};
89 { AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 89
90 { AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" }, 90static const struct omap_clkctrl_reg_data am3_l3_clkctrl_regs[] __initconst = {
91 { AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 91 { AM3_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
92 { AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 92 { AM3_L3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck" },
93 { AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 93 { AM3_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
94 { AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 94 { AM3_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
95 { AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" }, 95 { AM3_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
96 { AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 96 { AM3_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
97 { AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" }, 97 { AM3_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
98 { AM3_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
99 { AM3_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
100 { AM3_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
101 { 0 },
102};
103
104static const struct omap_clkctrl_reg_data am3_l4hs_clkctrl_regs[] __initconst = {
105 { AM3_L4HS_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
106 { 0 },
107};
108
109static const struct omap_clkctrl_reg_data am3_pruss_ocp_clkctrl_regs[] __initconst = {
110 { AM3_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk" },
111 { 0 },
112};
113
114static const struct omap_clkctrl_reg_data am3_cpsw_125mhz_clkctrl_regs[] __initconst = {
115 { AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
116 { 0 },
117};
118
119static const struct omap_clkctrl_reg_data am3_lcdc_clkctrl_regs[] __initconst = {
120 { AM3_LCDC_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk" },
121 { 0 },
122};
123
124static const struct omap_clkctrl_reg_data am3_clk_24mhz_clkctrl_regs[] __initconst = {
125 { AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck" },
98 { 0 }, 126 { 0 },
99}; 127};
100 128
@@ -108,19 +136,33 @@ static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
108 { 0 }, 136 { 0 },
109}; 137};
110 138
139static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
140 { AM3_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
141 { AM3_L4_WKUP_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
142 { AM3_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
143 { AM3_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
144 { AM3_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
145 { AM3_L4_WKUP_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
146 { AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
147 { AM3_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
148 { AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
149 { AM3_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
150 { 0 },
151};
152
111static const char * const am3_dbg_sysclk_ck_parents[] __initconst = { 153static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
112 "sys_clkin_ck", 154 "sys_clkin_ck",
113 NULL, 155 NULL,
114}; 156};
115 157
116static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = { 158static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
117 "l4_wkup_cm:clk:0010:19", 159 "l3-aon-clkctrl:0000:19",
118 "l4_wkup_cm:clk:0010:30", 160 "l3-aon-clkctrl:0000:30",
119 NULL, 161 NULL,
120}; 162};
121 163
122static const char * const am3_trace_clk_div_ck_parents[] __initconst = { 164static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
123 "l4_wkup_cm:clk:0010:20", 165 "l3-aon-clkctrl:0000:20",
124 NULL, 166 NULL,
125}; 167};
126 168
@@ -130,7 +172,7 @@ static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst
130}; 172};
131 173
132static const char * const am3_stm_clk_div_ck_parents[] __initconst = { 174static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
133 "l4_wkup_cm:clk:0010:22", 175 "l3-aon-clkctrl:0000:22",
134 NULL, 176 NULL,
135}; 177};
136 178
@@ -154,66 +196,69 @@ static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
154 { 0 }, 196 { 0 },
155}; 197};
156 198
157static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = { 199static const struct omap_clkctrl_reg_data am3_l3_aon_clkctrl_regs[] __initconst = {
158 { AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, 200 { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
159 { AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, 201 { 0 },
160 { AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, 202};
161 { AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" }, 203
162 { AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" }, 204static const struct omap_clkctrl_reg_data am3_l4_wkup_aon_clkctrl_regs[] __initconst = {
163 { AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" }, 205 { AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck" },
164 { AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
165 { AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
166 { AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
167 { AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
168 { AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
169 { AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
170 { 0 }, 206 { 0 },
171}; 207};
172 208
173static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = { 209static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
174 { AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" }, 210 { AM3_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
175 { 0 }, 211 { 0 },
176}; 212};
177 213
178static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = { 214static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
179 { AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" }, 215 { AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
180 { 0 }, 216 { 0 },
181}; 217};
182 218
183static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = { 219static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
184 { AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" }, 220 { AM3_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
185 { 0 }, 221 { 0 },
186}; 222};
187 223
188static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = { 224static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
189 { AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" }, 225 { AM3_L4_CEFUSE_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
190 { 0 }, 226 { 0 },
191}; 227};
192 228
193const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = { 229const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = {
194 { 0x44e00014, am3_l4_per_clkctrl_regs }, 230 { 0x44e00038, am3_l4ls_clkctrl_regs },
195 { 0x44e00404, am3_l4_wkup_clkctrl_regs }, 231 { 0x44e0001c, am3_l3s_clkctrl_regs },
196 { 0x44e00604, am3_mpu_clkctrl_regs }, 232 { 0x44e00024, am3_l3_clkctrl_regs },
233 { 0x44e00120, am3_l4hs_clkctrl_regs },
234 { 0x44e000e8, am3_pruss_ocp_clkctrl_regs },
235 { 0x44e00000, am3_cpsw_125mhz_clkctrl_regs },
236 { 0x44e00018, am3_lcdc_clkctrl_regs },
237 { 0x44e0014c, am3_clk_24mhz_clkctrl_regs },
238 { 0x44e00400, am3_l4_wkup_clkctrl_regs },
239 { 0x44e00414, am3_l3_aon_clkctrl_regs },
240 { 0x44e004b0, am3_l4_wkup_aon_clkctrl_regs },
241 { 0x44e00600, am3_mpu_clkctrl_regs },
197 { 0x44e00800, am3_l4_rtc_clkctrl_regs }, 242 { 0x44e00800, am3_l4_rtc_clkctrl_regs },
198 { 0x44e00904, am3_gfx_l3_clkctrl_regs }, 243 { 0x44e00900, am3_gfx_l3_clkctrl_regs },
199 { 0x44e00a20, am3_l4_cefuse_clkctrl_regs }, 244 { 0x44e00a00, am3_l4_cefuse_clkctrl_regs },
200 { 0 }, 245 { 0 },
201}; 246};
202 247
203static struct ti_dt_clk am33xx_clks[] = { 248static struct ti_dt_clk am33xx_clks[] = {
204 DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"), 249 DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"),
205 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), 250 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
206 DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"), 251 DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"),
207 DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"), 252 DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
208 DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"), 253 DT_CLK(NULL, "dbg_sysclk_ck", "l3-aon-clkctrl:0000:19"),
209 DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"), 254 DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0008:18"),
210 DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"), 255 DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0074:18"),
211 DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"), 256 DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0078:18"),
212 DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"), 257 DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:007c:18"),
213 DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"), 258 DT_CLK(NULL, "stm_clk_div_ck", "l3-aon-clkctrl:0000:27"),
214 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"), 259 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l3-aon-clkctrl:0000:22"),
215 DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"), 260 DT_CLK(NULL, "trace_clk_div_ck", "l3-aon-clkctrl:0000:24"),
216 DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"), 261 DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l3-aon-clkctrl:0000:20"),
217 { .node_name = NULL }, 262 { .node_name = NULL },
218}; 263};
219 264
@@ -232,7 +277,10 @@ int __init am33xx_dt_clk_init(void)
232{ 277{
233 struct clk *clk1, *clk2; 278 struct clk *clk1, *clk2;
234 279
235 ti_dt_clocks_register(am33xx_clks); 280 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
281 ti_dt_clocks_register(am33xx_compat_clks);
282 else
283 ti_dt_clocks_register(am33xx_clks);
236 284
237 omap2_clk_disable_autoidle_all(); 285 omap2_clk_disable_autoidle_all();
238 286
diff --git a/drivers/clk/ti/clk-43xx-compat.c b/drivers/clk/ti/clk-43xx-compat.c
new file mode 100644
index 000000000000..513039843392
--- /dev/null
+++ b/drivers/clk/ti/clk-43xx-compat.c
@@ -0,0 +1,225 @@
1/*
2 * AM43XX Clock init
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/clk.h>
20#include <linux/clk-provider.h>
21#include <linux/clk/ti.h>
22#include <dt-bindings/clock/am4.h>
23
24#include "clock.h"
25
26static const char * const am4_synctimer_32kclk_parents[] __initconst = {
27 "mux_synctimer32k_ck",
28 NULL,
29};
30
31static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
32 { 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
33 { 0 },
34};
35
36static const char * const am4_gpio0_dbclk_parents[] __initconst = {
37 "gpio0_dbclk_mux_ck",
38 NULL,
39};
40
41static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
42 { 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
43 { 0 },
44};
45
46static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
47 { AM4_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck", "l3s_tsc_clkdm" },
48 { AM4_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
49 { AM4_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "sys_clkin_ck" },
50 { AM4_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0210:8" },
51 { AM4_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck", "l4_wkup_clkdm" },
52 { AM4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck", "l4_wkup_clkdm" },
53 { AM4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
54 { AM4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
55 { AM4_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck", "l4_wkup_clkdm" },
56 { AM4_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck", "l4_wkup_clkdm" },
57 { AM4_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
58 { AM4_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
59 { 0 },
60};
61
62static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
63 { AM4_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
64 { 0 },
65};
66
67static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
68 { AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
69 { 0 },
70};
71
72static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
73 { AM4_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
74 { 0 },
75};
76
77static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
78 "dpll_per_clkdcoldo",
79 NULL,
80};
81
82static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
83 { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
84 { 0 },
85};
86
87static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {
88 { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
89 { 0 },
90};
91
92static const char * const am4_gpio1_dbclk_parents[] __initconst = {
93 "clkdiv32k_ick",
94 NULL,
95};
96
97static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {
98 { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
99 { 0 },
100};
101
102static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {
103 { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
104 { 0 },
105};
106
107static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {
108 { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
109 { 0 },
110};
111
112static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {
113 { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
114 { 0 },
115};
116
117static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
118 { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
119 { 0 },
120};
121
122static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst = {
123 { AM4_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
124 { AM4_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
125 { AM4_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
126 { AM4_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
127 { AM4_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
128 { AM4_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
129 { AM4_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
130 { AM4_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
131 { AM4_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
132 { AM4_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
133 { AM4_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
134 { AM4_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
135 { AM4_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l3_clkdm" },
136 { AM4_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
137 { AM4_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
138 { AM4_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
139 { AM4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
140 { AM4_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
141 { AM4_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
142 { AM4_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
143 { AM4_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
144 { AM4_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
145 { AM4_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
146 { AM4_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
147 { AM4_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
148 { AM4_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
149 { AM4_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
150 { AM4_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
151 { AM4_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
152 { AM4_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
153 { AM4_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
154 { AM4_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
155 { AM4_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
156 { AM4_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
157 { AM4_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
158 { AM4_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
159 { AM4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
160 { AM4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
161 { AM4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
162 { AM4_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
163 { AM4_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
164 { AM4_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
165 { AM4_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
166 { AM4_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
167 { AM4_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
168 { AM4_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
169 { AM4_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
170 { AM4_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
171 { AM4_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
172 { AM4_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
173 { AM4_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
174 { AM4_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
175 { AM4_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
176 { AM4_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
177 { AM4_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
178 { AM4_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
179 { AM4_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
180 { AM4_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
181 { AM4_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
182 { AM4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
183 { AM4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
184 { AM4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
185 { AM4_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
186 { AM4_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
187 { AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
188 { AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
189 { AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" },
190 { AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk", "dss_clkdm" },
191 { AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
192 { 0 },
193};
194
195const struct omap_clkctrl_data am4_clkctrl_compat_data[] __initconst = {
196 { 0x44df2820, am4_l4_wkup_clkctrl_regs },
197 { 0x44df8320, am4_mpu_clkctrl_regs },
198 { 0x44df8420, am4_gfx_l3_clkctrl_regs },
199 { 0x44df8520, am4_l4_rtc_clkctrl_regs },
200 { 0x44df8820, am4_l4_per_clkctrl_regs },
201 { 0 },
202};
203
204const struct omap_clkctrl_data am438x_clkctrl_compat_data[] __initconst = {
205 { 0x44df2820, am4_l4_wkup_clkctrl_regs },
206 { 0x44df8320, am4_mpu_clkctrl_regs },
207 { 0x44df8420, am4_gfx_l3_clkctrl_regs },
208 { 0x44df8820, am4_l4_per_clkctrl_regs },
209 { 0 },
210};
211
212struct ti_dt_clk am43xx_compat_clks[] = {
213 DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
214 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
215 DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0348:8"),
216 DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0458:8"),
217 DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0460:8"),
218 DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0468:8"),
219 DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0470:8"),
220 DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0478:8"),
221 DT_CLK(NULL, "synctimer_32kclk", "l4_wkup_cm:0210:8"),
222 DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l4_per_cm:0240:8"),
223 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l4_per_cm:0248:8"),
224 { .node_name = NULL },
225};
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 63c5ddb50187..2782d91838ac 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -23,6 +23,11 @@
23 23
24#include "clock.h" 24#include "clock.h"
25 25
26static const struct omap_clkctrl_reg_data am4_l3s_tsc_clkctrl_regs[] __initconst = {
27 { AM4_L3S_TSC_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
28 { 0 },
29};
30
26static const char * const am4_synctimer_32kclk_parents[] __initconst = { 31static const char * const am4_synctimer_32kclk_parents[] __initconst = {
27 "mux_synctimer32k_ck", 32 "mux_synctimer32k_ck",
28 NULL, 33 NULL,
@@ -33,6 +38,12 @@ static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst
33 { 0 }, 38 { 0 },
34}; 39};
35 40
41static const struct omap_clkctrl_reg_data am4_l4_wkup_aon_clkctrl_regs[] __initconst = {
42 { AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sys_clkin_ck" },
43 { AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4-wkup-aon-clkctrl:0008:8" },
44 { 0 },
45};
46
36static const char * const am4_gpio0_dbclk_parents[] __initconst = { 47static const char * const am4_gpio0_dbclk_parents[] __initconst = {
37 "gpio0_dbclk_mux_ck", 48 "gpio0_dbclk_mux_ck",
38 NULL, 49 NULL,
@@ -44,33 +55,45 @@ static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
44}; 55};
45 56
46static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = { 57static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
47 { AM4_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck", "l3s_tsc_clkdm" }, 58 { AM4_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
48 { AM4_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" }, 59 { AM4_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
49 { AM4_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "sys_clkin_ck" }, 60 { AM4_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
50 { AM4_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0210:8" }, 61 { AM4_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
51 { AM4_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck", "l4_wkup_clkdm" }, 62 { AM4_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
52 { AM4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck", "l4_wkup_clkdm" }, 63 { AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
53 { AM4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" }, 64 { AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
54 { AM4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" }, 65 { AM4_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
55 { AM4_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck", "l4_wkup_clkdm" }, 66 { AM4_L4_WKUP_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck" },
56 { AM4_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck", "l4_wkup_clkdm" },
57 { AM4_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
58 { AM4_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
59 { 0 }, 67 { 0 },
60}; 68};
61 69
62static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = { 70static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
63 { AM4_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" }, 71 { AM4_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
64 { 0 }, 72 { 0 },
65}; 73};
66 74
67static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = { 75static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
68 { AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" }, 76 { AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
69 { 0 }, 77 { 0 },
70}; 78};
71 79
72static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = { 80static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
73 { AM4_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" }, 81 { AM4_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
82 { 0 },
83};
84
85static const struct omap_clkctrl_reg_data am4_l3_clkctrl_regs[] __initconst = {
86 { AM4_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
87 { AM4_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
88 { AM4_L3_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
89 { AM4_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
90 { AM4_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
91 { AM4_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
92 { AM4_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
93 { AM4_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
94 { AM4_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
95 { AM4_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
96 { AM4_L3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
74 { 0 }, 97 { 0 },
75}; 98};
76 99
@@ -89,6 +112,24 @@ static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst
89 { 0 }, 112 { 0 },
90}; 113};
91 114
115static const struct omap_clkctrl_reg_data am4_l3s_clkctrl_regs[] __initconst = {
116 { AM4_L3S_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
117 { AM4_L3S_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
118 { AM4_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
119 { AM4_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
120 { AM4_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
121 { AM4_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
122 { AM4_L3S_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
123 { AM4_L3S_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk" },
124 { AM4_L3S_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk" },
125 { 0 },
126};
127
128static const struct omap_clkctrl_reg_data am4_pruss_ocp_clkctrl_regs[] __initconst = {
129 { AM4_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk" },
130 { 0 },
131};
132
92static const char * const am4_gpio1_dbclk_parents[] __initconst = { 133static const char * const am4_gpio1_dbclk_parents[] __initconst = {
93 "clkdiv32k_ick", 134 "clkdiv32k_ick",
94 NULL, 135 NULL,
@@ -119,108 +160,115 @@ static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
119 { 0 }, 160 { 0 },
120}; 161};
121 162
122static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst = { 163static const struct omap_clkctrl_reg_data am4_l4ls_clkctrl_regs[] __initconst = {
123 { AM4_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 164 { AM4_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
124 { AM4_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" }, 165 { AM4_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
125 { AM4_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 166 { AM4_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
126 { AM4_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 167 { AM4_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
127 { AM4_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 168 { AM4_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
128 { AM4_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 169 { AM4_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
129 { AM4_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" }, 170 { AM4_L4LS_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
130 { AM4_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" }, 171 { AM4_L4LS_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
131 { AM4_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 172 { AM4_L4LS_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
132 { AM4_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 173 { AM4_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
133 { AM4_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 174 { AM4_L4LS_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
134 { AM4_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 175 { AM4_L4LS_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
135 { AM4_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l3_clkdm" }, 176 { AM4_L4LS_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
136 { AM4_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, 177 { AM4_L4LS_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
137 { AM4_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" }, 178 { AM4_L4LS_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
138 { AM4_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" }, 179 { AM4_L4LS_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
139 { AM4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" }, 180 { AM4_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
140 { AM4_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, 181 { AM4_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
141 { AM4_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, 182 { AM4_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
142 { AM4_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, 183 { AM4_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
143 { AM4_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" }, 184 { AM4_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
144 { AM4_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 185 { AM4_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
145 { AM4_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" }, 186 { AM4_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
146 { AM4_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" }, 187 { AM4_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
147 { AM4_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 188 { AM4_L4LS_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
148 { AM4_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 189 { AM4_L4LS_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
149 { AM4_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 190 { AM4_L4LS_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
150 { AM4_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 191 { AM4_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
151 { AM4_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 192 { AM4_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
152 { AM4_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 193 { AM4_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
153 { AM4_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 194 { AM4_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
154 { AM4_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 195 { AM4_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
155 { AM4_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 196 { AM4_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
156 { AM4_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 197 { AM4_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
157 { AM4_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 198 { AM4_L4LS_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
158 { AM4_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 199 { AM4_L4LS_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
159 { AM4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" }, 200 { AM4_L4LS_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
160 { AM4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 201 { AM4_L4LS_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
161 { AM4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 202 { AM4_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
162 { AM4_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 203 { AM4_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
163 { AM4_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 204 { AM4_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
164 { AM4_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 205 { AM4_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
165 { AM4_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" }, 206 { AM4_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
166 { AM4_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 207 { AM4_L4LS_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
167 { AM4_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 208 { AM4_L4LS_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
168 { AM4_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 209 { 0 },
169 { AM4_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 210};
170 { AM4_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 211
171 { AM4_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 212static const struct omap_clkctrl_reg_data am4_emif_clkctrl_regs[] __initconst = {
172 { AM4_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" }, 213 { AM4_EMIF_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck" },
173 { AM4_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" }, 214 { 0 },
174 { AM4_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" }, 215};
175 { AM4_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" }, 216
176 { AM4_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" }, 217static const struct omap_clkctrl_reg_data am4_dss_clkctrl_regs[] __initconst = {
177 { AM4_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" }, 218 { AM4_DSS_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk" },
178 { AM4_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" }, 219 { 0 },
179 { AM4_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" }, 220};
180 { AM4_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" }, 221
181 { AM4_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" }, 222static const struct omap_clkctrl_reg_data am4_cpsw_125mhz_clkctrl_regs[] __initconst = {
182 { AM4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 223 { AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
183 { AM4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
184 { AM4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
185 { AM4_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
186 { AM4_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
187 { AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
188 { AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
189 { AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" },
190 { AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk", "dss_clkdm" },
191 { AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
192 { 0 }, 224 { 0 },
193}; 225};
194 226
195const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = { 227const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = {
196 { 0x44df2820, am4_l4_wkup_clkctrl_regs }, 228 { 0x44df2920, am4_l3s_tsc_clkctrl_regs },
229 { 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
230 { 0x44df2a20, am4_l4_wkup_clkctrl_regs },
197 { 0x44df8320, am4_mpu_clkctrl_regs }, 231 { 0x44df8320, am4_mpu_clkctrl_regs },
198 { 0x44df8420, am4_gfx_l3_clkctrl_regs }, 232 { 0x44df8420, am4_gfx_l3_clkctrl_regs },
199 { 0x44df8520, am4_l4_rtc_clkctrl_regs }, 233 { 0x44df8520, am4_l4_rtc_clkctrl_regs },
200 { 0x44df8820, am4_l4_per_clkctrl_regs }, 234 { 0x44df8820, am4_l3_clkctrl_regs },
235 { 0x44df8868, am4_l3s_clkctrl_regs },
236 { 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
237 { 0x44df8c20, am4_l4ls_clkctrl_regs },
238 { 0x44df8f20, am4_emif_clkctrl_regs },
239 { 0x44df9220, am4_dss_clkctrl_regs },
240 { 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
201 { 0 }, 241 { 0 },
202}; 242};
203 243
204const struct omap_clkctrl_data am438x_clkctrl_data[] __initconst = { 244const struct omap_clkctrl_data am438x_clkctrl_data[] __initconst = {
205 { 0x44df2820, am4_l4_wkup_clkctrl_regs }, 245 { 0x44df2920, am4_l3s_tsc_clkctrl_regs },
246 { 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
247 { 0x44df2a20, am4_l4_wkup_clkctrl_regs },
206 { 0x44df8320, am4_mpu_clkctrl_regs }, 248 { 0x44df8320, am4_mpu_clkctrl_regs },
207 { 0x44df8420, am4_gfx_l3_clkctrl_regs }, 249 { 0x44df8420, am4_gfx_l3_clkctrl_regs },
208 { 0x44df8820, am4_l4_per_clkctrl_regs }, 250 { 0x44df8820, am4_l3_clkctrl_regs },
251 { 0x44df8868, am4_l3s_clkctrl_regs },
252 { 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
253 { 0x44df8c20, am4_l4ls_clkctrl_regs },
254 { 0x44df8f20, am4_emif_clkctrl_regs },
255 { 0x44df9220, am4_dss_clkctrl_regs },
256 { 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
209 { 0 }, 257 { 0 },
210}; 258};
211 259
212static struct ti_dt_clk am43xx_clks[] = { 260static struct ti_dt_clk am43xx_clks[] = {
213 DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), 261 DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
214 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), 262 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
215 DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0348:8"), 263 DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0148:8"),
216 DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0458:8"), 264 DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0058:8"),
217 DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0460:8"), 265 DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0060:8"),
218 DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0468:8"), 266 DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:0068:8"),
219 DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0470:8"), 267 DT_CLK(NULL, "gpio4_dbclk", "l4ls-clkctrl:0070:8"),
220 DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0478:8"), 268 DT_CLK(NULL, "gpio5_dbclk", "l4ls-clkctrl:0078:8"),
221 DT_CLK(NULL, "synctimer_32kclk", "l4_wkup_cm:0210:8"), 269 DT_CLK(NULL, "synctimer_32kclk", "l4-wkup-aon-clkctrl:0008:8"),
222 DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l4_per_cm:0240:8"), 270 DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l3s-clkctrl:01f8:8"),
223 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l4_per_cm:0248:8"), 271 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3s-clkctrl:0200:8"),
224 { .node_name = NULL }, 272 { .node_name = NULL },
225}; 273};
226 274
@@ -228,7 +276,10 @@ int __init am43xx_dt_clk_init(void)
228{ 276{
229 struct clk *clk1, *clk2; 277 struct clk *clk1, *clk2;
230 278
231 ti_dt_clocks_register(am43xx_clks); 279 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
280 ti_dt_clocks_register(am43xx_compat_clks);
281 else
282 ti_dt_clocks_register(am43xx_clks);
232 283
233 omap2_clk_disable_autoidle_all(); 284 omap2_clk_disable_autoidle_all();
234 285
diff --git a/drivers/clk/ti/clk-7xx-compat.c b/drivers/clk/ti/clk-7xx-compat.c
new file mode 100644
index 000000000000..e3cb7f0b03ae
--- /dev/null
+++ b/drivers/clk/ti/clk-7xx-compat.c
@@ -0,0 +1,823 @@
1/*
2 * DRA7 Clock init
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Tero Kristo (t-kristo@ti.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/list.h>
15#include <linux/clk.h>
16#include <linux/clkdev.h>
17#include <linux/clk/ti.h>
18#include <dt-bindings/clock/dra7.h>
19
20#include "clock.h"
21
22#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
23#define DRA7_DPLL_USB_DEFFREQ 960000000
24
25static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
26 { DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
27 { 0 },
28};
29
30static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
31 "per_abe_x1_gfclk2_div",
32 "video1_clk2_div",
33 "video2_clk2_div",
34 "hdmi_clk2_div",
35 NULL,
36};
37
38static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
39 "abe_24m_fclk",
40 "abe_sys_clk_div",
41 "func_24m_clk",
42 "atl_clkin3_ck",
43 "atl_clkin2_ck",
44 "atl_clkin1_ck",
45 "atl_clkin0_ck",
46 "sys_clkin2",
47 "ref_clkin0_ck",
48 "ref_clkin1_ck",
49 "ref_clkin2_ck",
50 "ref_clkin3_ck",
51 "mlb_clk",
52 "mlbp_clk",
53 NULL,
54};
55
56static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
57 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
58 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
59 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
60 { 0 },
61};
62
63static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
64 "timer_sys_clk_div",
65 "sys_32k_ck",
66 "sys_clkin2",
67 "ref_clkin0_ck",
68 "ref_clkin1_ck",
69 "ref_clkin2_ck",
70 "ref_clkin3_ck",
71 "abe_giclk_div",
72 "video1_div_clk",
73 "video2_div_clk",
74 "hdmi_div_clk",
75 "clkoutmux0_clk_mux",
76 NULL,
77};
78
79static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
80 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
81 { 0 },
82};
83
84static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
85 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
86 { 0 },
87};
88
89static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
90 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
91 { 0 },
92};
93
94static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
95 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
96 { 0 },
97};
98
99static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
100 "func_48m_fclk",
101 "dpll_per_m2x2_ck",
102 NULL,
103};
104
105static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
106 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
107 { 0 },
108};
109
110static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
111 { DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" },
112 { DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" },
113 { DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" },
114 { DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" },
115 { DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" },
116 { DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
117 { DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" },
118 { 0 },
119};
120
121static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
122 { DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
123 { 0 },
124};
125
126static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
127 { DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
128 { DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
129 { 0 },
130};
131
132static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
133 { DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
134 { DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
135 { DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
136 { DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
137 { DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
138 { DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
139 { DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
140 { 0 },
141};
142
143static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
144 { DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
145 { 0 },
146};
147
148static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
149 { DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
150 { 0 },
151};
152
153static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
154 "sys_32k_ck",
155 "video1_clkin_ck",
156 "video2_clkin_ck",
157 "hdmi_clkin_ck",
158 NULL,
159};
160
161static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
162 "l3_iclk_div",
163 "dpll_abe_m2_ck",
164 "atl_cm:clk:0000:24",
165 NULL,
166};
167
168static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
169 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
170 { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
171 { 0 },
172};
173
174static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
175 { DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" },
176 { 0 },
177};
178
179static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
180 { DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
181 { DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
182 { DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
183 { DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
184 { DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
185 { DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
186 { DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
187 { DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
188 { DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
189 { DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
190 { DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
191 { DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
192 { DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
193 { DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
194 { DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
195 { 0 },
196};
197
198static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
199 { DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
200 { DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
201 { 0 },
202};
203
204static const char * const dra7_dss_dss_clk_parents[] __initconst = {
205 "dpll_per_h12x2_ck",
206 NULL,
207};
208
209static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
210 "func_48m_fclk",
211 NULL,
212};
213
214static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
215 "hdmi_dpll_clk_mux",
216 NULL,
217};
218
219static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
220 "sys_32k_ck",
221 NULL,
222};
223
224static const char * const dra7_dss_video1_clk_parents[] __initconst = {
225 "video1_dpll_clk_mux",
226 NULL,
227};
228
229static const char * const dra7_dss_video2_clk_parents[] __initconst = {
230 "video2_dpll_clk_mux",
231 NULL,
232};
233
234static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
235 { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
236 { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
237 { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
238 { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
239 { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
240 { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
241 { 0 },
242};
243
244static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
245 { DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
246 { DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
247 { 0 },
248};
249
250static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
251 "func_128m_clk",
252 "dpll_per_m2x2_ck",
253 NULL,
254};
255
256static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
257 "l3init_cm:clk:0008:24",
258 NULL,
259};
260
261static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
262 .max_div = 4,
263 .flags = CLK_DIVIDER_POWER_OF_TWO,
264};
265
266static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
267 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
268 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
269 { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
270 { 0 },
271};
272
273static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
274 "l3init_cm:clk:0010:24",
275 NULL,
276};
277
278static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
279 .max_div = 4,
280 .flags = CLK_DIVIDER_POWER_OF_TWO,
281};
282
283static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
284 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
285 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
286 { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
287 { 0 },
288};
289
290static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
291 "l3init_960m_gfclk",
292 NULL,
293};
294
295static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
296 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
297 { 0 },
298};
299
300static const char * const dra7_sata_ref_clk_parents[] __initconst = {
301 "sys_clkin1",
302 NULL,
303};
304
305static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
306 { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
307 { 0 },
308};
309
310static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
311 "apll_pcie_ck",
312 NULL,
313};
314
315static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
316 "optfclk_pciephy_div",
317 NULL,
318};
319
320static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
321 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
322 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
323 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
324 { 0 },
325};
326
327static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
328 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
329 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
330 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
331 { 0 },
332};
333
334static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
335 "dpll_gmac_h11x2_ck",
336 "rmii_clk_ck",
337 NULL,
338};
339
340static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
341 "video1_clkin_ck",
342 "video2_clkin_ck",
343 "dpll_abe_m2_ck",
344 "hdmi_clkin_ck",
345 "l3_iclk_div",
346 NULL,
347};
348
349static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
350 { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
351 { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
352 { 0 },
353};
354
355static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
356 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
357 { 0 },
358};
359
360static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
361 { DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
362 { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
363 { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
364 { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
365 { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
366 { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
367 { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
368 { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
369 { DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" },
370 { DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
371 { DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
372 { DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
373 { 0 },
374};
375
376static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
377 "timer_sys_clk_div",
378 "sys_32k_ck",
379 "sys_clkin2",
380 "ref_clkin0_ck",
381 "ref_clkin1_ck",
382 "ref_clkin2_ck",
383 "ref_clkin3_ck",
384 "abe_giclk_div",
385 "video1_div_clk",
386 "video2_div_clk",
387 "hdmi_div_clk",
388 NULL,
389};
390
391static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
392 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
393 { 0 },
394};
395
396static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
397 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
398 { 0 },
399};
400
401static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
402 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
403 { 0 },
404};
405
406static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
407 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
408 { 0 },
409};
410
411static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
412 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
413 { 0 },
414};
415
416static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
417 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
418 { 0 },
419};
420
421static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
422 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
423 { 0 },
424};
425
426static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
427 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
428 { 0 },
429};
430
431static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
432 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
433 { 0 },
434};
435
436static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
437 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
438 { 0 },
439};
440
441static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
442 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
443 { 0 },
444};
445
446static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
447 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
448 { 0 },
449};
450
451static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
452 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
453 { 0 },
454};
455
456static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
457 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
458 { 0 },
459};
460
461static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
462 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
463 { 0 },
464};
465
466static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
467 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
468 { 0 },
469};
470
471static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
472 "l4per_cm:clk:0120:24",
473 NULL,
474};
475
476static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
477 .max_div = 4,
478 .flags = CLK_DIVIDER_POWER_OF_TWO,
479};
480
481static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
482 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
483 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
484 { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
485 { 0 },
486};
487
488static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
489 "l4per_cm:clk:0128:24",
490 NULL,
491};
492
493static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
494 .max_div = 4,
495 .flags = CLK_DIVIDER_POWER_OF_TWO,
496};
497
498static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
499 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
500 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
501 { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
502 { 0 },
503};
504
505static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
506 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
507 { 0 },
508};
509
510static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
511 "func_128m_clk",
512 "dpll_per_h13x2_ck",
513 NULL,
514};
515
516static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
517 "l4per_cm:clk:0138:24",
518 NULL,
519};
520
521static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
522 .max_div = 4,
523 .flags = CLK_DIVIDER_POWER_OF_TWO,
524};
525
526static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
527 { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
528 { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
529 { 0 },
530};
531
532static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
533 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
534 { 0 },
535};
536
537static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
538 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
539 { 0 },
540};
541
542static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
543 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
544 { 0 },
545};
546
547static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
548 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
549 { 0 },
550};
551
552static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
553 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
554 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
555 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
556 { 0 },
557};
558
559static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
560 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
561 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
562 { 0 },
563};
564
565static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
566 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
567 { 0 },
568};
569
570static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
571 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
572 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
573 { 0 },
574};
575
576static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
577 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
578 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
579 { 0 },
580};
581
582static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
583 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
584 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
585 { 0 },
586};
587
588static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
589 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
590 { 0 },
591};
592
593static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
594 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
595 { 0 },
596};
597
598static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
599 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
600 { 0 },
601};
602
603static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
604 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
605 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
606 { 0 },
607};
608
609static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
610 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
611 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
612 { 0 },
613};
614
615static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
616 { DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" },
617 { DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" },
618 { DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
619 { DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
620 { DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" },
621 { DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" },
622 { DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" },
623 { DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" },
624 { DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
625 { DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
626 { DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
627 { DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
628 { DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
629 { DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
630 { DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
631 { DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
632 { DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
633 { DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
634 { DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
635 { DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
636 { DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
637 { DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
638 { DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
639 { DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" },
640 { DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" },
641 { DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" },
642 { DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
643 { DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
644 { DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
645 { DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
646 { DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
647 { DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
648 { DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" },
649 { DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" },
650 { DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" },
651 { DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" },
652 { DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" },
653 { DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" },
654 { DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" },
655 { DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" },
656 { DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" },
657 { DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" },
658 { DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" },
659 { DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" },
660 { DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" },
661 { DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" },
662 { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
663 { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
664 { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
665 { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
666 { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
667 { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
668 { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
669 { DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" },
670 { DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" },
671 { DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" },
672 { DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" },
673 { 0 },
674};
675
676static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
677 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
678 { 0 },
679};
680
681static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
682 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
683 { 0 },
684};
685
686static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
687 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
688 { 0 },
689};
690
691static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
692 "sys_clkin1",
693 "sys_clkin2",
694 NULL,
695};
696
697static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
698 { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
699 { 0 },
700};
701
702static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
703 { DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
704 { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
705 { DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
706 { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
707 { DRA7_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },
708 { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
709 { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
710 { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
711 { DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"},
712 { 0 },
713};
714
715const struct omap_clkctrl_data dra7_clkctrl_compat_data[] __initconst = {
716 { 0x4a005320, dra7_mpu_clkctrl_regs },
717 { 0x4a005540, dra7_ipu_clkctrl_regs },
718 { 0x4a005740, dra7_rtc_clkctrl_regs },
719 { 0x4a008620, dra7_coreaon_clkctrl_regs },
720 { 0x4a008720, dra7_l3main1_clkctrl_regs },
721 { 0x4a008a20, dra7_dma_clkctrl_regs },
722 { 0x4a008b20, dra7_emif_clkctrl_regs },
723 { 0x4a008c00, dra7_atl_clkctrl_regs },
724 { 0x4a008d20, dra7_l4cfg_clkctrl_regs },
725 { 0x4a008e20, dra7_l3instr_clkctrl_regs },
726 { 0x4a009120, dra7_dss_clkctrl_regs },
727 { 0x4a009320, dra7_l3init_clkctrl_regs },
728 { 0x4a009700, dra7_l4per_clkctrl_regs },
729 { 0x4ae07820, dra7_wkupaon_clkctrl_regs },
730 { 0 },
731};
732
733struct ti_dt_clk dra7xx_compat_clks[] = {
734 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
735 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
736 DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
737 DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"),
738 DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"),
739 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"),
740 DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
741 DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
742 DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
743 DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"),
744 DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"),
745 DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"),
746 DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"),
747 DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
748 DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"),
749 DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"),
750 DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"),
751 DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"),
752 DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"),
753 DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"),
754 DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"),
755 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"),
756 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"),
757 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"),
758 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"),
759 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"),
760 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"),
761 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"),
762 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"),
763 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"),
764 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"),
765 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"),
766 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"),
767 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"),
768 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"),
769 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"),
770 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"),
771 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"),
772 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"),
773 DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"),
774 DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"),
775 DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
776 DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"),
777 DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"),
778 DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
779 DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"),
780 DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"),
781 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"),
782 DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"),
783 DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"),
784 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"),
785 DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"),
786 DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"),
787 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"),
788 DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"),
789 DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"),
790 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"),
791 DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"),
792 DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"),
793 DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"),
794 DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
795 DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"),
796 DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"),
797 DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"),
798 DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"),
799 DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"),
800 DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"),
801 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
802 DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"),
803 DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"),
804 DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"),
805 DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"),
806 DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"),
807 DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"),
808 DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"),
809 DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"),
810 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"),
811 DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"),
812 DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"),
813 DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"),
814 DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"),
815 DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"),
816 DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"),
817 DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"),
818 DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"),
819 DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"),
820 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"),
821 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"),
822 { .node_name = NULL },
823};
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 71a122b2dc67..597fb4a59318 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -23,7 +23,28 @@
23#define DRA7_DPLL_USB_DEFFREQ 960000000 23#define DRA7_DPLL_USB_DEFFREQ 960000000
24 24
25static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = { 25static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
26 { DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" }, 26 { DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
27 { 0 },
28};
29
30static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = {
31 { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_dsp_m2_ck" },
32 { 0 },
33};
34
35static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {
36 "dpll_abe_m2x2_ck",
37 "dpll_core_h22x2_ck",
38 NULL,
39};
40
41static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = {
42 { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
43 { 0 },
44};
45
46static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = {
47 { DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP, "ipu1-clkctrl:0000:24" },
27 { 0 }, 48 { 0 },
28}; 49};
29 50
@@ -108,45 +129,55 @@ static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
108}; 129};
109 130
110static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = { 131static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
111 { DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" }, 132 { DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },
112 { DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" }, 133 { DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" },
113 { DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" }, 134 { DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" },
114 { DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" }, 135 { DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" },
115 { DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" }, 136 { DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" },
116 { DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 137 { DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
117 { DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" }, 138 { DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" },
139 { 0 },
140};
141
142static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = {
143 { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_dsp_m2_ck" },
118 { 0 }, 144 { 0 },
119}; 145};
120 146
121static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = { 147static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
122 { DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 148 { DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
123 { 0 }, 149 { 0 },
124}; 150};
125 151
126static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = { 152static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
127 { DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, 153 { DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
128 { DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, 154 { DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
129 { 0 }, 155 { 0 },
130}; 156};
131 157
132static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = { 158static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
133 { DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 159 { DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
134 { DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 160 { DRA7_L3MAIN1_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
135 { DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" }, 161 { DRA7_L3MAIN1_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
136 { DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 162 { DRA7_L3MAIN1_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
137 { DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 163 { DRA7_L3MAIN1_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
138 { DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 164 { DRA7_L3MAIN1_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
139 { DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 165 { DRA7_L3MAIN1_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
166 { 0 },
167};
168
169static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = {
170 { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" },
140 { 0 }, 171 { 0 },
141}; 172};
142 173
143static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = { 174static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
144 { DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 175 { DRA7_DMA_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
145 { 0 }, 176 { 0 },
146}; 177};
147 178
148static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = { 179static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
149 { DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 180 { DRA7_EMIF_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
150 { 0 }, 181 { 0 },
151}; 182};
152 183
@@ -161,7 +192,7 @@ static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
161static const char * const dra7_atl_gfclk_mux_parents[] __initconst = { 192static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
162 "l3_iclk_div", 193 "l3_iclk_div",
163 "dpll_abe_m2_ck", 194 "dpll_abe_m2_ck",
164 "atl_cm:clk:0000:24", 195 "atl-clkctrl:0000:24",
165 NULL, 196 NULL,
166}; 197};
167 198
@@ -172,32 +203,32 @@ static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
172}; 203};
173 204
174static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = { 205static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
175 { DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" }, 206 { DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" },
176 { 0 }, 207 { 0 },
177}; 208};
178 209
179static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = { 210static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
180 { DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" }, 211 { DRA7_L4CFG_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
181 { DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" }, 212 { DRA7_L4CFG_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
182 { DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 213 { DRA7_L4CFG_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
183 { DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 214 { DRA7_L4CFG_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
184 { DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" }, 215 { DRA7_L4CFG_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
185 { DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" }, 216 { DRA7_L4CFG_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
186 { DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" }, 217 { DRA7_L4CFG_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
187 { DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" }, 218 { DRA7_L4CFG_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
188 { DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" }, 219 { DRA7_L4CFG_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
189 { DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" }, 220 { DRA7_L4CFG_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
190 { DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" }, 221 { DRA7_L4CFG_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
191 { DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" }, 222 { DRA7_L4CFG_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
192 { DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" }, 223 { DRA7_L4CFG_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
193 { DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" }, 224 { DRA7_L4CFG_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
194 { DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" }, 225 { DRA7_L4CFG_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
195 { 0 }, 226 { 0 },
196}; 227};
197 228
198static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = { 229static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
199 { DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 230 { DRA7_L3INSTR_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
200 { DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 231 { DRA7_L3INSTR_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
201 { 0 }, 232 { 0 },
202}; 233};
203 234
@@ -242,8 +273,8 @@ static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst =
242}; 273};
243 274
244static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = { 275static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
245 { DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" }, 276 { DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
246 { DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" }, 277 { DRA7_DSS_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
247 { 0 }, 278 { 0 },
248}; 279};
249 280
@@ -254,7 +285,7 @@ static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
254}; 285};
255 286
256static const char * const dra7_mmc1_fclk_div_parents[] __initconst = { 287static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
257 "l3init_cm:clk:0008:24", 288 "l3init-clkctrl:0008:24",
258 NULL, 289 NULL,
259}; 290};
260 291
@@ -271,7 +302,7 @@ static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
271}; 302};
272 303
273static const char * const dra7_mmc2_fclk_div_parents[] __initconst = { 304static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
274 "l3init_cm:clk:0010:24", 305 "l3init-clkctrl:0010:24",
275 NULL, 306 NULL,
276}; 307};
277 308
@@ -307,6 +338,24 @@ static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
307 { 0 }, 338 { 0 },
308}; 339};
309 340
341static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
342 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
343 { 0 },
344};
345
346static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
347 { DRA7_L3INIT_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
348 { DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
349 { DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
350 { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
351 { DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
352 { DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
353 { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
354 { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
355 { DRA7_L3INIT_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
356 { 0 },
357};
358
310static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = { 359static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
311 "apll_pcie_ck", 360 "apll_pcie_ck",
312 NULL, 361 NULL,
@@ -331,6 +380,12 @@ static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
331 { 0 }, 380 { 0 },
332}; 381};
333 382
383static const struct omap_clkctrl_reg_data dra7_pcie_clkctrl_regs[] __initconst = {
384 { DRA7_PCIE_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
385 { DRA7_PCIE_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
386 { 0 },
387};
388
334static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = { 389static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
335 "dpll_gmac_h11x2_ck", 390 "dpll_gmac_h11x2_ck",
336 "rmii_clk_ck", 391 "rmii_clk_ck",
@@ -352,24 +407,8 @@ static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
352 { 0 }, 407 { 0 },
353}; 408};
354 409
355static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = { 410static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
356 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL }, 411 { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck" },
357 { 0 },
358};
359
360static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
361 { DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
362 { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
363 { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
364 { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
365 { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
366 { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
367 { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
368 { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
369 { DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" },
370 { DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
371 { DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
372 { DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
373 { 0 }, 412 { 0 },
374}; 413};
375 414
@@ -443,21 +482,6 @@ static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
443 { 0 }, 482 { 0 },
444}; 483};
445 484
446static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
447 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
448 { 0 },
449};
450
451static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
452 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
453 { 0 },
454};
455
456static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
457 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
458 { 0 },
459};
460
461static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = { 485static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
462 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 486 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
463 { 0 }, 487 { 0 },
@@ -469,7 +493,7 @@ static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
469}; 493};
470 494
471static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = { 495static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
472 "l4per_cm:clk:0120:24", 496 "l4per-clkctrl:00f8:24",
473 NULL, 497 NULL,
474}; 498};
475 499
@@ -486,7 +510,7 @@ static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
486}; 510};
487 511
488static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = { 512static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
489 "l4per_cm:clk:0128:24", 513 "l4per-clkctrl:0100:24",
490 NULL, 514 NULL,
491}; 515};
492 516
@@ -502,8 +526,72 @@ static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
502 { 0 }, 526 { 0 },
503}; 527};
504 528
505static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = { 529static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
506 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 530 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
531 { 0 },
532};
533
534static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
535 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
536 { 0 },
537};
538
539static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
540 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
541 { 0 },
542};
543
544static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
545 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
546 { 0 },
547};
548
549static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
550 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
551 { 0 },
552};
553
554static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
555 { DRA7_L4PER_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0000:24" },
556 { DRA7_L4PER_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
557 { DRA7_L4PER_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
558 { DRA7_L4PER_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
559 { DRA7_L4PER_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
560 { DRA7_L4PER_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
561 { DRA7_L4PER_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
562 { DRA7_L4PER_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
563 { DRA7_L4PER_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
564 { DRA7_L4PER_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
565 { DRA7_L4PER_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
566 { DRA7_L4PER_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
567 { DRA7_L4PER_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
568 { DRA7_L4PER_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
569 { DRA7_L4PER_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
570 { DRA7_L4PER_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
571 { DRA7_L4PER_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
572 { DRA7_L4PER_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
573 { DRA7_L4PER_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
574 { DRA7_L4PER_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
575 { DRA7_L4PER_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
576 { DRA7_L4PER_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
577 { DRA7_L4PER_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
578 { DRA7_L4PER_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
579 { DRA7_L4PER_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:00f8:25" },
580 { DRA7_L4PER_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0100:25" },
581 { DRA7_L4PER_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0118:24" },
582 { DRA7_L4PER_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0120:24" },
583 { DRA7_L4PER_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0128:24" },
584 { DRA7_L4PER_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0130:24" },
585 { DRA7_L4PER_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0148:24" },
586 { 0 },
587};
588
589static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst = {
590 { DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
591 { DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
592 { DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
593 { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "" },
594 { DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
507 { 0 }, 595 { 0 },
508}; 596};
509 597
@@ -514,7 +602,7 @@ static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
514}; 602};
515 603
516static const char * const dra7_qspi_gfclk_div_parents[] __initconst = { 604static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
517 "l4per_cm:clk:0138:24", 605 "l4per2-clkctrl:012c:24",
518 NULL, 606 NULL,
519}; 607};
520 608
@@ -529,26 +617,6 @@ static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
529 { 0 }, 617 { 0 },
530}; 618};
531 619
532static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
533 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
534 { 0 },
535};
536
537static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
538 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
539 { 0 },
540};
541
542static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
543 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
544 { 0 },
545};
546
547static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
548 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
549 { 0 },
550};
551
552static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = { 620static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
553 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 621 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
554 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 622 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
@@ -562,11 +630,6 @@ static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
562 { 0 }, 630 { 0 },
563}; 631};
564 632
565static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
566 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
567 { 0 },
568};
569
570static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = { 633static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
571 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 634 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
572 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 635 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
@@ -612,64 +675,54 @@ static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
612 { 0 }, 675 { 0 },
613}; 676};
614 677
615static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = { 678static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst = {
616 { DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" }, 679 { DRA7_L4PER2_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div" },
617 { DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" }, 680 { DRA7_L4PER2_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "" },
618 { DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" }, 681 { DRA7_L4PER2_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "" },
619 { DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" }, 682 { DRA7_L4PER2_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
620 { DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" }, 683 { DRA7_L4PER2_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
621 { DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" }, 684 { DRA7_L4PER2_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
622 { DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" }, 685 { DRA7_L4PER2_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:012c:25" },
623 { DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" }, 686 { DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
624 { DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 687 { DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
625 { DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 688 { DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
626 { DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 689 { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:24" },
627 { DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 690 { DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
628 { DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 691 { DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
629 { DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 692 { DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
630 { DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" }, 693 { DRA7_L4PER2_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01dc:24" },
631 { DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" }, 694 { DRA7_L4PER2_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1" },
632 { DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" }, 695 { DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01f8:22" },
633 { DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 696 { DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01fc:22" },
634 { DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 697 { 0 },
635 { DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 698};
636 { DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 699
637 { DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 700static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
638 { DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" }, 701 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
639 { DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" }, 702 { 0 },
640 { DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" }, 703};
641 { DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" }, 704
642 { DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 705static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
643 { DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 706 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
644 { DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 707 { 0 },
645 { DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 708};
646 { DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 709
647 { DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 710static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
648 { DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" }, 711 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
649 { DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" }, 712 { 0 },
650 { DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" }, 713};
651 { DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" }, 714
652 { DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" }, 715static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
653 { DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" }, 716 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
654 { DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" }, 717 { 0 },
655 { DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" }, 718};
656 { DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" }, 719
657 { DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" }, 720static const struct omap_clkctrl_reg_data dra7_l4per3_clkctrl_regs[] __initconst = {
658 { DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" }, 721 { DRA7_L4PER3_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div" },
659 { DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" }, 722 { DRA7_L4PER3_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00b4:24" },
660 { DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" }, 723 { DRA7_L4PER3_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00bc:24" },
661 { DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" }, 724 { DRA7_L4PER3_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00c4:24" },
662 { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, 725 { DRA7_L4PER3_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:011c:24" },
663 { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
664 { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
665 { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
666 { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
667 { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
668 { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
669 { DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" },
670 { DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" },
671 { DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" },
672 { DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" },
673 { 0 }, 726 { 0 },
674}; 727};
675 728
@@ -700,24 +753,28 @@ static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
700}; 753};
701 754
702static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = { 755static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
703 { DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 756 { DRA7_WKUPAON_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
704 { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 757 { DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
705 { DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, 758 { DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
706 { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" }, 759 { DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
707 { DRA7_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" }, 760 { DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },
708 { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 761 { DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
709 { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" }, 762 { DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" },
710 { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" }, 763 { DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" },
711 { DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"}, 764 { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk" },
712 { 0 }, 765 { 0 },
713}; 766};
714 767
715const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = { 768const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
716 { 0x4a005320, dra7_mpu_clkctrl_regs }, 769 { 0x4a005320, dra7_mpu_clkctrl_regs },
717 { 0x4a005540, dra7_ipu_clkctrl_regs }, 770 { 0x4a005420, dra7_dsp1_clkctrl_regs },
718 { 0x4a005740, dra7_rtc_clkctrl_regs }, 771 { 0x4a005520, dra7_ipu1_clkctrl_regs },
772 { 0x4a005550, dra7_ipu_clkctrl_regs },
773 { 0x4a005620, dra7_dsp2_clkctrl_regs },
774 { 0x4a005720, dra7_rtc_clkctrl_regs },
719 { 0x4a008620, dra7_coreaon_clkctrl_regs }, 775 { 0x4a008620, dra7_coreaon_clkctrl_regs },
720 { 0x4a008720, dra7_l3main1_clkctrl_regs }, 776 { 0x4a008720, dra7_l3main1_clkctrl_regs },
777 { 0x4a008920, dra7_ipu2_clkctrl_regs },
721 { 0x4a008a20, dra7_dma_clkctrl_regs }, 778 { 0x4a008a20, dra7_dma_clkctrl_regs },
722 { 0x4a008b20, dra7_emif_clkctrl_regs }, 779 { 0x4a008b20, dra7_emif_clkctrl_regs },
723 { 0x4a008c00, dra7_atl_clkctrl_regs }, 780 { 0x4a008c00, dra7_atl_clkctrl_regs },
@@ -725,7 +782,12 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
725 { 0x4a008e20, dra7_l3instr_clkctrl_regs }, 782 { 0x4a008e20, dra7_l3instr_clkctrl_regs },
726 { 0x4a009120, dra7_dss_clkctrl_regs }, 783 { 0x4a009120, dra7_dss_clkctrl_regs },
727 { 0x4a009320, dra7_l3init_clkctrl_regs }, 784 { 0x4a009320, dra7_l3init_clkctrl_regs },
728 { 0x4a009700, dra7_l4per_clkctrl_regs }, 785 { 0x4a0093b0, dra7_pcie_clkctrl_regs },
786 { 0x4a0093d0, dra7_gmac_clkctrl_regs },
787 { 0x4a009728, dra7_l4per_clkctrl_regs },
788 { 0x4a0098a0, dra7_l4sec_clkctrl_regs },
789 { 0x4a00970c, dra7_l4per2_clkctrl_regs },
790 { 0x4a009714, dra7_l4per3_clkctrl_regs },
729 { 0x4ae07820, dra7_wkupaon_clkctrl_regs }, 791 { 0x4ae07820, dra7_wkupaon_clkctrl_regs },
730 { 0 }, 792 { 0 },
731}; 793};
@@ -734,91 +796,92 @@ static struct ti_dt_clk dra7xx_clks[] = {
734 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 796 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
735 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"), 797 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
736 DT_CLK(NULL, "sys_clkin", "sys_clkin1"), 798 DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
737 DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"), 799 DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"),
738 DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"), 800 DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"),
739 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"), 801 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"),
740 DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"), 802 DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
741 DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"), 803 DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
742 DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"), 804 DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
743 DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"), 805 DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"),
744 DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"), 806 DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"),
745 DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"), 807 DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"),
746 DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"), 808 DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"),
747 DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"), 809 DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
748 DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"), 810 DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"),
749 DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"), 811 DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"),
750 DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"), 812 DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"),
751 DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"), 813 DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"),
752 DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"), 814 DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"),
753 DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"), 815 DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"),
754 DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"), 816 DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"),
755 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"), 817 DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"),
756 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"), 818 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"),
757 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"), 819 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"),
758 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"), 820 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"),
759 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"), 821 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"),
760 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"), 822 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"),
761 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"), 823 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"),
762 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"), 824 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"),
763 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"), 825 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"),
764 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"), 826 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"),
765 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"), 827 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"),
766 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"), 828 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"),
767 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"), 829 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"),
768 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"), 830 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"),
769 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"), 831 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
770 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"), 832 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
771 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"), 833 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
772 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"), 834 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:22"),
773 DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"), 835 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:24"),
774 DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"), 836 DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
775 DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"), 837 DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
776 DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"), 838 DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
777 DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"), 839 DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"),
778 DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"), 840 DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"),
779 DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"), 841 DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
780 DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"), 842 DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"),
781 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"), 843 DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"),
782 DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"), 844 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"),
783 DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"), 845 DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"),
784 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"), 846 DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"),
785 DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"), 847 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"),
786 DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"), 848 DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"),
787 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"), 849 DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"),
788 DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"), 850 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"),
789 DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"), 851 DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"),
790 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"), 852 DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"),
791 DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"), 853 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"),
792 DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"), 854 DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"),
793 DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"), 855 DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"),
794 DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"), 856 DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"),
795 DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"), 857 DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
796 DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"), 858 DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"),
797 DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"), 859 DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"),
798 DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"), 860 DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"),
799 DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"), 861 DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"),
800 DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"), 862 DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"),
801 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"), 863 DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"),
802 DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"), 864 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
803 DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"), 865 DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"),
804 DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"), 866 DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"),
805 DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"), 867 DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"),
806 DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"), 868 DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"),
807 DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"), 869 DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"),
808 DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"), 870 DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"),
809 DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"), 871 DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"),
810 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"), 872 DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"),
811 DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"), 873 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"),
812 DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"), 874 DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"),
813 DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"), 875 DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"),
814 DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"), 876 DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"),
815 DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"), 877 DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"),
816 DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"), 878 DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"),
817 DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"), 879 DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"),
818 DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"), 880 DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"),
819 DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"), 881 DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"),
820 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"), 882 DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"),
821 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"), 883 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"),
884 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"),
822 { .node_name = NULL }, 885 { .node_name = NULL },
823}; 886};
824 887
@@ -827,7 +890,10 @@ int __init dra7xx_dt_clk_init(void)
827 int rc; 890 int rc;
828 struct clk *dpll_ck, *hdcp_ck; 891 struct clk *dpll_ck, *hdcp_ck;
829 892
830 ti_dt_clocks_register(dra7xx_clks); 893 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
894 ti_dt_clocks_register(dra7xx_compat_clks);
895 else
896 ti_dt_clocks_register(dra7xx_clks);
831 897
832 omap2_clk_disable_autoidle_all(); 898 omap2_clk_disable_autoidle_all();
833 899
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index 33001a75d90c..1c690e57a3f1 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -34,7 +34,7 @@
34struct ti_clk_ll_ops *ti_clk_ll_ops; 34struct ti_clk_ll_ops *ti_clk_ll_ops;
35static struct device_node *clocks_node_ptr[CLK_MAX_MEMMAPS]; 35static struct device_node *clocks_node_ptr[CLK_MAX_MEMMAPS];
36 36
37static struct ti_clk_features ti_clk_features; 37struct ti_clk_features ti_clk_features;
38 38
39struct clk_iomap { 39struct clk_iomap {
40 struct regmap *regmap; 40 struct regmap *regmap;
@@ -140,6 +140,9 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
140 int ret; 140 int ret;
141 static bool clkctrl_nodes_missing; 141 static bool clkctrl_nodes_missing;
142 static bool has_clkctrl_data; 142 static bool has_clkctrl_data;
143 static bool compat_mode;
144
145 compat_mode = ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT;
143 146
144 for (c = oclks; c->node_name != NULL; c++) { 147 for (c = oclks; c->node_name != NULL; c++) {
145 strcpy(buf, c->node_name); 148 strcpy(buf, c->node_name);
@@ -164,7 +167,7 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
164 continue; 167 continue;
165 168
166 node = of_find_node_by_name(NULL, buf); 169 node = of_find_node_by_name(NULL, buf);
167 if (num_args) { 170 if (num_args && compat_mode) {
168 parent = node; 171 parent = node;
169 node = of_get_child_by_name(parent, "clk"); 172 node = of_get_child_by_name(parent, "clk");
170 of_node_put(parent); 173 of_node_put(parent);
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
index 240e911a3db9..469f560ae1cf 100644
--- a/drivers/clk/ti/clkctrl.c
+++ b/drivers/clk/ti/clkctrl.c
@@ -259,8 +259,13 @@ _ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider,
259 struct omap_clkctrl_clk *clkctrl_clk; 259 struct omap_clkctrl_clk *clkctrl_clk;
260 int ret = 0; 260 int ret = 0;
261 261
262 init.name = kasprintf(GFP_KERNEL, "%pOFn:%pOFn:%04x:%d", node->parent, 262 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
263 node, offset, bit); 263 init.name = kasprintf(GFP_KERNEL, "%pOFn:%pOFn:%04x:%d",
264 node->parent, node, offset,
265 bit);
266 else
267 init.name = kasprintf(GFP_KERNEL, "%pOFn:%04x:%d", node,
268 offset, bit);
264 clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL); 269 clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
265 if (!init.name || !clkctrl_clk) { 270 if (!init.name || !clkctrl_clk) {
266 ret = -ENOMEM; 271 ret = -ENOMEM;
@@ -440,6 +445,11 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
440 const __be32 *addrp; 445 const __be32 *addrp;
441 u32 addr; 446 u32 addr;
442 int ret; 447 int ret;
448 char *c;
449
450 if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) &&
451 !strcmp(node->name, "clk"))
452 ti_clk_features.flags |= TI_CLK_CLKCTRL_COMPAT;
443 453
444 addrp = of_get_address(node, 0, NULL, NULL); 454 addrp = of_get_address(node, 0, NULL, NULL);
445 addr = (u32)of_translate_address(node, addrp); 455 addr = (u32)of_translate_address(node, addrp);
@@ -453,18 +463,35 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
453 data = omap5_clkctrl_data; 463 data = omap5_clkctrl_data;
454#endif 464#endif
455#ifdef CONFIG_SOC_DRA7XX 465#ifdef CONFIG_SOC_DRA7XX
456 if (of_machine_is_compatible("ti,dra7")) 466 if (of_machine_is_compatible("ti,dra7")) {
457 data = dra7_clkctrl_data; 467 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
468 data = dra7_clkctrl_compat_data;
469 else
470 data = dra7_clkctrl_data;
471 }
458#endif 472#endif
459#ifdef CONFIG_SOC_AM33XX 473#ifdef CONFIG_SOC_AM33XX
460 if (of_machine_is_compatible("ti,am33xx")) 474 if (of_machine_is_compatible("ti,am33xx")) {
461 data = am3_clkctrl_data; 475 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
476 data = am3_clkctrl_compat_data;
477 else
478 data = am3_clkctrl_data;
479 }
462#endif 480#endif
463#ifdef CONFIG_SOC_AM43XX 481#ifdef CONFIG_SOC_AM43XX
464 if (of_machine_is_compatible("ti,am4372")) 482 if (of_machine_is_compatible("ti,am4372")) {
465 data = am4_clkctrl_data; 483 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
466 if (of_machine_is_compatible("ti,am438x")) 484 data = am4_clkctrl_compat_data;
467 data = am438x_clkctrl_data; 485 else
486 data = am4_clkctrl_data;
487 }
488
489 if (of_machine_is_compatible("ti,am438x")) {
490 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
491 data = am438x_clkctrl_compat_data;
492 else
493 data = am438x_clkctrl_data;
494 }
468#endif 495#endif
469#ifdef CONFIG_SOC_TI81XX 496#ifdef CONFIG_SOC_TI81XX
470 if (of_machine_is_compatible("ti,dm814")) 497 if (of_machine_is_compatible("ti,dm814"))
@@ -492,19 +519,43 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
492 519
493 provider->base = of_iomap(node, 0); 520 provider->base = of_iomap(node, 0);
494 521
495 provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFnxxx", node->parent); 522 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) {
496 if (!provider->clkdm_name) { 523 provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFnxxx", node->parent);
497 kfree(provider); 524 if (!provider->clkdm_name) {
498 return; 525 kfree(provider);
526 return;
527 }
528
529 /*
530 * Create default clkdm name, replace _cm from end of parent
531 * node name with _clkdm
532 */
533 provider->clkdm_name[strlen(provider->clkdm_name) - 5] = 0;
534 } else {
535 provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFn", node);
536 if (!provider->clkdm_name) {
537 kfree(provider);
538 return;
539 }
540
541 /*
542 * Create default clkdm name, replace _clkctrl from end of
543 * node name with _clkdm
544 */
545 provider->clkdm_name[strlen(provider->clkdm_name) - 7] = 0;
499 } 546 }
500 547
501 /*
502 * Create default clkdm name, replace _cm from end of parent node
503 * name with _clkdm
504 */
505 provider->clkdm_name[strlen(provider->clkdm_name) - 5] = 0;
506 strcat(provider->clkdm_name, "clkdm"); 548 strcat(provider->clkdm_name, "clkdm");
507 549
550 /* Replace any dash from the clkdm name with underscore */
551 c = provider->clkdm_name;
552
553 while (*c) {
554 if (*c == '-')
555 *c = '_';
556 c++;
557 }
558
508 INIT_LIST_HEAD(&provider->clocks); 559 INIT_LIST_HEAD(&provider->clocks);
509 560
510 /* Generate clocks */ 561 /* Generate clocks */
@@ -537,9 +588,13 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
537 init.flags = 0; 588 init.flags = 0;
538 if (reg_data->flags & CLKF_SET_RATE_PARENT) 589 if (reg_data->flags & CLKF_SET_RATE_PARENT)
539 init.flags |= CLK_SET_RATE_PARENT; 590 init.flags |= CLK_SET_RATE_PARENT;
540 init.name = kasprintf(GFP_KERNEL, "%pOFn:%pOFn:%04x:%d", 591 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
541 node->parent, node, 592 init.name = kasprintf(GFP_KERNEL, "%pOFn:%pOFn:%04x:%d",
542 reg_data->offset, 0); 593 node->parent, node,
594 reg_data->offset, 0);
595 else
596 init.name = kasprintf(GFP_KERNEL, "%pOFn:%04x:%d",
597 node, reg_data->offset, 0);
543 clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL); 598 clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
544 if (!init.name || !clkctrl_clk) 599 if (!init.name || !clkctrl_clk)
545 goto cleanup; 600 goto cleanup;
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index b58278077226..9f312a219510 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -24,6 +24,7 @@ struct clk_omap_divider {
24 u8 flags; 24 u8 flags;
25 s8 latch; 25 s8 latch;
26 const struct clk_div_table *table; 26 const struct clk_div_table *table;
27 u32 context;
27}; 28};
28 29
29#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw) 30#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
@@ -36,6 +37,7 @@ struct clk_omap_mux {
36 u8 shift; 37 u8 shift;
37 s8 latch; 38 s8 latch;
38 u8 flags; 39 u8 flags;
40 u8 saved_parent;
39}; 41};
40 42
41#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw) 43#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
@@ -184,9 +186,16 @@ struct omap_clkctrl_data {
184extern const struct omap_clkctrl_data omap4_clkctrl_data[]; 186extern const struct omap_clkctrl_data omap4_clkctrl_data[];
185extern const struct omap_clkctrl_data omap5_clkctrl_data[]; 187extern const struct omap_clkctrl_data omap5_clkctrl_data[];
186extern const struct omap_clkctrl_data dra7_clkctrl_data[]; 188extern const struct omap_clkctrl_data dra7_clkctrl_data[];
189extern const struct omap_clkctrl_data dra7_clkctrl_compat_data[];
190extern struct ti_dt_clk dra7xx_compat_clks[];
187extern const struct omap_clkctrl_data am3_clkctrl_data[]; 191extern const struct omap_clkctrl_data am3_clkctrl_data[];
192extern const struct omap_clkctrl_data am3_clkctrl_compat_data[];
193extern struct ti_dt_clk am33xx_compat_clks[];
188extern const struct omap_clkctrl_data am4_clkctrl_data[]; 194extern const struct omap_clkctrl_data am4_clkctrl_data[];
195extern const struct omap_clkctrl_data am4_clkctrl_compat_data[];
196extern struct ti_dt_clk am43xx_compat_clks[];
189extern const struct omap_clkctrl_data am438x_clkctrl_data[]; 197extern const struct omap_clkctrl_data am438x_clkctrl_data[];
198extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[];
190extern const struct omap_clkctrl_data dm814_clkctrl_data[]; 199extern const struct omap_clkctrl_data dm814_clkctrl_data[];
191extern const struct omap_clkctrl_data dm816_clkctrl_data[]; 200extern const struct omap_clkctrl_data dm816_clkctrl_data[];
192 201
@@ -233,6 +242,8 @@ extern const struct clk_ops ti_clk_divider_ops;
233extern const struct clk_ops ti_clk_mux_ops; 242extern const struct clk_ops ti_clk_mux_ops;
234extern const struct clk_ops omap_gate_clk_ops; 243extern const struct clk_ops omap_gate_clk_ops;
235 244
245extern struct ti_clk_features ti_clk_features;
246
236void omap2_init_clk_clkdm(struct clk_hw *hw); 247void omap2_init_clk_clkdm(struct clk_hw *hw);
237int omap2_clkops_enable_clkdm(struct clk_hw *hw); 248int omap2_clkops_enable_clkdm(struct clk_hw *hw);
238void omap2_clkops_disable_clkdm(struct clk_hw *hw); 249void omap2_clkops_disable_clkdm(struct clk_hw *hw);
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index 4fcb337a6d1c..8d77090ad94a 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -268,10 +268,46 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
268 return 0; 268 return 0;
269} 269}
270 270
271/**
272 * clk_divider_save_context - Save the divider value
273 * @hw: pointer struct clk_hw
274 *
275 * Save the divider value
276 */
277static int clk_divider_save_context(struct clk_hw *hw)
278{
279 struct clk_omap_divider *divider = to_clk_omap_divider(hw);
280 u32 val;
281
282 val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
283 divider->context = val & div_mask(divider);
284
285 return 0;
286}
287
288/**
289 * clk_divider_restore_context - restore the saved the divider value
290 * @hw: pointer struct clk_hw
291 *
292 * Restore the saved the divider value
293 */
294static void clk_divider_restore_context(struct clk_hw *hw)
295{
296 struct clk_omap_divider *divider = to_clk_omap_divider(hw);
297 u32 val;
298
299 val = ti_clk_ll_ops->clk_readl(&divider->reg);
300 val &= ~(div_mask(divider) << divider->shift);
301 val |= divider->context << divider->shift;
302 ti_clk_ll_ops->clk_writel(val, &divider->reg);
303}
304
271const struct clk_ops ti_clk_divider_ops = { 305const struct clk_ops ti_clk_divider_ops = {
272 .recalc_rate = ti_clk_divider_recalc_rate, 306 .recalc_rate = ti_clk_divider_recalc_rate,
273 .round_rate = ti_clk_divider_round_rate, 307 .round_rate = ti_clk_divider_round_rate,
274 .set_rate = ti_clk_divider_set_rate, 308 .set_rate = ti_clk_divider_set_rate,
309 .save_context = clk_divider_save_context,
310 .restore_context = clk_divider_restore_context,
275}; 311};
276 312
277static struct clk *_register_divider(struct device *dev, const char *name, 313static struct clk *_register_divider(struct device *dev, const char *name,
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 2e80c5ead74a..92e28af7afba 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -39,6 +39,8 @@ static const struct clk_ops dpll_m4xen_ck_ops = {
39 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 39 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
40 .determine_rate = &omap4_dpll_regm4xen_determine_rate, 40 .determine_rate = &omap4_dpll_regm4xen_determine_rate,
41 .get_parent = &omap2_init_dpll_parent, 41 .get_parent = &omap2_init_dpll_parent,
42 .save_context = &omap3_core_dpll_save_context,
43 .restore_context = &omap3_core_dpll_restore_context,
42}; 44};
43#else 45#else
44static const struct clk_ops dpll_m4xen_ck_ops = {}; 46static const struct clk_ops dpll_m4xen_ck_ops = {};
@@ -62,6 +64,8 @@ static const struct clk_ops dpll_ck_ops = {
62 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 64 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
63 .determine_rate = &omap3_noncore_dpll_determine_rate, 65 .determine_rate = &omap3_noncore_dpll_determine_rate,
64 .get_parent = &omap2_init_dpll_parent, 66 .get_parent = &omap2_init_dpll_parent,
67 .save_context = &omap3_noncore_dpll_save_context,
68 .restore_context = &omap3_noncore_dpll_restore_context,
65}; 69};
66 70
67static const struct clk_ops dpll_no_gate_ck_ops = { 71static const struct clk_ops dpll_no_gate_ck_ops = {
@@ -72,6 +76,8 @@ static const struct clk_ops dpll_no_gate_ck_ops = {
72 .set_parent = &omap3_noncore_dpll_set_parent, 76 .set_parent = &omap3_noncore_dpll_set_parent,
73 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 77 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
74 .determine_rate = &omap3_noncore_dpll_determine_rate, 78 .determine_rate = &omap3_noncore_dpll_determine_rate,
79 .save_context = &omap3_noncore_dpll_save_context,
80 .restore_context = &omap3_noncore_dpll_restore_context
75}; 81};
76#else 82#else
77static const struct clk_ops dpll_core_ck_ops = {}; 83static const struct clk_ops dpll_core_ck_ops = {};
diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c
index 4534de2ef455..44b6b6403753 100644
--- a/drivers/clk/ti/dpll3xxx.c
+++ b/drivers/clk/ti/dpll3xxx.c
@@ -782,6 +782,130 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
782 return rate; 782 return rate;
783} 783}
784 784
785/**
786 * omap3_core_dpll_save_context - Save the m and n values of the divider
787 * @hw: pointer struct clk_hw
788 *
789 * Before the dpll registers are lost save the last rounded rate m and n
790 * and the enable mask.
791 */
792int omap3_core_dpll_save_context(struct clk_hw *hw)
793{
794 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
795 struct dpll_data *dd;
796 u32 v;
797
798 dd = clk->dpll_data;
799
800 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
801 clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
802
803 if (clk->context == DPLL_LOCKED) {
804 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
805 dd->last_rounded_m = (v & dd->mult_mask) >>
806 __ffs(dd->mult_mask);
807 dd->last_rounded_n = ((v & dd->div1_mask) >>
808 __ffs(dd->div1_mask)) + 1;
809 }
810
811 return 0;
812}
813
814/**
815 * omap3_core_dpll_restore_context - restore the m and n values of the divider
816 * @hw: pointer struct clk_hw
817 *
818 * Restore the last rounded rate m and n
819 * and the enable mask.
820 */
821void omap3_core_dpll_restore_context(struct clk_hw *hw)
822{
823 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
824 const struct dpll_data *dd;
825 u32 v;
826
827 dd = clk->dpll_data;
828
829 if (clk->context == DPLL_LOCKED) {
830 _omap3_dpll_write_clken(clk, 0x4);
831 _omap3_wait_dpll_status(clk, 0);
832
833 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
834 v &= ~(dd->mult_mask | dd->div1_mask);
835 v |= dd->last_rounded_m << __ffs(dd->mult_mask);
836 v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
837 ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
838
839 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
840 _omap3_wait_dpll_status(clk, 1);
841 } else {
842 _omap3_dpll_write_clken(clk, clk->context);
843 }
844}
845
846/**
847 * omap3_non_core_dpll_save_context - Save the m and n values of the divider
848 * @hw: pointer struct clk_hw
849 *
850 * Before the dpll registers are lost save the last rounded rate m and n
851 * and the enable mask.
852 */
853int omap3_noncore_dpll_save_context(struct clk_hw *hw)
854{
855 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
856 struct dpll_data *dd;
857 u32 v;
858
859 dd = clk->dpll_data;
860
861 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
862 clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
863
864 if (clk->context == DPLL_LOCKED) {
865 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
866 dd->last_rounded_m = (v & dd->mult_mask) >>
867 __ffs(dd->mult_mask);
868 dd->last_rounded_n = ((v & dd->div1_mask) >>
869 __ffs(dd->div1_mask)) + 1;
870 }
871
872 return 0;
873}
874
875/**
876 * omap3_core_dpll_restore_context - restore the m and n values of the divider
877 * @hw: pointer struct clk_hw
878 *
879 * Restore the last rounded rate m and n
880 * and the enable mask.
881 */
882void omap3_noncore_dpll_restore_context(struct clk_hw *hw)
883{
884 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
885 const struct dpll_data *dd;
886 u32 ctrl, mult_div1;
887
888 dd = clk->dpll_data;
889
890 ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
891 mult_div1 = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
892
893 if (clk->context == ((ctrl & dd->enable_mask) >>
894 __ffs(dd->enable_mask)) &&
895 dd->last_rounded_m == ((mult_div1 & dd->mult_mask) >>
896 __ffs(dd->mult_mask)) &&
897 dd->last_rounded_n == ((mult_div1 & dd->div1_mask) >>
898 __ffs(dd->div1_mask)) + 1) {
899 /* nothing to be done */
900 return;
901 }
902
903 if (clk->context == DPLL_LOCKED)
904 omap3_noncore_dpll_program(clk, 0);
905 else
906 _omap3_dpll_write_clken(clk, clk->context);
907}
908
785/* OMAP3/4 non-CORE DPLL clkops */ 909/* OMAP3/4 non-CORE DPLL clkops */
786const struct clk_hw_omap_ops clkhwops_omap3_dpll = { 910const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
787 .allow_idle = omap3_dpll_allow_idle, 911 .allow_idle = omap3_dpll_allow_idle,
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
index d4b5638e8b99..1c78fff5513c 100644
--- a/drivers/clk/ti/gate.c
+++ b/drivers/clk/ti/gate.c
@@ -33,6 +33,7 @@ static const struct clk_ops omap_gate_clkdm_clk_ops = {
33 .init = &omap2_init_clk_clkdm, 33 .init = &omap2_init_clk_clkdm,
34 .enable = &omap2_clkops_enable_clkdm, 34 .enable = &omap2_clkops_enable_clkdm,
35 .disable = &omap2_clkops_disable_clkdm, 35 .disable = &omap2_clkops_disable_clkdm,
36 .restore_context = clk_gate_restore_context,
36}; 37};
37 38
38const struct clk_ops omap_gate_clk_ops = { 39const struct clk_ops omap_gate_clk_ops = {
@@ -40,6 +41,7 @@ const struct clk_ops omap_gate_clk_ops = {
40 .enable = &omap2_dflt_clk_enable, 41 .enable = &omap2_dflt_clk_enable,
41 .disable = &omap2_dflt_clk_disable, 42 .disable = &omap2_dflt_clk_disable,
42 .is_enabled = &omap2_dflt_clk_is_enabled, 43 .is_enabled = &omap2_dflt_clk_is_enabled,
44 .restore_context = clk_gate_restore_context,
43}; 45};
44 46
45static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = { 47static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
@@ -47,6 +49,7 @@ static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
47 .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore, 49 .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
48 .disable = &omap2_dflt_clk_disable, 50 .disable = &omap2_dflt_clk_disable,
49 .is_enabled = &omap2_dflt_clk_is_enabled, 51 .is_enabled = &omap2_dflt_clk_is_enabled,
52 .restore_context = clk_gate_restore_context,
50}; 53};
51 54
52/** 55/**
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index 18be7eb51546..883bdde94d04 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -91,10 +91,39 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
91 return 0; 91 return 0;
92} 92}
93 93
94/**
95 * clk_mux_save_context - Save the parent selcted in the mux
96 * @hw: pointer struct clk_hw
97 *
98 * Save the parent mux value.
99 */
100static int clk_mux_save_context(struct clk_hw *hw)
101{
102 struct clk_omap_mux *mux = to_clk_omap_mux(hw);
103
104 mux->saved_parent = ti_clk_mux_get_parent(hw);
105 return 0;
106}
107
108/**
109 * clk_mux_restore_context - Restore the parent in the mux
110 * @hw: pointer struct clk_hw
111 *
112 * Restore the saved parent mux value.
113 */
114static void clk_mux_restore_context(struct clk_hw *hw)
115{
116 struct clk_omap_mux *mux = to_clk_omap_mux(hw);
117
118 ti_clk_mux_set_parent(hw, mux->saved_parent);
119}
120
94const struct clk_ops ti_clk_mux_ops = { 121const struct clk_ops ti_clk_mux_ops = {
95 .get_parent = ti_clk_mux_get_parent, 122 .get_parent = ti_clk_mux_get_parent,
96 .set_parent = ti_clk_mux_set_parent, 123 .set_parent = ti_clk_mux_set_parent,
97 .determine_rate = __clk_mux_determine_rate, 124 .determine_rate = __clk_mux_determine_rate,
125 .save_context = clk_mux_save_context,
126 .restore_context = clk_mux_restore_context,
98}; 127};
99 128
100static struct clk *_register_mux(struct device *dev, const char *name, 129static struct clk *_register_mux(struct device *dev, const char *name,
diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h
index b396f00e481d..86a8806e2140 100644
--- a/include/dt-bindings/clock/am3.h
+++ b/include/dt-bindings/clock/am3.h
@@ -16,6 +16,8 @@
16#define AM3_CLKCTRL_OFFSET 0x0 16#define AM3_CLKCTRL_OFFSET 0x0
17#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) 17#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)
18 18
19/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
20
19/* l4_per clocks */ 21/* l4_per clocks */
20#define AM3_L4_PER_CLKCTRL_OFFSET 0x14 22#define AM3_L4_PER_CLKCTRL_OFFSET 0x14
21#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) 23#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
@@ -105,4 +107,121 @@
105#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) 107#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
106#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) 108#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
107 109
110/* XXX: Compatibility part end */
111
112/* l4ls clocks */
113#define AM3_L4LS_CLKCTRL_OFFSET 0x38
114#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET)
115#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38)
116#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c)
117#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40)
118#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44)
119#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48)
120#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c)
121#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50)
122#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60)
123#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c)
124#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70)
125#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74)
126#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78)
127#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c)
128#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80)
129#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84)
130#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88)
131#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90)
132#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac)
133#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0)
134#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4)
135#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0)
136#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4)
137#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc)
138#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4)
139#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8)
140#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec)
141#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0)
142#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4)
143#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c)
144#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110)
145#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130)
146
147/* l3s clocks */
148#define AM3_L3S_CLKCTRL_OFFSET 0x1c
149#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET)
150#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c)
151#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30)
152#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34)
153#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68)
154#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8)
155
156/* l3 clocks */
157#define AM3_L3_CLKCTRL_OFFSET 0x24
158#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET)
159#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24)
160#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28)
161#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c)
162#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94)
163#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0)
164#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc)
165#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc)
166#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0)
167#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc)
168#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100)
169
170/* l4hs clocks */
171#define AM3_L4HS_CLKCTRL_OFFSET 0x120
172#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET)
173#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120)
174
175/* pruss_ocp clocks */
176#define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8
177#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)
178#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8)
179
180/* cpsw_125mhz clocks */
181#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14)
182
183/* lcdc clocks */
184#define AM3_LCDC_CLKCTRL_OFFSET 0x18
185#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET)
186#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18)
187
188/* clk_24mhz clocks */
189#define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c
190#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)
191#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c)
192
193/* l4_wkup clocks */
194#define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
195#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8)
196#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc)
197#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4)
198#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8)
199#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc)
200#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0)
201#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4)
202#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8)
203#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4)
204
205/* l3_aon clocks */
206#define AM3_L3_AON_CLKCTRL_OFFSET 0x14
207#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET)
208#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14)
209
210/* l4_wkup_aon clocks */
211#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0
212#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)
213#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0)
214
215/* mpu clocks */
216#define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
217
218/* l4_rtc clocks */
219#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
220
221/* gfx_l3 clocks */
222#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
223
224/* l4_cefuse clocks */
225#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20)
226
108#endif 227#endif
diff --git a/include/dt-bindings/clock/am4.h b/include/dt-bindings/clock/am4.h
index d21df00b3270..0f545b5afd60 100644
--- a/include/dt-bindings/clock/am4.h
+++ b/include/dt-bindings/clock/am4.h
@@ -16,6 +16,8 @@
16#define AM4_CLKCTRL_OFFSET 0x20 16#define AM4_CLKCTRL_OFFSET 0x20
17#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET) 17#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET)
18 18
19/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
20
19/* l4_wkup clocks */ 21/* l4_wkup clocks */
20#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120) 22#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
21#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220) 23#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
@@ -110,4 +112,134 @@
110#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20) 112#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20)
111#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20) 113#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20)
112 114
115/* XXX: Compatibility part end. */
116
117/* l3s_tsc clocks */
118#define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
119#define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET)
120#define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
121
122/* l4_wkup_aon clocks */
123#define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
124#define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET)
125#define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
126#define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
127
128/* l4_wkup clocks */
129#define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
130#define AM4_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET)
131#define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
132#define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
133#define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
134#define AM4_L4_WKUP_I2C1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x340)
135#define AM4_L4_WKUP_UART1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x348)
136#define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x350)
137#define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x358)
138#define AM4_L4_WKUP_CONTROL_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x360)
139#define AM4_L4_WKUP_GPIO1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x368)
140
141/* mpu clocks */
142#define AM4_MPU_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
143
144/* gfx_l3 clocks */
145#define AM4_GFX_L3_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
146
147/* l4_rtc clocks */
148#define AM4_L4_RTC_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
149
150/* l3 clocks */
151#define AM4_L3_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
152#define AM4_L3_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28)
153#define AM4_L3_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30)
154#define AM4_L3_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40)
155#define AM4_L3_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50)
156#define AM4_L3_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58)
157#define AM4_L3_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78)
158#define AM4_L3_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80)
159#define AM4_L3_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88)
160#define AM4_L3_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90)
161#define AM4_L3_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0)
162
163/* l3s clocks */
164#define AM4_L3S_CLKCTRL_OFFSET 0x68
165#define AM4_L3S_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_CLKCTRL_OFFSET)
166#define AM4_L3S_VPFE0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x68)
167#define AM4_L3S_VPFE1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x70)
168#define AM4_L3S_GPMC_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x220)
169#define AM4_L3S_MCASP0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x238)
170#define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240)
171#define AM4_L3S_MMC3_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x248)
172#define AM4_L3S_QSPI_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x258)
173#define AM4_L3S_USB_OTG_SS0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x260)
174#define AM4_L3S_USB_OTG_SS1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x268)
175
176/* pruss_ocp clocks */
177#define AM4_PRUSS_OCP_CLKCTRL_OFFSET 0x320
178#define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET)
179#define AM4_PRUSS_OCP_PRUSS_CLKCTRL AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320)
180
181/* l4ls clocks */
182#define AM4_L4LS_CLKCTRL_OFFSET 0x420
183#define AM4_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM4_L4LS_CLKCTRL_OFFSET)
184#define AM4_L4LS_L4_LS_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x420)
185#define AM4_L4LS_D_CAN0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x428)
186#define AM4_L4LS_D_CAN1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x430)
187#define AM4_L4LS_EPWMSS0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x438)
188#define AM4_L4LS_EPWMSS1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x440)
189#define AM4_L4LS_EPWMSS2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x448)
190#define AM4_L4LS_EPWMSS3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x450)
191#define AM4_L4LS_EPWMSS4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x458)
192#define AM4_L4LS_EPWMSS5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x460)
193#define AM4_L4LS_ELM_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x468)
194#define AM4_L4LS_GPIO2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x478)
195#define AM4_L4LS_GPIO3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x480)
196#define AM4_L4LS_GPIO4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x488)
197#define AM4_L4LS_GPIO5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x490)
198#define AM4_L4LS_GPIO6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x498)
199#define AM4_L4LS_HDQ1W_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a0)
200#define AM4_L4LS_I2C2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a8)
201#define AM4_L4LS_I2C3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b0)
202#define AM4_L4LS_MAILBOX_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b8)
203#define AM4_L4LS_MMC1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c0)
204#define AM4_L4LS_MMC2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c8)
205#define AM4_L4LS_RNG_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4e0)
206#define AM4_L4LS_SPI0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x500)
207#define AM4_L4LS_SPI1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x508)
208#define AM4_L4LS_SPI2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x510)
209#define AM4_L4LS_SPI3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x518)
210#define AM4_L4LS_SPI4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x520)
211#define AM4_L4LS_SPINLOCK_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x528)
212#define AM4_L4LS_TIMER2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x530)
213#define AM4_L4LS_TIMER3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x538)
214#define AM4_L4LS_TIMER4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x540)
215#define AM4_L4LS_TIMER5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x548)
216#define AM4_L4LS_TIMER6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x550)
217#define AM4_L4LS_TIMER7_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x558)
218#define AM4_L4LS_TIMER8_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x560)
219#define AM4_L4LS_TIMER9_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x568)
220#define AM4_L4LS_TIMER10_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x570)
221#define AM4_L4LS_TIMER11_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x578)
222#define AM4_L4LS_UART2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x580)
223#define AM4_L4LS_UART3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x588)
224#define AM4_L4LS_UART4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x590)
225#define AM4_L4LS_UART5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x598)
226#define AM4_L4LS_UART6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5a0)
227#define AM4_L4LS_OCP2SCP0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5b8)
228#define AM4_L4LS_OCP2SCP1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5c0)
229
230/* emif clocks */
231#define AM4_EMIF_CLKCTRL_OFFSET 0x720
232#define AM4_EMIF_CLKCTRL_INDEX(offset) ((offset) - AM4_EMIF_CLKCTRL_OFFSET)
233#define AM4_EMIF_EMIF_CLKCTRL AM4_EMIF_CLKCTRL_INDEX(0x720)
234
235/* dss clocks */
236#define AM4_DSS_CLKCTRL_OFFSET 0xa20
237#define AM4_DSS_CLKCTRL_INDEX(offset) ((offset) - AM4_DSS_CLKCTRL_OFFSET)
238#define AM4_DSS_DSS_CORE_CLKCTRL AM4_DSS_CLKCTRL_INDEX(0xa20)
239
240/* cpsw_125mhz clocks */
241#define AM4_CPSW_125MHZ_CLKCTRL_OFFSET 0xb20
242#define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset) ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET)
243#define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20)
244
113#endif 245#endif
diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h
index d7549c57cac3..ec969b5aeb25 100644
--- a/include/dt-bindings/clock/dra7.h
+++ b/include/dt-bindings/clock/dra7.h
@@ -16,19 +16,21 @@
16#define DRA7_CLKCTRL_OFFSET 0x20 16#define DRA7_CLKCTRL_OFFSET 0x20
17#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET) 17#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET)
18 18
19/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
20
19/* mpu clocks */ 21/* mpu clocks */
20#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 22#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
21 23
22/* ipu clocks */ 24/* ipu clocks */
23#define DRA7_IPU_CLKCTRL_OFFSET 0x40 25#define _DRA7_IPU_CLKCTRL_OFFSET 0x40
24#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET) 26#define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET)
25#define DRA7_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50) 27#define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50)
26#define DRA7_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58) 28#define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58)
27#define DRA7_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60) 29#define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60)
28#define DRA7_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68) 30#define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68)
29#define DRA7_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70) 31#define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70)
30#define DRA7_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78) 32#define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78)
31#define DRA7_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80) 33#define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80)
32 34
33/* rtc clocks */ 35/* rtc clocks */
34#define DRA7_RTC_CLKCTRL_OFFSET 0x40 36#define DRA7_RTC_CLKCTRL_OFFSET 0x40
@@ -99,65 +101,65 @@
99#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) 101#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
100 102
101/* l4per clocks */ 103/* l4per clocks */
102#define DRA7_L4PER_CLKCTRL_OFFSET 0x0 104#define _DRA7_L4PER_CLKCTRL_OFFSET 0x0
103#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET) 105#define _DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET)
104#define DRA7_L4_PER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc) 106#define DRA7_L4_PER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc)
105#define DRA7_L4_PER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x14) 107#define DRA7_L4_PER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x14)
106#define DRA7_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28) 108#define DRA7_TIMER10_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x28)
107#define DRA7_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30) 109#define DRA7_TIMER11_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x30)
108#define DRA7_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38) 110#define DRA7_TIMER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x38)
109#define DRA7_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40) 111#define DRA7_TIMER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x40)
110#define DRA7_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48) 112#define DRA7_TIMER4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x48)
111#define DRA7_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50) 113#define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50)
112#define DRA7_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58) 114#define DRA7_ELM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x58)
113#define DRA7_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60) 115#define DRA7_GPIO2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x60)
114#define DRA7_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68) 116#define DRA7_GPIO3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x68)
115#define DRA7_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70) 117#define DRA7_GPIO4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x70)
116#define DRA7_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78) 118#define DRA7_GPIO5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x78)
117#define DRA7_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80) 119#define DRA7_GPIO6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x80)
118#define DRA7_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88) 120#define DRA7_HDQ1W_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x88)
119#define DRA7_EPWMSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x90) 121#define DRA7_EPWMSS1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x90)
120#define DRA7_EPWMSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x98) 122#define DRA7_EPWMSS2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x98)
121#define DRA7_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0) 123#define DRA7_I2C1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa0)
122#define DRA7_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8) 124#define DRA7_I2C2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa8)
123#define DRA7_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0) 125#define DRA7_I2C3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb0)
124#define DRA7_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8) 126#define DRA7_I2C4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb8)
125#define DRA7_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0) 127#define DRA7_L4_PER1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc0)
126#define DRA7_EPWMSS0_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc4) 128#define DRA7_EPWMSS0_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc4)
127#define DRA7_TIMER13_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc8) 129#define DRA7_TIMER13_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc8)
128#define DRA7_TIMER14_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd0) 130#define DRA7_TIMER14_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd0)
129#define DRA7_TIMER15_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd8) 131#define DRA7_TIMER15_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd8)
130#define DRA7_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0) 132#define DRA7_MCSPI1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf0)
131#define DRA7_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8) 133#define DRA7_MCSPI2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf8)
132#define DRA7_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100) 134#define DRA7_MCSPI3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x100)
133#define DRA7_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108) 135#define DRA7_MCSPI4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x108)
134#define DRA7_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110) 136#define DRA7_GPIO7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x110)
135#define DRA7_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118) 137#define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118)
136#define DRA7_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120) 138#define DRA7_MMC3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x120)
137#define DRA7_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128) 139#define DRA7_MMC4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x128)
138#define DRA7_TIMER16_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x130) 140#define DRA7_TIMER16_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x130)
139#define DRA7_QSPI_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x138) 141#define DRA7_QSPI_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x138)
140#define DRA7_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140) 142#define DRA7_UART1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x140)
141#define DRA7_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148) 143#define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148)
142#define DRA7_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150) 144#define DRA7_UART3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x150)
143#define DRA7_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158) 145#define DRA7_UART4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x158)
144#define DRA7_MCASP2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x160) 146#define DRA7_MCASP2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x160)
145#define DRA7_MCASP3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x168) 147#define DRA7_MCASP3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x168)
146#define DRA7_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170) 148#define DRA7_UART5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x170)
147#define DRA7_MCASP5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x178) 149#define DRA7_MCASP5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x178)
148#define DRA7_MCASP8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x190) 150#define DRA7_MCASP8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x190)
149#define DRA7_MCASP4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x198) 151#define DRA7_MCASP4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x198)
150#define DRA7_AES1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a0) 152#define DRA7_AES1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
151#define DRA7_AES2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a8) 153#define DRA7_AES2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
152#define DRA7_DES_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1b0) 154#define DRA7_DES_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
153#define DRA7_RNG_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c0) 155#define DRA7_RNG_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
154#define DRA7_SHAM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c8) 156#define DRA7_SHAM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
155#define DRA7_UART7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1d0) 157#define DRA7_UART7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
156#define DRA7_UART8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e0) 158#define DRA7_UART8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
157#define DRA7_UART9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e8) 159#define DRA7_UART9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
158#define DRA7_DCAN2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1f0) 160#define DRA7_DCAN2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
159#define DRA7_MCASP6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x204) 161#define DRA7_MCASP6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x204)
160#define DRA7_MCASP7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x208) 162#define DRA7_MCASP7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x208)
161 163
162/* wkupaon clocks */ 164/* wkupaon clocks */
163#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 165#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
@@ -170,4 +172,192 @@
170#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) 172#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
171#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) 173#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
172 174
175/* XXX: Compatibility part end. */
176
177/* mpu clocks */
178#define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
179
180/* dsp1 clocks */
181#define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
182
183/* ipu1 clocks */
184#define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
185
186/* ipu clocks */
187#define DRA7_IPU_CLKCTRL_OFFSET 0x50
188#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
189#define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
190#define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
191#define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
192#define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
193#define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
194#define DRA7_IPU_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78)
195#define DRA7_IPU_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80)
196
197/* dsp2 clocks */
198#define DRA7_DSP2_MMU0_DSP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
199
200/* rtc clocks */
201#define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44)
202
203/* coreaon clocks */
204#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
205#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
206
207/* l3main1 clocks */
208#define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
209#define DRA7_L3MAIN1_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
210#define DRA7_L3MAIN1_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
211#define DRA7_L3MAIN1_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
212#define DRA7_L3MAIN1_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
213#define DRA7_L3MAIN1_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
214#define DRA7_L3MAIN1_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
215
216/* ipu2 clocks */
217#define DRA7_IPU2_MMU_IPU2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
218
219/* dma clocks */
220#define DRA7_DMA_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
221
222/* emif clocks */
223#define DRA7_EMIF_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
224
225/* atl clocks */
226#define DRA7_ATL_CLKCTRL_OFFSET 0x0
227#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
228#define DRA7_ATL_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0)
229
230/* l4cfg clocks */
231#define DRA7_L4CFG_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
232#define DRA7_L4CFG_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
233#define DRA7_L4CFG_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
234#define DRA7_L4CFG_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
235#define DRA7_L4CFG_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
236#define DRA7_L4CFG_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
237#define DRA7_L4CFG_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
238#define DRA7_L4CFG_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
239#define DRA7_L4CFG_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
240#define DRA7_L4CFG_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
241#define DRA7_L4CFG_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
242#define DRA7_L4CFG_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
243#define DRA7_L4CFG_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
244#define DRA7_L4CFG_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98)
245#define DRA7_L4CFG_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
246
247/* l3instr clocks */
248#define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
249#define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
250
251/* dss clocks */
252#define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
253#define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
254
255/* l3init clocks */
256#define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
257#define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
258#define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
259#define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
260#define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
261#define DRA7_L3INIT_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
262#define DRA7_L3INIT_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0)
263#define DRA7_L3INIT_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8)
264#define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
265
266/* pcie clocks */
267#define DRA7_PCIE_CLKCTRL_OFFSET 0xb0
268#define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET)
269#define DRA7_PCIE_PCIE1_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb0)
270#define DRA7_PCIE_PCIE2_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb8)
271
272/* gmac clocks */
273#define DRA7_GMAC_CLKCTRL_OFFSET 0xd0
274#define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET)
275#define DRA7_GMAC_GMAC_CLKCTRL DRA7_GMAC_CLKCTRL_INDEX(0xd0)
276
277/* l4per clocks */
278#define DRA7_L4PER_CLKCTRL_OFFSET 0x28
279#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
280#define DRA7_L4PER_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28)
281#define DRA7_L4PER_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30)
282#define DRA7_L4PER_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38)
283#define DRA7_L4PER_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40)
284#define DRA7_L4PER_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48)
285#define DRA7_L4PER_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50)
286#define DRA7_L4PER_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58)
287#define DRA7_L4PER_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60)
288#define DRA7_L4PER_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68)
289#define DRA7_L4PER_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70)
290#define DRA7_L4PER_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78)
291#define DRA7_L4PER_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80)
292#define DRA7_L4PER_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88)
293#define DRA7_L4PER_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
294#define DRA7_L4PER_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
295#define DRA7_L4PER_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
296#define DRA7_L4PER_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
297#define DRA7_L4PER_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0)
298#define DRA7_L4PER_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0)
299#define DRA7_L4PER_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8)
300#define DRA7_L4PER_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100)
301#define DRA7_L4PER_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108)
302#define DRA7_L4PER_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110)
303#define DRA7_L4PER_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118)
304#define DRA7_L4PER_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
305#define DRA7_L4PER_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
306#define DRA7_L4PER_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140)
307#define DRA7_L4PER_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148)
308#define DRA7_L4PER_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150)
309#define DRA7_L4PER_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158)
310#define DRA7_L4PER_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170)
311
312/* l4sec clocks */
313#define DRA7_L4SEC_CLKCTRL_OFFSET 0x1a0
314#define DRA7_L4SEC_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET)
315#define DRA7_L4SEC_AES1_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a0)
316#define DRA7_L4SEC_AES2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a8)
317#define DRA7_L4SEC_DES_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1b0)
318#define DRA7_L4SEC_RNG_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c0)
319#define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8)
320
321/* l4per2 clocks */
322#define DRA7_L4PER2_CLKCTRL_OFFSET 0xc
323#define DRA7_L4PER2_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET)
324#define DRA7_L4PER2_L4_PER2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc)
325#define DRA7_L4PER2_PRUSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x18)
326#define DRA7_L4PER2_PRUSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x20)
327#define DRA7_L4PER2_EPWMSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x90)
328#define DRA7_L4PER2_EPWMSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x98)
329#define DRA7_L4PER2_EPWMSS0_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc4)
330#define DRA7_L4PER2_QSPI_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x138)
331#define DRA7_L4PER2_MCASP2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x160)
332#define DRA7_L4PER2_MCASP3_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x168)
333#define DRA7_L4PER2_MCASP5_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x178)
334#define DRA7_L4PER2_MCASP8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x190)
335#define DRA7_L4PER2_MCASP4_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x198)
336#define DRA7_L4PER2_UART7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1d0)
337#define DRA7_L4PER2_UART8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e0)
338#define DRA7_L4PER2_UART9_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e8)
339#define DRA7_L4PER2_DCAN2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1f0)
340#define DRA7_L4PER2_MCASP6_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x204)
341#define DRA7_L4PER2_MCASP7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x208)
342
343/* l4per3 clocks */
344#define DRA7_L4PER3_CLKCTRL_OFFSET 0x14
345#define DRA7_L4PER3_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET)
346#define DRA7_L4PER3_L4_PER3_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x14)
347#define DRA7_L4PER3_TIMER13_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xc8)
348#define DRA7_L4PER3_TIMER14_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd0)
349#define DRA7_L4PER3_TIMER15_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd8)
350#define DRA7_L4PER3_TIMER16_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x130)
351
352/* wkupaon clocks */
353#define DRA7_WKUPAON_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
354#define DRA7_WKUPAON_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
355#define DRA7_WKUPAON_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
356#define DRA7_WKUPAON_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
357#define DRA7_WKUPAON_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
358#define DRA7_WKUPAON_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
359#define DRA7_WKUPAON_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
360#define DRA7_WKUPAON_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
361#define DRA7_WKUPAON_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
362
173#endif 363#endif
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 08b1aa70a38d..60c51871b04b 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -119,6 +119,11 @@ struct clk_duty {
119 * Called with enable_lock held. This function must not 119 * Called with enable_lock held. This function must not
120 * sleep. 120 * sleep.
121 * 121 *
122 * @save_context: Save the context of the clock in prepration for poweroff.
123 *
124 * @restore_context: Restore the context of the clock after a restoration
125 * of power.
126 *
122 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 127 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
123 * parent rate is an input parameter. It is up to the caller to 128 * parent rate is an input parameter. It is up to the caller to
124 * ensure that the prepare_mutex is held across this call. 129 * ensure that the prepare_mutex is held across this call.
@@ -223,6 +228,8 @@ struct clk_ops {
223 void (*disable)(struct clk_hw *hw); 228 void (*disable)(struct clk_hw *hw);
224 int (*is_enabled)(struct clk_hw *hw); 229 int (*is_enabled)(struct clk_hw *hw);
225 void (*disable_unused)(struct clk_hw *hw); 230 void (*disable_unused)(struct clk_hw *hw);
231 int (*save_context)(struct clk_hw *hw);
232 void (*restore_context)(struct clk_hw *hw);
226 unsigned long (*recalc_rate)(struct clk_hw *hw, 233 unsigned long (*recalc_rate)(struct clk_hw *hw,
227 unsigned long parent_rate); 234 unsigned long parent_rate);
228 long (*round_rate)(struct clk_hw *hw, unsigned long rate, 235 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
@@ -1011,5 +1018,7 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
1011 1018
1012#endif /* platform dependent I/O accessors */ 1019#endif /* platform dependent I/O accessors */
1013 1020
1021void clk_gate_restore_context(struct clk_hw *hw);
1022
1014#endif /* CONFIG_COMMON_CLK */ 1023#endif /* CONFIG_COMMON_CLK */
1015#endif /* CLK_PROVIDER_H */ 1024#endif /* CLK_PROVIDER_H */
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 4f750c481b82..7da754d79f9d 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -629,6 +629,23 @@ struct clk *clk_get_parent(struct clk *clk);
629 */ 629 */
630struct clk *clk_get_sys(const char *dev_id, const char *con_id); 630struct clk *clk_get_sys(const char *dev_id, const char *con_id);
631 631
632/**
633 * clk_save_context - save clock context for poweroff
634 *
635 * Saves the context of the clock register for powerstates in which the
636 * contents of the registers will be lost. Occurs deep within the suspend
637 * code so locking is not necessary.
638 */
639int clk_save_context(void);
640
641/**
642 * clk_restore_context - restore clock context after poweroff
643 *
644 * This occurs with all clocks enabled. Occurs deep within the resume code
645 * so locking is not necessary.
646 */
647void clk_restore_context(void);
648
632#else /* !CONFIG_HAVE_CLK */ 649#else /* !CONFIG_HAVE_CLK */
633 650
634static inline struct clk *clk_get(struct device *dev, const char *id) 651static inline struct clk *clk_get(struct device *dev, const char *id)
@@ -728,6 +745,14 @@ static inline struct clk *clk_get_sys(const char *dev_id, const char *con_id)
728{ 745{
729 return NULL; 746 return NULL;
730} 747}
748
749static inline int clk_save_context(void)
750{
751 return 0;
752}
753
754static inline void clk_restore_context(void) {}
755
731#endif 756#endif
732 757
733/* clk_prepare_enable helps cases using clk_enable in non-atomic context. */ 758/* clk_prepare_enable helps cases using clk_enable in non-atomic context. */
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index a8faa38b1ed6..eacc5df57b99 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -159,6 +159,7 @@ struct clk_hw_omap {
159 const char *clkdm_name; 159 const char *clkdm_name;
160 struct clockdomain *clkdm; 160 struct clockdomain *clkdm;
161 const struct clk_hw_omap_ops *ops; 161 const struct clk_hw_omap_ops *ops;
162 u32 context;
162}; 163};
163 164
164/* 165/*
@@ -290,9 +291,15 @@ struct ti_clk_features {
290#define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1) 291#define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1)
291#define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2) 292#define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2)
292#define TI_CLK_ERRATA_I810 BIT(3) 293#define TI_CLK_ERRATA_I810 BIT(3)
294#define TI_CLK_CLKCTRL_COMPAT BIT(4)
293 295
294void ti_clk_setup_features(struct ti_clk_features *features); 296void ti_clk_setup_features(struct ti_clk_features *features);
295const struct ti_clk_features *ti_clk_get_features(void); 297const struct ti_clk_features *ti_clk_get_features(void);
298int omap3_noncore_dpll_save_context(struct clk_hw *hw);
299void omap3_noncore_dpll_restore_context(struct clk_hw *hw);
300
301int omap3_core_dpll_save_context(struct clk_hw *hw);
302void omap3_core_dpll_restore_context(struct clk_hw *hw);
296 303
297extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; 304extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
298 305
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-04 17:01:46 -0400