diff options
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_cursor.c | 49 |
1 files changed, 19 insertions, 30 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c index fa661744a1f5..afaf346bd50e 100644 --- a/drivers/gpu/drm/radeon/radeon_cursor.c +++ b/drivers/gpu/drm/radeon/radeon_cursor.c | |||
| @@ -91,15 +91,34 @@ static void radeon_show_cursor(struct drm_crtc *crtc) | |||
| 91 | struct radeon_device *rdev = crtc->dev->dev_private; | 91 | struct radeon_device *rdev = crtc->dev->dev_private; |
| 92 | 92 | ||
| 93 | if (ASIC_IS_DCE4(rdev)) { | 93 | if (ASIC_IS_DCE4(rdev)) { |
| 94 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, | ||
| 95 | upper_32_bits(radeon_crtc->cursor_addr)); | ||
| 96 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | ||
| 97 | lower_32_bits(radeon_crtc->cursor_addr)); | ||
| 94 | WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); | 98 | WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); |
| 95 | WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | | 99 | WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | |
| 96 | EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | | 100 | EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | |
| 97 | EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); | 101 | EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); |
| 98 | } else if (ASIC_IS_AVIVO(rdev)) { | 102 | } else if (ASIC_IS_AVIVO(rdev)) { |
| 103 | if (rdev->family >= CHIP_RV770) { | ||
| 104 | if (radeon_crtc->crtc_id) | ||
| 105 | WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, | ||
| 106 | upper_32_bits(radeon_crtc->cursor_addr)); | ||
| 107 | else | ||
| 108 | WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, | ||
| 109 | upper_32_bits(radeon_crtc->cursor_addr)); | ||
| 110 | } | ||
| 111 | |||
| 112 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | ||
| 113 | lower_32_bits(radeon_crtc->cursor_addr)); | ||
| 99 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); | 114 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); |
| 100 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | | 115 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | |
| 101 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); | 116 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
| 102 | } else { | 117 | } else { |
| 118 | /* offset is from DISP(2)_BASE_ADDRESS */ | ||
| 119 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, | ||
| 120 | radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr); | ||
| 121 | |||
| 103 | switch (radeon_crtc->crtc_id) { | 122 | switch (radeon_crtc->crtc_id) { |
| 104 | case 0: | 123 | case 0: |
| 105 | WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); | 124 | WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); |
| @@ -228,34 +247,6 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc, | |||
| 228 | return ret; | 247 | return ret; |
| 229 | } | 248 | } |
| 230 | 249 | ||
| 231 | static void radeon_set_cursor(struct drm_crtc *crtc) | ||
| 232 | { | ||
| 233 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | ||
| 234 | struct radeon_device *rdev = crtc->dev->dev_private; | ||
| 235 | |||
| 236 | if (ASIC_IS_DCE4(rdev)) { | ||
| 237 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, | ||
| 238 | upper_32_bits(radeon_crtc->cursor_addr)); | ||
| 239 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | ||
| 240 | lower_32_bits(radeon_crtc->cursor_addr)); | ||
| 241 | } else if (ASIC_IS_AVIVO(rdev)) { | ||
| 242 | if (rdev->family >= CHIP_RV770) { | ||
| 243 | if (radeon_crtc->crtc_id) | ||
| 244 | WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, | ||
| 245 | upper_32_bits(radeon_crtc->cursor_addr)); | ||
| 246 | else | ||
| 247 | WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, | ||
| 248 | upper_32_bits(radeon_crtc->cursor_addr)); | ||
| 249 | } | ||
| 250 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | ||
| 251 | lower_32_bits(radeon_crtc->cursor_addr)); | ||
| 252 | } else { | ||
| 253 | /* offset is from DISP(2)_BASE_ADDRESS */ | ||
| 254 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, | ||
| 255 | radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr); | ||
| 256 | } | ||
| 257 | } | ||
| 258 | |||
| 259 | int radeon_crtc_cursor_set2(struct drm_crtc *crtc, | 250 | int radeon_crtc_cursor_set2(struct drm_crtc *crtc, |
| 260 | struct drm_file *file_priv, | 251 | struct drm_file *file_priv, |
| 261 | uint32_t handle, | 252 | uint32_t handle, |
| @@ -324,7 +315,6 @@ int radeon_crtc_cursor_set2(struct drm_crtc *crtc, | |||
| 324 | radeon_crtc->cursor_hot_y = hot_y; | 315 | radeon_crtc->cursor_hot_y = hot_y; |
| 325 | } | 316 | } |
| 326 | 317 | ||
| 327 | radeon_set_cursor(crtc); | ||
| 328 | radeon_show_cursor(crtc); | 318 | radeon_show_cursor(crtc); |
| 329 | 319 | ||
| 330 | radeon_lock_cursor(crtc, false); | 320 | radeon_lock_cursor(crtc, false); |
| @@ -362,7 +352,6 @@ void radeon_cursor_reset(struct drm_crtc *crtc) | |||
| 362 | radeon_cursor_move_locked(crtc, radeon_crtc->cursor_x, | 352 | radeon_cursor_move_locked(crtc, radeon_crtc->cursor_x, |
| 363 | radeon_crtc->cursor_y); | 353 | radeon_crtc->cursor_y); |
| 364 | 354 | ||
| 365 | radeon_set_cursor(crtc); | ||
| 366 | radeon_show_cursor(crtc); | 355 | radeon_show_cursor(crtc); |
| 367 | 356 | ||
| 368 | radeon_lock_cursor(crtc, false); | 357 | radeon_lock_cursor(crtc, false); |
