10 files changed, 401 insertions, 39 deletions

diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
index 833af72c852a..9bbb30a9dc20 100644
--- a/arch/mips/bcm63xx/Makefile
+++ b/arch/mips/bcm63xx/Makefile
@@ -1,6 +1,6 @@
 obj-y           += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
                    dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \
-                   dev-spi.o dev-uart.o dev-wdt.o
+                   dev-spi.o dev-uart.o dev-wdt.o dev-usb-usbd.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
 
 obj-y           += boards/
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index feb05258a4d1..ea4ea77c6297 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -24,6 +24,7 @@
 #include <bcm63xx_dev_flash.h>
 #include <bcm63xx_dev_pcmcia.h>
 #include <bcm63xx_dev_spi.h>
+#include <bcm63xx_dev_usb_usbd.h>
 #include <board_bcm963xx.h>
 
 #define PFX     "board_bcm963xx: "
@@ -42,6 +43,12 @@ static struct board_info __initdata board_96328avng = {
 
         .has_uart0                      = 1,
         .has_pci                        = 1,
+        .has_usbd                       = 0,
+
+        .usbd = {
+                .use_fullspeed          = 0,
+                .port_no                = 0,
+        },
 
         .leds = {
                 {
@@ -888,6 +895,9 @@ int __init board_register_devices(void)
             !board_get_mac_address(board.enet1.mac_addr))
                 bcm63xx_enet_register(1, &board.enet1);
 
+        if (board.has_usbd)
+                bcm63xx_usbd_register(&board.usbd);
+
         if (board.has_dsp)
                 bcm63xx_dsp_register(&board.dsp);
 
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 1db48adb543a..dff79ab6005e 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -160,7 +160,9 @@ static struct clk clk_pcm = {
  */
 static void usbh_set(struct clk *clk, int enable)
 {
-        if (BCMCPU_IS_6348())
+        if (BCMCPU_IS_6328())
+                bcm_hwclock_set(CKCTL_6328_USBH_EN, enable);
+        else if (BCMCPU_IS_6348())
                 bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
         else if (BCMCPU_IS_6368())
                 bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
@@ -171,6 +173,21 @@ static struct clk clk_usbh = {
 };
 
 /*
+ * USB device clock
+ */
+static void usbd_set(struct clk *clk, int enable)
+{
+        if (BCMCPU_IS_6328())
+                bcm_hwclock_set(CKCTL_6328_USBD_EN, enable);
+        else if (BCMCPU_IS_6368())
+                bcm_hwclock_set(CKCTL_6368_USBD_EN, enable);
+}
+
+static struct clk clk_usbd = {
+        .set    = usbd_set,
+};
+
+/*
  * SPI clock
  */
 static void spi_set(struct clk *clk, int enable)
@@ -284,6 +301,8 @@ struct clk *clk_get(struct device *dev, const char *id)
                 return &clk_ephy;
         if (!strcmp(id, "usbh"))
                 return &clk_usbh;
+        if (!strcmp(id, "usbd"))
+                return &clk_usbd;
         if (!strcmp(id, "spi"))
                 return &clk_spi;
         if (!strcmp(id, "xtm"))
diff --git a/arch/mips/bcm63xx/dev-usb-usbd.c b/arch/mips/bcm63xx/dev-usb-usbd.c
new file mode 100644
index 000000000000..508bd9d8df27
--- /dev/null
+++ b/arch/mips/bcm63xx/dev-usb-usbd.c
@@ -0,0 +1,65 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+ * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>
+ * Copyright (C) 2012 Broadcom Corporation
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <bcm63xx_cpu.h>
+#include <bcm63xx_dev_usb_usbd.h>
+
+#define NUM_MMIO                2
+#define NUM_IRQ                 7
+
+static struct resource usbd_resources[NUM_MMIO + NUM_IRQ];
+
+static u64 usbd_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device bcm63xx_usbd_device = {
+        .name           = "bcm63xx_udc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(usbd_resources),
+        .resource       = usbd_resources,
+        .dev            = {
+                .dma_mask               = &usbd_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+int __init bcm63xx_usbd_register(const struct bcm63xx_usbd_platform_data *pd)
+{
+        const int irq_list[NUM_IRQ] = { IRQ_USBD,
+                IRQ_USBD_RXDMA0, IRQ_USBD_TXDMA0,
+                IRQ_USBD_RXDMA1, IRQ_USBD_TXDMA1,
+                IRQ_USBD_RXDMA2, IRQ_USBD_TXDMA2 };
+        int i;
+
+        if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368())
+                return 0;
+
+        usbd_resources[0].start = bcm63xx_regset_address(RSET_USBD);
+        usbd_resources[0].end = usbd_resources[0].start + RSET_USBD_SIZE - 1;
+        usbd_resources[0].flags = IORESOURCE_MEM;
+
+        usbd_resources[1].start = bcm63xx_regset_address(RSET_USBDMA);
+        usbd_resources[1].end = usbd_resources[1].start + RSET_USBDMA_SIZE - 1;
+        usbd_resources[1].flags = IORESOURCE_MEM;
+
+        for (i = 0; i < NUM_IRQ; i++) {
+                struct resource *r = &usbd_resources[NUM_MMIO + i];
+
+                r->start = r->end = bcm63xx_get_irq_number(irq_list[i]);
+                r->flags = IORESOURCE_IRQ;
+        }
+
+        platform_device_add_data(&bcm63xx_usbd_device, pd, sizeof(*pd));
+
+        return platform_device_register(&bcm63xx_usbd_device);
+}
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index e104ddb694a8..1ac5704623f2 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -120,6 +120,8 @@ enum bcm63xx_regs_set {
         RSET_OHCI0,
         RSET_OHCI_PRIV,
         RSET_USBH_PRIV,
+        RSET_USBD,
+        RSET_USBDMA,
         RSET_MPI,
         RSET_PCMCIA,
         RSET_PCIE,
@@ -162,6 +164,8 @@ enum bcm63xx_regs_set {
 #define RSET_UDC_SIZE                   256
 #define RSET_OHCI_SIZE                  256
 #define RSET_EHCI_SIZE                  256
+#define RSET_USBD_SIZE                  256
+#define RSET_USBDMA_SIZE                1280
 #define RSET_PCMCIA_SIZE                12
 #define RSET_M2M_SIZE                   256
 #define RSET_ATM_SIZE                   4096
@@ -183,10 +187,11 @@ enum bcm63xx_regs_set {
 #define BCM_6328_GPIO_BASE              (0xb0000080)
 #define BCM_6328_SPI_BASE               (0xdeadbeef)
 #define BCM_6328_UDC0_BASE              (0xdeadbeef)
-#define BCM_6328_USBDMA_BASE            (0xdeadbeef)
-#define BCM_6328_OHCI0_BASE             (0xdeadbeef)
+#define BCM_6328_USBDMA_BASE            (0xb000c000)
+#define BCM_6328_OHCI0_BASE             (0xb0002600)
 #define BCM_6328_OHCI_PRIV_BASE         (0xdeadbeef)
-#define BCM_6328_USBH_PRIV_BASE         (0xdeadbeef)
+#define BCM_6328_USBH_PRIV_BASE         (0xb0002700)
+#define BCM_6328_USBD_BASE              (0xb0002400)
 #define BCM_6328_MPI_BASE               (0xdeadbeef)
 #define BCM_6328_PCMCIA_BASE            (0xdeadbeef)
 #define BCM_6328_PCIE_BASE              (0xb0e40000)
@@ -199,7 +204,7 @@ enum bcm63xx_regs_set {
 #define BCM_6328_ENETDMAC_BASE          (0xb000da00)
 #define BCM_6328_ENETDMAS_BASE          (0xb000dc00)
 #define BCM_6328_ENETSW_BASE            (0xb0e00000)
-#define BCM_6328_EHCI0_BASE             (0x10002500)
+#define BCM_6328_EHCI0_BASE             (0xb0002500)
 #define BCM_6328_SDRAM_BASE             (0xdeadbeef)
 #define BCM_6328_MEMC_BASE              (0xdeadbeef)
 #define BCM_6328_DDR_BASE               (0xb0003000)
@@ -232,6 +237,7 @@ enum bcm63xx_regs_set {
 #define BCM_6338_OHCI0_BASE             (0xdeadbeef)
 #define BCM_6338_OHCI_PRIV_BASE         (0xfffe3000)
 #define BCM_6338_USBH_PRIV_BASE         (0xdeadbeef)
+#define BCM_6338_USBD_BASE              (0xdeadbeef)
 #define BCM_6338_MPI_BASE               (0xfffe3160)
 #define BCM_6338_PCMCIA_BASE            (0xdeadbeef)
 #define BCM_6338_PCIE_BASE              (0xdeadbeef)
@@ -286,6 +292,7 @@ enum bcm63xx_regs_set {
 #define BCM_6345_OHCI0_BASE             (0xfffe2100)
 #define BCM_6345_OHCI_PRIV_BASE         (0xfffe2200)
 #define BCM_6345_USBH_PRIV_BASE         (0xdeadbeef)
+#define BCM_6345_USBD_BASE              (0xdeadbeef)
 #define BCM_6345_SDRAM_REGS_BASE        (0xfffe2300)
 #define BCM_6345_DSL_BASE               (0xdeadbeef)
 #define BCM_6345_UBUS_BASE              (0xdeadbeef)
@@ -319,9 +326,11 @@ enum bcm63xx_regs_set {
 #define BCM_6348_GPIO_BASE              (0xfffe0400)
 #define BCM_6348_SPI_BASE               (0xfffe0c00)
 #define BCM_6348_UDC0_BASE              (0xfffe1000)
+#define BCM_6348_USBDMA_BASE            (0xdeadbeef)
 #define BCM_6348_OHCI0_BASE             (0xfffe1b00)
 #define BCM_6348_OHCI_PRIV_BASE         (0xfffe1c00)
 #define BCM_6348_USBH_PRIV_BASE         (0xdeadbeef)
+#define BCM_6348_USBD_BASE              (0xdeadbeef)
 #define BCM_6348_MPI_BASE               (0xfffe2000)
 #define BCM_6348_PCMCIA_BASE            (0xfffe2054)
 #define BCM_6348_PCIE_BASE              (0xdeadbeef)
@@ -362,9 +371,11 @@ enum bcm63xx_regs_set {
 #define BCM_6358_GPIO_BASE              (0xfffe0080)
 #define BCM_6358_SPI_BASE               (0xfffe0800)
 #define BCM_6358_UDC0_BASE              (0xfffe0800)
+#define BCM_6358_USBDMA_BASE            (0xdeadbeef)
 #define BCM_6358_OHCI0_BASE             (0xfffe1400)
 #define BCM_6358_OHCI_PRIV_BASE         (0xdeadbeef)
 #define BCM_6358_USBH_PRIV_BASE         (0xfffe1500)
+#define BCM_6358_USBD_BASE              (0xdeadbeef)
 #define BCM_6358_MPI_BASE               (0xfffe1000)
 #define BCM_6358_PCMCIA_BASE            (0xfffe1054)
 #define BCM_6358_PCIE_BASE              (0xdeadbeef)
@@ -406,9 +417,11 @@ enum bcm63xx_regs_set {
 #define BCM_6368_GPIO_BASE              (0xb0000080)
 #define BCM_6368_SPI_BASE               (0xb0000800)
 #define BCM_6368_UDC0_BASE              (0xdeadbeef)
+#define BCM_6368_USBDMA_BASE            (0xb0004800)
 #define BCM_6368_OHCI0_BASE             (0xb0001600)
 #define BCM_6368_OHCI_PRIV_BASE         (0xdeadbeef)
 #define BCM_6368_USBH_PRIV_BASE         (0xb0001700)
+#define BCM_6368_USBD_BASE              (0xb0001400)
 #define BCM_6368_MPI_BASE               (0xb0001000)
 #define BCM_6368_PCMCIA_BASE            (0xb0001054)
 #define BCM_6368_PCIE_BASE              (0xdeadbeef)
@@ -458,6 +471,8 @@ extern const unsigned long *bcm63xx_regs_base;
         __GEN_RSET_BASE(__cpu, OHCI0)                                   \
         __GEN_RSET_BASE(__cpu, OHCI_PRIV)                               \
         __GEN_RSET_BASE(__cpu, USBH_PRIV)                               \
+        __GEN_RSET_BASE(__cpu, USBD)                                    \
+        __GEN_RSET_BASE(__cpu, USBDMA)                                  \
         __GEN_RSET_BASE(__cpu, MPI)                                     \
         __GEN_RSET_BASE(__cpu, PCMCIA)                                  \
         __GEN_RSET_BASE(__cpu, PCIE)                                    \
@@ -499,6 +514,8 @@ extern const unsigned long *bcm63xx_regs_base;
         [RSET_OHCI0]            = BCM_## __cpu ##_OHCI0_BASE,           \
         [RSET_OHCI_PRIV]        = BCM_## __cpu ##_OHCI_PRIV_BASE,       \
         [RSET_USBH_PRIV]        = BCM_## __cpu ##_USBH_PRIV_BASE,       \
+        [RSET_USBD]             = BCM_## __cpu ##_USBD_BASE,            \
+        [RSET_USBDMA]           = BCM_## __cpu ##_USBDMA_BASE,          \
         [RSET_MPI]              = BCM_## __cpu ##_MPI_BASE,             \
         [RSET_PCMCIA]           = BCM_## __cpu ##_PCMCIA_BASE,          \
         [RSET_PCIE]             = BCM_## __cpu ##_PCIE_BASE,            \
@@ -569,6 +586,13 @@ enum bcm63xx_irq {
         IRQ_ENET_PHY,
         IRQ_OHCI0,
         IRQ_EHCI0,
+        IRQ_USBD,
+        IRQ_USBD_RXDMA0,
+        IRQ_USBD_TXDMA0,
+        IRQ_USBD_RXDMA1,
+        IRQ_USBD_TXDMA1,
+        IRQ_USBD_RXDMA2,
+        IRQ_USBD_TXDMA2,
         IRQ_ENET0_RXDMA,
         IRQ_ENET0_TXDMA,
         IRQ_ENET1_RXDMA,
@@ -602,8 +626,15 @@ enum bcm63xx_irq {
 #define BCM_6328_ENET0_IRQ              0
 #define BCM_6328_ENET1_IRQ              0
 #define BCM_6328_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 12)
-#define BCM_6328_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 9)
-#define BCM_6328_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 10)
+#define BCM_6328_OHCI0_IRQ              (BCM_6328_HIGH_IRQ_BASE + 9)
+#define BCM_6328_EHCI0_IRQ              (BCM_6328_HIGH_IRQ_BASE + 10)
+#define BCM_6328_USBD_IRQ               (IRQ_INTERNAL_BASE + 4)
+#define BCM_6328_USBD_RXDMA0_IRQ        (IRQ_INTERNAL_BASE + 5)
+#define BCM_6328_USBD_TXDMA0_IRQ        (IRQ_INTERNAL_BASE + 6)
+#define BCM_6328_USBD_RXDMA1_IRQ        (IRQ_INTERNAL_BASE + 7)
+#define BCM_6328_USBD_TXDMA1_IRQ        (IRQ_INTERNAL_BASE + 8)
+#define BCM_6328_USBD_RXDMA2_IRQ        (IRQ_INTERNAL_BASE + 9)
+#define BCM_6328_USBD_TXDMA2_IRQ        (IRQ_INTERNAL_BASE + 10)
 #define BCM_6328_PCMCIA_IRQ             0
 #define BCM_6328_ENET0_RXDMA_IRQ        0
 #define BCM_6328_ENET0_TXDMA_IRQ        0
@@ -642,6 +673,13 @@ enum bcm63xx_irq {
 #define BCM_6338_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 #define BCM_6338_OHCI0_IRQ              0
 #define BCM_6338_EHCI0_IRQ              0
+#define BCM_6338_USBD_IRQ               0
+#define BCM_6338_USBD_RXDMA0_IRQ        0
+#define BCM_6338_USBD_TXDMA0_IRQ        0
+#define BCM_6338_USBD_RXDMA1_IRQ        0
+#define BCM_6338_USBD_TXDMA1_IRQ        0
+#define BCM_6338_USBD_RXDMA2_IRQ        0
+#define BCM_6338_USBD_TXDMA2_IRQ        0
 #define BCM_6338_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
 #define BCM_6338_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
 #define BCM_6338_ENET1_RXDMA_IRQ        0
@@ -673,6 +711,13 @@ enum bcm63xx_irq {
 #define BCM_6345_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 12)
 #define BCM_6345_OHCI0_IRQ              0
 #define BCM_6345_EHCI0_IRQ              0
+#define BCM_6345_USBD_IRQ               0
+#define BCM_6345_USBD_RXDMA0_IRQ        0
+#define BCM_6345_USBD_TXDMA0_IRQ        0
+#define BCM_6345_USBD_RXDMA1_IRQ        0
+#define BCM_6345_USBD_TXDMA1_IRQ        0
+#define BCM_6345_USBD_RXDMA2_IRQ        0
+#define BCM_6345_USBD_TXDMA2_IRQ        0
 #define BCM_6345_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 13 + 1)
 #define BCM_6345_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 13 + 2)
 #define BCM_6345_ENET1_RXDMA_IRQ        0
@@ -704,6 +749,13 @@ enum bcm63xx_irq {
 #define BCM_6348_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 #define BCM_6348_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 12)
 #define BCM_6348_EHCI0_IRQ              0
+#define BCM_6348_USBD_IRQ               0
+#define BCM_6348_USBD_RXDMA0_IRQ        0
+#define BCM_6348_USBD_TXDMA0_IRQ        0
+#define BCM_6348_USBD_RXDMA1_IRQ        0
+#define BCM_6348_USBD_TXDMA1_IRQ        0
+#define BCM_6348_USBD_RXDMA2_IRQ        0
+#define BCM_6348_USBD_TXDMA2_IRQ        0
 #define BCM_6348_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 20)
 #define BCM_6348_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 21)
 #define BCM_6348_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 22)
@@ -735,6 +787,13 @@ enum bcm63xx_irq {
 #define BCM_6358_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 #define BCM_6358_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
 #define BCM_6358_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 10)
+#define BCM_6358_USBD_IRQ               0
+#define BCM_6358_USBD_RXDMA0_IRQ        0
+#define BCM_6358_USBD_TXDMA0_IRQ        0
+#define BCM_6358_USBD_RXDMA1_IRQ        0
+#define BCM_6358_USBD_TXDMA1_IRQ        0
+#define BCM_6358_USBD_RXDMA2_IRQ        0
+#define BCM_6358_USBD_TXDMA2_IRQ        0
 #define BCM_6358_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
 #define BCM_6358_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
 #define BCM_6358_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 17)
@@ -775,6 +834,13 @@ enum bcm63xx_irq {
 #define BCM_6368_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 15)
 #define BCM_6368_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
 #define BCM_6368_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 7)
+#define BCM_6368_USBD_IRQ               (IRQ_INTERNAL_BASE + 8)
+#define BCM_6368_USBD_RXDMA0_IRQ        (IRQ_INTERNAL_BASE + 26)
+#define BCM_6368_USBD_TXDMA0_IRQ        (IRQ_INTERNAL_BASE + 27)
+#define BCM_6368_USBD_RXDMA1_IRQ        (IRQ_INTERNAL_BASE + 28)
+#define BCM_6368_USBD_TXDMA1_IRQ        (IRQ_INTERNAL_BASE + 29)
+#define BCM_6368_USBD_RXDMA2_IRQ        (IRQ_INTERNAL_BASE + 30)
+#define BCM_6368_USBD_TXDMA2_IRQ        (IRQ_INTERNAL_BASE + 31)
 #define BCM_6368_PCMCIA_IRQ             0
 #define BCM_6368_ENET0_RXDMA_IRQ        0
 #define BCM_6368_ENET0_TXDMA_IRQ        0
@@ -815,6 +881,13 @@ extern const int *bcm63xx_irqs;
         [IRQ_ENET_PHY]          = BCM_## __cpu ##_ENET_PHY_IRQ,         \
         [IRQ_OHCI0]             = BCM_## __cpu ##_OHCI0_IRQ,            \
         [IRQ_EHCI0]             = BCM_## __cpu ##_EHCI0_IRQ,            \
+        [IRQ_USBD]              = BCM_## __cpu ##_USBD_IRQ,             \
+        [IRQ_USBD_RXDMA0]       = BCM_## __cpu ##_USBD_RXDMA0_IRQ,      \
+        [IRQ_USBD_TXDMA0]       = BCM_## __cpu ##_USBD_TXDMA0_IRQ,      \
+        [IRQ_USBD_RXDMA1]       = BCM_## __cpu ##_USBD_RXDMA1_IRQ,      \
+        [IRQ_USBD_TXDMA1]       = BCM_## __cpu ##_USBD_TXDMA1_IRQ,      \
+        [IRQ_USBD_RXDMA2]       = BCM_## __cpu ##_USBD_RXDMA2_IRQ,      \
+        [IRQ_USBD_TXDMA2]       = BCM_## __cpu ##_USBD_TXDMA2_IRQ,      \
         [IRQ_ENET0_RXDMA]       = BCM_## __cpu ##_ENET0_RXDMA_IRQ,      \
         [IRQ_ENET0_TXDMA]       = BCM_## __cpu ##_ENET0_TXDMA_IRQ,      \
         [IRQ_ENET1_RXDMA]       = BCM_## __cpu ##_ENET1_RXDMA_IRQ,      \
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h
new file mode 100644
index 000000000000..5d6d6986f40b
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h
@@ -0,0 +1,17 @@
+#ifndef BCM63XX_DEV_USB_USBD_H_
+#define BCM63XX_DEV_USB_USBD_H_
+
+/*
+ * usb device platform data
+ */
+struct bcm63xx_usbd_platform_data {
+        /* board can only support full speed (USB 1.1) */
+        int use_fullspeed;
+
+        /* 0-based port index, for chips with >1 USB PHY */
+        int port_no;
+};
+
+int bcm63xx_usbd_register(const struct bcm63xx_usbd_platform_data *pd);
+
+#endif /* BCM63XX_DEV_USB_USBD_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h
new file mode 100644
index 000000000000..a5bbff31c898
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h
@@ -0,0 +1,38 @@
+#ifndef BCM63XX_IUDMA_H_
+#define BCM63XX_IUDMA_H_
+
+#include <linux/types.h>
+
+/*
+ * rx/tx dma descriptor
+ */
+struct bcm_enet_desc {
+        u32 len_stat;
+        u32 address;
+};
+
+/* control */
+#define DMADESC_LENGTH_SHIFT    16
+#define DMADESC_LENGTH_MASK     (0xfff << DMADESC_LENGTH_SHIFT)
+#define DMADESC_OWNER_MASK      (1 << 15)
+#define DMADESC_EOP_MASK        (1 << 14)
+#define DMADESC_SOP_MASK        (1 << 13)
+#define DMADESC_ESOP_MASK       (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
+#define DMADESC_WRAP_MASK       (1 << 12)
+#define DMADESC_USB_NOZERO_MASK (1 << 1)
+#define DMADESC_USB_ZERO_MASK   (1 << 0)
+
+/* status */
+#define DMADESC_UNDER_MASK      (1 << 9)
+#define DMADESC_APPEND_CRC      (1 << 8)
+#define DMADESC_OVSIZE_MASK     (1 << 4)
+#define DMADESC_RXER_MASK       (1 << 2)
+#define DMADESC_CRC_MASK        (1 << 1)
+#define DMADESC_OV_MASK         (1 << 0)
+#define DMADESC_ERR_MASK        (DMADESC_UNDER_MASK | \
+                                DMADESC_OVSIZE_MASK | \
+                                DMADESC_RXER_MASK | \
+                                DMADESC_CRC_MASK | \
+                                DMADESC_OV_MASK)
+
+#endif /* ! BCM63XX_IUDMA_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 61f2a2a5099d..5e4b91866586 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -543,6 +543,12 @@
 #define GPIO_MODE_6368_SPI_SSN5         (1 << 31)
 
 
+#define GPIO_PINMUX_OTHR_REG            0x24
+#define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
+#define GPIO_PINMUX_OTHR_6328_USB_MASK  (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
+#define GPIO_PINMUX_OTHR_6328_USB_HOST  (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
+#define GPIO_PINMUX_OTHR_6328_USB_DEV   (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
+
 #define GPIO_BASEMODE_6368_REG          0x38
 #define GPIO_BASEMODE_6368_UART2        0x1
 #define GPIO_BASEMODE_6368_GPIO         0x0
@@ -670,6 +676,12 @@
 #define ENETDMA_BUFALLOC_FORCE_SHIFT    31
 #define ENETDMA_BUFALLOC_FORCE_MASK     (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
 
+/* Global interrupt status */
+#define ENETDMA_GLB_IRQSTAT_REG         (0x40)
+
+/* Global interrupt mask */
+#define ENETDMA_GLB_IRQMASK_REG         (0x44)
+
 /* Channel Configuration register */
 #define ENETDMA_CHANCFG_REG(x)          (0x100 + (x) * 0x10)
 #define ENETDMA_CHANCFG_EN_SHIFT        0
@@ -709,9 +721,11 @@
 /* Channel Configuration register */
 #define ENETDMAC_CHANCFG_REG(x)         ((x) * 0x10)
 #define ENETDMAC_CHANCFG_EN_SHIFT       0
-#define ENETDMAC_CHANCFG_EN_MASK        (1 << ENETDMA_CHANCFG_EN_SHIFT)
+#define ENETDMAC_CHANCFG_EN_MASK        (1 << ENETDMAC_CHANCFG_EN_SHIFT)
 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT  1
-#define ENETDMAC_CHANCFG_PKTHALT_MASK   (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
+#define ENETDMAC_CHANCFG_PKTHALT_MASK   (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
+#define ENETDMAC_CHANCFG_BUFHALT_SHIFT  2
+#define ENETDMAC_CHANCFG_BUFHALT_MASK   (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
 
 /* Interrupt Control/Status register */
 #define ENETDMAC_IR_REG(x)              (0x4 + (x) * 0x10)
@@ -770,6 +784,8 @@
 #define USBH_PRIV_SWAP_6358_REG         0x0
 #define USBH_PRIV_SWAP_6368_REG         0x1c
 
+#define USBH_PRIV_SWAP_USBD_SHIFT       6
+#define USBH_PRIV_SWAP_USBD_MASK        (1 << USBH_PRIV_SWAP_USBD_SHIFT)
 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT  4
 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK   (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT  3
@@ -779,6 +795,12 @@
 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT  0
 #define USBH_PRIV_SWAP_OHCI_DATA_MASK   (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
 
+#define USBH_PRIV_UTMI_CTL_6368_REG     0x10
+#define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12
+#define USBH_PRIV_UTMI_CTL_NODRIV_MASK  (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
+#define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT  0
+#define USBH_PRIV_UTMI_CTL_HOSTB_MASK   (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)
+
 #define USBH_PRIV_TEST_6358_REG         0x24
 #define USBH_PRIV_TEST_6368_REG         0x14
 
@@ -787,6 +809,147 @@
 #define USBH_PRIV_SETUP_IOC_MASK        (1 << USBH_PRIV_SETUP_IOC_SHIFT)
 
 
+/*************************************************************************
+ * _REG relative to RSET_USBD
+ *************************************************************************/
+
+/* General control */
+#define USBD_CONTROL_REG                0x00
+#define USBD_CONTROL_TXZLENINS_SHIFT    14
+#define USBD_CONTROL_TXZLENINS_MASK     (1 << USBD_CONTROL_TXZLENINS_SHIFT)
+#define USBD_CONTROL_AUTO_CSRS_SHIFT    13
+#define USBD_CONTROL_AUTO_CSRS_MASK     (1 << USBD_CONTROL_AUTO_CSRS_SHIFT)
+#define USBD_CONTROL_RXZSCFG_SHIFT      12
+#define USBD_CONTROL_RXZSCFG_MASK       (1 << USBD_CONTROL_RXZSCFG_SHIFT)
+#define USBD_CONTROL_INIT_SEL_SHIFT     8
+#define USBD_CONTROL_INIT_SEL_MASK      (0xf << USBD_CONTROL_INIT_SEL_SHIFT)
+#define USBD_CONTROL_FIFO_RESET_SHIFT   6
+#define USBD_CONTROL_FIFO_RESET_MASK    (3 << USBD_CONTROL_FIFO_RESET_SHIFT)
+#define USBD_CONTROL_SETUPERRLOCK_SHIFT 5
+#define USBD_CONTROL_SETUPERRLOCK_MASK  (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)
+#define USBD_CONTROL_DONE_CSRS_SHIFT    0
+#define USBD_CONTROL_DONE_CSRS_MASK     (1 << USBD_CONTROL_DONE_CSRS_SHIFT)
+
+/* Strap options */
+#define USBD_STRAPS_REG                 0x04
+#define USBD_STRAPS_APP_SELF_PWR_SHIFT  10
+#define USBD_STRAPS_APP_SELF_PWR_MASK   (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)
+#define USBD_STRAPS_APP_DISCON_SHIFT    9
+#define USBD_STRAPS_APP_DISCON_MASK     (1 << USBD_STRAPS_APP_DISCON_SHIFT)
+#define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8
+#define USBD_STRAPS_APP_CSRPRGSUP_MASK  (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)
+#define USBD_STRAPS_APP_RMTWKUP_SHIFT   6
+#define USBD_STRAPS_APP_RMTWKUP_MASK    (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)
+#define USBD_STRAPS_APP_RAM_IF_SHIFT    7
+#define USBD_STRAPS_APP_RAM_IF_MASK     (1 << USBD_STRAPS_APP_RAM_IF_SHIFT)
+#define USBD_STRAPS_APP_8BITPHY_SHIFT   2
+#define USBD_STRAPS_APP_8BITPHY_MASK    (1 << USBD_STRAPS_APP_8BITPHY_SHIFT)
+#define USBD_STRAPS_SPEED_SHIFT         0
+#define USBD_STRAPS_SPEED_MASK          (3 << USBD_STRAPS_SPEED_SHIFT)
+
+/* Stall control */
+#define USBD_STALL_REG                  0x08
+#define USBD_STALL_UPDATE_SHIFT         7
+#define USBD_STALL_UPDATE_MASK          (1 << USBD_STALL_UPDATE_SHIFT)
+#define USBD_STALL_ENABLE_SHIFT         6
+#define USBD_STALL_ENABLE_MASK          (1 << USBD_STALL_ENABLE_SHIFT)
+#define USBD_STALL_EPNUM_SHIFT          0
+#define USBD_STALL_EPNUM_MASK           (0xf << USBD_STALL_EPNUM_SHIFT)
+
+/* General status */
+#define USBD_STATUS_REG                 0x0c
+#define USBD_STATUS_SOF_SHIFT           16
+#define USBD_STATUS_SOF_MASK            (0x7ff << USBD_STATUS_SOF_SHIFT)
+#define USBD_STATUS_SPD_SHIFT           12
+#define USBD_STATUS_SPD_MASK            (3 << USBD_STATUS_SPD_SHIFT)
+#define USBD_STATUS_ALTINTF_SHIFT       8
+#define USBD_STATUS_ALTINTF_MASK        (0xf << USBD_STATUS_ALTINTF_SHIFT)
+#define USBD_STATUS_INTF_SHIFT          4
+#define USBD_STATUS_INTF_MASK           (0xf << USBD_STATUS_INTF_SHIFT)
+#define USBD_STATUS_CFG_SHIFT           0
+#define USBD_STATUS_CFG_MASK            (0xf << USBD_STATUS_CFG_SHIFT)
+
+/* Other events */
+#define USBD_EVENTS_REG                 0x10
+#define USBD_EVENTS_USB_LINK_SHIFT      10
+#define USBD_EVENTS_USB_LINK_MASK       (1 << USBD_EVENTS_USB_LINK_SHIFT)
+
+/* IRQ status */
+#define USBD_EVENT_IRQ_STATUS_REG       0x14
+
+/* IRQ level (2 bits per IRQ event) */
+#define USBD_EVENT_IRQ_CFG_HI_REG       0x18
+
+#define USBD_EVENT_IRQ_CFG_LO_REG       0x1c
+
+#define USBD_EVENT_IRQ_CFG_SHIFT(x)     ((x & 0xf) << 1)
+#define USBD_EVENT_IRQ_CFG_MASK(x)      (3 << USBD_EVENT_IRQ_CFG_SHIFT(x))
+#define USBD_EVENT_IRQ_CFG_RISING(x)    (0 << USBD_EVENT_IRQ_CFG_SHIFT(x))
+#define USBD_EVENT_IRQ_CFG_FALLING(x)   (1 << USBD_EVENT_IRQ_CFG_SHIFT(x))
+
+/* IRQ mask (1=unmasked) */
+#define USBD_EVENT_IRQ_MASK_REG         0x20
+
+/* IRQ bits */
+#define USBD_EVENT_IRQ_USB_LINK         10
+#define USBD_EVENT_IRQ_SETCFG           9
+#define USBD_EVENT_IRQ_SETINTF          8
+#define USBD_EVENT_IRQ_ERRATIC_ERR      7
+#define USBD_EVENT_IRQ_SET_CSRS         6
+#define USBD_EVENT_IRQ_SUSPEND          5
+#define USBD_EVENT_IRQ_EARLY_SUSPEND    4
+#define USBD_EVENT_IRQ_SOF              3
+#define USBD_EVENT_IRQ_ENUM_ON          2
+#define USBD_EVENT_IRQ_SETUP            1
+#define USBD_EVENT_IRQ_USB_RESET        0
+
+/* TX FIFO partitioning */
+#define USBD_TXFIFO_CONFIG_REG          0x40
+#define USBD_TXFIFO_CONFIG_END_SHIFT    16
+#define USBD_TXFIFO_CONFIG_END_MASK     (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
+#define USBD_TXFIFO_CONFIG_START_SHIFT  0
+#define USBD_TXFIFO_CONFIG_START_MASK   (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
+
+/* RX FIFO partitioning */
+#define USBD_RXFIFO_CONFIG_REG          0x44
+#define USBD_RXFIFO_CONFIG_END_SHIFT    16
+#define USBD_RXFIFO_CONFIG_END_MASK     (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
+#define USBD_RXFIFO_CONFIG_START_SHIFT  0
+#define USBD_RXFIFO_CONFIG_START_MASK   (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
+
+/* TX FIFO/endpoint configuration */
+#define USBD_TXFIFO_EPSIZE_REG          0x48
+
+/* RX FIFO/endpoint configuration */
+#define USBD_RXFIFO_EPSIZE_REG          0x4c
+
+/* Endpoint<->DMA mappings */
+#define USBD_EPNUM_TYPEMAP_REG          0x50
+#define USBD_EPNUM_TYPEMAP_TYPE_SHIFT   8
+#define USBD_EPNUM_TYPEMAP_TYPE_MASK    (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)
+#define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0
+#define USBD_EPNUM_TYPEMAP_DMA_CH_MASK  (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
+
+/* Misc per-endpoint settings */
+#define USBD_CSR_SETUPADDR_REG          0x80
+#define USBD_CSR_SETUPADDR_DEF          0xb550
+
+#define USBD_CSR_EP_REG(x)              (0x84 + (x) * 4)
+#define USBD_CSR_EP_MAXPKT_SHIFT        19
+#define USBD_CSR_EP_MAXPKT_MASK         (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT)
+#define USBD_CSR_EP_ALTIFACE_SHIFT      15
+#define USBD_CSR_EP_ALTIFACE_MASK       (0xf << USBD_CSR_EP_ALTIFACE_SHIFT)
+#define USBD_CSR_EP_IFACE_SHIFT         11
+#define USBD_CSR_EP_IFACE_MASK          (0xf << USBD_CSR_EP_IFACE_SHIFT)
+#define USBD_CSR_EP_CFG_SHIFT           7
+#define USBD_CSR_EP_CFG_MASK            (0xf << USBD_CSR_EP_CFG_SHIFT)
+#define USBD_CSR_EP_TYPE_SHIFT          5
+#define USBD_CSR_EP_TYPE_MASK           (3 << USBD_CSR_EP_TYPE_SHIFT)
+#define USBD_CSR_EP_DIR_SHIFT           4
+#define USBD_CSR_EP_DIR_MASK            (1 << USBD_CSR_EP_DIR_SHIFT)
+#define USBD_CSR_EP_LOG_SHIFT           0
+#define USBD_CSR_EP_LOG_MASK            (0xf << USBD_CSR_EP_LOG_SHIFT)
+
 
 /*************************************************************************
  * _REG relative to RSET_MPI
diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
index 474daaa53497..b0dd4bb53f7e 100644
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -5,6 +5,7 @@
 #include <linux/gpio.h>
 #include <linux/leds.h>
 #include <bcm63xx_dev_enet.h>
+#include <bcm63xx_dev_usb_usbd.h>
 #include <bcm63xx_dev_dsp.h>
 
 /*
@@ -44,6 +45,7 @@ struct board_info {
         unsigned int    has_pccard:1;
         unsigned int    has_ohci0:1;
         unsigned int    has_ehci0:1;
+        unsigned int    has_usbd:1;
         unsigned int    has_dsp:1;
         unsigned int    has_uart0:1;
         unsigned int    has_uart1:1;
@@ -52,6 +54,9 @@ struct board_info {
         struct bcm63xx_enet_platform_data enet0;
         struct bcm63xx_enet_platform_data enet1;
 
+        /* USB config */
+        struct bcm63xx_usbd_platform_data usbd;
+
         /* DSP config */
         struct bcm63xx_dsp_platform_data dsp;
 
diff --git a/drivers/net/ethernet/broadcom/bcm63xx_enet.h b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
index 0e3048b788c2..133d5857b9e2 100644
--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
@@ -10,6 +10,7 @@
 #include <bcm63xx_regs.h>
 #include <bcm63xx_irq.h>
 #include <bcm63xx_io.h>
+#include <bcm63xx_iudma.h>
 
 /* default number of descriptor */
 #define BCMENET_DEF_RX_DESC     64
@@ -31,35 +32,6 @@
 #define BCMENET_MAX_MTU         2046
 
 /*
- * rx/tx dma descriptor
- */
-struct bcm_enet_desc {
-        u32 len_stat;
-        u32 address;
-};
-
-#define DMADESC_LENGTH_SHIFT    16
-#define DMADESC_LENGTH_MASK     (0xfff << DMADESC_LENGTH_SHIFT)
-#define DMADESC_OWNER_MASK      (1 << 15)
-#define DMADESC_EOP_MASK        (1 << 14)
-#define DMADESC_SOP_MASK        (1 << 13)
-#define DMADESC_ESOP_MASK       (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
-#define DMADESC_WRAP_MASK       (1 << 12)
-
-#define DMADESC_UNDER_MASK      (1 << 9)
-#define DMADESC_APPEND_CRC      (1 << 8)
-#define DMADESC_OVSIZE_MASK     (1 << 4)
-#define DMADESC_RXER_MASK       (1 << 2)
-#define DMADESC_CRC_MASK        (1 << 1)
-#define DMADESC_OV_MASK         (1 << 0)
-#define DMADESC_ERR_MASK        (DMADESC_UNDER_MASK | \
-                                DMADESC_OVSIZE_MASK | \
-                                DMADESC_RXER_MASK | \
-                                DMADESC_CRC_MASK | \
-                                DMADESC_OV_MASK)
-
-
-/*
  * MIB Counters register definitions
 */
 #define ETH_MIB_TX_GD_OCTETS                    0