3 files changed, 43 insertions, 3 deletions

diff --git a/drivers/crypto/marvell/cesa.h b/drivers/crypto/marvell/cesa.h
index a768da7138a1..b7872f62f674 100644
--- a/drivers/crypto/marvell/cesa.h
+++ b/drivers/crypto/marvell/cesa.h
@@ -273,7 +273,8 @@ struct mv_cesa_op_ctx {
 #define CESA_TDMA_SRC_IN_SRAM                   BIT(30)
 #define CESA_TDMA_END_OF_REQ                    BIT(29)
 #define CESA_TDMA_BREAK_CHAIN                   BIT(28)
-#define CESA_TDMA_TYPE_MSK                      GENMASK(27, 0)
+#define CESA_TDMA_SET_STATE                     BIT(27)
+#define CESA_TDMA_TYPE_MSK                      GENMASK(26, 0)
 #define CESA_TDMA_DUMMY                         0
 #define CESA_TDMA_DATA                          1
 #define CESA_TDMA_OP                            2
diff --git a/drivers/crypto/marvell/hash.c b/drivers/crypto/marvell/hash.c
index 2a9260559654..585c90f9f606 100644
--- a/drivers/crypto/marvell/hash.c
+++ b/drivers/crypto/marvell/hash.c
@@ -281,13 +281,32 @@ static void mv_cesa_ahash_std_prepare(struct ahash_request *req)
         sreq->offset = 0;
 }
 
+static void mv_cesa_ahash_dma_step(struct ahash_request *req)
+{
+        struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
+        struct mv_cesa_req *base = &creq->base;
+
+        /* We must explicitly set the digest state. */
+        if (base->chain.first->flags & CESA_TDMA_SET_STATE) {
+                struct mv_cesa_engine *engine = base->engine;
+                int i;
+
+                /* Set the hash state in the IVDIG regs. */
+                for (i = 0; i < ARRAY_SIZE(creq->state); i++)
+                        writel_relaxed(creq->state[i], engine->regs +
+                                       CESA_IVDIG(i));
+        }
+
+        mv_cesa_dma_step(base);
+}
+
 static void mv_cesa_ahash_step(struct crypto_async_request *req)
 {
         struct ahash_request *ahashreq = ahash_request_cast(req);
         struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
 
         if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
-                mv_cesa_dma_step(&creq->base);
+                mv_cesa_ahash_dma_step(ahashreq);
         else
                 mv_cesa_ahash_std_step(ahashreq);
 }
@@ -585,12 +604,16 @@ static int mv_cesa_ahash_dma_req_init(struct ahash_request *req)
         struct mv_cesa_ahash_dma_iter iter;
         struct mv_cesa_op_ctx *op = NULL;
         unsigned int frag_len;
+        bool set_state = false;
         int ret;
         u32 type;
 
         basereq->chain.first = NULL;
         basereq->chain.last = NULL;
 
+        if (!mv_cesa_mac_op_is_first_frag(&creq->op_tmpl))
+                set_state = true;
+
         if (creq->src_nents) {
                 ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents,
                                  DMA_TO_DEVICE);
@@ -684,6 +707,15 @@ static int mv_cesa_ahash_dma_req_init(struct ahash_request *req)
         if (type != CESA_TDMA_RESULT)
                 basereq->chain.last->flags |= CESA_TDMA_BREAK_CHAIN;
 
+        if (set_state) {
+                /*
+                 * Put the CESA_TDMA_SET_STATE flag on the first tdma desc to
+                 * let the step logic know that the IVDIG registers should be
+                 * explicitly set before launching a TDMA chain.
+                 */
+                basereq->chain.first->flags |= CESA_TDMA_SET_STATE;
+        }
+
         return 0;
 
 err_free_tdma:
diff --git a/drivers/crypto/marvell/tdma.c b/drivers/crypto/marvell/tdma.c
index 4416b88eca70..c76375ff376d 100644
--- a/drivers/crypto/marvell/tdma.c
+++ b/drivers/crypto/marvell/tdma.c
@@ -109,7 +109,14 @@ void mv_cesa_tdma_chain(struct mv_cesa_engine *engine,
                 last->next = dreq->chain.first;
                 engine->chain.last = dreq->chain.last;
 
-                if (!(last->flags & CESA_TDMA_BREAK_CHAIN))
+                /*
+                 * Break the DMA chain if the CESA_TDMA_BREAK_CHAIN is set on
+                 * the last element of the current chain, or if the request
+                 * being queued needs the IV regs to be set before lauching
+                 * the request.
+                 */
+                if (!(last->flags & CESA_TDMA_BREAK_CHAIN) &&
+                    !(dreq->chain.first->flags & CESA_TDMA_SET_STATE))
                         last->next_dma = dreq->chain.first->cur_dma;
         }
 }