3 files changed, 22 insertions, 12 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fc586fbd96b5..e4e57a51425e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1573,7 +1573,8 @@ enum skl_disp_power_wells {
 #define RING_NOPID(base)        ((base)+0x94)
 #define RING_IMR(base)          ((base)+0xa8)
 #define RING_HWSTAM(base)       ((base)+0x98)
-#define RING_TIMESTAMP(base)    ((base)+0x358)
+#define RING_TIMESTAMP(base)            ((base)+0x358)
+#define RING_TIMESTAMP_UDW(base)        ((base)+0x358 + 4)
 #define   TAIL_ADDR             0x001FFFF8
 #define   HEAD_WRAP_COUNT       0xFFE00000
 #define   HEAD_WRAP_ONE         0x00200000
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index f0f97b288d0e..03fdfbd3484c 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1261,12 +1261,14 @@ void intel_uncore_fini(struct drm_device *dev)
 #define GEN_RANGE(l, h) GENMASK(h, l)
 
 static const struct register_whitelist {
-        uint64_t offset;
+        uint32_t offset_ldw, offset_udw;
         uint32_t size;
         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
         uint32_t gen_bitmask;
 } whitelist[] = {
-        { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) },
+        { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
+          .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
+          .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
 };
 
 int i915_reg_read_ioctl(struct drm_device *dev,
@@ -1276,11 +1278,11 @@ int i915_reg_read_ioctl(struct drm_device *dev,
         struct drm_i915_reg_read *reg = data;
         struct register_whitelist const *entry = whitelist;
         unsigned size;
-        u64 offset;
+        uint32_t offset_ldw, offset_udw;
         int i, ret = 0;
 
         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
-                if (entry->offset == (reg->offset & -entry->size) &&
+                if (entry->offset_ldw == (reg->offset & -entry->size) &&
                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
                         break;
         }
@@ -1292,27 +1294,28 @@ int i915_reg_read_ioctl(struct drm_device *dev,
          * be naturally aligned (and those that are not so aligned merely
          * limit the available flags for that register).
          */
-        offset = entry->offset;
+        offset_ldw = entry->offset_ldw;
+        offset_udw = entry->offset_udw;
         size = entry->size;
-        size |= reg->offset ^ offset;
+        size |= reg->offset ^ offset_ldw;
 
         intel_runtime_pm_get(dev_priv);
 
         switch (size) {
         case 8 | 1:
-                reg->val = I915_READ64_2x32(offset, offset+4);
+                reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
                 break;
         case 8:
-                reg->val = I915_READ64(offset);
+                reg->val = I915_READ64(offset_ldw);
                 break;
         case 4:
-                reg->val = I915_READ(offset);
+                reg->val = I915_READ(offset_ldw);
                 break;
         case 2:
-                reg->val = I915_READ16(offset);
+                reg->val = I915_READ16(offset_ldw);
                 break;
         case 1:
-                reg->val = I915_READ8(offset);
+                reg->val = I915_READ8(offset_ldw);
                 break;
         default:
                 ret = -EINVAL;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 67cebe6d978f..67ef73a5d6eb 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1079,6 +1079,12 @@ struct drm_i915_gem_context_destroy {
 };
 
 struct drm_i915_reg_read {
+        /*
+         * Register offset.
+         * For 64bit wide registers where the upper 32bits don't immediately
+         * follow the lower 32bits, the offset of the lower 32bits must
+         * be specified
+         */
         __u64 offset;
         __u64 val; /* Return value */
 };