diff options
| -rw-r--r-- | drivers/clocksource/timer-fttmr010.c | 18 | ||||
| -rw-r--r-- | drivers/clocksource/timer-ti-32k.c | 3 |
2 files changed, 14 insertions, 7 deletions
diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index c020038ebfab..cf93f6419b51 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c | |||
| @@ -130,13 +130,17 @@ static int fttmr010_timer_set_next_event(unsigned long cycles, | |||
| 130 | cr &= ~fttmr010->t1_enable_val; | 130 | cr &= ~fttmr010->t1_enable_val; |
| 131 | writel(cr, fttmr010->base + TIMER_CR); | 131 | writel(cr, fttmr010->base + TIMER_CR); |
| 132 | 132 | ||
| 133 | /* Setup the match register forward/backward in time */ | 133 | if (fttmr010->count_down) { |
| 134 | cr = readl(fttmr010->base + TIMER1_COUNT); | 134 | /* |
| 135 | if (fttmr010->count_down) | 135 | * ASPEED Timer Controller will load TIMER1_LOAD register |
| 136 | cr -= cycles; | 136 | * into TIMER1_COUNT register when the timer is re-enabled. |
| 137 | else | 137 | */ |
| 138 | cr += cycles; | 138 | writel(cycles, fttmr010->base + TIMER1_LOAD); |
| 139 | writel(cr, fttmr010->base + TIMER1_MATCH1); | 139 | } else { |
| 140 | /* Setup the match register forward in time */ | ||
| 141 | cr = readl(fttmr010->base + TIMER1_COUNT); | ||
| 142 | writel(cr + cycles, fttmr010->base + TIMER1_MATCH1); | ||
| 143 | } | ||
| 140 | 144 | ||
| 141 | /* Start */ | 145 | /* Start */ |
| 142 | cr = readl(fttmr010->base + TIMER_CR); | 146 | cr = readl(fttmr010->base + TIMER_CR); |
diff --git a/drivers/clocksource/timer-ti-32k.c b/drivers/clocksource/timer-ti-32k.c index 29e2e1a78a43..6949a9113dbb 100644 --- a/drivers/clocksource/timer-ti-32k.c +++ b/drivers/clocksource/timer-ti-32k.c | |||
| @@ -97,6 +97,9 @@ static int __init ti_32k_timer_init(struct device_node *np) | |||
| 97 | return -ENXIO; | 97 | return -ENXIO; |
| 98 | } | 98 | } |
| 99 | 99 | ||
| 100 | if (!of_machine_is_compatible("ti,am43")) | ||
| 101 | ti_32k_timer.cs.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; | ||
| 102 | |||
| 100 | ti_32k_timer.counter = ti_32k_timer.base; | 103 | ti_32k_timer.counter = ti_32k_timer.base; |
| 101 | 104 | ||
| 102 | /* | 105 | /* |
