diff options
| -rw-r--r-- | Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt | 3 | ||||
| -rw-r--r-- | include/dt-bindings/clock/axg-audio-clkc.h | 10 |
2 files changed, 12 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt index 61777ad24f61..0f777749f4f1 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt | |||
| @@ -6,7 +6,8 @@ devices. | |||
| 6 | 6 | ||
| 7 | Required Properties: | 7 | Required Properties: |
| 8 | 8 | ||
| 9 | - compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D | 9 | - compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D, |
| 10 | "amlogic,g12a-audio-clkc" for G12A. | ||
| 10 | - reg : physical base address of the clock controller and length of | 11 | - reg : physical base address of the clock controller and length of |
| 11 | memory mapped region. | 12 | memory mapped region. |
| 12 | - clocks : a list of phandle + clock-specifier pairs for the clocks listed | 13 | - clocks : a list of phandle + clock-specifier pairs for the clocks listed |
diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h index eafb0de8466b..75901c636893 100644 --- a/include/dt-bindings/clock/axg-audio-clkc.h +++ b/include/dt-bindings/clock/axg-audio-clkc.h | |||
| @@ -70,5 +70,15 @@ | |||
| 70 | #define AUD_CLKID_TDMOUT_A_LRCLK 134 | 70 | #define AUD_CLKID_TDMOUT_A_LRCLK 134 |
| 71 | #define AUD_CLKID_TDMOUT_B_LRCLK 135 | 71 | #define AUD_CLKID_TDMOUT_B_LRCLK 135 |
| 72 | #define AUD_CLKID_TDMOUT_C_LRCLK 136 | 72 | #define AUD_CLKID_TDMOUT_C_LRCLK 136 |
| 73 | #define AUD_CLKID_SPDIFOUT_B 151 | ||
| 74 | #define AUD_CLKID_SPDIFOUT_B_CLK 152 | ||
| 75 | #define AUD_CLKID_TDM_MCLK_PAD0 155 | ||
| 76 | #define AUD_CLKID_TDM_MCLK_PAD1 156 | ||
| 77 | #define AUD_CLKID_TDM_LRCLK_PAD0 157 | ||
| 78 | #define AUD_CLKID_TDM_LRCLK_PAD1 158 | ||
| 79 | #define AUD_CLKID_TDM_LRCLK_PAD2 159 | ||
| 80 | #define AUD_CLKID_TDM_SCLK_PAD0 160 | ||
| 81 | #define AUD_CLKID_TDM_SCLK_PAD1 161 | ||
| 82 | #define AUD_CLKID_TDM_SCLK_PAD2 162 | ||
| 73 | 83 | ||
| 74 | #endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ | 84 | #endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ |
