17 files changed, 37 insertions, 65 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 26388562e300..212ff92920d2 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -65,6 +65,7 @@ config MIPS
         select ARCH_CLOCKSOURCE_DATA
         select HANDLE_DOMAIN_IRQ
         select HAVE_EXIT_THREAD
+        select HAVE_REGS_AND_STACK_ACCESS_API
 
 menu "Machine selection"
 
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index f0e314ceb8ba..7f975b20b20c 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -113,42 +113,6 @@ config SPINLOCK_TEST
         help
           Add several files to the debugfs to test spinlock speed.
 
-if CPU_MIPSR6
-
-choice
-        prompt "Compact branch policy"
-        default MIPS_COMPACT_BRANCHES_OPTIMAL
-
-config MIPS_COMPACT_BRANCHES_NEVER
-        bool "Never (force delay slot branches)"
-        help
-          Pass the -mcompact-branches=never flag to the compiler in order to
-          force it to always emit branches with delay slots, and make no use
-          of the compact branch instructions introduced by MIPSr6. This is
-          useful if you suspect there may be an issue with compact branches in
-          either the compiler or the CPU.
-
-config MIPS_COMPACT_BRANCHES_OPTIMAL
-        bool "Optimal (use where beneficial)"
-        help
-          Pass the -mcompact-branches=optimal flag to the compiler in order for
-          it to make use of compact branch instructions where it deems them
-          beneficial, and use branches with delay slots elsewhere. This is the
-          default compiler behaviour, and should be used unless you have a
-          reason to choose otherwise.
-
-config MIPS_COMPACT_BRANCHES_ALWAYS
-        bool "Always (force compact branches)"
-        help
-          Pass the -mcompact-branches=always flag to the compiler in order to
-          force it to always emit compact branches, making no use of branch
-          instructions with delay slots. This can result in more compact code
-          which may be beneficial in some scenarios.
-
-endchoice
-
-endif # CPU_MIPSR6
-
 config SCACHE_DEBUGFS
         bool "L2 cache debugfs entries"
         depends on DEBUG_FS
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index efd7a9dc93c4..598ab2930fce 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -203,10 +203,6 @@ endif
 toolchain-virt                          := $(call cc-option-yn,$(mips-cflags) -mvirt)
 cflags-$(toolchain-virt)                += -DTOOLCHAIN_SUPPORTS_VIRT
 
-cflags-$(CONFIG_MIPS_COMPACT_BRANCHES_NEVER)    += -mcompact-branches=never
-cflags-$(CONFIG_MIPS_COMPACT_BRANCHES_OPTIMAL)  += -mcompact-branches=optimal
-cflags-$(CONFIG_MIPS_COMPACT_BRANCHES_ALWAYS)   += -mcompact-branches=always
-
 #
 # Firmware support
 #
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index 2e7378467c5c..cc3a1e33a600 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -96,7 +96,7 @@ static struct clk * __init ath79_reg_ffclk(const char *name,
         struct clk *clk;
 
         clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
-        if (!clk)
+        if (IS_ERR(clk))
                 panic("failed to allocate %s clock structure", name);
 
         return clk;
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index b31fbc9d6eae..37a932d9148c 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -1059,7 +1059,7 @@ static int __init octeon_publish_devices(void)
 {
         return of_platform_bus_probe(NULL, octeon_ids, NULL);
 }
-device_initcall(octeon_publish_devices);
+arch_initcall(octeon_publish_devices);
 
 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
 MODULE_LICENSE("GPL");
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index 56584a659183..83054f79f72a 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -157,6 +157,7 @@
         ldc1    $f28, THREAD_FPR28(\thread)
         ldc1    $f30, THREAD_FPR30(\thread)
         ctc1    \tmp, fcr31
+        .set    pop
         .endm
 
         .macro  fpu_restore_16odd thread
diff --git a/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h b/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
index 0cf5ac1f7245..8ff2cbdf2c3e 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
@@ -15,8 +15,8 @@
 static inline bool __should_swizzle_bits(volatile void *a)
 {
         extern const bool octeon_should_swizzle_table[];
+        u64 did = ((u64)(uintptr_t)a >> 40) & 0xff;
 
-        unsigned long did = ((unsigned long)a >> 40) & 0xff;
         return octeon_should_swizzle_table[did];
 }
 
@@ -29,7 +29,7 @@ static inline bool __should_swizzle_bits(volatile void *a)
 
 #define __should_swizzle_bits(a)        false
 
-static inline bool __should_swizzle_addr(unsigned long p)
+static inline bool __should_swizzle_addr(u64 p)
 {
         /* boot bus? */
         return ((p >> 40) & 0xff) == 0;
diff --git a/arch/mips/include/asm/mach-paravirt/kernel-entry-init.h b/arch/mips/include/asm/mach-paravirt/kernel-entry-init.h
index 2f82bfa3a773..c9f5769dfc8f 100644
--- a/arch/mips/include/asm/mach-paravirt/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-paravirt/kernel-entry-init.h
@@ -11,11 +11,13 @@
 #define CP0_EBASE $15, 1
 
         .macro  kernel_entry_setup
+#ifdef CONFIG_SMP
         mfc0    t0, CP0_EBASE
         andi    t0, t0, 0x3ff           # CPUNum
         beqz    t0, 1f
         # CPUs other than zero goto smp_bootstrap
         j       smp_bootstrap
+#endif /* CONFIG_SMP */
 
 1:
         .endm
diff --git a/arch/mips/kernel/mips-r2-to-r6-emul.c b/arch/mips/kernel/mips-r2-to-r6-emul.c
index c3372cac6db2..0a7e10b5f9e3 100644
--- a/arch/mips/kernel/mips-r2-to-r6-emul.c
+++ b/arch/mips/kernel/mips-r2-to-r6-emul.c
@@ -1164,7 +1164,9 @@ fpu_emul:
                 regs->regs[31] = r31;
                 regs->cp0_epc = epc;
                 if (!used_math()) {     /* First time FPU user.  */
+                        preempt_disable();
                         err = init_fpu();
+                        preempt_enable();
                         set_used_math();
                 }
                 lose_fpu(1);    /* Save FPU state for the emulator. */
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 7429ad09fbe3..d2d061520a23 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -605,14 +605,14 @@ int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
                 return -EOPNOTSUPP;
 
         /* Avoid inadvertently triggering emulation */
-        if ((value & PR_FP_MODE_FR) && cpu_has_fpu &&
-            !(current_cpu_data.fpu_id & MIPS_FPIR_F64))
+        if ((value & PR_FP_MODE_FR) && raw_cpu_has_fpu &&
+            !(raw_current_cpu_data.fpu_id & MIPS_FPIR_F64))
                 return -EOPNOTSUPP;
-        if ((value & PR_FP_MODE_FRE) && cpu_has_fpu && !cpu_has_fre)
+        if ((value & PR_FP_MODE_FRE) && raw_cpu_has_fpu && !cpu_has_fre)
                 return -EOPNOTSUPP;
 
         /* FR = 0 not supported in MIPS R6 */
-        if (!(value & PR_FP_MODE_FR) && cpu_has_fpu && cpu_has_mips_r6)
+        if (!(value & PR_FP_MODE_FR) && raw_cpu_has_fpu && cpu_has_mips_r6)
                 return -EOPNOTSUPP;
 
         /* Proceed with the mode switch */
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 36cf8d65c47d..3be0e6ba2797 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -87,6 +87,13 @@ void __init add_memory_region(phys_addr_t start, phys_addr_t size, long type)
         int x = boot_mem_map.nr_map;
         int i;
 
+        /*
+         * If the region reaches the top of the physical address space, adjust
+         * the size slightly so that (start + size) doesn't overflow
+         */
+        if (start + size - 1 == (phys_addr_t)ULLONG_MAX)
+                --size;
+
         /* Sanity check */
         if (start + size < start) {
                 pr_warn("Trying to add an invalid memory region, skipped\n");
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index f95f094f36e4..b0baf48951fa 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -322,6 +322,9 @@ asmlinkage void start_secondary(void)
         cpumask_set_cpu(cpu, &cpu_coherent_mask);
         notify_cpu_starting(cpu);
 
+        cpumask_set_cpu(cpu, &cpu_callin_map);
+        synchronise_count_slave(cpu);
+
         set_cpu_online(cpu, true);
 
         set_cpu_sibling_map(cpu);
@@ -329,10 +332,6 @@ asmlinkage void start_secondary(void)
 
         calculate_cpu_foreign_map();
 
-        cpumask_set_cpu(cpu, &cpu_callin_map);
-
-        synchronise_count_slave(cpu);
-
         /*
          * irq will be enabled in ->smp_finish(), enabling it too early
          * is dangerous.
diff --git a/arch/mips/kernel/uprobes.c b/arch/mips/kernel/uprobes.c
index 8452d933a645..1149b30c9aeb 100644
--- a/arch/mips/kernel/uprobes.c
+++ b/arch/mips/kernel/uprobes.c
@@ -222,7 +222,7 @@ int arch_uprobe_exception_notify(struct notifier_block *self,
                 return NOTIFY_DONE;
 
         switch (val) {
-        case DIE_BREAK:
+        case DIE_UPROBE:
                 if (uprobe_pre_sstep_notifier(regs))
                         return NOTIFY_STOP;
                 break;
diff --git a/arch/mips/kernel/vdso.c b/arch/mips/kernel/vdso.c
index 9abe447a4b48..f9dbfb14af33 100644
--- a/arch/mips/kernel/vdso.c
+++ b/arch/mips/kernel/vdso.c
@@ -39,16 +39,16 @@ static struct vm_special_mapping vdso_vvar_mapping = {
 static void __init init_vdso_image(struct mips_vdso_image *image)
 {
         unsigned long num_pages, i;
+        unsigned long data_pfn;
 
         BUG_ON(!PAGE_ALIGNED(image->data));
         BUG_ON(!PAGE_ALIGNED(image->size));
 
         num_pages = image->size / PAGE_SIZE;
 
-        for (i = 0; i < num_pages; i++) {
-                image->mapping.pages[i] =
-                        virt_to_page(image->data + (i * PAGE_SIZE));
-        }
+        data_pfn = __phys_to_pfn(__pa_symbol(image->data));
+        for (i = 0; i < num_pages; i++)
+                image->mapping.pages[i] = pfn_to_page(data_pfn + i);
 }
 
 static int __init init_vdso(void)
diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
index 72a4642eee2c..4a094f7acb3d 100644
--- a/arch/mips/math-emu/dsemul.c
+++ b/arch/mips/math-emu/dsemul.c
@@ -298,5 +298,6 @@ bool do_dsemulret(struct pt_regs *xcp)
         /* Set EPC to return to post-branch instruction */
         xcp->cp0_epc = current->thread.bd_emu_cont_pc;
         pr_debug("dsemulret to 0x%08lx\n", xcp->cp0_epc);
+        MIPS_FPU_EMU_INC_STATS(ds_emul);
         return true;
 }
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index cd72805b64a7..fa7d8d3790bf 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -800,7 +800,7 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end)
                  * If address-based cache ops don't require an SMP call, then
                  * use them exclusively for small flushes.
                  */
-                size = start - end;
+                size = end - start;
                 cache_size = icache_size;
                 if (!cpu_has_ic_fills_f_dc) {
                         size *= 2;
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index a5509e7dcad2..2c3749d98f04 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -261,7 +261,6 @@ unsigned __weak platform_maar_init(unsigned num_pairs)
 {
         struct maar_config cfg[BOOT_MEM_MAP_MAX];
         unsigned i, num_configured, num_cfg = 0;
-        phys_addr_t skip;
 
         for (i = 0; i < boot_mem_map.nr_map; i++) {
                 switch (boot_mem_map.map[i].type) {
@@ -272,14 +271,14 @@ unsigned __weak platform_maar_init(unsigned num_pairs)
                         continue;
                 }
 
-                skip = 0x10000 - (boot_mem_map.map[i].addr & 0xffff);
-
+                /* Round lower up */
                 cfg[num_cfg].lower = boot_mem_map.map[i].addr;
-                cfg[num_cfg].lower += skip;
+                cfg[num_cfg].lower = (cfg[num_cfg].lower + 0xffff) & ~0xffff;
 
-                cfg[num_cfg].upper = cfg[num_cfg].lower;
-                cfg[num_cfg].upper += boot_mem_map.map[i].size - 1;
-                cfg[num_cfg].upper -= skip;
+                /* Round upper down */
+                cfg[num_cfg].upper = boot_mem_map.map[i].addr +
+                                        boot_mem_map.map[i].size;
+                cfg[num_cfg].upper = (cfg[num_cfg].upper & ~0xffff) - 1;
 
                 cfg[num_cfg].attrs = MIPS_MAAR_S;
                 num_cfg++;