5 files changed, 25 insertions, 1 deletions

diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index d7201333e3bc..2db99433e17f 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -138,8 +138,8 @@
 
                 mipi_phy: video-phy@10020710 {
                         compatible = "samsung,s5pv210-mipi-video-phy";
-                        reg = <0x10020710 8>;
                         #phy-cells = <1>;
+                        syscon = <&pmu_system_controller>;
                 };
 
                 pd_cam: cam-power-domain@10023C00 {
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index e0abfc3324d1..e050d85cdacd 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -127,6 +127,10 @@
         };
 };
 
+&cpu0 {
+        cpu0-supply = <&buck1_reg>;
+};
+
 &fimd {
         pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>;
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 98f3ce65cb9a..ba34886f8b65 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -188,6 +188,10 @@
         };
 };
 
+&cpu0 {
+        cpu0-supply = <&varm_breg>;
+};
+
 &dsi_0 {
         vddcore-supply = <&vusb_reg>;
         vddio-supply = <&vmipi_reg>;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d4f2b11319dd..775892b2cc6a 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -548,6 +548,10 @@
         };
 };
 
+&cpu0 {
+        cpu0-supply = <&vdd_arm_reg>;
+};
+
 &pinctrl_1 {
         hdmi_hpd: hdmi-hpd {
                 samsung,pins = "gpx3-7";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 10d3c173396e..3e5ba665d200 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -40,6 +40,18 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <0x900>;
+                        clocks = <&clock CLK_ARM_CLK>;
+                        clock-names = "cpu";
+                        clock-latency = <160000>;
+
+                        operating-points = <
+                                1200000 1250000
+                                1000000 1150000
+                                800000  1075000
+                                500000  975000
+                                400000  975000
+                                200000  950000
+                        >;
                         cooling-min-level = <4>;
                         cooling-max-level = <2>;
                         #cooling-cells = <2>; /* min followed by max */