10 files changed, 123 insertions, 62 deletions

diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 718ab307a500..4d2f53ae9f0f 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -185,12 +185,6 @@ static int gvt_dma_map_page(struct intel_vgpu *vgpu, unsigned long gfn,
         if (ret)
                 return ret;
 
-        if (!pfn_valid(pfn)) {
-                gvt_vgpu_err("pfn 0x%lx is not mem backed\n", pfn);
-                vfio_unpin_pages(mdev_dev(vgpu->vdev.mdev), &gfn, 1);
-                return -EINVAL;
-        }
-
         /* Setup DMA mapping. */
         *dma_addr = dma_map_page(dev, page, 0, size, PCI_DMA_BIDIRECTIONAL);
         ret = dma_mapping_error(dev, *dma_addr);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b3aefd623557..f9ce35da4123 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1218,7 +1218,8 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
-                seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold);
+                seq_printf(m, "Up threshold: %d%%\n",
+                           rps->power.up_threshold);
 
                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
@@ -1226,7 +1227,8 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
-                seq_printf(m, "Down threshold: %d%%\n", rps->down_threshold);
+                seq_printf(m, "Down threshold: %d%%\n",
+                           rps->power.down_threshold);
 
                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
                             rp_state_cap >> 16) & 0xff;
@@ -2218,6 +2220,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
         seq_printf(m, "Boosts outstanding? %d\n",
                    atomic_read(&rps->num_waiters));
+        seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
         seq_printf(m, "Frequency requested %d\n",
                    intel_gpu_freq(dev_priv, rps->cur_freq));
         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
@@ -2261,13 +2264,13 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 
                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
-                           rps_power_to_str(rps->power));
+                           rps_power_to_str(rps->power.mode));
                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
                            rpup && rpupei ? 100 * rpup / rpupei : 0,
-                           rps->up_threshold);
+                           rps->power.up_threshold);
                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
                            rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
-                           rps->down_threshold);
+                           rps->power.down_threshold);
         } else {
                 seq_puts(m, "\nRPS Autotuning inactive\n");
         }
@@ -2606,13 +2609,22 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data)
                 "sink internal error",
         };
         struct drm_connector *connector = m->private;
+        struct drm_i915_private *dev_priv = to_i915(connector->dev);
         struct intel_dp *intel_dp =
                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
+        int ret;
+
+        if (!CAN_PSR(dev_priv)) {
+                seq_puts(m, "PSR Unsupported\n");
+                return -ENODEV;
+        }
 
         if (connector->status != connector_status_connected)
                 return -ENODEV;
 
-        if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) == 1) {
+        ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
+
+        if (ret == 1) {
                 const char *str = "unknown";
 
                 val &= DP_PSR_SINK_STATE_MASK;
@@ -2620,7 +2632,7 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data)
                         str = sink_status[val];
                 seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str);
         } else {
-                DRM_ERROR("dpcd read (at %u) failed\n", DP_PSR_STATUS);
+                return ret;
         }
 
         return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0f49f9988dfa..4aca5344863d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -779,11 +779,17 @@ struct intel_rps {
         u8 rp0_freq;            /* Non-overclocked max frequency. */
         u16 gpll_ref_freq;      /* vlv/chv GPLL reference frequency */
 
-        u8 up_threshold; /* Current %busy required to uplock */
-        u8 down_threshold; /* Current %busy required to downclock */
-
         int last_adj;
-        enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
+
+        struct {
+                struct mutex mutex;
+
+                enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
+                unsigned int interactive;
+
+                u8 up_threshold; /* Current %busy required to uplock */
+                u8 down_threshold; /* Current %busy required to downclock */
+        } power;
 
         bool enabled;
         atomic_t num_waiters;
@@ -3422,6 +3428,8 @@ extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
+extern void intel_rps_mark_interactive(struct drm_i915_private *i915,
+                                       bool interactive);
 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
                                   bool enable);
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5dadefca2ad2..90628a47ae17 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1265,9 +1265,9 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
                 c0 = max(render, media);
                 c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */
 
-                if (c0 > time * rps->up_threshold)
+                if (c0 > time * rps->power.up_threshold)
                         events = GEN6_PM_RP_UP_THRESHOLD;
-                else if (c0 < time * rps->down_threshold)
+                else if (c0 < time * rps->power.down_threshold)
                         events = GEN6_PM_RP_DOWN_THRESHOLD;
         }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8af945d8a995..91e7483228e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2780,9 +2780,6 @@ enum i915_power_well_id {
 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE     (1 << 6)
 #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE    (1 << 1)
 
-#define GEN10_CACHE_MODE_SS                     _MMIO(0xe420)
-#define   FLOAT_BLEND_OPTIMIZATION_ENABLE       (1 << 4)
-
 #define GEN6_BLITTER_ECOSKPD    _MMIO(0x221d0)
 #define   GEN6_BLITTER_LOCK_SHIFT                       16
 #define   GEN6_BLITTER_FBC_NOTIFY                       (1 << 3)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 87e4cfbfd096..ed3fa1c8a983 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13104,6 +13104,19 @@ intel_prepare_plane_fb(struct drm_plane *plane,
                 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
         }
 
+        /*
+         * We declare pageflips to be interactive and so merit a small bias
+         * towards upclocking to deliver the frame on time. By only changing
+         * the RPS thresholds to sample more regularly and aim for higher
+         * clocks we can hopefully deliver low power workloads (like kodi)
+         * that are not quite steady state without resorting to forcing
+         * maximum clocks following a vblank miss (see do_rps_boost()).
+         */
+        if (!intel_state->rps_interactive) {
+                intel_rps_mark_interactive(dev_priv, true);
+                intel_state->rps_interactive = true;
+        }
+
         return 0;
 }
 
@@ -13120,8 +13133,15 @@ void
 intel_cleanup_plane_fb(struct drm_plane *plane,
                        struct drm_plane_state *old_state)
 {
+        struct intel_atomic_state *intel_state =
+                to_intel_atomic_state(old_state->state);
         struct drm_i915_private *dev_priv = to_i915(plane->dev);
 
+        if (intel_state->rps_interactive) {
+                intel_rps_mark_interactive(dev_priv, false);
+                intel_state->rps_interactive = false;
+        }
+
         /* Should only be called after a successful intel_prepare_plane_fb()! */
         mutex_lock(&dev_priv->drm.struct_mutex);
         intel_plane_unpin_fb(to_intel_plane_state(old_state));
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c275f91244a6..17af06d8a43e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -484,6 +484,8 @@ struct intel_atomic_state {
          */
         bool skip_intermediate_wm;
 
+        bool rps_interactive;
+
         /* Gen9+ only */
         struct skl_ddb_values wm_results;
 
diff --git a/drivers/gpu/drm/i915/intel_lpe_audio.c b/drivers/gpu/drm/i915/intel_lpe_audio.c
index 6269750e2b54..430732720e65 100644
--- a/drivers/gpu/drm/i915/intel_lpe_audio.c
+++ b/drivers/gpu/drm/i915/intel_lpe_audio.c
@@ -126,9 +126,7 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
                 return platdev;
         }
 
-        pm_runtime_forbid(&platdev->dev);
-        pm_runtime_set_active(&platdev->dev);
-        pm_runtime_enable(&platdev->dev);
+        pm_runtime_no_callbacks(&platdev->dev);
 
         return platdev;
 }
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7312ecb73415..43ae9de12ba3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6264,42 +6264,15 @@ static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
         return limits;
 }
 
-static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
+static void rps_set_power(struct drm_i915_private *dev_priv, int new_power)
 {
         struct intel_rps *rps = &dev_priv->gt_pm.rps;
-        int new_power;
         u32 threshold_up = 0, threshold_down = 0; /* in % */
         u32 ei_up = 0, ei_down = 0;
 
-        new_power = rps->power;
-        switch (rps->power) {
-        case LOW_POWER:
-                if (val > rps->efficient_freq + 1 &&
-                    val > rps->cur_freq)
-                        new_power = BETWEEN;
-                break;
-
-        case BETWEEN:
-                if (val <= rps->efficient_freq &&
-                    val < rps->cur_freq)
-                        new_power = LOW_POWER;
-                else if (val >= rps->rp0_freq &&
-                         val > rps->cur_freq)
-                        new_power = HIGH_POWER;
-                break;
+        lockdep_assert_held(&rps->power.mutex);
 
-        case HIGH_POWER:
-                if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 &&
-                    val < rps->cur_freq)
-                        new_power = BETWEEN;
-                break;
-        }
-        /* Max/min bins are special */
-        if (val <= rps->min_freq_softlimit)
-                new_power = LOW_POWER;
-        if (val >= rps->max_freq_softlimit)
-                new_power = HIGH_POWER;
-        if (new_power == rps->power)
+        if (new_power == rps->power.mode)
                 return;
 
         /* Note the units here are not exactly 1us, but 1280ns. */
@@ -6362,12 +6335,71 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
                    GEN6_RP_DOWN_IDLE_AVG);
 
 skip_hw_write:
-        rps->power = new_power;
-        rps->up_threshold = threshold_up;
-        rps->down_threshold = threshold_down;
+        rps->power.mode = new_power;
+        rps->power.up_threshold = threshold_up;
+        rps->power.down_threshold = threshold_down;
+}
+
+static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
+{
+        struct intel_rps *rps = &dev_priv->gt_pm.rps;
+        int new_power;
+
+        new_power = rps->power.mode;
+        switch (rps->power.mode) {
+        case LOW_POWER:
+                if (val > rps->efficient_freq + 1 &&
+                    val > rps->cur_freq)
+                        new_power = BETWEEN;
+                break;
+
+        case BETWEEN:
+                if (val <= rps->efficient_freq &&
+                    val < rps->cur_freq)
+                        new_power = LOW_POWER;
+                else if (val >= rps->rp0_freq &&
+                         val > rps->cur_freq)
+                        new_power = HIGH_POWER;
+                break;
+
+        case HIGH_POWER:
+                if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 &&
+                    val < rps->cur_freq)
+                        new_power = BETWEEN;
+                break;
+        }
+        /* Max/min bins are special */
+        if (val <= rps->min_freq_softlimit)
+                new_power = LOW_POWER;
+        if (val >= rps->max_freq_softlimit)
+                new_power = HIGH_POWER;
+
+        mutex_lock(&rps->power.mutex);
+        if (rps->power.interactive)
+                new_power = HIGH_POWER;
+        rps_set_power(dev_priv, new_power);
+        mutex_unlock(&rps->power.mutex);
         rps->last_adj = 0;
 }
 
+void intel_rps_mark_interactive(struct drm_i915_private *i915, bool interactive)
+{
+        struct intel_rps *rps = &i915->gt_pm.rps;
+
+        if (INTEL_GEN(i915) < 6)
+                return;
+
+        mutex_lock(&rps->power.mutex);
+        if (interactive) {
+                if (!rps->power.interactive++ && READ_ONCE(i915->gt.awake))
+                        rps_set_power(i915, HIGH_POWER);
+        } else {
+                GEM_BUG_ON(!rps->power.interactive);
+                rps->power.interactive--;
+        }
+        mutex_unlock(&rps->power.mutex);
+}
+
 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
 {
         struct intel_rps *rps = &dev_priv->gt_pm.rps;
@@ -6780,7 +6812,7 @@ static void reset_rps(struct drm_i915_private *dev_priv,
         u8 freq = rps->cur_freq;
 
         /* force a reset */
-        rps->power = -1;
+        rps->power.mode = -1;
         rps->cur_freq = -1;
 
         if (set(dev_priv, freq))
@@ -9604,6 +9636,7 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
 void intel_pm_setup(struct drm_i915_private *dev_priv)
 {
         mutex_init(&dev_priv->pcu_lock);
+        mutex_init(&dev_priv->gt_pm.rps.power.mutex);
 
         atomic_set(&dev_priv->gt_pm.rps.num_waiters, 0);
 
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index f8bb32e974f6..4bcdeaf8d98f 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -508,9 +508,6 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
                 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
                                   GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
 
-        /* WaEnableFloatBlendOptimization:icl */
-        WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);
-
         return 0;
 }