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-rw-r--r--drivers/clk/rockchip/clk-rk3368.c97
1 files changed, 60 insertions, 37 deletions
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 31facd8426f7..3cc03689fec6 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -243,6 +243,34 @@ static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
243 RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1), 243 RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1),
244}; 244};
245 245
246static struct rockchip_clk_branch rk3368_i2s_8ch_fracmux __initdata =
247 MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
248 RK3368_CLKSEL_CON(27), 8, 2, MFLAGS);
249
250static struct rockchip_clk_branch rk3368_spdif_8ch_fracmux __initdata =
251 MUX(0, "spdif_8ch_pre", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
252 RK3368_CLKSEL_CON(31), 8, 2, MFLAGS);
253
254static struct rockchip_clk_branch rk3368_i2s_2ch_fracmux __initdata =
255 MUX(0, "i2s_2ch_pre", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
256 RK3368_CLKSEL_CON(53), 8, 2, MFLAGS);
257
258static struct rockchip_clk_branch rk3368_uart0_fracmux __initdata =
259 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
260 RK3368_CLKSEL_CON(33), 8, 2, MFLAGS);
261
262static struct rockchip_clk_branch rk3368_uart1_fracmux __initdata =
263 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
264 RK3368_CLKSEL_CON(35), 8, 2, MFLAGS);
265
266static struct rockchip_clk_branch rk3368_uart3_fracmux __initdata =
267 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
268 RK3368_CLKSEL_CON(39), 8, 2, MFLAGS);
269
270static struct rockchip_clk_branch rk3368_uart4_fracmux __initdata =
271 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
272 RK3368_CLKSEL_CON(41), 8, 2, MFLAGS);
273
246static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { 274static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
247 /* 275 /*
248 * Clock-Architecture Diagram 2 276 * Clock-Architecture Diagram 2
@@ -339,11 +367,10 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
339 COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0, 367 COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
340 RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS, 368 RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
341 RK3368_CLKGATE_CON(6), 1, GFLAGS), 369 RK3368_CLKGATE_CON(6), 1, GFLAGS),
342 COMPOSITE_FRAC(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT, 370 COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
343 RK3368_CLKSEL_CON(28), 0, 371 RK3368_CLKSEL_CON(28), 0,
344 RK3368_CLKGATE_CON(6), 2, GFLAGS), 372 RK3368_CLKGATE_CON(6), 2, GFLAGS,
345 MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT, 373 &rk3368_i2s_8ch_fracmux),
346 RK3368_CLKSEL_CON(27), 8, 2, MFLAGS),
347 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0, 374 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
348 RK3368_CLKSEL_CON(27), 15, 1, MFLAGS, 375 RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
349 RK3368_CLKGATE_CON(6), 0, GFLAGS), 376 RK3368_CLKGATE_CON(6), 0, GFLAGS),
@@ -352,21 +379,21 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
352 COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0, 379 COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
353 RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS, 380 RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS,
354 RK3368_CLKGATE_CON(6), 4, GFLAGS), 381 RK3368_CLKGATE_CON(6), 4, GFLAGS),
355 COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT, 382 COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
356 RK3368_CLKSEL_CON(32), 0, 383 RK3368_CLKSEL_CON(32), 0,
357 RK3368_CLKGATE_CON(6), 5, GFLAGS), 384 RK3368_CLKGATE_CON(6), 5, GFLAGS,
358 COMPOSITE_NODIV(SCLK_SPDIF_8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, CLK_SET_RATE_PARENT, 385 &rk3368_spdif_8ch_fracmux),
359 RK3368_CLKSEL_CON(31), 8, 2, MFLAGS, 386 GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
360 RK3368_CLKGATE_CON(6), 6, GFLAGS), 387 RK3368_CLKGATE_CON(6), 6, GFLAGS),
361 COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0, 388 COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
362 RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS, 389 RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS,
363 RK3368_CLKGATE_CON(5), 13, GFLAGS), 390 RK3368_CLKGATE_CON(5), 13, GFLAGS),
364 COMPOSITE_FRAC(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT, 391 COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
365 RK3368_CLKSEL_CON(54), 0, 392 RK3368_CLKSEL_CON(54), 0,
366 RK3368_CLKGATE_CON(5), 14, GFLAGS), 393 RK3368_CLKGATE_CON(5), 14, GFLAGS,
367 COMPOSITE_NODIV(SCLK_I2S_2CH, "sclk_i2s_2ch", mux_i2s_2ch_p, CLK_SET_RATE_PARENT, 394 &rk3368_i2s_2ch_fracmux),
368 RK3368_CLKSEL_CON(53), 8, 2, MFLAGS, 395 GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_pre", CLK_SET_RATE_PARENT,
369 RK3368_CLKGATE_CON(5), 15, GFLAGS), 396 RK3368_CLKGATE_CON(5), 15, GFLAGS),
370 397
371 COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0, 398 COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
372 RK3368_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS, 399 RK3368_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
@@ -562,38 +589,34 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
562 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb_usb_p, 0, 589 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb_usb_p, 0,
563 RK3368_CLKSEL_CON(33), 12, 2, MFLAGS, 0, 7, DFLAGS, 590 RK3368_CLKSEL_CON(33), 12, 2, MFLAGS, 0, 7, DFLAGS,
564 RK3368_CLKGATE_CON(2), 0, GFLAGS), 591 RK3368_CLKGATE_CON(2), 0, GFLAGS),
565 COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, 592 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
566 RK3368_CLKSEL_CON(34), 0, 593 RK3368_CLKSEL_CON(34), 0,
567 RK3368_CLKGATE_CON(2), 1, GFLAGS), 594 RK3368_CLKGATE_CON(2), 1, GFLAGS,
568 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, 595 &rk3368_uart0_fracmux),
569 RK3368_CLKSEL_CON(33), 8, 2, MFLAGS),
570 596
571 COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0, 597 COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
572 RK3368_CLKSEL_CON(35), 0, 7, DFLAGS, 598 RK3368_CLKSEL_CON(35), 0, 7, DFLAGS,
573 RK3368_CLKGATE_CON(2), 2, GFLAGS), 599 RK3368_CLKGATE_CON(2), 2, GFLAGS),
574 COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, 600 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
575 RK3368_CLKSEL_CON(36), 0, 601 RK3368_CLKSEL_CON(36), 0,
576 RK3368_CLKGATE_CON(2), 3, GFLAGS), 602 RK3368_CLKGATE_CON(2), 3, GFLAGS,
577 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, 603 &rk3368_uart1_fracmux),
578 RK3368_CLKSEL_CON(35), 8, 2, MFLAGS),
579 604
580 COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0, 605 COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
581 RK3368_CLKSEL_CON(39), 0, 7, DFLAGS, 606 RK3368_CLKSEL_CON(39), 0, 7, DFLAGS,
582 RK3368_CLKGATE_CON(2), 6, GFLAGS), 607 RK3368_CLKGATE_CON(2), 6, GFLAGS),
583 COMPOSITE_FRAC(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT, 608 COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
584 RK3368_CLKSEL_CON(40), 0, 609 RK3368_CLKSEL_CON(40), 0,
585 RK3368_CLKGATE_CON(2), 7, GFLAGS), 610 RK3368_CLKGATE_CON(2), 7, GFLAGS,
586 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, 611 &rk3368_uart3_fracmux),
587 RK3368_CLKSEL_CON(39), 8, 2, MFLAGS),
588 612
589 COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0, 613 COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
590 RK3368_CLKSEL_CON(41), 0, 7, DFLAGS, 614 RK3368_CLKSEL_CON(41), 0, 7, DFLAGS,
591 RK3368_CLKGATE_CON(2), 8, GFLAGS), 615 RK3368_CLKGATE_CON(2), 8, GFLAGS),
592 COMPOSITE_FRAC(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT, 616 COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
593 RK3368_CLKSEL_CON(42), 0, 617 RK3368_CLKSEL_CON(42), 0,
594 RK3368_CLKGATE_CON(2), 9, GFLAGS), 618 RK3368_CLKGATE_CON(2), 9, GFLAGS,
595 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT, 619 &rk3368_uart4_fracmux),
596 RK3368_CLKSEL_CON(41), 8, 2, MFLAGS),
597 620
598 COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0, 621 COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
599 RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS, 622 RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-31 19:09:59 -0400