201 files changed, 3312 insertions, 998 deletions

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d191305d560b..c945d4670ea3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -401,6 +401,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
         imx6dl-icore-rqs.dtb \
         imx6dl-nit6xlite.dtb \
         imx6dl-nitrogen6x.dtb \
+        imx6dl-phytec-mira-rdk-nand.dtb \
         imx6dl-phytec-pbab01.dtb \
         imx6dl-rex-basic.dtb \
         imx6dl-riotboard.dtb \
@@ -440,6 +441,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
         imx6q-dfi-fs700-m60.dtb \
         imx6q-display5-tianma-tm070-1280x768.dtb \
         imx6q-dmo-edmqmx6.dtb \
+        imx6q-dms-ba16.dtb \
         imx6q-evi.dtb \
         imx6q-gk802.dtb \
         imx6q-gw51xx.dtb \
@@ -470,6 +472,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
         imx6q-nitrogen6_max.dtb \
         imx6q-nitrogen6_som2.dtb \
         imx6q-novena.dtb \
+        imx6q-phytec-mira-rdk-emmc.dtb \
+        imx6q-phytec-mira-rdk-nand.dtb \
         imx6q-phytec-pbab01.dtb \
         imx6q-pistachio.dtb \
         imx6q-rex-pro.dtb \
@@ -499,6 +503,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
         imx6q-zii-rdu2.dtb \
         imx6qp-nitrogen6_max.dtb \
         imx6qp-nitrogen6_som2.dtb \
+        imx6qp-phytec-mira-rdk-nand.dtb \
         imx6qp-sabreauto.dtb \
         imx6qp-sabresd.dtb \
         imx6qp-tx6qp-8037.dtb \
@@ -531,7 +536,9 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
         imx6ul-tx6ul-0010.dtb \
         imx6ul-tx6ul-0011.dtb \
         imx6ul-tx6ul-mainboard.dtb \
-        imx6ull-14x14-evk.dtb
+        imx6ull-14x14-evk.dtb \
+        imx6ull-colibri-eval-v3.dtb \
+        imx6ull-colibri-wifi-eval-v3.dtb
 dtb-$(CONFIG_SOC_IMX7D) += \
         imx7d-cl-som-imx7.dtb \
         imx7d-colibri-emmc-eval-v3.dtb \
diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/imx1-ads.dts
index 5ea28ee07cf4..6354e4c87313 100644
--- a/arch/arm/boot/dts/imx1-ads.dts
+++ b/arch/arm/boot/dts/imx1-ads.dts
@@ -20,7 +20,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@8000000 {
                 reg = <0x08000000 0x04000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx1-apf9328.dts b/arch/arm/boot/dts/imx1-apf9328.dts
index e8b4b52c2418..11515c0cb195 100644
--- a/arch/arm/boot/dts/imx1-apf9328.dts
+++ b/arch/arm/boot/dts/imx1-apf9328.dts
@@ -20,7 +20,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@8000000 {
                 reg = <0x08000000 0x00800000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi
index 20f6565c337d..f7b9edf93f5e 100644
--- a/arch/arm/boot/dts/imx1.dtsi
+++ b/arch/arm/boot/dts/imx1.dtsi
@@ -25,7 +25,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index 57e29977ba06..9d92ece82560 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -16,7 +16,7 @@
         model = "Freescale i.MX23 Evaluation Kit";
         compatible = "fsl,imx23-evk", "fsl,imx23";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index a8b1c53ebe46..e9351774c619 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -19,7 +19,7 @@
         model = "i.MX23 Olinuxino Low Cost Board";
         compatible = "olimex,imx23-olinuxino", "fsl,imx23";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x04000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx23-sansa.dts b/arch/arm/boot/dts/imx23-sansa.dts
index 221fd55e967e..67de7863ad79 100644
--- a/arch/arm/boot/dts/imx23-sansa.dts
+++ b/arch/arm/boot/dts/imx23-sansa.dts
@@ -49,7 +49,7 @@
         model = "SanDisk Sansa Fuze+";
         compatible = "sandisk,sansa_fuze_plus", "fsl,imx23";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x04000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
index 455169e99d49..95c7b918f6d6 100644
--- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -16,7 +16,7 @@
         model = "Freescale STMP378x Development Board";
         compatible = "fsl,stmp378x-devb", "fsl,imx23";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x04000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx23-xfi3.dts b/arch/arm/boot/dts/imx23-xfi3.dts
index 025cf949662d..9616e500b996 100644
--- a/arch/arm/boot/dts/imx23-xfi3.dts
+++ b/arch/arm/boot/dts/imx23-xfi3.dts
@@ -48,7 +48,7 @@
         model = "Creative ZEN X-Fi3";
         compatible = "creative,x-fi3", "fsl,imx23";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x04000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 10d57f9cbb42..cb0a3fe32718 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -23,7 +23,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 gpio0 = &gpio0;
@@ -222,7 +222,8 @@
                                         fsl,pull-up = <MXS_PULL_DISABLE>;
                                 };
 
-                                gpmi_pins_fixup: gpmi-pins-fixup {
+                                gpmi_pins_fixup: gpmi-pins-fixup@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX23_PAD_GPMI_WPN__GPMI_WPN
                                                 MX23_PAD_GPMI_WRN__GPMI_WRN
@@ -266,7 +267,8 @@
                                         fsl,pull-up = <MXS_PULL_ENABLE>;
                                 };
 
-                                mmc0_pins_fixup: mmc0-pins-fixup {
+                                mmc0_pins_fixup: mmc0-pins-fixup@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX23_PAD_SSP1_DETECT__SSP1_DETECT
                                                 MX23_PAD_SSP1_SCK__SSP1_SCK
diff --git a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
index d6f27641c0ef..e316fe08837a 100644
--- a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
+++ b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
@@ -17,7 +17,7 @@
         model = "Eukrea CPUIMX25";
         compatible = "eukrea,cpuimx25", "fsl,imx25";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x4000000>; /* 64M */
         };
 };
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
index 0f053721d80f..6273a1f243ed 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -88,12 +88,12 @@
 
                 pinctrl_esdhc1: esdhc1grp {
                         fsl,pins = <
-                                MX25_PAD_SD1_CMD__SD1_CMD               0x400000c0
-                                MX25_PAD_SD1_CLK__SD1_CLK               0x400000c0
-                                MX25_PAD_SD1_DATA0__SD1_DATA0           0x400000c0
-                                MX25_PAD_SD1_DATA1__SD1_DATA1           0x400000c0
-                                MX25_PAD_SD1_DATA2__SD1_DATA2           0x400000c0
-                                MX25_PAD_SD1_DATA3__SD1_DATA3           0x400000c0
+                                MX25_PAD_SD1_CMD__ESDHC1_CMD            0x400000c0
+                                MX25_PAD_SD1_CLK__ESDHC1_CLK            0x400000c0
+                                MX25_PAD_SD1_DATA0__ESDHC1_DAT0         0x400000c0
+                                MX25_PAD_SD1_DATA1__ESDHC1_DAT1         0x400000c0
+                                MX25_PAD_SD1_DATA2__ESDHC1_DAT2         0x400000c0
+                                MX25_PAD_SD1_DATA3__ESDHC1_DAT3         0x400000c0
                         >;
                 };
 
diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts
index 30a62d4be8d9..5cb6967866c0 100644
--- a/arch/arm/boot/dts/imx25-karo-tx25.dts
+++ b/arch/arm/boot/dts/imx25-karo-tx25.dts
@@ -36,7 +36,7 @@
                 };
         };
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index 2d15ce72d006..7f9bd052b84e 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -18,7 +18,7 @@
         model = "Freescale i.MX25 Product Development Kit";
         compatible = "fsl,imx25-pdk", "fsl,imx25";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x4000000>;
         };
 
@@ -165,12 +165,12 @@
 
                 pinctrl_esdhc1: esdhc1grp {
                         fsl,pins = <
-                                MX25_PAD_SD1_CMD__SD1_CMD               0x80000000
-                                MX25_PAD_SD1_CLK__SD1_CLK               0x80000000
-                                MX25_PAD_SD1_DATA0__SD1_DATA0           0x80000000
-                                MX25_PAD_SD1_DATA1__SD1_DATA1           0x80000000
-                                MX25_PAD_SD1_DATA2__SD1_DATA2           0x80000000
-                                MX25_PAD_SD1_DATA3__SD1_DATA3           0x80000000
+                                MX25_PAD_SD1_CMD__ESDHC1_CMD            0x80000000
+                                MX25_PAD_SD1_CLK__ESDHC1_CLK            0x80000000
+                                MX25_PAD_SD1_DATA0__ESDHC1_DAT0         0x80000000
+                                MX25_PAD_SD1_DATA1__ESDHC1_DAT1         0x80000000
+                                MX25_PAD_SD1_DATA2__ESDHC1_DAT2         0x80000000
+                                MX25_PAD_SD1_DATA3__ESDHC1_DAT3         0x80000000
                                 MX25_PAD_A14__GPIO_2_0                  0x80000000
                                 MX25_PAD_A15__GPIO_2_1                  0x80000000
                         >;
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
index 6c63dca1b9b8..a4807062a90f 100644
--- a/arch/arm/boot/dts/imx25-pinfunc.h
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -151,21 +151,21 @@
 #define MX25_PAD_D15__D15                       0x088 0x280 0x000 0x00 0x000
 #define MX25_PAD_D15__LD16                      0x088 0x280 0x000 0x01 0x000
 #define MX25_PAD_D15__GPIO_4_5                  0x088 0x280 0x000 0x05 0x000
-#define MX25_PAD_D15__SDHC1_DAT7                0x088 0x280 0x4d8 0x06 0x000
+#define MX25_PAD_D15__ESDHC1_DAT7               0x088 0x280 0x4d8 0x06 0x000
 
 #define MX25_PAD_D14__D14                       0x08c 0x284 0x000 0x00 0x000
 #define MX25_PAD_D14__LD17                      0x08c 0x284 0x000 0x01 0x000
 #define MX25_PAD_D14__GPIO_4_6                  0x08c 0x284 0x000 0x05 0x000
-#define MX25_PAD_D14__SDHC1_DAT6                0x08c 0x284 0x4d4 0x06 0x000
+#define MX25_PAD_D14__ESDHC1_DAT6               0x08c 0x284 0x4d4 0x06 0x000
 
 #define MX25_PAD_D13__D13                       0x090 0x288 0x000 0x00 0x000
 #define MX25_PAD_D13__LD18                      0x090 0x288 0x000 0x01 0x000
 #define MX25_PAD_D13__GPIO_4_7                  0x090 0x288 0x000 0x05 0x000
-#define MX25_PAD_D13__SDHC1_DAT5                0x090 0x288 0x4d0 0x06 0x000
+#define MX25_PAD_D13__ESDHC1_DAT5               0x090 0x288 0x4d0 0x06 0x000
 
 #define MX25_PAD_D12__D12                       0x094 0x28c 0x000 0x00 0x000
 #define MX25_PAD_D12__GPIO_4_8                  0x094 0x28c 0x000 0x05 0x000
-#define MX25_PAD_D12__SDHC1_DAT4                0x094 0x28c 0x4cc 0x06 0x000
+#define MX25_PAD_D12__ESDHC1_DAT4               0x094 0x28c 0x4cc 0x06 0x000
 
 #define MX25_PAD_D11__D11                       0x098 0x290 0x000 0x00 0x000
 #define MX25_PAD_D11__GPIO_4_9                  0x098 0x290 0x000 0x05 0x000
@@ -236,12 +236,13 @@
 #define MX25_PAD_LD8__LD8                       0x0e8 0x2e0 0x000 0x00 0x000
 #define MX25_PAD_LD8__UART4_RXD                 0x0e8 0x2e0 0x570 0x02 0x000
 #define MX25_PAD_LD8__FEC_TX_ERR                0x0e8 0x2e0 0x000 0x05 0x000
-#define MX25_PAD_LD8__SDHC2_CMD                 0x0e8 0x2e0 0x4e0 0x06 0x000
+/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
+#define MX25_PAD_LD8__ESDHC2_CMD                0x0e8 0x2e0 0x4e0 0x16 0x000
 
 #define MX25_PAD_LD9__LD9                       0x0ec 0x2e4 0x000 0x00 0x000
 #define MX25_PAD_LD9__UART4_TXD                 0x0ec 0x2e4 0x000 0x02 0x000
 #define MX25_PAD_LD9__FEC_COL                   0x0ec 0x2e4 0x504 0x05 0x001
-#define MX25_PAD_LD9__SDHC2_CLK                 0x0ec 0x2e4 0x4dc 0x06 0x000
+#define MX25_PAD_LD9__ESDHC2_CLK                0x0ec 0x2e4 0x4dc 0x06 0x000
 
 #define MX25_PAD_LD10__LD10                     0x0f0 0x2e8 0x000 0x00 0x000
 #define MX25_PAD_LD10__UART4_RTS                0x0f0 0x2e8 0x56c 0x02 0x000
@@ -250,7 +251,7 @@
 #define MX25_PAD_LD11__LD11                     0x0f4 0x2ec 0x000 0x00 0x000
 #define MX25_PAD_LD11__UART4_CTS                0x0f4 0x2ec 0x000 0x02 0x000
 #define MX25_PAD_LD11__FEC_RDATA2               0x0f4 0x2ec 0x50c 0x05 0x001
-#define MX25_PAD_LD11__SDHC2_DAT1               0x0f4 0x2ec 0x4e8 0x06 0x000
+#define MX25_PAD_LD11__ESDHC2_DAT1              0x0f4 0x2ec 0x4e8 0x06 0x000
 
 #define MX25_PAD_LD12__LD12                     0x0f8 0x2f0 0x000 0x00 0x000
 #define MX25_PAD_LD12__CSPI2_MOSI               0x0f8 0x2f0 0x4a0 0x02 0x000
@@ -316,12 +317,13 @@
 #define MX25_PAD_CSI_D5__CSPI3_RDY              0x12c 0x324 0x000 0x07 0x000
 
 #define MX25_PAD_CSI_D6__CSI_D6                 0x130 0x328 0x000 0x00 0x000
-#define MX25_PAD_CSI_D6__SDHC2_CMD              0x130 0x328 0x4e0 0x02 0x001
+/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
+#define MX25_PAD_CSI_D6__ESDHC2_CMD             0x130 0x328 0x4e0 0x12 0x001
 #define MX25_PAD_CSI_D6__SIM1_PD0               0x130 0x328 0x000 0x04 0x000
 #define MX25_PAD_CSI_D6__GPIO_1_31              0x130 0x328 0x000 0x05 0x000
 
 #define MX25_PAD_CSI_D7__CSI_D7                 0x134 0x32c 0x000 0x00 0x000
-#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK          0x134 0x32C 0x4dc 0x02 0x001
+#define MX25_PAD_CSI_D7__ESDHC2_CLK             0x134 0x32C 0x4dc 0x02 0x001
 #define MX25_PAD_CSI_D7__GPIO_1_6               0x134 0x32c 0x000 0x05 0x000
 
 #define MX25_PAD_CSI_D8__CSI_D8                 0x138 0x330 0x000 0x00 0x000
@@ -336,22 +338,22 @@
 
 #define MX25_PAD_CSI_MCLK__CSI_MCLK             0x140 0x338 0x000 0x00 0x000
 #define MX25_PAD_CSI_MCLK__AUD6_TXD             0x140 0x338 0x000 0x01 0x000
-#define MX25_PAD_CSI_MCLK__SDHC2_DAT0           0x140 0x338 0x4e4 0x02 0x001
+#define MX25_PAD_CSI_MCLK__ESDHC2_DAT0          0x140 0x338 0x4e4 0x02 0x001
 #define MX25_PAD_CSI_MCLK__GPIO_1_8             0x140 0x338 0x000 0x05 0x000
 
 #define MX25_PAD_CSI_VSYNC__CSI_VSYNC           0x144 0x33c 0x000 0x00 0x000
 #define MX25_PAD_CSI_VSYNC__AUD6_RXD            0x144 0x33c 0x000 0x01 0x000
-#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1          0x144 0x33c 0x4e8 0x02 0x001
+#define MX25_PAD_CSI_VSYNC__ESDHC2_DAT1         0x144 0x33c 0x4e8 0x02 0x001
 #define MX25_PAD_CSI_VSYNC__GPIO_1_9            0x144 0x33c 0x000 0x05 0x000
 
 #define MX25_PAD_CSI_HSYNC__CSI_HSYNC           0x148 0x340 0x000 0x00 0x000
 #define MX25_PAD_CSI_HSYNC__AUD6_TXC            0x148 0x340 0x000 0x01 0x000
-#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2          0x148 0x340 0x4ec 0x02 0x001
+#define MX25_PAD_CSI_HSYNC__ESDHC2_DAT2         0x148 0x340 0x4ec 0x02 0x001
 #define MX25_PAD_CSI_HSYNC__GPIO_1_10           0x148 0x340 0x000 0x05 0x000
 
 #define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK         0x14c 0x344 0x000 0x00 0x000
 #define MX25_PAD_CSI_PIXCLK__AUD6_TXFS          0x14c 0x344 0x000 0x01 0x000
-#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3         0x14c 0x344 0x4f0 0x02 0x001
+#define MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3        0x14c 0x344 0x4f0 0x02 0x001
 #define MX25_PAD_CSI_PIXCLK__GPIO_1_11          0x14c 0x344 0x000 0x05 0x000
 
 #define MX25_PAD_I2C1_CLK__I2C1_CLK             0x150 0x348 0x000 0x00 0x000
@@ -419,37 +421,37 @@
 #define MX25_PAD_UART2_CTS__GPIO_4_29           0x18c 0x384 0x000 0x05 0x000
 
 /*
- * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD
+ * Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD
  * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM
  * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon
- * bug that configuring the SD1_CMD function doesn't enable the input path for
- * this pin.
+ * bug that configuring the ESDHCn_CMD function doesn't enable the input path
+ * for this pin.
  * This might have side effects for other hardware units that are connected to
  * that pin and use the respective function as input.
  */
-#define MX25_PAD_SD1_CMD__SD1_CMD               0x190 0x388 0x000 0x10 0x000
+#define MX25_PAD_SD1_CMD__ESDHC1_CMD            0x190 0x388 0x000 0x10 0x000
 #define MX25_PAD_SD1_CMD__CSPI2_MOSI            0x190 0x388 0x4a0 0x01 0x001
 #define MX25_PAD_SD1_CMD__FEC_RDATA2            0x190 0x388 0x50c 0x02 0x002
 #define MX25_PAD_SD1_CMD__GPIO_2_23             0x190 0x388 0x000 0x05 0x000
 
-#define MX25_PAD_SD1_CLK__SD1_CLK               0x194 0x38c 0x000 0x00 0x000
+#define MX25_PAD_SD1_CLK__ESDHC1_CLK            0x194 0x38c 0x000 0x00 0x000
 #define MX25_PAD_SD1_CLK__CSPI2_MISO            0x194 0x38c 0x49c 0x01 0x001
 #define MX25_PAD_SD1_CLK__FEC_RDATA3            0x194 0x38c 0x510 0x02 0x002
 #define MX25_PAD_SD1_CLK__GPIO_2_24             0x194 0x38c 0x000 0x05 0x000
 
-#define MX25_PAD_SD1_DATA0__SD1_DATA0           0x198 0x390 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA0__ESDHC1_DAT0         0x198 0x390 0x000 0x00 0x000
 #define MX25_PAD_SD1_DATA0__CSPI2_SCLK          0x198 0x390 0x494 0x01 0x001
 #define MX25_PAD_SD1_DATA0__GPIO_2_25           0x198 0x390 0x000 0x05 0x000
 
-#define MX25_PAD_SD1_DATA1__SD1_DATA1           0x19c 0x394 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA1__ESDHC1_DAT1         0x19c 0x394 0x000 0x00 0x000
 #define MX25_PAD_SD1_DATA1__AUD7_RXD            0x19c 0x394 0x478 0x03 0x000
 #define MX25_PAD_SD1_DATA1__GPIO_2_26           0x19c 0x394 0x000 0x05 0x000
 
-#define MX25_PAD_SD1_DATA2__SD1_DATA2           0x1a0 0x398 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA2__ESDHC1_DAT2         0x1a0 0x398 0x000 0x00 0x000
 #define MX25_PAD_SD1_DATA2__FEC_RX_CLK          0x1a0 0x398 0x514 0x02 0x002
 #define MX25_PAD_SD1_DATA2__GPIO_2_27           0x1a0 0x398 0x000 0x05 0x000
 
-#define MX25_PAD_SD1_DATA3__SD1_DATA3           0x1a4 0x39c 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA3__ESDHC1_DAT3         0x1a4 0x39c 0x000 0x00 0x000
 #define MX25_PAD_SD1_DATA3__FEC_CRS             0x1a4 0x39c 0x508 0x02 0x002
 #define MX25_PAD_SD1_DATA3__GPIO_2_28           0x1a4 0x39c 0x000 0x05 0x000
 
@@ -496,6 +498,8 @@
 #define MX25_PAD_KPP_COL3__GPIO_3_4             0x1c4 0x3bc 0x000 0x05 0x000
 
 #define MX25_PAD_FEC_MDC__FEC_MDC               0x1c8 0x3c0 0x000 0x00 0x000
+/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
+#define MX25_PAD_FEC_MDC__ESDHC2_CMD            0x1c8 0x3c0 0x4e0 0x11 0x002
 #define MX25_PAD_FEC_MDC__AUD4_TXD              0x1c8 0x3c0 0x464 0x02 0x001
 #define MX25_PAD_FEC_MDC__GPIO_3_5              0x1c8 0x3c0 0x000 0x05 0x000
 
@@ -601,4 +605,28 @@
 #define MX25_PAD_BOOT_MODE1__BOOT_MODE1         0x228 0x000 0x000 0x00 0x000
 #define MX25_PAD_BOOT_MODE1__GPIO_4_31          0x228 0x000 0x000 0x05 0x000
 
+/*
+ * Compatibility defines for out-of-tree users. You should update if you make
+ * use of one of them.
+ */
+#define MX25_PAD_D15__SDHC1_DAT7                MX25_PAD_D15__ESDHC1_DAT7
+#define MX25_PAD_D14__SDHC1_DAT6                MX25_PAD_D14__ESDHC1_DAT6
+#define MX25_PAD_D13__SDHC1_DAT5                MX25_PAD_D13__ESDHC1_DAT5
+#define MX25_PAD_D12__SDHC1_DAT4                MX25_PAD_D12__ESDHC1_DAT4
+#define MX25_PAD_LD8__SDHC2_CMD                 MX25_PAD_LD8__ESDHC2_CMD
+#define MX25_PAD_LD9__SDHC2_CLK                 MX25_PAD_LD9__ESDHC2_CLK
+#define MX25_PAD_LD11__SDHC2_DAT1               MX25_PAD_LD11__ESDHC2_DAT1
+#define MX25_PAD_CSI_D6__SDHC2_CMD              MX25_PAD_CSI_D6__ESDHC2_CMD
+#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK          MX25_PAD_CSI_D7__ESDHC2_CLK
+#define MX25_PAD_CSI_MCLK__SDHC2_DAT0           MX25_PAD_CSI_MCLK__ESDHC2_DAT0
+#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1          MX25_PAD_CSI_VSYNC__ESDHC2_DAT1
+#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2          MX25_PAD_CSI_HSYNC__ESDHC2_DAT2
+#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3         MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3
+#define MX25_PAD_SD1_CMD__SD1_CMD               MX25_PAD_SD1_CMD__ESDHC1_CMD
+#define MX25_PAD_SD1_CLK__SD1_CLK               MX25_PAD_SD1_CLK__ESDHC1_CLK
+#define MX25_PAD_SD1_DATA0__SD1_DATA0           MX25_PAD_SD1_DATA0__ESDHC1_DAT0
+#define MX25_PAD_SD1_DATA1__SD1_DATA1           MX25_PAD_SD1_DATA1__ESDHC1_DAT1
+#define MX25_PAD_SD1_DATA2__SD1_DATA2           MX25_PAD_SD1_DATA2__ESDHC1_DAT2
+#define MX25_PAD_SD1_DATA3__SD1_DATA3           MX25_PAD_SD1_DATA3__ESDHC1_DAT3
+
 #endif /* __DTS_IMX25_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 9445f8e1473c..cf70df20b19c 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -22,7 +22,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec;
@@ -269,6 +269,7 @@
                                 dmas = <&sdma 24 1 0>,
                                        <&sdma 25 1 0>;
                                 dma-names = "rx", "tx";
+                                fsl,fifo-depth = <15>;
                                 status = "disabled";
                         };
 
@@ -329,6 +330,7 @@
                                 dmas = <&sdma 28 1 0>,
                                        <&sdma 29 1 0>;
                                 dma-names = "rx", "tx";
+                                fsl,fifo-depth = <15>;
                                 status = "disabled";
                         };
 
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
index 73aae4f5e539..66941cdbf244 100644
--- a/arch/arm/boot/dts/imx27-apf27.dts
+++ b/arch/arm/boot/dts/imx27-apf27.dts
@@ -19,7 +19,7 @@
         model = "Armadeus Systems APF27 module";
         compatible = "armadeus,imx27-apf27", "fsl,imx27";
 
-        memory {
+        memory@a0000000 {
                 reg = <0xa0000000 0x04000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
index 2cf896c505f9..9c455dcbe6eb 100644
--- a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
+++ b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
@@ -16,21 +16,14 @@
         model = "Eukrea CPUIMX27";
         compatible = "eukrea,cpuimx27", "fsl,imx27";
 
-        memory {
+        memory@a0000000 {
                 reg = <0xa0000000 0x04000000>;
         };
 
-        clocks {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "simple-bus";
-
-                clk14745600: clock@0 {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <14745600>;
-                        reg = <0>;
-                };
+        clk14745600: clk-uart {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <14745600>;
         };
 };
 
diff --git a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
index f56535768ee8..15145e7f9778 100644
--- a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
+++ b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
@@ -84,7 +84,7 @@
         cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
         status = "okay";
 
-        ads7846 {
+        ads7846@0 {
                 compatible = "ti,ads7846";
                 pinctrl-names = "default";
                 pinctrl-0 = <&pinctrl_touch>;
diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts
index 2a140c8ae6d2..924b90c9985d 100644
--- a/arch/arm/boot/dts/imx27-pdk.dts
+++ b/arch/arm/boot/dts/imx27-pdk.dts
@@ -16,7 +16,7 @@
         model = "Freescale i.MX27 Product Development Kit";
         compatible = "fsl,imx27-pdk", "fsl,imx27";
 
-        memory {
+        memory@a0000000 {
                 reg = <0xa0000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
index 0b8490b21a38..cbad7c88c58c 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
@@ -17,7 +17,7 @@
         model = "Phytec pca100";
         compatible = "phytec,imx27-pca100", "fsl,imx27";
 
-        memory {
+        memory@a0000000 {
                 reg = <0xa0000000 0x08000000>; /* 128MB */
         };
 };
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
index c9095b7654c6..ec466b4bfd41 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -16,7 +16,7 @@
         model = "Phytec pcm038";
         compatible = "phytec,imx27-pcm038", "fsl,imx27";
 
-        memory {
+        memory@a0000000 {
                 reg = <0xa0000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 15d85f1f85fd..6585b00c3917 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -26,7 +26,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts
index 070e59cbdd8b..bab78346fa9f 100644
--- a/arch/arm/boot/dts/imx28-apf28.dts
+++ b/arch/arm/boot/dts/imx28-apf28.dts
@@ -16,7 +16,7 @@
         model = "Armadeus Systems APF28 module";
         compatible = "armadeus,imx28-apf28", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index ae078341fb60..96faa53ba44c 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -6,7 +6,7 @@
         model = "Bluegiga APX4 Development Kit";
         compatible = "bluegiga,apx4devkit", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x04000000>;
         };
 
@@ -82,7 +82,8 @@
                                         fsl,pull-up = <MXS_PULL_ENABLE>;
                                 };
 
-                                mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 {
+                                mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_SSP0_DATA7__SSP2_SCK
                                         >;
@@ -146,6 +147,7 @@
                                 sgtl5000: codec@a {
                                         compatible = "fsl,sgtl5000";
                                         reg = <0x0a>;
+                                        #sound-dai-cells = <0>;
                                         VDDA-supply = <&reg_3p3v>;
                                         VDDIO-supply = <&reg_3p3v>;
                                         clocks = <&saif0>;
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index 570aa339a05e..e54f5aba7091 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -16,7 +16,7 @@
         model = "Crystalfontz CFA-10036 Board";
         compatible = "crystalfontz,cfa10036", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 4cd52d53cf00..60e5c7fd5035 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -19,6 +19,71 @@
         model = "Crystalfontz CFA-10049 Board";
         compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
 
+        i2cmux {
+                compatible = "i2c-mux-gpio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2cmux_pins_cfa10049>;
+                mux-gpios = <&gpio1 22 0 &gpio1 23 0>;
+                i2c-parent = <&i2c1>;
+
+                i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+
+                        adc0: nau7802@2a {
+                                compatible = "nuvoton,nau7802";
+                                reg = <0x2a>;
+                                nuvoton,vldo = <3000>;
+                        };
+                };
+
+                i2c@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <1>;
+
+                        adc1: nau7802@2a {
+                                compatible = "nuvoton,nau7802";
+                                reg = <0x2a>;
+                                nuvoton,vldo = <3000>;
+                        };
+                };
+
+                i2c@2 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <2>;
+
+                                adc2: nau7802@2a {
+                                compatible = "nuvoton,nau7802";
+                                reg = <0x2a>;
+                                nuvoton,vldo = <3000>;
+                        };
+                };
+
+                i2c@3 {
+                        reg = <3>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        pca9555: pca9555@20 {
+                                compatible = "nxp,pca9555";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pca_pins_cfa10049>;
+                                interrupt-parent = <&gpio2>;
+                                interrupts = <19 0x2>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x20>;
+                        };
+                };
+        };
+
         apb@80000000 {
                 apbh@80000000 {
                         pinctrl@80018000 {
@@ -219,71 +284,6 @@
                                 status = "okay";
                         };
 
-                        i2cmux {
-                                compatible = "i2c-mux-gpio";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&i2cmux_pins_cfa10049>;
-                                mux-gpios = <&gpio1 22 0 &gpio1 23 0>;
-                                i2c-parent = <&i2c1>;
-
-                                i2c@0 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <0>;
-
-                                        adc0: nau7802@2a {
-                                                compatible = "nuvoton,nau7802";
-                                                reg = <0x2a>;
-                                                nuvoton,vldo = <3000>;
-                                        };
-                                };
-
-                                i2c@1 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <1>;
-
-                                        adc1: nau7802@2a {
-                                                compatible = "nuvoton,nau7802";
-                                                reg = <0x2a>;
-                                                nuvoton,vldo = <3000>;
-                                        };
-                                };
-
-                                i2c@2 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <2>;
-
-                                        adc2: nau7802@2a {
-                                                compatible = "nuvoton,nau7802";
-                                                reg = <0x2a>;
-                                                nuvoton,vldo = <3000>;
-                                        };
-                                };
-
-                                i2c@3 {
-                                        reg = <3>;
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-
-                                        pca9555: pca9555@20 {
-                                                compatible = "nxp,pca9555";
-                                                pinctrl-names = "default";
-                                                pinctrl-0 = <&pca_pins_cfa10049>;
-                                                interrupt-parent = <&gpio2>;
-                                                interrupts = <19 0x2>;
-                                                gpio-controller;
-                                                #gpio-cells = <2>;
-                                                interrupt-controller;
-                                                #interrupt-cells = <2>;
-                                                reg = <0x20>;
-                                        };
-                                };
-                        };
-
                         usbphy1: usbphy@8007e000 {
                                 status = "okay";
                         };
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-485.dts b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
index bd3fd470f9c3..97084e463d7c 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-485.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
@@ -19,7 +19,7 @@
         model = "I2SE Duckbill 2 485";
         compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
index 4450047885eb..7f8d40a9c67e 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
@@ -20,7 +20,7 @@
         model = "I2SE Duckbill 2 EnOcean";
         compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
index 927732efca98..13e7b134da9e 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
@@ -23,7 +23,7 @@
                 ethernet1 = &qca7000;
         };
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-duckbill-2.dts b/arch/arm/boot/dts/imx28-duckbill-2.dts
index 7fa3d759505c..88556c93b00f 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2.dts
@@ -19,7 +19,7 @@
         model = "I2SE Duckbill 2";
         compatible = "i2se,duckbill-2", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts
index 3e4385d4ed78..f286bfe699be 100644
--- a/arch/arm/boot/dts/imx28-duckbill.dts
+++ b/arch/arm/boot/dts/imx28-duckbill.dts
@@ -18,7 +18,7 @@
         model = "I2SE Duckbill";
         compatible = "i2se,duckbill", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
index 7c1572c5a4fb..b70f3349c350 100644
--- a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
@@ -23,7 +23,7 @@
         model = "Eukrea Electromatique MBMX283LC";
         compatible = "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x04000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
index b61fd61eb1c7..65efb78ac040 100644
--- a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
@@ -22,7 +22,7 @@
         model = "Eukrea Electromatique MBMX287LC";
         compatible = "eukrea,mbmx287lc", "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
index 49ab40838e69..ff1328ce7d37 100644
--- a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
@@ -151,6 +151,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 VDDA-supply = <&reg_3p3v>;
                 VDDIO-supply = <&reg_3p3v>;
                 clocks = <&saif0>;
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 7f5b80402c54..b0d39654aeb3 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -16,7 +16,7 @@
         model = "Freescale i.MX28 Evaluation Kit";
         compatible = "fsl,imx28-evk", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
@@ -197,6 +197,7 @@
                                 sgtl5000: codec@a {
                                         compatible = "fsl,sgtl5000";
                                         reg = <0x0a>;
+                                        #sound-dai-cells = <0>;
                                         VDDA-supply = <&reg_3p3v>;
                                         VDDIO-supply = <&reg_3p3v>;
                                         clocks = <&saif0>;
diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi
index a69856e41ba4..0ec415e1ff58 100644
--- a/arch/arm/boot/dts/imx28-m28.dtsi
+++ b/arch/arm/boot/dts/imx28-m28.dtsi
@@ -15,7 +15,7 @@
         model = "Aries/DENX M28";
         compatible = "aries,m28", "denx,m28", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts
index 9d6c8fe28d74..3bb5ffc644d6 100644
--- a/arch/arm/boot/dts/imx28-m28cu3.dts
+++ b/arch/arm/boot/dts/imx28-m28cu3.dts
@@ -16,7 +16,7 @@
         model = "MSR M28CU3";
         compatible = "msr,m28cu3", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 22aa025cab1e..7d97a0ce74a3 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -140,6 +140,7 @@
                                 sgtl5000: codec@a {
                                         compatible = "fsl,sgtl5000";
                                         reg = <0x0a>;
+                                        #sound-dai-cells = <0>;
                                         VDDA-supply = <&reg_3p3v>;
                                         VDDIO-supply = <&reg_3p3v>;
                                         clocks = <&saif0>;
diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts
index 0ce3cb8e7914..2393e83979e0 100644
--- a/arch/arm/boot/dts/imx28-sps1.dts
+++ b/arch/arm/boot/dts/imx28-sps1.dts
@@ -16,7 +16,7 @@
         model = "SchulerControl GmbH, SC SPS 1";
         compatible = "schulercontrol,imx28-sps1", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-ts4600.dts b/arch/arm/boot/dts/imx28-ts4600.dts
index 1e391c9f1b7a..f8a09a8c2c36 100644
--- a/arch/arm/boot/dts/imx28-ts4600.dts
+++ b/arch/arm/boot/dts/imx28-ts4600.dts
@@ -19,7 +19,7 @@
         model = "Technologic Systems i.MX28 TS-4600";
         compatible = "technologic,imx28-ts4600", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x10000000>;   /* 256MB */
         };
 
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index 152621ea37db..687186358c18 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -65,8 +65,8 @@
                 usbotg = &usb0;
         };
 
-        memory {
-                reg = <0 0>; /* will be filled in by U-Boot */
+        memory@40000000 {
+                reg = <0x40000000 0>; /* will be filled in by U-Boot */
         };
 
         onewire {
@@ -531,7 +531,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins {
+        tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_SSP0_DATA6__GPIO_2_6 /* RESET */
                         MX28_PAD_SSP0_DATA5__GPIO_2_5 /* IRQ */
@@ -542,7 +543,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins {
+        tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_LCD_D00__GPIO_1_0
                 >;
@@ -551,7 +553,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_lcdif_23bit_pins: tx28-lcdif-23bit {
+        tx28_lcdif_23bit_pins: tx28-lcdif-23bit@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         /* LCD_D00 may be used as Flexcan Transceiver Enable on STK5-V5 */
                         MX28_PAD_LCD_D01__LCD_D1
@@ -583,7 +586,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl {
+        tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_LCD_ENABLE__GPIO_1_31 /* Enable */
                         MX28_PAD_LCD_RESET__GPIO_3_30  /* Reset */
@@ -593,7 +597,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_mac0_pins_gpio: tx28-mac0-gpio-pins {
+        tx28_mac0_pins_gpio: tx28-mac0-gpio-pins@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_ENET0_MDC__GPIO_4_0
                         MX28_PAD_ENET0_MDIO__GPIO_4_1
@@ -610,7 +615,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_pca9554_pins: tx28-pca9554-pins {
+        tx28_pca9554_pins: tx28-pca9554-pins@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_PWM3__GPIO_3_28
                 >;
@@ -619,7 +625,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_spi_gpio_pins: spi-gpiogrp {
+        tx28_spi_gpio_pins: spi-gpiogrp@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_AUART2_RX__GPIO_3_8
                         MX28_PAD_AUART2_TX__GPIO_3_9
@@ -633,7 +640,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_tsc2007_pins: tx28-tsc2007-pins {
+        tx28_tsc2007_pins: tx28-tsc2007-pins@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */
                 >;
@@ -643,7 +651,8 @@
         };
 
 
-        tx28_usbphy0_pins: tx28-usbphy0-pins {
+        tx28_usbphy0_pins: tx28-usbphy0-pins@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_GPMI_CE2N__GPIO_0_18 /* USBOTG_VBUSEN */
                         MX28_PAD_GPMI_CE3N__GPIO_0_19 /* USBOTH_OC */
@@ -653,7 +662,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_usbphy1_pins: tx28-usbphy1-pins {
+        tx28_usbphy1_pins: tx28-usbphy1-pins@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_SPDIF__GPIO_3_27 /* USBH_VBUSEN */
                         MX28_PAD_JTAG_RTCK__GPIO_4_20 /* USBH_OC */
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index e52e05c0fe56..9ad8d3556859 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -24,7 +24,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &mac0;
@@ -283,7 +283,8 @@
                                         fsl,pull-up = <MXS_PULL_DISABLE>;
                                 };
 
-                                gpmi_status_cfg: gpmi-status-cfg {
+                                gpmi_status_cfg: gpmi-status-cfg@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_GPMI_RDN__GPMI_RDN
                                                 MX28_PAD_GPMI_WRN__GPMI_WRN
@@ -527,14 +528,16 @@
                                         fsl,pull-up = <MXS_PULL_ENABLE>;
                                 };
 
-                                mmc0_cd_cfg: mmc0-cd-cfg {
+                                mmc0_cd_cfg: mmc0-cd-cfg@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
                                         >;
                                         fsl,pull-up = <MXS_PULL_DISABLE>;
                                 };
 
-                                mmc0_sck_cfg: mmc0-sck-cfg {
+                                mmc0_sck_cfg: mmc0-sck-cfg@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_SSP0_SCK__SSP0_SCK
                                         >;
@@ -558,14 +561,16 @@
                                         fsl,pull-up = <MXS_PULL_ENABLE>;
                                 };
 
-                                mmc1_cd_cfg: mmc1-cd-cfg {
+                                mmc1_cd_cfg: mmc1-cd-cfg@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
                                         >;
                                         fsl,pull-up = <MXS_PULL_DISABLE>;
                                 };
 
-                                mmc1_sck_cfg: mmc1-sck-cfg {
+                                mmc1_sck_cfg: mmc1-sck-cfg@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_GPMI_WRN__SSP1_SCK
                                         >;
@@ -606,7 +611,8 @@
                                         fsl,pull-up = <MXS_PULL_ENABLE>;
                                 };
 
-                                mmc2_cd_cfg: mmc2-cd-cfg {
+                                mmc2_cd_cfg: mmc2-cd-cfg@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
                                         >;
diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts
index ae6cebbed84b..6ee4ff8e4e8f 100644
--- a/arch/arm/boot/dts/imx31-bug.dts
+++ b/arch/arm/boot/dts/imx31-bug.dts
@@ -16,7 +16,7 @@
         model = "Buglabs i.MX31 Bug 1.x";
         compatible = "buglabs,imx31-bug", "fsl,imx31";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x8000000>; /* 128M */
         };
 };
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index a72031407ebd..ebc3f2dbb6fd 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -19,7 +19,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 serial0 = &uart1;
diff --git a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
index 9c2b715ab8bf..ba39d938f289 100644
--- a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
+++ b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
@@ -17,7 +17,7 @@
         model = "Eukrea CPUIMX35";
         compatible = "eukrea,cpuimx35", "fsl,imx35";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x8000000>; /* 128M */
         };
 };
diff --git a/arch/arm/boot/dts/imx35-pdk.dts b/arch/arm/boot/dts/imx35-pdk.dts
index 9bb628f22502..646b1257bba2 100644
--- a/arch/arm/boot/dts/imx35-pdk.dts
+++ b/arch/arm/boot/dts/imx35-pdk.dts
@@ -17,7 +17,7 @@
         model = "Freescale i.MX35 Product Development Kit";
         compatible = "fsl,imx35-pdk", "fsl,imx35";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x8000000>,
                       <0x90000000 0x8000000>;
         };
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index e08c0c193767..bf343195697e 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -20,7 +20,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts
index 98b5faa06e27..23f1833e23fa 100644
--- a/arch/arm/boot/dts/imx50-evk.dts
+++ b/arch/arm/boot/dts/imx50-evk.dts
@@ -18,7 +18,7 @@
         model = "Freescale i.MX50 Evaluation Kit";
         compatible = "fsl,imx50-evk", "fsl,imx50";
 
-        memory {
+        memory@70000000 {
                 reg = <0x70000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 35955e63d6c5..7954e79d0a16 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -25,7 +25,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index c83ac1600322..79d80036f74d 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -21,7 +21,7 @@
         model = "Armadeus Systems APF51 module";
         compatible = "armadeus,imx51-apf51", "fsl,imx51";
 
-        memory {
+        memory@90000000 {
                 reg = <0x90000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 4ac5ab614a7f..cf7a1963df25 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -21,7 +21,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@90000000 {
                 reg = <0x90000000 0x20000000>;
         };
 
@@ -369,6 +369,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 clocks = <&clk_audio>;
                 VDDA-supply = <&vdig_reg>;
                 VDDIO-supply = <&vvideo_reg>;
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
index b821066a0d2a..5761a66e8a0d 100644
--- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
+++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
@@ -16,7 +16,7 @@
         model = "Digi ConnectCore CC(W)-MX51";
         compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51";
 
-        memory {
+        memory@90000000 {
                 reg = <0x90000000 0x08000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
index 63164266af83..f8902a338e49 100644
--- a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
+++ b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
@@ -22,7 +22,7 @@
         model = "Eukrea CPUIMX51";
         compatible = "eukrea,cpuimx51", "fsl,imx51";
 
-        memory {
+        memory@90000000 {
                 reg = <0x90000000 0x10000000>; /* 256M */
         };
 };
diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts
index f59b02bae68d..39eb067904c3 100644
--- a/arch/arm/boot/dts/imx51-ts4800.dts
+++ b/arch/arm/boot/dts/imx51-ts4800.dts
@@ -17,7 +17,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@90000000 {
                 reg = <0x90000000 0x10000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts
index 5306b78de0ca..0c99ac04ad08 100644
--- a/arch/arm/boot/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
@@ -51,6 +51,11 @@
                 stdout-path = &uart1;
         };
 
+        /* Will be filled by the bootloader */
+        memory@90000000 {
+                reg = <0x90000000 0>;
+        };
+
         aliases {
                 mdio-gpio0 = &mdio_gpio;
                 rtc0 = &ds1341;
@@ -568,6 +573,15 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3>;
         status = "okay";
+
+        rave-sp {
+                compatible = "zii,rave-sp-rdu1";
+                current-speed = <38400>;
+
+                watchdog {
+                        compatible = "zii,rave-sp-watchdog";
+                };
+        };
 };
 
 &usbh1 {
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 00d30bd70068..5d390a64e976 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -26,7 +26,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 4486bc47d140..80fc00705d92 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -17,7 +17,7 @@
         model = "Freescale i.MX53 Automotive Reference Design Board";
         compatible = "fsl,imx53-ard", "fsl,imx53";
 
-        memory {
+        memory@70000000 {
                 reg = <0x70000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx53-cx9020.dts b/arch/arm/boot/dts/imx53-cx9020.dts
index 5e67e43004e7..cf70ebc4399a 100644
--- a/arch/arm/boot/dts/imx53-cx9020.dts
+++ b/arch/arm/boot/dts/imx53-cx9020.dts
@@ -21,7 +21,7 @@
                 stdout-path = &uart2;
         };
 
-        memory {
+        memory@70000000 {
                 reg = <0x70000000 0x20000000>,
                       <0xb0000000 0x20000000>;
         };
diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi
index 7ce69c63510c..3da6dd5edb79 100644
--- a/arch/arm/boot/dts/imx53-m53.dtsi
+++ b/arch/arm/boot/dts/imx53-m53.dtsi
@@ -15,7 +15,7 @@
         model = "Aries/DENX M53";
         compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53";
 
-        memory {
+        memory@70000000 {
                 reg = <0x70000000 0x20000000>,
                       <0xb0000000 0x20000000>;
         };
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index e48525763b1b..3935fe6490ed 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -153,6 +153,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 VDDA-supply = <&reg_3p2v>;
                 VDDIO-supply = <&reg_3p2v>;
                 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts
index cce959438a79..d5628af2e301 100644
--- a/arch/arm/boot/dts/imx53-ppd.dts
+++ b/arch/arm/boot/dts/imx53-ppd.dts
@@ -132,6 +132,14 @@
                 enable-active-high;
         };
 
+        reg_tsiref: regulator-tsiref {
+                compatible = "regulator-fixed";
+                regulator-name = "tsiref";
+                regulator-min-microvolt = <2500000>;
+                regulator-max-microvolt = <2500000>;
+                regulator-always-on;
+        };
+
         pwm_bl: backlight {
                 compatible = "pwm-backlight";
                 pwms = <&pwm2 0 50000>;
@@ -294,6 +302,8 @@
                 interrupt-parent = <&gpio3>;
                 interrupts = <12 0x8>;
                 spi-max-frequency = <1000000>;
+                dlg,tsi-as-adc;
+                tsiref-supply = <&reg_tsiref>;
 
                 regulators {
                         buck1_reg: buck1 {
@@ -436,6 +446,7 @@
                         sgtl5000: codec@a {
                                 compatible = "fsl,sgtl5000";
                                 reg = <0xa>;
+                                #sound-dai-cells = <0>;
                                 VDDA-supply = <&reg_sgtl5k>;
                                 VDDIO-supply = <&reg_sgtl5k>;
                                 clocks = <&cko2_11M>;
@@ -525,6 +536,7 @@
 
         touchscreen@4b {
                 compatible = "atmel,maxtouch";
+                reset-gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
                 reg = <0x4b>;
                 interrupt-parent = <&gpio5>;
                 interrupts = <4 0x8>;
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi
index 41a2e2a2b079..485a69d45e1c 100644
--- a/arch/arm/boot/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -17,7 +17,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@70000000 {
                 reg = <0x70000000 0x20000000>,
                       <0xb0000000 0x20000000>;
         };
@@ -317,6 +317,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 VDDA-supply = <&reg_3p2v>;
                 VDDIO-supply = <&reg_3p2v>;
                 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 51f4a42a55e2..fd030128666c 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -17,7 +17,7 @@
         model = "Freescale i.MX53 Smart Mobile Reference Design Board";
         compatible = "fsl,imx53-smd", "fsl,imx53";
 
-        memory {
+        memory@70000000 {
                 reg = <0x70000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
index eecdc1c55eef..a72b8981fc3b 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -16,7 +16,7 @@
         model = "TQ TQMa53";
         compatible = "tq,tqma53", "fsl,imx53";
 
-        memory {
+        memory@70000000 {
                 reg = <0x70000000 0x40000000>; /* Up to 1GiB */
         };
 
diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/imx53-tx53-x03x.dts
index fe15c9555d6e..af8ec5e4417b 100644
--- a/arch/arm/boot/dts/imx53-tx53-x03x.dts
+++ b/arch/arm/boot/dts/imx53-tx53-x03x.dts
@@ -230,6 +230,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 VDDA-supply = <&reg_2v5>;
                 VDDIO-supply = <&reg_3v3>;
                 clocks = <&mclk>;
diff --git a/arch/arm/boot/dts/imx53-tx53-x13x.dts b/arch/arm/boot/dts/imx53-tx53-x13x.dts
index f2b2ad3ce9e5..6cdf2082c742 100644
--- a/arch/arm/boot/dts/imx53-tx53-x13x.dts
+++ b/arch/arm/boot/dts/imx53-tx53-x13x.dts
@@ -131,6 +131,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 VDDA-supply = <&reg_2v5>;
                 VDDIO-supply = <&reg_3v3>;
                 clocks = <&mclk>;
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
index a22e461fc168..69a2af7d6c11 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -49,6 +49,11 @@
         model = "Ka-Ro electronics TX53 module";
         compatible = "karo,tx53", "fsl,imx53";
 
+        /* Will be filled by the bootloader */
+        memory@70000000 {
+                reg = <0x70000000 0>;
+        };
+
         aliases {
                 can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */
                 can1 = &can1;
diff --git a/arch/arm/boot/dts/imx53-usbarmory.dts b/arch/arm/boot/dts/imx53-usbarmory.dts
index 6782d7fc5961..f6268d0ded29 100644
--- a/arch/arm/boot/dts/imx53-usbarmory.dts
+++ b/arch/arm/boot/dts/imx53-usbarmory.dts
@@ -57,7 +57,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@70000000 {
                 reg = <0x70000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts b/arch/arm/boot/dts/imx53-voipac-bsb.dts
index 25c78f19826c..957053755c3c 100644
--- a/arch/arm/boot/dts/imx53-voipac-bsb.dts
+++ b/arch/arm/boot/dts/imx53-voipac-bsb.dts
@@ -133,6 +133,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 VDDA-supply = <&reg_3p3v>;
                 VDDIO-supply = <&reg_3p3v>;
                 clocks = <&clks 150>;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 1040251f2951..7d647d043f52 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -26,7 +26,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx6dl-apf6dev.dts b/arch/arm/boot/dts/imx6dl-apf6dev.dts
index df26e542ab3a..4a7f86de6c39 100644
--- a/arch/arm/boot/dts/imx6dl-apf6dev.dts
+++ b/arch/arm/boot/dts/imx6dl-apf6dev.dts
@@ -54,7 +54,7 @@
         model = "Armadeus APF6 Solo Module on APF6Dev Board";
         compatible = "armadeus,imx6dl-apf6dev", "armadeus,imx6dl-apf6", "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts
index 5f0d196495d0..7128c76d5721 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts
@@ -48,7 +48,7 @@
         model = "aristainetos2 i.MX6 Dual Lite Board 4";
         compatible = "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts
index 805b1318b7f7..240f3661469f 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts
@@ -48,7 +48,7 @@
         model = "aristainetos2 i.MX6 Dual Lite Board 7";
         compatible = "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
index 3c9f4af9e9ff..ad7733662fe5 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
@@ -27,7 +27,7 @@
                 status = "okay";
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
index 96cd835ccbf6..64ed84e3c512 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
@@ -16,7 +16,7 @@
         model = "aristainetos i.MX6 Dual Lite Board 7";
         compatible = "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
index dcf9206f3e0d..ea184d108491 100644
--- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -53,6 +53,11 @@
         compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl",
                      "fsl,imx6dl";
 
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
+
         aliases {
                 i2c0 = &i2c2;
                 i2c1 = &i2c3;
@@ -63,6 +68,10 @@
                 rtc1 = &snvs_rtc;
         };
 
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
         clocks {
                 /* Fixed crystal dedicated to mcp251x */
                 clk16m: clk@1 {
diff --git a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts
index 994f96a3fb54..89384cb618f6 100644
--- a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts
+++ b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts
@@ -20,4 +20,9 @@
 / {
         model = "DFI FS700-M60-6DL i.MX6dl Q7 Board";
         compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl";
+
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
new file mode 100644
index 000000000000..a8adcb2ec3fd
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-mira.dtsi"
+
+/ {
+        model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND";
+        compatible = "phytec,imx6dl-pbac06-nand", "phytec,imx6dl-pbac06",
+                     "phytec,imx6qdl-pcm058", "fsl,imx6dl";
+
+        chosen {
+                linux,stdout-path = &uart2;
+        };
+};
+
+&ethphy {
+        max-speed = <100>;
+};
+
+&fec {
+        status = "okay";
+};
+
+&gpmi {
+        status = "okay";
+};
+
+&hdmi {
+        status = "okay";
+};
+
+&i2c1 {
+        status = "okay";
+};
+
+&i2c2 {
+        status = "okay";
+};
+
+&i2c_rtc {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
+&usbotg {
+        status = "okay";
+};
+
+&usdhc1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi
index 964bc2ad3c5d..7d9888937f12 100644
--- a/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi
@@ -16,7 +16,7 @@
         model = "Phytec phyFLEX-i.MX6 DualLite/Solo";
         compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6dl-rex-basic.dts b/arch/arm/boot/dts/imx6dl-rex-basic.dts
index c3a14a4330a2..3fb7f4ee2496 100644
--- a/arch/arm/boot/dts/imx6dl-rex-basic.dts
+++ b/arch/arm/boot/dts/imx6dl-rex-basic.dts
@@ -16,7 +16,7 @@
         model = "Rex Basic i.MX6 Dual Lite Board";
         compatible = "rex,imx6dl-rex-basic", "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
index 23e108204e1e..2e98c92adff7 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -15,7 +15,7 @@
         model = "RIoTboard i.MX6S";
         compatible = "riot,imx6s-riotboard", "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6dl-ts4900.dts b/arch/arm/boot/dts/imx6dl-ts4900.dts
index 6ea0b780677d..cc01a7a22e30 100644
--- a/arch/arm/boot/dts/imx6dl-ts4900.dts
+++ b/arch/arm/boot/dts/imx6dl-ts4900.dts
@@ -46,4 +46,9 @@
 / {
         model = "Technologic Systems i.MX6 Solo/DualLite TS-4900 (Default Device Tree)";
         compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl";
+
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx6dl-ts7970.dts b/arch/arm/boot/dts/imx6dl-ts7970.dts
index d104daf305d9..82435d5bf33f 100644
--- a/arch/arm/boot/dts/imx6dl-ts7970.dts
+++ b/arch/arm/boot/dts/imx6dl-ts7970.dts
@@ -47,4 +47,9 @@
 / {
         model = "Technologic Systems i.MX6 Solo/DualLite TS-7970 (Default Device Tree)";
         compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl";
+
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts b/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts
index 8c314eee4fdd..5727fa48cfd5 100644
--- a/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts
+++ b/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts
@@ -16,7 +16,7 @@
         model = "Wandboard i.MX6 Dual Lite Board rev B1";
         compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts
index aa4d4faaaec4..a72c07db7dda 100644
--- a/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts
+++ b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts
@@ -16,7 +16,7 @@
         model = "Wandboard i.MX6 Dual Lite Board revD1";
         compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts
index bbb616723097..a09f274cd1f4 100644
--- a/arch/arm/boot/dts/imx6dl-wandboard.dts
+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
@@ -16,7 +16,7 @@
         model = "Wandboard i.MX6 Dual Lite Board";
         compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index c01674fa098a..558bce81209d 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -80,11 +80,6 @@
                                 reg = <0x020f4000 0x4000>;
                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
                         };
-
-                        lcdif: lcdif@20f8000 {
-                                reg = <0x020f8000 0x4000>;
-                                interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
-                        };
                 };
 
                 aips2: aips-bus@2100000 {
@@ -109,11 +104,6 @@
                 compatible = "fsl,imx-display-subsystem";
                 ports = <&ipu1_di0>, <&ipu1_di1>;
         };
-
-        gpu-subsystem {
-                compatible = "fsl,imx-gpu-subsystem";
-                cores = <&gpu_2d>, <&gpu_3d>;
-        };
 };
 
 &gpio1 {
diff --git a/arch/arm/boot/dts/imx6q-apf6dev.dts b/arch/arm/boot/dts/imx6q-apf6dev.dts
index 4e4de821d9e5..5e72f81cdf8b 100644
--- a/arch/arm/boot/dts/imx6q-apf6dev.dts
+++ b/arch/arm/boot/dts/imx6q-apf6dev.dts
@@ -54,7 +54,7 @@
         model = "Armadeus APF6 Quad / Dual Module on APF6Dev Board";
         compatible = "armadeus,imx6q-apf6dev", "armadeus,imx6q-apf6", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 4989d0bff10f..953a5b5a8ea4 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -18,7 +18,7 @@
         model = "Freescale i.MX6 Quad Armadillo2 Board";
         compatible = "fsl,imx6q-arm2", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
index 5fcb0372d58b..bf4bdb385de9 100644
--- a/arch/arm/boot/dts/imx6q-ba16.dtsi
+++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
@@ -46,7 +46,7 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
index 916ea94d75ca..990e411cbca0 100644
--- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -353,6 +353,14 @@
         };
 };
 
+&pmu {
+        secure-reg-access;
+};
+
+&usdhc2 {
+        status = "disabled";
+};
+
 &usdhc4 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_usdhc4>;
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
index bc7587c383f6..65ef4cacbc71 100644
--- a/arch/arm/boot/dts/imx6q-cm-fx6.dts
+++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
@@ -50,7 +50,7 @@
         model = "CompuLab CM-FX6";
         compatible = "compulab,cm-fx6", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts
index fd0ad9a8866c..ad12d76bbb89 100644
--- a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts
+++ b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts
@@ -20,4 +20,9 @@
 / {
         model = "DFI FS700-M60-6QD i.MX6qd Q7 Board";
         compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q";
+
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx6q-display5.dtsi b/arch/arm/boot/dts/imx6q-display5.dtsi
index 09085fde3341..85232c7c36a0 100644
--- a/arch/arm/boot/dts/imx6q-display5.dtsi
+++ b/arch/arm/boot/dts/imx6q-display5.dtsi
@@ -47,7 +47,7 @@
         model = "Liebherr (LWN) display5 i.MX6 Quad Board";
         compatible = "lwn,display5", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index f0316ea96898..b3c6a4a7897d 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -29,7 +29,7 @@
                 stmpe-i2c1 = &stmpe2;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-dms-ba16.dts b/arch/arm/boot/dts/imx6q-dms-ba16.dts
new file mode 100644
index 000000000000..57761f3172fa
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-dms-ba16.dts
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6q-ba16.dtsi"
+
+/ {
+        model = "Advantech DMS-BA16";
+        compatible = "advantech,imx6q-dms-ba16", "advantech,imx6q-ba16", "fsl,imx6q";
+
+        reg_usb_otg_vbus: regulator-usbotgvbus {
+                compatible = "regulator-fixed";
+                regulator-name = "usb_otg_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_usbotgvbus>;
+                gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        sys_mclk: clock-sys-mclk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <22000000>;
+        };
+
+        sound {
+                compatible = "fsl,imx6q-ba16-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx6q-ba16-sgtl5000";
+                ssi-controller = <&ssi1>;
+                audio-codec = <&sgtl5000>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                mux-int-port = <1>;
+                mux-ext-port = <4>;
+        };
+};
+
+&ecspi5 {
+        cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi5>;
+        status = "okay";
+
+        m25_eeprom: m25p80@0 {
+                compatible = "atmel,at25256B", "atmel,at25";
+                spi-max-frequency = <20000000>;
+                size = <0x8000>;
+                pagesize = <64>;
+                reg = <0>;
+                address-width = <16>;
+        };
+};
+
+&iomuxc {
+        pinctrl_i2c1_gpio: i2c1gpiogrp {
+                fsl,pins = <
+                        MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26        0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27        0x1b0b0
+                >;
+        };
+
+        pinctrl_i2c2_gpio: i2c2gpiogrp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0
+                        MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0
+                >;
+        };
+
+        pinctrl_i2c3_gpio: i2c3gpiogrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_3__GPIO1_IO03   0x1b0b0
+                        MX6QDL_PAD_GPIO_6__GPIO1_IO06   0x1b0b0
+                >;
+        };
+
+        pinctrl_usbotgvbus: usbotgvbusgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+                        MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0
+                >;
+        };
+};
+
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+
+        sgtl5000: codec@a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                clocks = <&sys_mclk>;
+                lrclk-strength = <0x3>;
+                VDDA-supply = <&reg_1p8v>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
+};
+
+&pwm2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm2>;
+        status = "okay";
+};
+
+&sata {
+        fsl,no-spread-spectrum;
+        fsl,transmit-atten-16ths = <12>;
+        fsl,transmit-boost-mdB = <3330>;
+        fsl,transmit-level-mV = <1133>;
+        fsl,receive-dpll-mode = <1>;
+        status = "okay";
+};
+
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        dr_mode = "otg";
+        disable-over-current;
+        status = "okay";
+};
+
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        bus-width = <8>;
+        cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+        no-1-8-v;
+        keep-power-in-suspend;
+        wakeup-source;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index e0aea782c666..fcd257bc5ac3 100644
--- a/arch/arm/boot/dts/imx6q-evi.dts
+++ b/arch/arm/boot/dts/imx6q-evi.dts
@@ -50,7 +50,7 @@
         model = "Uniwest Evi";
         compatible = "uniwest,imx6q-evi", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts
index b715deb4ea46..0be375611382 100644
--- a/arch/arm/boot/dts/imx6q-gk802.dts
+++ b/arch/arm/boot/dts/imx6q-gk802.dts
@@ -18,7 +18,7 @@
                 stdout-path = &uart4;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index 29adaa7c72f8..a8f70b4266ef 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -60,7 +60,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/imx6q-h100.dts
index 8a2ea6c58902..714e09e04dcb 100644
--- a/arch/arm/boot/dts/imx6q-h100.dts
+++ b/arch/arm/boot/dts/imx6q-h100.dts
@@ -49,6 +49,11 @@
         model = "Auvidea H100";
         compatible = "auvidea,h100", "fsl,imx6q";
 
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
+
         aliases {
                 rtc0 = &rtc;
                 rtc1 = &snvs_rtc;
@@ -161,7 +166,7 @@
         status = "okay";
 
         eeprom: 24c02@51 {
-                compatible = "microchip,24c02", "at24";
+                compatible = "microchip,24c02", "atmel,24c02";
                 reg = <0x51>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts
index 432291bedcf1..dd763f205819 100644
--- a/arch/arm/boot/dts/imx6q-marsboard.dts
+++ b/arch/arm/boot/dts/imx6q-marsboard.dts
@@ -47,7 +47,7 @@
         model = "Embest MarS Board i.MX6Dual";
         compatible = "embest,imx6q-marsboard", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts b/arch/arm/boot/dts/imx6q-mccmon6.dts
index cab36f48d5f1..b7e9f38cec72 100644
--- a/arch/arm/boot/dts/imx6q-mccmon6.dts
+++ b/arch/arm/boot/dts/imx6q-mccmon6.dts
@@ -19,7 +19,7 @@
         model = "Liebherr (LWN) monitor6 i.MX6 Quad Board";
         compatible = "lwn,mccmon6", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts
index 7d7dc59507cf..52f39371188d 100644
--- a/arch/arm/boot/dts/imx6q-novena.dts
+++ b/arch/arm/boot/dts/imx6q-novena.dts
@@ -55,6 +55,11 @@
         model = "Kosagi Novena Dual/Quad";
         compatible = "kosagi,imx6q-novena", "fsl,imx6q";
 
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
+
         chosen {
                 stdout-path = &uart2;
         };
diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
new file mode 100644
index 000000000000..8fdce3c8e5fa
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-mira.dtsi"
+
+/ {
+        model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC";
+        compatible = "phytec,imx6q-pbac06-emmc", "phytec,imx6q-pbac06",
+                     "phytec,imx6qdl-pcm058", "fsl,imx6q";
+
+        chosen {
+                linux,stdout-path = &uart2;
+        };
+};
+
+&can1 {
+        status = "okay";
+};
+
+&fec {
+        status = "okay";
+};
+
+&hdmi {
+        status = "okay";
+};
+
+&i2c1 {
+        status = "okay";
+};
+
+&i2c2 {
+        status = "okay";
+};
+
+&i2c_rtc {
+        status = "okay";
+};
+
+&m25p80 {
+        status = "okay";
+};
+
+&pcie {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
+&usbotg {
+        status = "okay";
+};
+
+&usdhc1 {
+        status = "okay";
+};
+
+&usdhc4 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
new file mode 100644
index 000000000000..8afa5ceb7d7c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-mira.dtsi"
+
+/ {
+        model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND";
+        compatible = "phytec,imx6q-pbac06-nand", "phytec,imx6q-pbac06",
+                     "phytec,imx6qdl-pcm058", "fsl,imx6q";
+
+        chosen {
+                linux,stdout-path = &uart2;
+        };
+};
+
+&can1 {
+        status = "okay";
+};
+
+&fec {
+        status = "okay";
+};
+
+&gpmi {
+        status = "okay";
+};
+
+&hdmi {
+        status = "okay";
+};
+
+&i2c1 {
+        status = "okay";
+};
+
+&i2c2 {
+        status = "okay";
+};
+
+&i2c_rtc {
+        status = "okay";
+};
+
+&m25p80 {
+        status = "okay";
+};
+
+&pcie {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
+&usbotg {
+        status = "okay";
+};
+
+&usdhc1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
index cd20d0a948de..fad858c30fe9 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -16,7 +16,7 @@
         model = "Phytec phyFLEX-i.MX6 Quad";
         compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6q-pistachio.dts b/arch/arm/boot/dts/imx6q-pistachio.dts
index 1effb58f304c..bd57b3b74db7 100644
--- a/arch/arm/boot/dts/imx6q-pistachio.dts
+++ b/arch/arm/boot/dts/imx6q-pistachio.dts
@@ -56,7 +56,7 @@
                 stdout-path = &uart4;
         };
 
-        memory: memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-rex-pro.dts b/arch/arm/boot/dts/imx6q-rex-pro.dts
index 90ea61ae04e9..d6cae73b1927 100644
--- a/arch/arm/boot/dts/imx6q-rex-pro.dts
+++ b/arch/arm/boot/dts/imx6q-rex-pro.dts
@@ -16,7 +16,7 @@
         model = "Rex Pro i.MX6 Quad Board";
         compatible = "rex,imx6q-rex-pro", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/imx6q-sbc6x.dts
index 255733063ea4..b7aa2f0b9f53 100644
--- a/arch/arm/boot/dts/imx6q-sbc6x.dts
+++ b/arch/arm/boot/dts/imx6q-sbc6x.dts
@@ -12,7 +12,7 @@
         model = "MicroSys sbc6x board";
         compatible = "microsys,sbc6x", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts
index a3cd7afac20a..505cba776a2d 100644
--- a/arch/arm/boot/dts/imx6q-tbs2910.dts
+++ b/arch/arm/boot/dts/imx6q-tbs2910.dts
@@ -59,7 +59,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-ts4900.dts b/arch/arm/boot/dts/imx6q-ts4900.dts
index fab76f8cd076..e655107edc56 100644
--- a/arch/arm/boot/dts/imx6q-ts4900.dts
+++ b/arch/arm/boot/dts/imx6q-ts4900.dts
@@ -46,6 +46,11 @@
 / {
         model = "Technologic Systems i.MX6 Quad TS-4900 (Default Device Tree)";
         compatible = "technologic,imx6q-ts4900", "fsl,imx6q";
+
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
 };
 
 &sata {
diff --git a/arch/arm/boot/dts/imx6q-ts7970.dts b/arch/arm/boot/dts/imx6q-ts7970.dts
index f19e18995e68..c615ac4feede 100644
--- a/arch/arm/boot/dts/imx6q-ts7970.dts
+++ b/arch/arm/boot/dts/imx6q-ts7970.dts
@@ -47,6 +47,11 @@
 / {
         model = "Technologic Systems i.MX6 Quad TS-7970 (Default Device Tree)";
         compatible = "technologic,imx6q-ts7970", "fsl,imx6q";
+
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
 };
 
 &sata {
diff --git a/arch/arm/boot/dts/imx6q-wandboard-revb1.dts b/arch/arm/boot/dts/imx6q-wandboard-revb1.dts
index 9207d80f9cfb..b763352cddae 100644
--- a/arch/arm/boot/dts/imx6q-wandboard-revb1.dts
+++ b/arch/arm/boot/dts/imx6q-wandboard-revb1.dts
@@ -16,7 +16,7 @@
         model = "Wandboard i.MX6 Quad Board rev B1";
         compatible = "wand,imx6q-wandboard", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6q-wandboard-revd1.dts b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts
index e87ddb168669..8691fab21058 100644
--- a/arch/arm/boot/dts/imx6q-wandboard-revd1.dts
+++ b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts
@@ -16,7 +16,7 @@
         model = "Wandboard i.MX6 Quad Board revD1";
         compatible = "wand,imx6q-wandboard", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6q-wandboard.dts b/arch/arm/boot/dts/imx6q-wandboard.dts
index 4a8a6ee13e9f..2a3d98c1489a 100644
--- a/arch/arm/boot/dts/imx6q-wandboard.dts
+++ b/arch/arm/boot/dts/imx6q-wandboard.dts
@@ -16,7 +16,7 @@
         model = "Wandboard i.MX6 Quad Board";
         compatible = "wand,imx6q-wandboard", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6q-zii-rdu2.dts b/arch/arm/boot/dts/imx6q-zii-rdu2.dts
index 6be8a1eea895..7da6dde9c857 100644
--- a/arch/arm/boot/dts/imx6q-zii-rdu2.dts
+++ b/arch/arm/boot/dts/imx6q-zii-rdu2.dts
@@ -47,4 +47,9 @@
 / {
         model = "ZII RDU2 Board";
         compatible = "zii,imx6q-zii-rdu2", "fsl,imx6q";
+
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index bc581aa5cf17..ae7b3f107893 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -215,11 +215,6 @@
                 compatible = "fsl,imx-display-subsystem";
                 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
         };
-
-        gpu-subsystem {
-                compatible = "fsl,imx-gpu-subsystem";
-                cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
-        };
 };
 
 &gpio1 {
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 4e776e036cbc..8206683172d2 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -47,6 +47,11 @@
         model = "Toradex Apalis iMX6Q/D Module";
         compatible = "toradex,apalis_imx6q", "fsl,imx6q";
 
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
+
         backlight: backlight {
                 compatible = "pwm-backlight";
                 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index d1cfdc264126..9332a31e6c8b 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -42,6 +42,11 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
+
         ir_recv: ir-receiver {
                 compatible = "gpio-ir-receiver";
                 gpios = <&gpio3 9 1>;
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index dea8fc43c692..17a7b9c083d0 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -44,7 +44,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 363a44394dad..b8044681006c 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -59,7 +59,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index c75385c0cad0..629908fbaa32 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -59,7 +59,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index eab75f3dbaf3..a1a6fb5541e1 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -59,7 +59,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
index 30d4662d4480..4e21b3849394 100644
--- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
@@ -74,7 +74,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
index c67c10605070..81dae5b5bc87 100644
--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -51,7 +51,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
index 1a0faa1a14c8..c5d95e8d2e09 100644
--- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
@@ -80,7 +80,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
index d894dde6e85d..b5986efe1090 100644
--- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
@@ -288,6 +288,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 clocks = <&clks IMX6QDL_CLK_CKO>;
                 VDDA-supply = <&reg_1p8v>;
                 VDDIO-supply = <&reg_3p3v>;
diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
index 444425153fc7..368132274a91 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
@@ -83,7 +83,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
index fd4b68be9fe9..58124adfd65b 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
@@ -93,7 +93,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
index 92583238ca4a..7e20b47de839 100644
--- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
@@ -40,6 +40,11 @@
  */
 
 / {
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
+
         chosen {
                 stdout-path = &uart1;
         };
@@ -239,10 +244,9 @@
 
                 pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
                         /*
-                         * Similar to pinctrl_usbotg_2, but we want it
-                         * pulled down for a fixed host connection.
+                         * We want it pulled down for a fixed host connection.
                          */
-                        fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
+                        fsl,pins = <MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059>;
                 };
 
                 pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi
index dffbc92e0023..98241acb08a6 100644
--- a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi
@@ -40,6 +40,11 @@
  */
 
 / {
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
+
         chosen {
                 stdout-path = &uart1;
         };
@@ -191,6 +196,7 @@
         sgtl5000: codec@a {
                 clocks = <&clks IMX6QDL_CLK_CKO>;
                 compatible = "fsl,sgtl5000";
+                #sound-dai-cells = <0>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&pinctrl_hummingboard2_sgtl5000>;
                 reg = <0x0a>;
@@ -409,8 +415,7 @@
 
                 pinctrl_hummingboard2_usbotg_id: hummingboard2-usbotg-id {
                         /*
-                         * Similar to pinctrl_usbotg_2, but we want it
-                         * pulled down for a fixed host connection.
+                         * We want it pulled down for a fixed host connection.
                          */
                         fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
                 };
diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
index b6220d62f6de..acc3b11fba2a 100644
--- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
@@ -44,7 +44,7 @@
 #include <dt-bindings/sound/fsl-imx-audmux.h>
 
 / {
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
@@ -200,7 +200,11 @@
         status = "okay";
 
         mdio {
-                eth_phy: ethernet-phy {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                eth_phy: ethernet-phy@0 {
+                        reg = <0x0>;
                         rxc-skew-ps = <1140>;
                         txc-skew-ps = <1140>;
                         txen-skew-ps = <600>;
diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi
index a1b469c142f1..b3a463a5908b 100644
--- a/arch/arm/boot/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi
@@ -45,7 +45,7 @@
 #include <dt-bindings/sound/fsl-imx-audmux.h>
 
 / {
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
index 4cc4e23cf99c..aab088f318e8 100644
--- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
@@ -46,7 +46,7 @@
                 stdout-path = &uart2;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
index fd05f7caa472..87ca6ead4098 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
@@ -46,7 +46,7 @@
                 stdout-path = &uart2;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0xF0000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
index 40942d6b94b3..f5b763d39285 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
@@ -46,7 +46,7 @@
                 stdout-path = &uart2;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 919b6b7619a4..596866b0a0d2 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -48,7 +48,7 @@
                 stdout-path = &uart2;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
new file mode 100644
index 000000000000..9ebd438dce7d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
@@ -0,0 +1,390 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+
+/ {
+        aliases {
+                rtc0 = &i2c_rtc;
+        };
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <7>;
+                power-supply = <&reg_backlight>;
+                pwms = <&pwm1 0 5000000>;
+                status = "okay";
+        };
+
+        gpio_leds: leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpioleds>;
+                status = "disabled";
+
+                red {
+                        label = "phyboard-mira:red";
+                        gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
+                };
+
+                green {
+                        label = "phyboard-mira:green";
+                        gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>;
+                };
+
+                blue {
+                        label = "phyboard-mira:blue";
+                        gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "mmc0";
+                };
+        };
+
+        reg_backlight: regulator-backlight {
+                compatible = "regulator-fixed";
+                regulator-name = "backlight_3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        reg_en_switch: regulator-en-switch {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_en_switch>;
+                regulator-name = "Enable Switch";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                enable-active-high;
+                gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+                regulator-always-on;
+        };
+
+        reg_flexcan1: regulator-flexcan1 {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_flexcan1_en>;
+                regulator-name = "flexcan1-reg";
+                regulator-min-microvolt = <1500000>;
+                regulator-max-microvolt = <1500000>;
+                gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        reg_panel: regulator-panel {
+                compatible = "regulator-fixed";
+                regulator-name = "panel-power-supply";
+                regulator-min-microvolt = <12000000>;
+                regulator-max-microvolt = <12000000>;
+                regulator-always-on;
+        };
+
+        reg_pcie: regulator-pcie {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pcie_reg>;
+                regulator-name = "mPCIe_1V5";
+                regulator-min-microvolt = <1500000>;
+                regulator-max-microvolt = <1500000>;
+                gpio = <&gpio3 0 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        reg_usb_h1_vbus: usb-h1-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_usbh1_vbus>;
+                regulator-name = "usb_h1_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        reg_usbotg_vbus: usbotg-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_usbotg_vbus>;
+                regulator-name = "usb_otg_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        panel {
+                compatible = "auo,g104sn02";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_panel_en>;
+                power-supply = <&reg_panel>;
+                enable-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+                backlight = <&backlight>;
+
+                port {
+                        panel_in: endpoint {
+                                remote-endpoint = <&lvds0_out>;
+                        };
+                };
+        };
+};
+
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_flexcan1>;
+        xceiver-supply = <&reg_flexcan1>;
+        status = "disabled";
+};
+
+&hdmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hdmicec>;
+        ddc-i2c-bus = <&i2c2>;
+        status = "disabled";
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        clock-frequency = <400000>;
+        status = "disabled";
+
+        stmpe: touchctrl@44 {
+                compatible = "st,stmpe811";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_stmpe>;
+                reg = <0x44>;
+                interrupt-parent = <&gpio7>;
+                interrupts = <12 IRQ_TYPE_NONE>;
+                status = "disabled";
+
+                stmpe_touchscreen {
+                        compatible = "st,stmpe-ts";
+                        st,sample-time = <4>;
+                        st,mod-12b = <1>;
+                        st,ref-sel = <0>;
+                        st,adc-freq = <1>;
+                        st,ave-ctrl = <1>;
+                        st,touch-det-delay = <2>;
+                        st,settling = <2>;
+                        st,fraction-z = <7>;
+                        st,i-drive = <1>;
+                };
+        };
+
+        i2c_rtc: rtc@68 {
+                compatible = "microcrystal,rv4162";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_rtc_int>;
+                reg = <0x68>;
+                interrupt-parent = <&gpio7>;
+                interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+};
+
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        clock-frequency = <100000>;
+        status = "disabled";
+};
+
+&ldb {
+        status = "okay";
+
+        lvds-channel@0 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <24>;
+                status = "disabled";
+
+                port@4 {
+                        reg = <4>;
+
+                        lvds0_out: endpoint {
+                                remote-endpoint = <&panel_in>;
+                        };
+                };
+        };
+};
+
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>;
+        vpcie-supply = <&reg_pcie>;
+        status = "disabled";
+};
+
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
+        uart-has-rtscts;
+        status = "disabled";
+};
+
+&usbh1 {
+        vbus-supply = <&reg_usb_h1_vbus>;
+        disable-over-current;
+        status = "disabled";
+};
+
+&usbotg {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        vbus-supply = <&reg_usbotg_vbus>;
+        disable-over-current;
+        status = "disabled";
+};
+
+&usdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc1>;
+        cd-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>;
+        no-1-8-v;
+        status = "disabled";
+};
+
+&iomuxc {
+        pinctrl_panel_en: panelen1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_EB0__GPIO2_IO28          0xb0b1
+                >;
+        };
+
+        pinctrl_en_switch: enswitchgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_DA4__GPIO3_IO04          0xb0b1
+                >;
+        };
+
+        pinctrl_flexcan1: flexcan1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
+                        MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
+                >;
+        };
+
+        pinctrl_flexcan1_en: flexcan1engrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_A18__GPIO2_IO20          0xb0b1
+                >;
+        };
+
+        pinctrl_gpioleds: gpioledsgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22        0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23        0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24        0x1b0b0
+                >;
+        };
+
+        pinctrl_hdmicec: hdmicecgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE   0x1f8b0
+                >;
+        };
+
+        pinctrl_i2c2: i2c2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                >;
+        };
+
+        pinctrl_i2c1: i2c1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                        MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+                >;
+        };
+
+        pinctrl_pcie: pciegrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_OE__GPIO2_IO25           0xb0b1
+                >;
+        };
+
+        pinctrl_pcie_reg: pciereggrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_DA0__GPIO3_IO00          0xb0b1
+                >;
+        };
+
+        pinctrl_pwm1: pwm1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
+                >;
+        };
+
+        pinctrl_rtc_int: rtcintgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x1b0b0
+                >;
+        };
+
+        pinctrl_stmpe: stmpegrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
+                >;
+        };
+
+        pinctrl_uart2: uart2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
+                        MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
+                >;
+        };
+
+        pinctrl_uart3: uart3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_EB3__UART3_CTS_B         0x1b0b1
+                        MX6QDL_PAD_EIM_D23__UART3_RTS_B         0x1b0b1
+                        MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
+                        MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
+                >;
+        };
+
+        pinctrl_usbh1_vbus: usbh1vbusgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_A20__GPIO2_IO18          0xb0b1
+                >;
+        };
+
+        pinctrl_usbotg: usbotggrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                >;
+        };
+
+        pinctrl_usbotg_vbus: usbotgvbusgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_A19__GPIO2_IO19          0xb0b1
+                >;
+        };
+
+        pinctrl_usdhc1: usdhc1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD1_CMD__SD1_CMD             0x170f9
+                        MX6QDL_PAD_SD1_CLK__SD1_CLK             0x100f9
+                        MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x170f9
+                        MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x170f9
+                        MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x170f9
+                        MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x170f9
+                        MX6QDL_PAD_EIM_BCLK__GPIO6_IO31         0xb0b1  /* CD */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index d81b0078a100..c58f3443d55d 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -15,7 +15,7 @@
         model = "Phytec phyFLEX-i.MX6 Quad";
         compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
new file mode 100644
index 000000000000..6486df3e2942
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -0,0 +1,279 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        aliases {
+                rtc1 = &da9062_rtc;
+                rtc2 = &snvs_rtc;
+        };
+
+        /*
+         * Set the minimum memory size here and
+         * let the bootloader set the real size.
+         */
+        memory@10000000 {
+                device_type = "memory";
+                reg = <0x10000000 0x8000000>;
+        };
+
+        gpio_leds_som: somleds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpioleds_som>;
+
+                som-led-green {
+                        label = "phycore:green";
+                        gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
+
+&ecspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1>;
+        cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+        status = "okay";
+
+        m25p80: flash@0 {
+                compatible = "jedec,spi-nor";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+                status = "disabled";
+        };
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-handle = <&ethphy>;
+        phy-mode = "rgmii";
+        phy-supply = <&vdd_eth_io>;
+        phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+        status = "disabled";
+
+        mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ethphy: ethernet-phy@3 {
+                        reg = <3>;
+                        txc-skew-ps = <1680>;
+                        rxc-skew-ps = <1860>;
+                };
+        };
+};
+
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        nand-on-flash-bbt;
+        status = "disabled";
+};
+
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        clock-frequency = <400000>;
+        status = "okay";
+
+        eeprom@50 {
+                compatible = "atmel,24c32";
+                reg = <0x50>;
+        };
+
+        pmic@58 {
+                compatible = "dlg,da9062";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pmic>;
+                reg = <0x58>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                interrupt-controller;
+
+                da9062_rtc: rtc {
+                        compatible = "dlg,da9062-rtc";
+                };
+
+                watchdog {
+                        compatible = "dlg,da9062-watchdog";
+                };
+
+                regulators {
+                        vdd_arm: buck1 {
+                                regulator-name = "vdd_arm";
+                                regulator-min-microvolt = <730000>;
+                                regulator-max-microvolt = <1380000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_soc: buck2 {
+                                regulator-name = "vdd_soc";
+                                regulator-min-microvolt = <730000>;
+                                regulator-max-microvolt = <1380000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_ddr3_1p5: buck3 {
+                                regulator-name = "vdd_ddr3";
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_eth_1p2: buck4 {
+                                regulator-name = "vdd_eth";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_snvs: ldo1 {
+                                regulator-name = "vdd_snvs";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_high: ldo2 {
+                                regulator-name = "vdd_high";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_eth_io: ldo3 {
+                                regulator-name = "vdd_eth_io";
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <2500000>;
+                        };
+
+                        vdd_emmc_1p8: ldo4 {
+                                regulator-name = "vdd_emmc";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+                };
+        };
+};
+
+&reg_arm {
+        vin-supply = <&vdd_arm>;
+};
+
+&reg_pu {
+        vin-supply = <&vdd_soc>;
+};
+
+&reg_soc {
+        vin-supply = <&vdd_soc>;
+};
+
+&snvs_poweroff {
+        status = "okay";
+};
+
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        bus-width = <8>;
+        non-removable;
+        vmmc-supply = <&vdd_emmc_1p8>;
+        status = "disabled";
+};
+
+&iomuxc {
+        pinctrl_enet: enetgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                        MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                        MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                        MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                        MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                        MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                        MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                        MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                        MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                        MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                        MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                        MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                        MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                        MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                        MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                        MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
+                        MX6QDL_PAD_SD2_DAT1__GPIO1_IO14         0x1b0b0
+                >;
+        };
+
+        pinctrl_gpioleds_som: gpioledssomgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0
+                >;
+        };
+
+        pinctrl_gpmi_nand: gpminandgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
+                        MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
+                        MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
+                        MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
+                        MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
+                        MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
+                        MX6QDL_PAD_NANDF_CS2__NAND_CE2_B        0xb0b1
+                        MX6QDL_PAD_NANDF_CS3__NAND_CE3_B        0xb0b1
+                        MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
+                        MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
+                        MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
+                        MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
+                        MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
+                        MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
+                        MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
+                        MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
+                        MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
+                        MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
+                        MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
+                >;
+        };
+
+        pinctrl_i2c3: i2c3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
+                        MX6QDL_PAD_GPIO_5__I2C3_SCL             0x4001b8b1
+                >;
+        };
+
+        pinctrl_ecspi1: ecspi1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
+                        MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
+                        MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
+                        MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x1b0b0
+                >;
+        };
+
+        pinctrl_pmic: pmicgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
+                >;
+        };
+
+        pinctrl_usdhc4: usdhc4grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
+                        MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
+                        MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
+                        MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
+                        MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
+                        MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
+                        MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
+                        MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
+                        MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
+                        MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi
index 6e9549ff11da..039e3b8306c4 100644
--- a/arch/arm/boot/dts/imx6qdl-rex.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi
@@ -137,7 +137,7 @@
         status = "okay";
 
         eeprom@57 {
-                compatible = "at,24c02";
+                compatible = "atmel,24c02";
                 reg = <0x57>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 82d6ccb46982..54b0139e978d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -13,7 +13,7 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 35de7adc997b..18b65052553d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -49,7 +49,7 @@
                 stdout-path = &uart2;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 0a50705b9c18..f019f9900369 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -19,7 +19,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
index 6abb66cd7d4a..f015e2d1cf35 100644
--- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
@@ -61,8 +61,8 @@
                 sdhc1 = &usdhc2;
         };
 
-        memory {
-                reg = <0 0>; /* will be filled by U-Boot */
+        memory@10000000 {
+                reg = <0x10000000 0>; /* will be filled by U-Boot */
         };
 
         clocks {
diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
index 4161b7d4323a..906387915dc5 100644
--- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
@@ -35,7 +35,7 @@
                 pinctrl-names = "default";
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi
index 421d6f527609..38080c1dfaec 100644
--- a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi
@@ -10,7 +10,7 @@
 #include <dt-bindings/sound/fsl-imx-audmux.h>
 
 / {
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
index 72f52fcecee1..911f7f0e3cea 100644
--- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
@@ -305,6 +305,15 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart4>;
         status = "okay";
+
+        rave-sp {
+                compatible = "zii,rave-sp-rdu2";
+                current-speed = <1000000>;
+
+                watchdog {
+                        compatible = "zii,rave-sp-watchdog";
+                };
+        };
 };
 
 &ecspi1 {
@@ -498,7 +507,7 @@
         };
 
         eeprom@54 {
-                compatible = "at,24c128";
+                compatible = "atmel,24c128";
                 reg = <0x54>;
         };
 
@@ -602,6 +611,8 @@
         wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
         vmmc-supply = <&reg_3p3v_sd>;
         vqmmc-supply = <&reg_3p3v>;
+        no-1-8-v;
+        no-sdio;
         status = "okay";
 };
 
@@ -613,6 +624,8 @@
         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
         vmmc-supply = <&reg_3p3v_sd>;
         vqmmc-supply = <&reg_3p3v>;
+        no-1-8-v;
+        no-sdio;
         status = "okay";
 };
 
@@ -622,7 +635,10 @@
         bus-width = <8>;
         vmmc-supply = <&reg_3p3v>;
         vqmmc-supply = <&reg_3p3v>;
+        no-1-8-v;
         non-removable;
+        no-sdio;
+        no-sd;
         status = "okay";
 };
 
@@ -805,6 +821,10 @@
         };
 };
 
+&wdog1 {
+        status = "disabled";
+};
+
 &iomuxc {
         pinctrl_accel: accelgrp {
                 fsl,pins = <
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 59ff86695a14..c003e62bf290 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -23,7 +23,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec;
@@ -143,7 +143,7 @@
                 };
         };
 
-        pmu {
+        pmu: pmu {
                 compatible = "arm,cortex-a9-pmu";
                 interrupt-parent = <&gpc>;
                 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
new file mode 100644
index 000000000000..3618e5316bf4
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
+ */
+
+/dts-v1/;
+#include "imx6qp.dtsi"
+#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-mira.dtsi"
+
+/ {
+        model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND";
+        compatible = "phytec,imx6qp-pbac06-nand", "phytec,imx6qp-pbac06",
+                     "phytec,imx6qdl-pcm058", "fsl,imx6qp";
+
+        chosen {
+                linux,stdout-path = &uart2;
+        };
+};
+
+&can1 {
+        status = "okay";
+};
+
+&fec {
+        status = "okay";
+};
+
+&gpmi {
+        status = "okay";
+};
+
+&hdmi {
+        status = "okay";
+};
+
+&i2c1 {
+        status = "okay";
+};
+
+&i2c2 {
+        status = "okay";
+};
+
+&i2c_rtc {
+        status = "okay";
+};
+
+&m25p80 {
+        status = "okay";
+};
+
+&pcie {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
+&usbotg {
+        status = "okay";
+};
+
+&usdhc1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts
index f7badd82ce8a..907ba0c74ba6 100644
--- a/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts
+++ b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts
@@ -16,7 +16,7 @@
         model = "Wandboard i.MX6 QuadPlus Board revD1";
         compatible = "wand,imx6qp-wandboard", "fsl,imx6qp";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts
index 547a76677ab3..de5b50df833c 100644
--- a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts
+++ b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts
@@ -47,4 +47,9 @@
 / {
         model = "ZII RDU2+ Board";
         compatible = "zii,imx6qp-zii-rdu2", "fsl,imx6qp";
+
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 2844ab541759..37e792fdc160 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -16,7 +16,7 @@
         model = "Freescale i.MX6 SoloLite EVK Board";
         compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts
index 72c7745f51d3..404e602e6781 100644
--- a/arch/arm/boot/dts/imx6sl-warp.dts
+++ b/arch/arm/boot/dts/imx6sl-warp.dts
@@ -54,7 +54,7 @@
         model = "WaRP Board";
         compatible = "warp,imx6sl-warp", "fsl,imx6sl";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index ae8df3cf687e..ab6a7e2e7e8f 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -21,7 +21,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
index f9d40ee14982..b58f770c40d9 100644
--- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
+++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
@@ -52,7 +52,7 @@
                 t_lcd = &t_lcd;
         };
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 240a2864d044..72da5acf35a2 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -14,7 +14,7 @@
         model = "Freescale i.MX6 SoloX Sabre Auto Board";
         compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index d35aa858f9db..f8f31872fa14 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -20,7 +20,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
index 4d8c6521845f..252175b59247 100644
--- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
+++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
@@ -20,7 +20,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts
index 0c1fc1a8f913..40ccdf43dffc 100644
--- a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts
@@ -48,7 +48,7 @@
         model = "UDOO Neo Basic";
         compatible = "udoo,neobasic", "fsl,imx6sx";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x20000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts
index 5d6c2274ee2b..42bfc8f8f7f6 100644
--- a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts
@@ -48,7 +48,7 @@
         model = "UDOO Neo Extended";
         compatible = "udoo,neoextended", "fsl,imx6sx";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts
index 653ceb29e28b..c84c877f09d4 100644
--- a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts
@@ -48,7 +48,7 @@
         model = "UDOO Neo Full";
         compatible = "udoo,neofull", "fsl,imx6sx";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index fd7879342d0d..49c7205b8db8 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -22,7 +22,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 can0 = &flexcan1;
@@ -188,6 +188,7 @@
                                  <&clks IMX6SX_CLK_GPU>,
                                  <&clks IMX6SX_CLK_GPU>;
                         clock-names = "bus", "core", "shader";
+                        power-domains = <&pd_pu>;
                 };
 
                 dma_apbh: dma-apbh@1804000 {
@@ -767,6 +768,18 @@
                                         #address-cells = <1>;
                                         #size-cells = <0>;
 
+                                        power-domain@0 {
+                                                reg = <0>;
+                                                #power-domain-cells = <0>;
+                                        };
+
+                                        pd_pu: power-domain@1 {
+                                                reg = <1>;
+                                                #power-domain-cells = <0>;
+                                                power-supply = <&reg_soc>;
+                                                clocks = <&clks IMX6SX_CLK_GPU>;
+                                        };
+
                                         pd_pci: power-domain@3 {
                                                 reg = <3>;
                                                 #power-domain-cells = <0>;
@@ -1355,9 +1368,4 @@
                         status = "disabled";
                 };
         };
-
-        gpu-subsystem {
-                compatible = "fsl,imx-gpu-subsystem";
-                cores = <&gpu>;
-        };
 };
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
index 18fdb088ba1e..6d720b20e7ed 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
@@ -9,487 +9,9 @@
 /dts-v1/;
 
 #include "imx6ul.dtsi"
+#include "imx6ul-14x14-evk.dtsi"
 
 / {
         model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
         compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
-
-        chosen {
-                stdout-path = &uart1;
-        };
-
-        memory {
-                reg = <0x80000000 0x20000000>;
-        };
-
-        backlight_display: backlight-display {
-                compatible = "pwm-backlight";
-                pwms = <&pwm1 0 5000000>;
-                brightness-levels = <0 4 8 16 32 64 128 255>;
-                default-brightness-level = <6>;
-                status = "okay";
-        };
-
-
-        reg_sd1_vmmc: regulator-sd1-vmmc {
-                compatible = "regulator-fixed";
-                regulator-name = "VSD_3V3";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
-                enable-active-high;
-        };
-
-        sound {
-                compatible = "simple-audio-card";
-                simple-audio-card,name = "mx6ul-wm8960";
-                simple-audio-card,format = "i2s";
-                simple-audio-card,bitclock-master = <&dailink_master>;
-                simple-audio-card,frame-master = <&dailink_master>;
-                simple-audio-card,widgets =
-                        "Microphone", "Mic Jack",
-                        "Line", "Line In",
-                        "Line", "Line Out",
-                        "Speaker", "Speaker",
-                        "Headphone", "Headphone Jack";
-                simple-audio-card,routing =
-                        "Headphone Jack", "HP_L",
-                        "Headphone Jack", "HP_R",
-                        "Speaker", "SPK_LP",
-                        "Speaker", "SPK_LN",
-                        "Speaker", "SPK_RP",
-                        "Speaker", "SPK_RN",
-                        "LINPUT1", "Mic Jack",
-                        "LINPUT3", "Mic Jack",
-                        "RINPUT1", "Mic Jack",
-                        "RINPUT2", "Mic Jack";
-
-                simple-audio-card,cpu {
-                        sound-dai = <&sai2>;
-                };
-
-                dailink_master: simple-audio-card,codec {
-                        sound-dai = <&codec>;
-                        clocks = <&clks IMX6UL_CLK_SAI2>;
-                };
-        };
-
-        panel {
-                compatible = "innolux,at043tn24";
-                backlight = <&backlight_display>;
-
-                port {
-                        panel_in: endpoint {
-                                remote-endpoint = <&display_out>;
-                        };
-                };
-        };
-};
-
-&clks {
-        assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
-        assigned-clock-rates = <786432000>;
-};
-
-&i2c2 {
-        clock_frequency = <100000>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c2>;
-        status = "okay";
-
-        codec: wm8960@1a {
-                #sound-dai-cells = <0>;
-                compatible = "wlf,wm8960";
-                reg = <0x1a>;
-                wlf,shared-lrclk;
-        };
-};
-
-&fec1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet1>;
-        phy-mode = "rmii";
-        phy-handle = <&ethphy0>;
-        status = "okay";
-};
-
-&fec2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet2>;
-        phy-mode = "rmii";
-        phy-handle = <&ethphy1>;
-        status = "okay";
-
-        mdio {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                ethphy0: ethernet-phy@2 {
-                        reg = <2>;
-                        micrel,led-mode = <1>;
-                        clocks = <&clks IMX6UL_CLK_ENET_REF>;
-                        clock-names = "rmii-ref";
-                };
-
-                ethphy1: ethernet-phy@1 {
-                        reg = <1>;
-                        micrel,led-mode = <1>;
-                        clocks = <&clks IMX6UL_CLK_ENET2_REF>;
-                        clock-names = "rmii-ref";
-                };
-        };
-};
-
-
-&lcdif {
-        assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
-        assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_lcdif_dat
-                     &pinctrl_lcdif_ctrl>;
-        status = "okay";
-
-        port {
-                display_out: endpoint {
-                        remote-endpoint = <&panel_in>;
-                };
-        };
-};
-
-&pwm1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_pwm1>;
-        status = "okay";
-};
-
-&qspi {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_qspi>;
-        status = "okay";
-
-        flash0: n25q256a@0 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "micron,n25q256a";
-                spi-max-frequency = <29000000>;
-                reg = <0>;
-        };
-};
-
-&sai2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_sai2>;
-        assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
-                          <&clks IMX6UL_CLK_SAI2>;
-        assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
-        assigned-clock-rates = <0>, <12288000>;
-        fsl,sai-mclk-direction-output;
-        status = "okay";
-};
-
-&snvs_poweroff {
-        status = "okay";
-};
-
-&tsc {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_tsc>;
-        xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
-        measure-delay-time = <0xffff>;
-        pre-charge-time = <0xfff>;
-        status = "okay";
-};
-
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1>;
-        status = "okay";
-};
-
-&uart2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2>;
-        uart-has-rtscts;
-        status = "okay";
-};
-
-&usbotg1 {
-        dr_mode = "otg";
-        status = "okay";
-};
-
-&usbotg2 {
-        dr_mode = "host";
-        disable-over-current;
-        status = "okay";
-};
-
-&usbphy1 {
-        fsl,tx-d-cal = <106>;
-};
-
-&usbphy2 {
-        fsl,tx-d-cal = <106>;
-};
-
-&usdhc1 {
-        pinctrl-names = "default", "state_100mhz", "state_200mhz";
-        pinctrl-0 = <&pinctrl_usdhc1>;
-        pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
-        pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
-        cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
-        keep-power-in-suspend;
-        wakeup-source;
-        vmmc-supply = <&reg_sd1_vmmc>;
-        status = "okay";
-};
-
-&usdhc2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc2>;
-        no-1-8-v;
-        keep-power-in-suspend;
-        wakeup-source;
-        status = "okay";
-};
-
-&wdog1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_wdog>;
-        fsl,ext-reset-output;
-};
-
-&iomuxc {
-        pinctrl-names = "default";
-
-        pinctrl_csi1: csi1grp {
-                fsl,pins = <
-                        MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
-                        MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
-                        MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
-                        MX6UL_PAD_CSI_HSYNC__CSI_HSYNC          0x1b088
-                        MX6UL_PAD_CSI_DATA00__CSI_DATA02        0x1b088
-                        MX6UL_PAD_CSI_DATA01__CSI_DATA03        0x1b088
-                        MX6UL_PAD_CSI_DATA02__CSI_DATA04        0x1b088
-                        MX6UL_PAD_CSI_DATA03__CSI_DATA05        0x1b088
-                        MX6UL_PAD_CSI_DATA04__CSI_DATA06        0x1b088
-                        MX6UL_PAD_CSI_DATA05__CSI_DATA07        0x1b088
-                        MX6UL_PAD_CSI_DATA06__CSI_DATA08        0x1b088
-                        MX6UL_PAD_CSI_DATA07__CSI_DATA09        0x1b088
-                >;
-        };
-
-        pinctrl_enet1: enet1grp {
-                fsl,pins = <
-                        MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
-                        MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
-                        MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
-                        MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
-                        MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
-                        MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
-                        MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
-                        MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
-                >;
-        };
-
-        pinctrl_enet2: enet2grp {
-                fsl,pins = <
-                        MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
-                        MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
-                        MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
-                        MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
-                        MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
-                        MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
-                        MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
-                        MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
-                        MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
-                        MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
-                >;
-        };
-
-        pinctrl_flexcan1: flexcan1grp{
-                fsl,pins = <
-                        MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
-                        MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
-                >;
-        };
-
-        pinctrl_flexcan2: flexcan2grp{
-                fsl,pins = <
-                        MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
-                        MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
-                >;
-        };
-
-        pinctrl_i2c1: i2c1grp {
-                fsl,pins = <
-                        MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
-                        MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
-                >;
-        };
-
-        pinctrl_i2c2: i2c2grp {
-                fsl,pins = <
-                        MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
-                        MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
-                >;
-        };
-
-        pinctrl_lcdif_dat: lcdifdatgrp {
-                fsl,pins = <
-                        MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
-                        MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
-                        MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
-                        MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
-                        MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
-                        MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
-                        MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
-                        MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
-                        MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
-                        MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
-                        MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
-                        MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
-                        MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
-                        MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
-                        MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
-                        MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
-                        MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
-                        MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
-                        MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
-                        MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
-                        MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
-                        MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
-                        MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
-                        MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
-                >;
-        };
-
-        pinctrl_lcdif_ctrl: lcdifctrlgrp {
-                fsl,pins = <
-                        MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
-                        MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
-                        MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
-                        MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
-                        /* used for lcd reset */
-                        MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
-                >;
-        };
-
-        pinctrl_qspi: qspigrp {
-                fsl,pins = <
-                        MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
-                        MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
-                        MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
-                        MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
-                        MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
-                        MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
-                >;
-        };
-
-        pinctrl_sai2: sai2grp {
-                fsl,pins = <
-                        MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
-                        MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
-                        MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x11088
-                        MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x11088
-                        MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x17088
-                        MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x17059
-                >;
-        };
-
-        pinctrl_pwm1: pwm1grp {
-                fsl,pins = <
-                        MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
-                >;
-        };
-
-        pinctrl_sim2: sim2grp {
-                fsl,pins = <
-                        MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD             0xb808
-                        MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK            0x31
-                        MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0xb808
-                        MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN           0xb808
-                        MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD           0xb809
-                        MX6UL_PAD_CSI_DATA02__GPIO4_IO23                0x3008
-                >;
-        };
-
-        pinctrl_tsc: tscgrp {
-                fsl,pins = <
-                        MX6UL_PAD_GPIO1_IO01__GPIO1_IO01                0xb0
-                        MX6UL_PAD_GPIO1_IO02__GPIO1_IO02                0xb0
-                        MX6UL_PAD_GPIO1_IO03__GPIO1_IO03                0xb0
-                        MX6UL_PAD_GPIO1_IO04__GPIO1_IO04                0xb0
-                >;
-        };
-
-        pinctrl_uart1: uart1grp {
-                fsl,pins = <
-                        MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
-                        MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
-                >;
-        };
-
-        pinctrl_uart2: uart2grp {
-                fsl,pins = <
-                        MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
-                        MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
-                        MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
-                        MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
-                >;
-        };
-
-        pinctrl_usdhc1: usdhc1grp {
-                fsl,pins = <
-                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
-                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
-                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
-                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
-                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
-                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
-                        MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
-                        MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
-                        MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
-                >;
-        };
-
-        pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
-                fsl,pins = <
-                        MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
-                        MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
-                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
-                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
-                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
-                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
-
-                >;
-        };
-
-        pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
-                fsl,pins = <
-                        MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
-                        MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
-                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
-                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
-                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
-                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
-                >;
-        };
-
-        pinctrl_usdhc2: usdhc2grp {
-                fsl,pins = <
-                        MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
-                        MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
-                        MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
-                        MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
-                        MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
-                        MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
-                >;
-        };
-
-        pinctrl_wdog: wdoggrp {
-                fsl,pins = <
-                        MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
-                >;
-        };
 };
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
new file mode 100644
index 000000000000..32a07232c034
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
@@ -0,0 +1,499 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+        chosen {
+                stdout-path = &uart1;
+        };
+
+        memory@80000000 {
+                reg = <0x80000000 0x20000000>;
+        };
+
+        backlight_display: backlight-display {
+                compatible = "pwm-backlight";
+                pwms = <&pwm1 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+                status = "okay";
+        };
+
+
+        reg_sd1_vmmc: regulator-sd1-vmmc {
+                compatible = "regulator-fixed";
+                regulator-name = "VSD_3V3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "mx6ul-wm8960";
+                simple-audio-card,format = "i2s";
+                simple-audio-card,bitclock-master = <&dailink_master>;
+                simple-audio-card,frame-master = <&dailink_master>;
+                simple-audio-card,widgets =
+                        "Microphone", "Mic Jack",
+                        "Line", "Line In",
+                        "Line", "Line Out",
+                        "Speaker", "Speaker",
+                        "Headphone", "Headphone Jack";
+                simple-audio-card,routing =
+                        "Headphone Jack", "HP_L",
+                        "Headphone Jack", "HP_R",
+                        "Speaker", "SPK_LP",
+                        "Speaker", "SPK_LN",
+                        "Speaker", "SPK_RP",
+                        "Speaker", "SPK_RN",
+                        "LINPUT1", "Mic Jack",
+                        "LINPUT3", "Mic Jack",
+                        "RINPUT1", "Mic Jack",
+                        "RINPUT2", "Mic Jack";
+
+                simple-audio-card,cpu {
+                        sound-dai = <&sai2>;
+                };
+
+                dailink_master: simple-audio-card,codec {
+                        sound-dai = <&codec>;
+                        clocks = <&clks IMX6UL_CLK_SAI2>;
+                };
+        };
+
+        panel {
+                compatible = "innolux,at043tn24";
+                backlight = <&backlight_display>;
+
+                port {
+                        panel_in: endpoint {
+                                remote-endpoint = <&display_out>;
+                        };
+                };
+        };
+};
+
+&clks {
+        assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+        assigned-clock-rates = <786432000>;
+};
+
+&i2c2 {
+        clock_frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+
+        codec: wm8960@1a {
+                #sound-dai-cells = <0>;
+                compatible = "wlf,wm8960";
+                reg = <0x1a>;
+                wlf,shared-lrclk;
+        };
+};
+
+&fec1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet1>;
+        phy-mode = "rmii";
+        phy-handle = <&ethphy0>;
+        status = "okay";
+};
+
+&fec2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet2>;
+        phy-mode = "rmii";
+        phy-handle = <&ethphy1>;
+        status = "okay";
+
+        mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ethphy0: ethernet-phy@2 {
+                        reg = <2>;
+                        micrel,led-mode = <1>;
+                        clocks = <&clks IMX6UL_CLK_ENET_REF>;
+                        clock-names = "rmii-ref";
+                };
+
+                ethphy1: ethernet-phy@1 {
+                        reg = <1>;
+                        micrel,led-mode = <1>;
+                        clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+                        clock-names = "rmii-ref";
+                };
+        };
+};
+
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+
+        mag3110@e {
+                compatible = "fsl,mag3110";
+                reg = <0x0e>;
+        };
+};
+
+&lcdif {
+        assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
+        assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcdif_dat
+                     &pinctrl_lcdif_ctrl>;
+        status = "okay";
+
+        port {
+                display_out: endpoint {
+                        remote-endpoint = <&panel_in>;
+                };
+        };
+};
+
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+        status = "okay";
+};
+
+&qspi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_qspi>;
+        status = "okay";
+
+        flash0: n25q256a@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "micron,n25q256a";
+                spi-max-frequency = <29000000>;
+                reg = <0>;
+        };
+};
+
+&sai2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_sai2>;
+        assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
+                          <&clks IMX6UL_CLK_SAI2>;
+        assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+        assigned-clock-rates = <0>, <12288000>;
+        fsl,sai-mclk-direction-output;
+        status = "okay";
+};
+
+&snvs_poweroff {
+        status = "okay";
+};
+
+&tsc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_tsc>;
+        xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+        measure-delay-time = <0xffff>;
+        pre-charge-time = <0xfff>;
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        uart-has-rtscts;
+        status = "okay";
+};
+
+&usbotg1 {
+        dr_mode = "otg";
+        status = "okay";
+};
+
+&usbotg2 {
+        dr_mode = "host";
+        disable-over-current;
+        status = "okay";
+};
+
+&usbphy1 {
+        fsl,tx-d-cal = <106>;
+};
+
+&usbphy2 {
+        fsl,tx-d-cal = <106>;
+};
+
+&usdhc1 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc1>;
+        pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+        cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+        keep-power-in-suspend;
+        wakeup-source;
+        vmmc-supply = <&reg_sd1_vmmc>;
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        no-1-8-v;
+        keep-power-in-suspend;
+        wakeup-source;
+        status = "okay";
+};
+
+&wdog1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_wdog>;
+        fsl,ext-reset-output;
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+
+        pinctrl_csi1: csi1grp {
+                fsl,pins = <
+                        MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
+                        MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
+                        MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
+                        MX6UL_PAD_CSI_HSYNC__CSI_HSYNC          0x1b088
+                        MX6UL_PAD_CSI_DATA00__CSI_DATA02        0x1b088
+                        MX6UL_PAD_CSI_DATA01__CSI_DATA03        0x1b088
+                        MX6UL_PAD_CSI_DATA02__CSI_DATA04        0x1b088
+                        MX6UL_PAD_CSI_DATA03__CSI_DATA05        0x1b088
+                        MX6UL_PAD_CSI_DATA04__CSI_DATA06        0x1b088
+                        MX6UL_PAD_CSI_DATA05__CSI_DATA07        0x1b088
+                        MX6UL_PAD_CSI_DATA06__CSI_DATA08        0x1b088
+                        MX6UL_PAD_CSI_DATA07__CSI_DATA09        0x1b088
+                >;
+        };
+
+        pinctrl_enet1: enet1grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
+                        MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
+                        MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+                        MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+                        MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
+                        MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+                        MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+                        MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
+                >;
+        };
+
+        pinctrl_enet2: enet2grp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
+                        MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
+                        MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
+                        MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
+                        MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+                        MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+                        MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
+                        MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+                        MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+                        MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
+                >;
+        };
+
+        pinctrl_flexcan1: flexcan1grp{
+                fsl,pins = <
+                        MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
+                        MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
+                >;
+        };
+
+        pinctrl_flexcan2: flexcan2grp{
+                fsl,pins = <
+                        MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
+                        MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
+                >;
+        };
+
+        pinctrl_i2c1: i2c1grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+                        MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+                >;
+        };
+
+        pinctrl_i2c2: i2c2grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+                        MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+                >;
+        };
+
+        pinctrl_lcdif_dat: lcdifdatgrp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
+                        MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
+                        MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
+                        MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
+                        MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
+                        MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
+                        MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
+                        MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
+                        MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
+                        MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
+                        MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
+                        MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
+                        MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
+                        MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
+                        MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
+                        MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
+                        MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
+                        MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
+                        MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
+                        MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
+                        MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
+                        MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
+                        MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
+                        MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
+                >;
+        };
+
+        pinctrl_lcdif_ctrl: lcdifctrlgrp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
+                        MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
+                        MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
+                        MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
+                        /* used for lcd reset */
+                        MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
+                >;
+        };
+
+        pinctrl_qspi: qspigrp {
+                fsl,pins = <
+                        MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
+                        MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
+                        MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
+                        MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
+                        MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
+                        MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
+                >;
+        };
+
+        pinctrl_sai2: sai2grp {
+                fsl,pins = <
+                        MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
+                        MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
+                        MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x11088
+                        MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x11088
+                        MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x17088
+                        MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x17059
+                >;
+        };
+
+        pinctrl_pwm1: pwm1grp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
+                >;
+        };
+
+        pinctrl_sim2: sim2grp {
+                fsl,pins = <
+                        MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD             0xb808
+                        MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK            0x31
+                        MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0xb808
+                        MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN           0xb808
+                        MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD           0xb809
+                        MX6UL_PAD_CSI_DATA02__GPIO4_IO23                0x3008
+                >;
+        };
+
+        pinctrl_tsc: tscgrp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO01__GPIO1_IO01                0xb0
+                        MX6UL_PAD_GPIO1_IO02__GPIO1_IO02                0xb0
+                        MX6UL_PAD_GPIO1_IO03__GPIO1_IO03                0xb0
+                        MX6UL_PAD_GPIO1_IO04__GPIO1_IO04                0xb0
+                >;
+        };
+
+        pinctrl_uart1: uart1grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+                        MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+                >;
+        };
+
+        pinctrl_uart2: uart2grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
+                        MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
+                        MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
+                        MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
+                >;
+        };
+
+        pinctrl_usdhc1: usdhc1grp {
+                fsl,pins = <
+                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
+                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
+                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
+                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
+                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
+                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
+                        MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
+                        MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
+                        MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
+                >;
+        };
+
+        pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+                fsl,pins = <
+                        MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
+                        MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
+                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+
+                >;
+        };
+
+        pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+                fsl,pins = <
+                        MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
+                        MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
+                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+                >;
+        };
+
+        pinctrl_usdhc2: usdhc2grp {
+                fsl,pins = <
+                        MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
+                        MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+                        MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+                        MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+                        MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+                        MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+                >;
+        };
+
+        pinctrl_wdog: wdoggrp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6ul-geam.dts b/arch/arm/boot/dts/imx6ul-geam.dts
index 571eea7f1c6b..d81d20f8fc8d 100644
--- a/arch/arm/boot/dts/imx6ul-geam.dts
+++ b/arch/arm/boot/dts/imx6ul-geam.dts
@@ -50,7 +50,7 @@
         model = "Engicam GEAM6UL Starter Kit";
         compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x08000000>;
         };
 
@@ -181,6 +181,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 clocks = <&clks IMX6UL_CLK_OSC>;
                 clock-names = "mclk";
                 VDDA-supply = <&reg_3p3v>;
diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi
index 950fb28b630a..b0ecebb512b3 100644
--- a/arch/arm/boot/dts/imx6ul-isiot.dtsi
+++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi
@@ -45,7 +45,7 @@
 #include "imx6ul.dtsi"
 
 / {
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6ul-litesom.dtsi b/arch/arm/boot/dts/imx6ul-litesom.dtsi
index 039721d3dcb4..8f775f6974d1 100644
--- a/arch/arm/boot/dts/imx6ul-litesom.dtsi
+++ b/arch/arm/boot/dts/imx6ul-litesom.dtsi
@@ -47,7 +47,7 @@
         model = "Grinn i.MX6UL liteSOM";
         compatible = "grinn,imx6ul-litesom", "fsl,imx6ul";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x20000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
index aec5ccce0321..a031bee311df 100644
--- a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
@@ -48,7 +48,7 @@
 #include "imx6ul.dtsi"
 
 / {
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0>; /* will be filled by U-Boot */
         };
 
diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts
index 3bf26ebd4df9..47682b8c023c 100644
--- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts
+++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts
@@ -51,7 +51,7 @@
         model = "Technexion Pico i.MX6UL Board";
         compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x10000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6ul-pinfunc.h b/arch/arm/boot/dts/imx6ul-pinfunc.h
index 0034eeb84542..7b9a4dc38456 100644
--- a/arch/arm/boot/dts/imx6ul-pinfunc.h
+++ b/arch/arm/boot/dts/imx6ul-pinfunc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2014 - 2015 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -34,14 +34,14 @@
 #define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M           0x0044 0x02d0 0x0000 3 0
 #define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY                0x0044 0x02d0 0x04c0 4 0
 #define MX6UL_PAD_JTAG_MOD__GPIO1_IO10                  0x0044 0x02d0 0x0000 5 0
-#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00            0x0044 0x02d0 0x0000 6 0
+#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00            0x0044 0x02d0 0x0610 6 0
 #define MX6UL_PAD_JTAG_TMS__SJC_TMS                     0x0048 0x02d4 0x0000 0 0
 #define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1               0x0048 0x02d4 0x0598 1 0
-#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK                   0x0048 0x02d4 0x0000 2 0
+#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK                   0x0048 0x02d4 0x05f0 2 0
 #define MX6UL_PAD_JTAG_TMS__CCM_CLKO1                   0x0048 0x02d4 0x0000 3 0
 #define MX6UL_PAD_JTAG_TMS__CCM_WAIT                    0x0048 0x02d4 0x0000 4 0
 #define MX6UL_PAD_JTAG_TMS__GPIO1_IO11                  0x0048 0x02d4 0x0000 5 0
-#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01            0x0048 0x02d4 0x0000 6 0
+#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01            0x0048 0x02d4 0x0614 6 0
 #define MX6UL_PAD_JTAG_TMS__EPIT1_OUT                   0x0048 0x02d4 0x0000 8 0
 #define MX6UL_PAD_JTAG_TDO__SJC_TDO                     0x004c 0x02d8 0x0000 0 0
 #define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2               0x004c 0x02d8 0x059c 1 0
@@ -63,12 +63,14 @@
 #define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA                0x0054 0x02e0 0x05f4 2 0
 #define MX6UL_PAD_JTAG_TCK__PWM7_OUT                    0x0054 0x02e0 0x0000 4 0
 #define MX6UL_PAD_JTAG_TCK__GPIO1_IO14                  0x0054 0x02e0 0x0000 5 0
+#define MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT                      0x0054 0x02e0 0x0000 6 0
 #define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL             0x0054 0x02e0 0x0000 8 0
 #define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB                0x0058 0x02e4 0x0000 0 0
 #define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3            0x0058 0x02e4 0x0000 1 0
 #define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA             0x0058 0x02e4 0x0000 2 0
 #define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT                 0x0058 0x02e4 0x0000 4 0
 #define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15               0x0058 0x02e4 0x0000 5 0
+#define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M              0x0058 0x02e4 0x0000 6 0
 #define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS         0x0058 0x02e4 0x0000 8 0
 #define MX6UL_PAD_GPIO1_IO00__I2C2_SCL                  0x005c 0x02e8 0x05ac 0 1
 #define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1             0x005c 0x02e8 0x058c 1 0
@@ -94,22 +96,24 @@
 #define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M         0x0064 0x02f0 0x0000 3 0
 #define MX6UL_PAD_GPIO1_IO02__USDHC1_WP                 0x0064 0x02f0 0x066c 4 0
 #define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02                0x0064 0x02f0 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00          0x0064 0x02f0 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00          0x0064 0x02f0 0x0610 6 1
 #define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET          0x0064 0x02f0 0x0000 7 0
 #define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX              0x0064 0x02f0 0x0000 8 0
 #define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX              0x0064 0x02f0 0x0624 8 0
 #define MX6UL_PAD_GPIO1_IO03__I2C1_SDA                  0x0068 0x02f4 0x05a8 0 1
 #define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3             0x0068 0x02f4 0x0000 1 0
 #define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC               0x0068 0x02f4 0x0660 2 0
+#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT            0x0068 0x02f4 0x0000 3 0
 #define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B               0x0068 0x02f4 0x0668 4 0
 #define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03                0x0068 0x02f4 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK           0x0068 0x02f4 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK           0x0068 0x02f4 0x0000 6 0
 #define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK            0x0068 0x02f4 0x0000 7 0
-#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX              0x0068 0x02f4 0x0000 8 0
 #define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX              0x0068 0x02f4 0x0624 8 1
+#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX              0x0068 0x02f4 0x0000 8 0
 #define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1            0x006c 0x02f8 0x0574 0 1
 #define MX6UL_PAD_GPIO1_IO04__PWM3_OUT                  0x006c 0x02f8 0x0000 1 0
 #define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR              0x006c 0x02f8 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M               0x006c 0x02f8 0x0000 3 0
 #define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B            0x006c 0x02f8 0x0000 4 0
 #define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04                0x006c 0x02f8 0x0000 5 0
 #define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN      0x006c 0x02f8 0x0000 6 0
@@ -200,7 +204,7 @@
 #define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06             0x0094 0x0320 0x04dc 3 0
 #define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1          0x0094 0x0320 0x058c 4 1
 #define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20             0x0094 0x0320 0x0000 5 0
-#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0             0x0094 0x0320 0x0000 8 0
+#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0             0x0094 0x0320 0x0560 8 0
 #define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX           0x0098 0x0324 0x062c 0 1
 #define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX           0x0098 0x0324 0x0000 0 0
 #define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03          0x0098 0x0324 0x0000 1 0
@@ -232,7 +236,7 @@
 #define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX           0x00a4 0x0330 0x0634 0 0
 #define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02          0x00a4 0x0330 0x0000 1 0
 #define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD          0x00a4 0x0330 0x0000 2 0
-#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01             0x00a4 0x0330 0x0000 3 0
+#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01             0x00a4 0x0330 0x04d4 3 0
 #define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS          0x00a4 0x0330 0x0000 4 0
 #define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS          0x00a4 0x0330 0x0628 4 2
 #define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24             0x00a4 0x0330 0x0000 5 0
@@ -242,7 +246,7 @@
 #define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX           0x00a8 0x0334 0x0000 0 0
 #define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03          0x00a8 0x0334 0x0000 1 0
 #define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD          0x00a8 0x0334 0x0000 2 0
-#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00             0x00a8 0x0334 0x0000 3 0
+#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00             0x00a8 0x0334 0x04d0 3 0
 #define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS          0x00a8 0x0334 0x0628 4 3
 #define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS          0x00a8 0x0334 0x0000 4 0
 #define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25             0x00a8 0x0334 0x0000 5 0
@@ -251,7 +255,7 @@
 #define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS            0x00ac 0x0338 0x0630 0 0
 #define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK             0x00ac 0x0338 0x0000 1 0
 #define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX              0x00ac 0x0338 0x0000 2 0
-#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10               0x00ac 0x0338 0x0000 3 0
+#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10               0x00ac 0x0338 0x04ec 3 0
 #define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN     0x00ac 0x0338 0x0000 4 0
 #define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26               0x00ac 0x0338 0x0000 5 0
 #define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT                0x00ac 0x0338 0x0000 8 0
@@ -259,7 +263,7 @@
 #define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS            0x00b0 0x033c 0x0000 0 0
 #define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER              0x00b0 0x033c 0x0000 1 0
 #define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX              0x00b0 0x033c 0x0584 2 0
-#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11               0x00b0 0x033c 0x0000 3 0
+#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11               0x00b0 0x033c 0x04f0 3 0
 #define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT    0x00b0 0x033c 0x0000 4 0
 #define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27               0x00b0 0x033c 0x0000 5 0
 #define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B             0x00b0 0x033c 0x0000 8 0
@@ -267,7 +271,7 @@
 #define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX           0x00b4 0x0340 0x063c 0 0
 #define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02          0x00b4 0x0340 0x0000 1 0
 #define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL               0x00b4 0x0340 0x05a4 2 1
-#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12             0x00b4 0x0340 0x0000 3 0
+#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12             0x00b4 0x0340 0x04f4 3 0
 #define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02    0x00b4 0x0340 0x0000 4 0
 #define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28             0x00b4 0x0340 0x0000 5 0
 #define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK            0x00b4 0x0340 0x0544 8 1
@@ -275,23 +279,23 @@
 #define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX           0x00b8 0x0344 0x0000 0 0
 #define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03          0x00b8 0x0344 0x0000 1 0
 #define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA               0x00b8 0x0344 0x05a8 2 2
-#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13             0x00b8 0x0344 0x0000 3 0
+#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13             0x00b8 0x0344 0x04f8 3 0
 #define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01    0x00b8 0x0344 0x0000 4 0
 #define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29             0x00b8 0x0344 0x0000 5 0
-#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0             0x00b8 0x0344 0x0000 8 0
+#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0             0x00b8 0x0344 0x0550 8 1
 #define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30             0x00bc 0x0348 0x0000 5 0
 #define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI            0x00bc 0x0348 0x054c 8 0
 #define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX           0x00bc 0x0348 0x0000 0 0
 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX           0x00bc 0x0348 0x0644 0 4
 #define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS              0x00bc 0x0348 0x0000 1 0
 #define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL               0x00bc 0x0348 0x05ac 2 2
-#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14             0x00bc 0x0348 0x0000 3 0
+#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14             0x00bc 0x0348 0x04fc 3 0
 #define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00    0x00bc 0x0348 0x0000 4 0
 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX           0x00c0 0x034c 0x0644 0 5
 #define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX           0x00c0 0x034c 0x0000 0 0
 #define MX6UL_PAD_UART5_RX_DATA__ENET2_COL              0x00c0 0x034c 0x0000 1 0
 #define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA               0x00c0 0x034c 0x05b0 2 2
-#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15             0x00c0 0x034c 0x0000 3 0
+#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15             0x00c0 0x034c 0x0500 3 0
 #define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB        0x00c0 0x034c 0x0000 4 0
 #define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31             0x00c0 0x034c 0x0000 5 0
 #define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO            0x00c0 0x034c 0x0548 8 1
@@ -299,59 +303,61 @@
 #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS         0x00c4 0x0350 0x0638 1 0
 #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS         0x00c4 0x0350 0x0000 1 0
 #define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT              0x00c4 0x0350 0x0000 2 0
-#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16            0x00c4 0x0350 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16            0x00c4 0x0350 0x0504 3 0
 #define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX           0x00c4 0x0350 0x0000 4 0
 #define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00            0x00c4 0x0350 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00             0x00c4 0x0350 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00             0x00c4 0x0350 0x05d0 6 0
 #define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL           0x00c4 0x0350 0x0000 8 0
 #define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01         0x00c8 0x0354 0x0000 0 0
 #define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS         0x00c8 0x0354 0x0000 1 0
 #define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS         0x00c8 0x0354 0x0638 1 1
 #define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT              0x00c8 0x0354 0x0000 2 0
-#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17            0x00c8 0x0354 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17            0x00c8 0x0354 0x0508 3 0
 #define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX           0x00c8 0x0354 0x0584 4 1
 #define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01            0x00c8 0x0354 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00             0x00c8 0x0354 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00             0x00c8 0x0354 0x05c4 6 0
 #define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL           0x00c8 0x0354 0x0000 8 0
 #define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN              0x00cc 0x0358 0x0000 0 0
 #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS            0x00cc 0x0358 0x0640 1 3
 #define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS            0x00cc 0x0358 0x0000 1 0
-#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18               0x00cc 0x0358 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT           0x00cc 0x0358 0x0000 2 0
+#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18               0x00cc 0x0358 0x050c 3 0
 #define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX              0x00cc 0x0358 0x0000 4 0
 #define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02               0x00cc 0x0358 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01                0x00cc 0x0358 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01                0x00cc 0x0358 0x05d4 6 0
 #define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT           0x00cc 0x0358 0x0000 8 0
 #define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00         0x00d0 0x035c 0x0000 0 0
 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS         0x00d0 0x035c 0x0000 1 0
 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS         0x00d0 0x035c 0x0640 1 4
-#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19            0x00d0 0x035c 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M           0x00d0 0x035c 0x0000 2 0
+#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19            0x00d0 0x035c 0x0510 3 0
 #define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX           0x00d0 0x035c 0x0588 4 1
 #define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03            0x00d0 0x035c 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01             0x00d0 0x035c 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01             0x00d0 0x035c 0x05c8 6 0
 #define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT        0x00d0 0x035c 0x0000 8 0
 #define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01         0x00d4 0x0360 0x0000 0 0
 #define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS         0x00d4 0x0360 0x0000 1 0
 #define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS         0x00d4 0x0360 0x0648 1 2
 #define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT              0x00d4 0x0360 0x0000 2 0
-#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20            0x00d4 0x0360 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20            0x00d4 0x0360 0x0514 3 0
 #define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO            0x00d4 0x0360 0x0580 4 1
 #define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04            0x00d4 0x0360 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02             0x00d4 0x0360 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02             0x00d4 0x0360 0x05d8 6 0
 #define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB  0x00d4 0x0360 0x0000 8 0
 #define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN              0x00d8 0x0364 0x0000 0 0
 #define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS            0x00d8 0x0364 0x0648 1 3
 #define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS            0x00d8 0x0364 0x0000 1 0
 #define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT                 0x00d8 0x0364 0x0000 2 0
-#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21               0x00d8 0x0364 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21               0x00d8 0x0364 0x0518 3 0
 #define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC                0x00d8 0x0364 0x0000 4 0
 #define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05               0x00d8 0x0364 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02                0x00d8 0x0364 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02                0x00d8 0x0364 0x05cc 6 0
 #define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB     0x00d8 0x0364 0x0000 8 0
 #define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK            0x00dc 0x0368 0x0000 0 0
 #define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS           0x00dc 0x0368 0x0000 1 0
 #define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS           0x00dc 0x0368 0x0650 1 0
 #define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT                0x00dc 0x0368 0x0000 2 0
-#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22              0x00dc 0x0368 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22              0x00dc 0x0368 0x051c 3 0
 #define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1          0x00dc 0x0368 0x0574 4 2
 #define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06              0x00dc 0x0368 0x0000 5 0
 #define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03               0x00dc 0x0368 0x0000 6 0
@@ -360,7 +366,7 @@
 #define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS            0x00e0 0x036c 0x0650 1 1
 #define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS            0x00e0 0x036c 0x0000 1 0
 #define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT                 0x00e0 0x036c 0x0000 2 0
-#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23               0x00e0 0x036c 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23               0x00e0 0x036c 0x0520 3 0
 #define MX6UL_PAD_ENET1_RX_ER__EIM_CRE                  0x00e0 0x036c 0x0000 4 0
 #define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07               0x00e0 0x036c 0x0000 5 0
 #define MX6UL_PAD_ENET1_RX_ER__KPP_COL03                0x00e0 0x036c 0x0000 6 0
@@ -377,7 +383,7 @@
 #define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01         0x00e8 0x0374 0x0000 0 0
 #define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX          0x00e8 0x0374 0x064c 1 2
 #define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX          0x00e8 0x0374 0x0000 1 0
-#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK        0x00e8 0x0374 0x0000 2 0
+#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK        0x00e8 0x0374 0x0000 2 0
 #define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA              0x00e8 0x0374 0x05b8 3 1
 #define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC             0x00e8 0x0374 0x0000 4 0
 #define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09            0x00e8 0x0374 0x0000 5 0
@@ -400,6 +406,7 @@
 #define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02            0x00f0 0x037c 0x0000 4 0
 #define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11            0x00f0 0x037c 0x0000 5 0
 #define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05             0x00f0 0x037c 0x0000 6 0
+#define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M           0x00f0 0x037c 0x0000 8 0
 #define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01         0x00f4 0x0380 0x0000 0 0
 #define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX          0x00f4 0x0380 0x0000 1 0
 #define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX          0x00f4 0x0380 0x065c 1 0
@@ -412,7 +419,7 @@
 #define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN              0x00f8 0x0384 0x0000 0 0
 #define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX             0x00f8 0x0384 0x065c 1 1
 #define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX             0x00f8 0x0384 0x0000 1 0
-#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK           0x00f8 0x0384 0x0000 2 0
+#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK           0x00f8 0x0384 0x0000 2 0
 #define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI              0x00f8 0x0384 0x056c 3 0
 #define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN         0x00f8 0x0384 0x0000 4 0
 #define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13               0x00f8 0x0384 0x0000 5 0
@@ -431,7 +438,7 @@
 #define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS            0x0100 0x038c 0x0658 1 1
 #define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS            0x0100 0x038c 0x0000 1 0
 #define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN          0x0100 0x038c 0x0000 2 0
-#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0               0x0100 0x038c 0x0000 3 0
+#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0               0x0100 0x038c 0x0570 3 0
 #define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25               0x0100 0x038c 0x0000 4 0
 #define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15               0x0100 0x038c 0x0000 5 0
 #define MX6UL_PAD_ENET2_RX_ER__KPP_COL07                0x0100 0x038c 0x0000 6 0
@@ -440,7 +447,7 @@
 #define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN                 0x0104 0x0390 0x0000 1 0
 #define MX6UL_PAD_LCD_CLK__UART4_DCE_TX                 0x0104 0x0390 0x0000 2 0
 #define MX6UL_PAD_LCD_CLK__UART4_DTE_RX                 0x0104 0x0390 0x063c 2 2
-#define MX6UL_PAD_LCD_CLK__SAI3_MCLK                    0x0104 0x0390 0x0000 3 0
+#define MX6UL_PAD_LCD_CLK__SAI3_MCLK                    0x0104 0x0390 0x0600 3 0
 #define MX6UL_PAD_LCD_CLK__EIM_CS2_B                    0x0104 0x0390 0x0000 4 0
 #define MX6UL_PAD_LCD_CLK__GPIO3_IO00                   0x0104 0x0390 0x0000 5 0
 #define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB         0x0104 0x0390 0x0000 8 0
@@ -464,7 +471,7 @@
 #define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY                 0x0110 0x039c 0x05dc 1 1
 #define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS              0x0110 0x039c 0x0638 2 3
 #define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS              0x0110 0x039c 0x0000 2 0
-#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA               0x0110 0x039c 0x0000 3 0
+#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA               0x0110 0x039c 0x0604 3 0
 #define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B               0x0110 0x039c 0x0000 4 0
 #define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03                 0x0110 0x039c 0x0000 5 0
 #define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2                 0x0110 0x039c 0x0000 8 0
@@ -477,13 +484,15 @@
 #define MX6UL_PAD_LCD_RESET__ECSPI2_SS3                 0x0114 0x03a0 0x0000 8 0
 #define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00              0x0118 0x03a4 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA00__PWM1_OUT                  0x0118 0x03a4 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0          0x0118 0x03a4 0x0000 2 0
 #define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN      0x0118 0x03a4 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA00__I2C3_SDA                  0x0118 0x03a4 0x05b8 4 2
 #define MX6UL_PAD_LCD_DATA00__GPIO3_IO05                0x0118 0x03a4 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00              0x0118 0x03a4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK                 0x0118 0x03a4 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK                 0x0118 0x03a4 0x05e0 8 1
 #define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01              0x011c 0x03a8 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA01__PWM2_OUT                  0x011c 0x03a8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1          0x011c 0x03a8 0x0000 2 0
 #define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT     0x011c 0x03a8 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA01__I2C3_SCL                  0x011c 0x03a8 0x05b4 4 2
 #define MX6UL_PAD_LCD_DATA01__GPIO3_IO06                0x011c 0x03a8 0x0000 5 0
@@ -491,6 +500,7 @@
 #define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC              0x011c 0x03a8 0x05ec 8 0
 #define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02              0x0120 0x03ac 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA02__PWM3_OUT                  0x0120 0x03ac 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2          0x0120 0x03ac 0x0000 2 0
 #define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN      0x0120 0x03ac 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA02__I2C4_SDA                  0x0120 0x03ac 0x05c0 4 2
 #define MX6UL_PAD_LCD_DATA02__GPIO3_IO07                0x0120 0x03ac 0x0000 5 0
@@ -498,14 +508,16 @@
 #define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK              0x0120 0x03ac 0x05e8 8 0
 #define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03              0x0124 0x03b0 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA03__PWM4_OUT                  0x0124 0x03b0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3          0x0124 0x03b0 0x0000 2 0
 #define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT     0x0124 0x03b0 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA03__I2C4_SCL                  0x0124 0x03b0 0x05bc 4 2
 #define MX6UL_PAD_LCD_DATA03__GPIO3_IO08                0x0124 0x03b0 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03              0x0124 0x03b0 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA              0x0124 0x03b0 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA              0x0124 0x03b0 0x05e4 8 0
 #define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04              0x0128 0x03b4 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS             0x0128 0x03b4 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS             0x0128 0x03b4 0x0658 1 2
+#define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4          0x0128 0x03b4 0x0000 2 0
 #define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN      0x0128 0x03b4 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK              0x0128 0x03b4 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA04__GPIO3_IO09                0x0128 0x03b4 0x0000 5 0
@@ -514,6 +526,7 @@
 #define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05              0x012c 0x03b8 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS             0x012c 0x03b8 0x0658 1 3
 #define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS             0x012c 0x03b8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5          0x012c 0x03b8 0x0000 2 0
 #define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT     0x012c 0x03b8 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA05__SPDIF_OUT                 0x012c 0x03b8 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA05__GPIO3_IO10                0x012c 0x03b8 0x0000 5 0
@@ -522,6 +535,7 @@
 #define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06              0x0130 0x03bc 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS             0x0130 0x03bc 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS             0x0130 0x03bc 0x0650 1 2
+#define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6          0x0130 0x03bc 0x0000 2 0
 #define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN      0x0130 0x03bc 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK                0x0130 0x03bc 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA06__GPIO3_IO11                0x0130 0x03bc 0x0000 5 0
@@ -530,6 +544,7 @@
 #define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07              0x0134 0x03c0 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS             0x0134 0x03c0 0x0650 1 3
 #define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS             0x0134 0x03c0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7          0x0134 0x03c0 0x0000 2 0
 #define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT     0x0134 0x03c0 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK             0x0134 0x03c0 0x061c 4 0
 #define MX6UL_PAD_LCD_DATA07__GPIO3_IO12                0x0134 0x03c0 0x0000 5 0
@@ -537,56 +552,64 @@
 #define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3                0x0134 0x03c0 0x0000 8 0
 #define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08              0x0138 0x03c4 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA08__SPDIF_IN                  0x0138 0x03c4 0x0618 1 2
-#define MX6UL_PAD_LCD_DATA08__CSI_DATA16                0x0138 0x03c4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8          0x0138 0x03c4 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA08__CSI_DATA16                0x0138 0x03c4 0x0504 3 1
 #define MX6UL_PAD_LCD_DATA08__EIM_DATA00                0x0138 0x03c4 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA08__GPIO3_IO13                0x0138 0x03c4 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08              0x0138 0x03c4 0x0000 6 0
 #define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX               0x0138 0x03c4 0x0000 8 0
 #define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09              0x013c 0x03c8 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK                 0x013c 0x03c8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA09__CSI_DATA17                0x013c 0x03c8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK                 0x013c 0x03c8 0x0600 1 1
+#define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9          0x013c 0x03c8 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA09__CSI_DATA17                0x013c 0x03c8 0x0508 3 1
 #define MX6UL_PAD_LCD_DATA09__EIM_DATA01                0x013c 0x03c8 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA09__GPIO3_IO14                0x013c 0x03c8 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09              0x013c 0x03c8 0x0000 6 0
 #define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX               0x013c 0x03c8 0x0584 8 2
 #define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10              0x0140 0x03cc 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC              0x0140 0x03cc 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA10__CSI_DATA18                0x0140 0x03cc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE10         0x0140 0x03cc 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA10__CSI_DATA18                0x0140 0x03cc 0x050c 3 1
 #define MX6UL_PAD_LCD_DATA10__EIM_DATA02                0x0140 0x03cc 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA10__GPIO3_IO15                0x0140 0x03cc 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10              0x0140 0x03cc 0x0000 6 0
 #define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX               0x0140 0x03cc 0x0000 8 0
 #define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11              0x0144 0x03d0 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK              0x0144 0x03d0 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA11__CSI_DATA19                0x0144 0x03d0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE11         0x0144 0x03d0 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA11__CSI_DATA19                0x0144 0x03d0 0x0510 3 1
 #define MX6UL_PAD_LCD_DATA11__EIM_DATA03                0x0144 0x03d0 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA11__GPIO3_IO16                0x0144 0x03d0 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11              0x0144 0x03d0 0x0000 6 0
 #define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX               0x0144 0x03d0 0x0588 8 2
 #define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12              0x0148 0x03d4 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC              0x0148 0x03d4 0x060c 1 1
-#define MX6UL_PAD_LCD_DATA12__CSI_DATA20                0x0148 0x03d4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE12         0x0148 0x03d4 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA12__CSI_DATA20                0x0148 0x03d4 0x0514 3 1
 #define MX6UL_PAD_LCD_DATA12__EIM_DATA04                0x0148 0x03d4 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA12__GPIO3_IO17                0x0148 0x03d4 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12              0x0148 0x03d4 0x0000 6 0
 #define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY                0x0148 0x03d4 0x0000 8 0
 #define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13              0x014c 0x03d8 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK              0x014c 0x03d8 0x0608 1 1
-#define MX6UL_PAD_LCD_DATA13__CSI_DATA21                0x014c 0x03d8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE13         0x014c 0x03d8 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA13__CSI_DATA21                0x014c 0x03d8 0x0518 3 1
 #define MX6UL_PAD_LCD_DATA13__EIM_DATA05                0x014c 0x03d8 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA13__GPIO3_IO18                0x014c 0x03d8 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13              0x014c 0x03d8 0x0000 6 0
 #define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B            0x014c 0x03d8 0x0000 8 0
 #define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14              0x0150 0x03dc 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA              0x0150 0x03dc 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA14__CSI_DATA22                0x0150 0x03dc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA              0x0150 0x03dc 0x0604 1 1
+#define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE14         0x0150 0x03dc 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA14__CSI_DATA22                0x0150 0x03dc 0x051c 3 1
 #define MX6UL_PAD_LCD_DATA14__EIM_DATA06                0x0150 0x03dc 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA14__GPIO3_IO19                0x0150 0x03dc 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14              0x0150 0x03dc 0x0000 6 0
 #define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4              0x0150 0x03dc 0x068c 8 0
 #define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15              0x0154 0x03e0 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA              0x0154 0x03e0 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA15__CSI_DATA23                0x0154 0x03e0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE15         0x0154 0x03e0 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA15__CSI_DATA23                0x0154 0x03e0 0x0520 3 1
 #define MX6UL_PAD_LCD_DATA15__EIM_DATA07                0x0154 0x03e0 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA15__GPIO3_IO20                0x0154 0x03e0 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15              0x0154 0x03e0 0x0000 6 0
@@ -594,7 +617,8 @@
 #define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16              0x0158 0x03e4 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX              0x0158 0x03e4 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX              0x0158 0x03e4 0x0654 1 2
-#define MX6UL_PAD_LCD_DATA16__CSI_DATA01                0x0158 0x03e4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK       0x0158 0x03e4 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA16__CSI_DATA01                0x0158 0x03e4 0x04d4 3 1
 #define MX6UL_PAD_LCD_DATA16__EIM_DATA08                0x0158 0x03e4 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA16__GPIO3_IO21                0x0158 0x03e4 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24              0x0158 0x03e4 0x0000 6 0
@@ -602,7 +626,8 @@
 #define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17              0x015c 0x03e8 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX              0x015c 0x03e8 0x0654 1 3
 #define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX              0x015c 0x03e8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA17__CSI_DATA00                0x015c 0x03e8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL       0x015c 0x03e8 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA17__CSI_DATA00                0x015c 0x03e8 0x04d0 3 1
 #define MX6UL_PAD_LCD_DATA17__EIM_DATA09                0x015c 0x03e8 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA17__GPIO3_IO22                0x015c 0x03e8 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25              0x015c 0x03e8 0x0000 6 0
@@ -610,7 +635,7 @@
 #define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18              0x0160 0x03ec 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA18__PWM5_OUT                  0x0160 0x03ec 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO          0x0160 0x03ec 0x0000 2 0
-#define MX6UL_PAD_LCD_DATA18__CSI_DATA10                0x0160 0x03ec 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA18__CSI_DATA10                0x0160 0x03ec 0x04ec 3 1
 #define MX6UL_PAD_LCD_DATA18__EIM_DATA10                0x0160 0x03ec 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA18__GPIO3_IO23                0x0160 0x03ec 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26              0x0160 0x03ec 0x0000 6 0
@@ -622,7 +647,7 @@
 #define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19              0x0164 0x03f0 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA19__PWM6_OUT                  0x0164 0x03f0 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY            0x0164 0x03f0 0x0000 2 0
-#define MX6UL_PAD_LCD_DATA19__CSI_DATA11                0x0164 0x03f0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA19__CSI_DATA11                0x0164 0x03f0 0x04f0 3 1
 #define MX6UL_PAD_LCD_DATA20__EIM_DATA12                0x0168 0x03f4 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA20__GPIO3_IO25                0x0168 0x03f4 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28              0x0168 0x03f4 0x0000 6 0
@@ -631,12 +656,12 @@
 #define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX              0x0168 0x03f4 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX              0x0168 0x03f4 0x065c 1 2
 #define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK               0x0168 0x03f4 0x0534 2 0
-#define MX6UL_PAD_LCD_DATA20__CSI_DATA12                0x0168 0x03f4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA20__CSI_DATA12                0x0168 0x03f4 0x04f4 3 1
 #define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21              0x016c 0x03f8 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX              0x016c 0x03f8 0x065c 1 3
 #define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX              0x016c 0x03f8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0                0x016c 0x03f8 0x0000 2 0
-#define MX6UL_PAD_LCD_DATA21__CSI_DATA13                0x016c 0x03f8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0                0x016c 0x03f8 0x0540 2 0
+#define MX6UL_PAD_LCD_DATA21__CSI_DATA13                0x016c 0x03f8 0x04f8 3 1
 #define MX6UL_PAD_LCD_DATA21__EIM_DATA13                0x016c 0x03f8 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA21__GPIO3_IO26                0x016c 0x03f8 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29              0x016c 0x03f8 0x0000 6 0
@@ -644,7 +669,7 @@
 #define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22              0x0170 0x03fc 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA22__MQS_RIGHT                 0x0170 0x03fc 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI               0x0170 0x03fc 0x053c 2 0
-#define MX6UL_PAD_LCD_DATA22__CSI_DATA14                0x0170 0x03fc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA22__CSI_DATA14                0x0170 0x03fc 0x04fc 3 1
 #define MX6UL_PAD_LCD_DATA22__EIM_DATA14                0x0170 0x03fc 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA22__GPIO3_IO27                0x0170 0x03fc 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30              0x0170 0x03fc 0x0000 6 0
@@ -652,7 +677,7 @@
 #define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23              0x0174 0x0400 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA23__MQS_LEFT                  0x0174 0x0400 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO               0x0174 0x0400 0x0538 2 0
-#define MX6UL_PAD_LCD_DATA23__CSI_DATA15                0x0174 0x0400 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA23__CSI_DATA15                0x0174 0x0400 0x0500 3 1
 #define MX6UL_PAD_LCD_DATA23__EIM_DATA15                0x0174 0x0400 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA23__GPIO3_IO28                0x0174 0x0400 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31              0x0174 0x0400 0x0000 6 0
@@ -660,42 +685,42 @@
 #define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B               0x0178 0x0404 0x0000 0 0
 #define MX6UL_PAD_NAND_RE_B__USDHC2_CLK                 0x0178 0x0404 0x0670 1 2
 #define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK                0x0178 0x0404 0x0000 2 0
-#define MX6UL_PAD_NAND_RE_B__KPP_ROW00                  0x0178 0x0404 0x0000 3 0
+#define MX6UL_PAD_NAND_RE_B__KPP_ROW00                  0x0178 0x0404 0x05d0 3 1
 #define MX6UL_PAD_NAND_RE_B__EIM_EB_B00                 0x0178 0x0404 0x0000 4 0
 #define MX6UL_PAD_NAND_RE_B__GPIO4_IO00                 0x0178 0x0404 0x0000 5 0
 #define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2                 0x0178 0x0404 0x0000 8 0
 #define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B               0x017c 0x0408 0x0000 0 0
 #define MX6UL_PAD_NAND_WE_B__USDHC2_CMD                 0x017c 0x0408 0x0678 1 2
 #define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B               0x017c 0x0408 0x0000 2 0
-#define MX6UL_PAD_NAND_WE_B__KPP_COL00                  0x017c 0x0408 0x0000 3 0
+#define MX6UL_PAD_NAND_WE_B__KPP_COL00                  0x017c 0x0408 0x05c4 3 1
 #define MX6UL_PAD_NAND_WE_B__EIM_EB_B01                 0x017c 0x0408 0x0000 4 0
 #define MX6UL_PAD_NAND_WE_B__GPIO4_IO01                 0x017c 0x0408 0x0000 5 0
 #define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3                 0x017c 0x0408 0x0000 8 0
 #define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00           0x0180 0x040c 0x0000 0 0
 #define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0             0x0180 0x040c 0x067c 1 2
 #define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B             0x0180 0x040c 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA00__KPP_ROW01                0x0180 0x040c 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA00__KPP_ROW01                0x0180 0x040c 0x05d4 3 1
 #define MX6UL_PAD_NAND_DATA00__EIM_AD08                 0x0180 0x040c 0x0000 4 0
 #define MX6UL_PAD_NAND_DATA00__GPIO4_IO02               0x0180 0x040c 0x0000 5 0
 #define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY               0x0180 0x040c 0x0000 8 0
 #define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01           0x0184 0x0410 0x0000 0 0
 #define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1             0x0184 0x0410 0x0680 1 2
 #define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS               0x0184 0x0410 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA01__KPP_COL01                0x0184 0x0410 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA01__KPP_COL01                0x0184 0x0410 0x05c8 3 1
 #define MX6UL_PAD_NAND_DATA01__EIM_AD09                 0x0184 0x0410 0x0000 4 0
 #define MX6UL_PAD_NAND_DATA01__GPIO4_IO03               0x0184 0x0410 0x0000 5 0
 #define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1               0x0184 0x0410 0x0000 8 0
 #define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02           0x0188 0x0414 0x0000 0 0
 #define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2             0x0188 0x0414 0x0684 1 1
 #define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00            0x0188 0x0414 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA02__KPP_ROW02                0x0188 0x0414 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA02__KPP_ROW02                0x0188 0x0414 0x05d8 3 1
 #define MX6UL_PAD_NAND_DATA02__EIM_AD10                 0x0188 0x0414 0x0000 4 0
 #define MX6UL_PAD_NAND_DATA02__GPIO4_IO04               0x0188 0x0414 0x0000 5 0
 #define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2               0x0188 0x0414 0x0000 8 0
 #define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03           0x018c 0x0418 0x0000 0 0
 #define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3             0x018c 0x0418 0x0688 1 2
 #define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01            0x018c 0x0418 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA03__KPP_COL02                0x018c 0x0418 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA03__KPP_COL02                0x018c 0x0418 0x05cc 3 1
 #define MX6UL_PAD_NAND_DATA03__EIM_AD11                 0x018c 0x0418 0x0000 4 0
 #define MX6UL_PAD_NAND_DATA03__GPIO4_IO05               0x018c 0x0418 0x0000 5 0
 #define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3               0x018c 0x0418 0x0000 8 0
@@ -726,7 +751,7 @@
 #define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07           0x019c 0x0428 0x0000 0 0
 #define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7             0x019c 0x0428 0x0698 1 1
 #define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B             0x019c 0x0428 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0               0x019c 0x0428 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0               0x019c 0x0428 0x0570 3 1
 #define MX6UL_PAD_NAND_DATA07__EIM_AD15                 0x019c 0x0428 0x0000 4 0
 #define MX6UL_PAD_NAND_DATA07__GPIO4_IO09               0x019c 0x0428 0x0000 5 0
 #define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS            0x019c 0x0428 0x0628 8 5
@@ -748,7 +773,7 @@
 #define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B         0x01a8 0x0434 0x0000 0 0
 #define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4            0x01a8 0x0434 0x0000 1 0
 #define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00           0x01a8 0x0434 0x0000 2 0
-#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0              0x01a8 0x0434 0x0000 3 0
+#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0              0x01a8 0x0434 0x0560 3 1
 #define MX6UL_PAD_NAND_READY_B__EIM_CS1_B               0x01a8 0x0434 0x0000 4 0
 #define MX6UL_PAD_NAND_READY_B__GPIO4_IO12              0x01a8 0x0434 0x0000 5 0
 #define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX            0x01a8 0x0434 0x0000 8 0
@@ -783,7 +808,7 @@
 #define MX6UL_PAD_NAND_DQS__PWM5_OUT                    0x01b8 0x0444 0x0000 3 0
 #define MX6UL_PAD_NAND_DQS__EIM_WAIT                    0x01b8 0x0444 0x0000 4 0
 #define MX6UL_PAD_NAND_DQS__GPIO4_IO16                  0x01b8 0x0444 0x0000 5 0
-#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01            0x01b8 0x0444 0x0000 6 0
+#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01            0x01b8 0x0444 0x0614 6 1
 #define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK               0x01b8 0x0444 0x061c 8 1
 #define MX6UL_PAD_SD1_CMD__USDHC1_CMD                   0x01bc 0x0448 0x0000 0 0
 #define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1                0x01bc 0x0448 0x0000 1 0
@@ -791,11 +816,11 @@
 #define MX6UL_PAD_SD1_CMD__SPDIF_OUT                    0x01bc 0x0448 0x0000 3 0
 #define MX6UL_PAD_SD1_CMD__EIM_ADDR19                   0x01bc 0x0448 0x0000 4 0
 #define MX6UL_PAD_SD1_CMD__GPIO2_IO16                   0x01bc 0x0448 0x0000 5 0
-#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00             0x01bc 0x0448 0x0000 6 0
+#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00             0x01bc 0x0448 0x0610 6 2
 #define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR                 0x01bc 0x0448 0x0000 8 0
 #define MX6UL_PAD_SD1_CLK__USDHC1_CLK                   0x01c0 0x044c 0x0000 0 0
 #define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2                0x01c0 0x044c 0x0000 1 0
-#define MX6UL_PAD_SD1_CLK__SAI2_MCLK                    0x01c0 0x044c 0x0000 2 0
+#define MX6UL_PAD_SD1_CLK__SAI2_MCLK                    0x01c0 0x044c 0x05f0 2 1
 #define MX6UL_PAD_SD1_CLK__SPDIF_IN                     0x01c0 0x044c 0x0618 3 3
 #define MX6UL_PAD_SD1_CLK__EIM_ADDR20                   0x01c0 0x044c 0x0000 4 0
 #define MX6UL_PAD_SD1_CLK__GPIO2_IO17                   0x01c0 0x044c 0x0000 5 0
@@ -878,10 +903,10 @@
 #define MX6UL_PAD_CSI_DATA01__CSI_DATA03                0x01e8 0x0474 0x04c8 0 0
 #define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1              0x01e8 0x0474 0x0680 1 0
 #define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN           0x01e8 0x0474 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0                0x01e8 0x0474 0x0000 3 0
+#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0                0x01e8 0x0474 0x0550 3 0
 #define MX6UL_PAD_CSI_DATA01__EIM_AD01                  0x01e8 0x0474 0x0000 4 0
 #define MX6UL_PAD_CSI_DATA01__GPIO4_IO22                0x01e8 0x0474 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK                 0x01e8 0x0474 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK                 0x01e8 0x0474 0x05e0 6 0
 #define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX              0x01e8 0x0474 0x0644 8 1
 #define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX              0x01e8 0x0474 0x0000 8 0
 #define MX6UL_PAD_CSI_DATA02__CSI_DATA04                0x01ec 0x0478 0x04d8 0 1
@@ -913,7 +938,7 @@
 #define MX6UL_PAD_CSI_DATA05__CSI_DATA07                0x01f8 0x0484 0x04e0 0 1
 #define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5              0x01f8 0x0484 0x0690 1 2
 #define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0x01f8 0x0484 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0                0x01f8 0x0484 0x0000 3 0
+#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0                0x01f8 0x0484 0x0540 3 1
 #define MX6UL_PAD_CSI_DATA05__EIM_AD05                  0x01f8 0x0484 0x0000 4 0
 #define MX6UL_PAD_CSI_DATA05__GPIO4_IO26                0x01f8 0x0484 0x0000 5 0
 #define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK              0x01f8 0x0484 0x05e8 6 1
@@ -924,7 +949,7 @@
 #define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI               0x01fc 0x0488 0x053c 3 1
 #define MX6UL_PAD_CSI_DATA06__EIM_AD06                  0x01fc 0x0488 0x0000 4 0
 #define MX6UL_PAD_CSI_DATA06__GPIO4_IO27                0x01fc 0x0488 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA              0x01fc 0x0488 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA              0x01fc 0x0488 0x05e4 6 1
 #define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B            0x01fc 0x0488 0x0000 8 0
 #define MX6UL_PAD_CSI_DATA07__CSI_DATA09                0x0200 0x048c 0x04e8 0 1
 #define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7              0x0200 0x048c 0x0698 1 2
diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
index 65111f9843f4..f678d18ad44a 100644
--- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
@@ -70,8 +70,8 @@
                 stdout-path = &uart1;
         };
 
-        memory {
-                reg = <0 0>; /* will be filled by U-Boot */
+        memory@80000000 {
+                reg = <0x80000000 0>; /* will be filled by U-Boot */
         };
 
         clocks {
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 5d6c3ba36cd1..1241972b16ba 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -22,7 +22,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec1;
@@ -86,15 +86,10 @@
                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
                                  <&clks IMX6UL_CLK_STEP>,
                                  <&clks IMX6UL_CLK_PLL1_SW>,
-                                 <&clks IMX6UL_CLK_PLL1_SYS>,
-                                 <&clks IMX6UL_PLL1_BYPASS>,
-                                 <&clks IMX6UL_CLK_PLL1>,
-                                 <&clks IMX6UL_PLL1_BYPASS_SRC>,
-                                 <&clks IMX6UL_CLK_OSC>;
+                                 <&clks IMX6UL_CLK_PLL1_SYS>;
                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
                                       "secondary_sel", "step", "pll1_sw",
-                                      "pll1_sys", "pll1_bypass", "pll1",
-                                      "pll1_bypass_src", "osc";
+                                      "pll1_sys";
                         arm-supply = <&reg_arm>;
                         soc-supply = <&reg_soc>;
                 };
@@ -102,14 +97,26 @@
 
         intc: interrupt-controller@a01000 {
                 compatible = "arm,gic-400", "arm,cortex-a7-gic";
+                interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
                 #interrupt-cells = <3>;
                 interrupt-controller;
+                interrupt-parent = <&intc>;
                 reg = <0x00a01000 0x1000>,
                       <0x00a02000 0x2000>,
                       <0x00a04000 0x2000>,
                       <0x00a06000 0x2000>;
         };
 
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+                interrupt-parent = <&intc>;
+                status = "disabled";
+        };
+
         ckil: clock-cli {
                 compatible = "fixed-clock";
                 #clock-cells = <0>;
@@ -924,6 +931,14 @@
                                 status = "disabled";
                         };
 
+                        wdog3: wdog@21e4000 {
+                                compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
+                                reg = <0x021e4000 0x4000>;
+                                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX6UL_CLK_WDOG3>;
+                                status = "disabled";
+                        };
+
                         uart2: serial@21e8000 {
                                 compatible = "fsl,imx6ul-uart",
                                              "fsl,imx6q-uart";
diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk.dts b/arch/arm/boot/dts/imx6ull-14x14-evk.dts
index 4741871434dd..30ef60344af3 100644
--- a/arch/arm/boot/dts/imx6ull-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ull-14x14-evk.dts
@@ -39,7 +39,10 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "imx6ul-14x14-evk.dts"
+/dts-v1/;
+
+#include "imx6ull.dtsi"
+#include "imx6ul-14x14-evk.dtsi"
 
 / {
         model = "Freescale i.MX6 UlltraLite 14x14 EVK Board";
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
new file mode 100644
index 000000000000..08669a18349e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 Toradex AG
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-eval-v3.dtsi"
+
+/ {
+        model = "Toradex Colibri iMX6ULL 256MB on Colibri Evaluation Board V3";
+        compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
new file mode 100644
index 000000000000..006690ea98c0
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017 Toradex AG
+ */
+
+/ {
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        /* fixed crystal dedicated to mcp2515 */
+        clk16m: clk16m {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <16000000>;
+        };
+
+        panel: panel {
+                compatible = "edt,et057090dhu";
+                backlight = <&bl>;
+                power-supply = <&reg_3v3>;
+
+                port {
+                        panel_in: endpoint {
+                                remote-endpoint = <&lcdif_out>;
+                        };
+                };
+        };
+
+        reg_3v3: regulator-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        reg_5v0: regulator-5v0 {
+                compatible = "regulator-fixed";
+                regulator-name = "5V";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
+
+        reg_usbh_vbus: regulator-usbh-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_usbh_reg>;
+                regulator-name = "VCC_USB[1-4]";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+                vin-supply = <&reg_5v0>;
+        };
+};
+
+&adc1 {
+        status = "okay";
+};
+
+&bl {
+        brightness-levels = <0 4 8 16 32 64 128 255>;
+        default-brightness-level = <6>;
+        power-supply = <&reg_3v3>;
+        pwms = <&pwm4 0 5000000 1>;
+        status = "okay";
+};
+
+&ecspi1 {
+        status = "okay";
+
+        mcp2515: can@0 {
+                compatible = "microchip,mcp2515";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_can_int>;
+                reg = <0>;
+                clocks = <&clk16m>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+                spi-max-frequency = <10000000>;
+                vdd-supply = <&reg_3v3>;
+                xceiver-supply = <&reg_5v0>;
+                status = "okay";
+        };
+};
+
+&i2c1 {
+        status = "okay";
+
+        /* M41T0M6 real time clock on carrier board */
+        m41t0m6: rtc@68 {
+                compatible = "st,m41t0";
+                reg = <0x68>;
+        };
+};
+
+&lcdif {
+        status = "okay";
+
+        port {
+                lcdif_out: endpoint {
+                        remote-endpoint = <&panel_in>;
+                };
+        };
+};
+
+/* PWM <A> */
+&pwm4 {
+        status = "okay";
+};
+
+/* PWM <B> */
+&pwm5 {
+        status = "okay";
+};
+
+/* PWM <C> */
+&pwm6 {
+        status = "okay";
+};
+
+/* PWM <D> */
+&pwm7 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&uart5 {
+        status = "okay";
+};
+
+&usbotg1 {
+        status = "okay";
+};
+
+&usbotg2 {
+        vbus-supply = <&reg_usbh_vbus>;
+        status = "okay";
+};
+
+&usdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
+        no-1-8-v;
+        cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+        disable-wp;
+        wakeup-source;
+        keep-power-in-suspend;
+        vmmc-supply = <&reg_3v3>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
new file mode 100644
index 000000000000..10ab4697950f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 Toradex AG
+ */
+
+#include "imx6ull-colibri.dtsi"
+
+/ {
+        memory@80000000 {
+                reg = <0x80000000 0x10000000>;
+        };
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
+                &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6>;
+};
+
+&iomuxc_snvs {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2 &pinctrl_snvs_gpio3>;
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
new file mode 100644
index 000000000000..df72ce1ae2cb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 Toradex AG
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-eval-v3.dtsi"
+
+/ {
+        model = "Toradex Colibri iMX6ULL 512MB on Colibri Evaluation Board V3";
+        compatible = "toradex,colibri-imx6ull-wifi-eval", "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
new file mode 100644
index 000000000000..3dffbcd50bf6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 Toradex AG
+ */
+
+#include "imx6ull-colibri.dtsi"
+
+/ {
+        memory@80000000 {
+                reg = <0x80000000 0x20000000>;
+        };
+
+        wifi_pwrseq: sdio-pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_snvs_wifi_pdn>;
+                reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+        };
+};
+
+&cpu0 {
+        clock-frequency = <792000000>;
+        operating-points = <
+                /* kHz  uV */
+                792000  1225000
+                528000  1175000
+                396000  1025000
+                198000  950000
+        >;
+        fsl,soc-operating-points = <
+                /* KHz  uV */
+                792000  1175000
+                528000  1175000
+                396000  1175000
+                198000  1175000
+        >;
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
+                &pinctrl_gpio4 &pinctrl_gpio5>;
+
+};
+
+&iomuxc_snvs {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2>;
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
+        assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+        assigned-clock-rates = <0>, <198000000>;
+        cap-power-off-card;
+        keep-power-in-suspend;
+        mmc-pwrseq = <&wifi_pwrseq>;
+        no-1-8-v;
+        non-removable;
+        vmmc-supply = <&reg_module_3v3>;
+        wakeup-source;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
new file mode 100644
index 000000000000..6c63a7384611
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -0,0 +1,553 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 Toradex AG
+ */
+
+#include "imx6ull.dtsi"
+
+/ {
+        aliases {
+                ethernet0 = &fec2;
+                ethernet1 = &fec1;
+        };
+
+        bl: backlight {
+                compatible = "pwm-backlight";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_bl_on>;
+                enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+                status = "disabled";
+        };
+
+        reg_module_3v3: regulator-module-3v3 {
+                compatible = "regulator-fixed";
+                regulator-always-on;
+                regulator-name = "+V3.3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        reg_module_3v3_avdd: regulator-module-3v3-avdd {
+                compatible = "regulator-fixed";
+                regulator-always-on;
+                regulator-name = "+V3.3_AVDD_AUDIO";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        reg_sd1_vmmc: regulator-sd1-vmmc {
+                compatible = "regulator-gpio";
+                gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_snvs_reg_sd>;
+                regulator-always-on;
+                regulator-name = "+V3.3_1.8_SD";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+                states = <1800000 0x1 3300000 0x0>;
+                vin-supply = <&reg_module_3v3>;
+        };
+};
+
+&adc1 {
+        num-channels = <10>;
+        vref-supply = <&reg_module_3v3_avdd>;
+};
+
+/* Colibri SPI */
+&ecspi1 {
+        cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
+};
+
+&fec2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet2>;
+        phy-mode = "rmii";
+        phy-handle = <&ethphy1>;
+        status = "okay";
+
+        mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ethphy1: ethernet-phy@2 {
+                        compatible = "ethernet-phy-ieee802.3-c22";
+                        max-speed = <100>;
+                        reg = <2>;
+                };
+        };
+};
+
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        nand-on-flash-bbt;
+        nand-ecc-mode = "hw";
+        nand-ecc-strength = <8>;
+        nand-ecc-step-size = <512>;
+        status = "okay";
+};
+
+&i2c1 {
+        pinctrl-names = "default", "gpio";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        pinctrl-1 = <&pinctrl_i2c1_gpio>;
+        sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+        scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+};
+
+&i2c2 {
+        pinctrl-names = "default", "gpio";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        pinctrl-1 = <&pinctrl_i2c2_gpio>;
+        sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+        scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+        status = "okay";
+
+        ad7879@2c {
+                compatible = "adi,ad7879-1";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
+                reg = <0x2c>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+                touchscreen-max-pressure = <4096>;
+                adi,resistance-plate-x = <120>;
+                adi,first-conversion-delay = /bits/ 8 <3>;
+                adi,acquisition-time = /bits/ 8 <1>;
+                adi,median-filter-size = /bits/ 8 <2>;
+                adi,averaging = /bits/ 8 <1>;
+                adi,conversion-interval = /bits/ 8 <255>;
+        };
+};
+
+&lcdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcdif_dat
+                     &pinctrl_lcdif_ctrl>;
+};
+
+&pwm4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm4>;
+        #pwm-cells = <3>;
+};
+
+&pwm5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm5>;
+        #pwm-cells = <3>;
+};
+
+&pwm6 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm6>;
+        #pwm-cells = <3>;
+};
+
+&pwm7 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm7>;
+        #pwm-cells = <3>;
+};
+
+&sdma {
+        status = "okay";
+};
+
+&snvs_pwrkey {
+        status = "disabled";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
+        uart-has-rtscts;
+        fsl,dte-mode;
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        uart-has-rtscts;
+        fsl,dte-mode;
+};
+
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        fsl,dte-mode;
+};
+
+&usbotg1 {
+        dr_mode = "otg";
+        srp-disable;
+        hnp-disable;
+        adp-disable;
+};
+
+&usbotg2 {
+        dr_mode = "host";
+};
+
+&usdhc1 {
+        assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
+        assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+        assigned-clock-rates = <0>, <198000000>;
+};
+
+&iomuxc {
+        pinctrl_can_int: canint-grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04    0X14 /* SODIMM 73 */
+                >;
+        };
+
+        pinctrl_enet2: enet2-grp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
+                        MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
+                        MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+                        MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+                        MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
+                        MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
+                        MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
+                        MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+                        MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+                        MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
+                >;
+        };
+
+        pinctrl_ecspi1_cs: ecspi1-cs-grp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_DATA21__GPIO3_IO26        0x000a0
+                >;
+        };
+
+        pinctrl_ecspi1: ecspi1-grp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK       0x000a0
+                        MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI       0x000a0
+                        MX6UL_PAD_LCD_DATA23__ECSPI1_MISO       0x100a0
+                >;
+        };
+
+        pinctrl_flexcan2: flexcan2-grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX   0x1b020
+                        MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX      0x1b020
+                >;
+        };
+
+        pinctrl_gpio_bl_on: gpio-bl-on-grp {
+                fsl,pins = <
+                        MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x000a0
+                >;
+        };
+
+        pinctrl_gpio1: gpio1-grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00    0x74 /* SODIMM 55 */
+                        MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01    0x74 /* SODIMM 63 */
+                        MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25     0X14 /* SODIMM 77 */
+                        MX6UL_PAD_JTAG_TCK__GPIO1_IO14          0x14 /* SODIMM 99 */
+                        MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x14 /* SODIMM 133 */
+                        MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24     0x14 /* SODIMM 135 */
+                        MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x14 /* SODIMM 100 */
+                        MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15       0x14 /* SODIMM 102 */
+                        MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07       0x14 /* SODIMM 104 */
+                        MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x14 /* SODIMM 186 */
+                >;
+        };
+
+        pinctrl_gpio2: gpio2-grp { /* Camera */
+                fsl,pins = <
+                        MX6UL_PAD_CSI_DATA04__GPIO4_IO25        0x74 /* SODIMM 69 */
+                        MX6UL_PAD_CSI_MCLK__GPIO4_IO17          0x14 /* SODIMM 75 */
+                        MX6UL_PAD_CSI_DATA06__GPIO4_IO27        0x14 /* SODIMM 85 */
+                        MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18        0x14 /* SODIMM 96 */
+                        MX6UL_PAD_CSI_DATA05__GPIO4_IO26        0x14 /* SODIMM 98 */
+                >;
+        };
+
+        pinctrl_gpio3: gpio3-grp { /* CAN2 */
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02       0x14 /* SODIMM 178 */
+                        MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03    0x14 /* SODIMM 188 */
+                >;
+        };
+
+        pinctrl_gpio4: gpio4-grp {
+                fsl,pins = <
+                        MX6UL_PAD_CSI_DATA07__GPIO4_IO28        0x74 /* SODIMM 65 */
+                >;
+        };
+
+        pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
+                fsl,pins = <
+                        MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x74 /* SODIMM 106 */
+                >;
+        };
+
+        pinctrl_gpio6: gpio6-grp { /* Wifi pins */
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x14 /* SODIMM 89 */
+                        MX6UL_PAD_CSI_DATA02__GPIO4_IO23        0x14 /* SODIMM 79 */
+                        MX6UL_PAD_CSI_VSYNC__GPIO4_IO19         0x14 /* SODIMM 81 */
+                        MX6UL_PAD_CSI_DATA03__GPIO4_IO24        0x14 /* SODIMM 97 */
+                        MX6UL_PAD_CSI_DATA00__GPIO4_IO21        0x14 /* SODIMM 101 */
+                        MX6UL_PAD_CSI_DATA01__GPIO4_IO22        0x14 /* SODIMM 103 */
+                        MX6UL_PAD_CSI_HSYNC__GPIO4_IO20         0x14 /* SODIMM 94 */
+                >;
+        };
+
+        pinctrl_gpmi_nand: gpmi-nand-grp {
+                fsl,pins = <
+                        MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x100a9
+                        MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x100a9
+                        MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x100a9
+                        MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x100a9
+                        MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x100a9
+                        MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x100a9
+                        MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x100a9
+                        MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x100a9
+                        MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x100a9
+                        MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x100a9
+                        MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x100a9
+                        MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x100a9
+                        MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x100a9
+                        MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
+                >;
+        };
+
+        pinctrl_i2c1: i2c1-grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+                        MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+                >;
+        };
+
+        pinctrl_i2c1_gpio: i2c1-gpio-grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
+                        MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
+                >;
+        };
+
+        pinctrl_i2c2: i2c2-grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+                        MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+                >;
+        };
+
+        pinctrl_i2c2_gpio: i2c2-gpio-grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
+                        MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
+                >;
+        };
+
+        pinctrl_lcdif_dat: lcdif-dat-grp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x00079
+                        MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x00079
+                        MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x00079
+                        MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x00079
+                        MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x00079
+                        MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x00079
+                        MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x00079
+                        MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x00079
+                        MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x00079
+                        MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x00079
+                        MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x00079
+                        MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x00079
+                        MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x00079
+                        MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x00079
+                        MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x00079
+                        MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x00079
+                        MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x00079
+                        MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x00079
+                >;
+        };
+
+        pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x00079
+                        MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x00079
+                        MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x00079
+                        MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x00079
+                >;
+        };
+
+        pinctrl_pwm4: pwm4-grp {
+                fsl,pins = <
+                        MX6UL_PAD_NAND_WP_B__PWM4_OUT   0x00079
+                >;
+        };
+
+        pinctrl_pwm5: pwm5-grp {
+                fsl,pins = <
+                        MX6UL_PAD_NAND_DQS__PWM5_OUT    0x00079
+                >;
+        };
+
+        pinctrl_pwm6: pwm6-grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079
+                >;
+        };
+
+        pinctrl_pwm7: pwm7-grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT        0x00079
+                >;
+        };
+
+        pinctrl_uart1: uart1-grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX   0x1b0b1
+                        MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX   0x1b0b1
+                        MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS    0x1b0b1
+                        MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS    0x1b0b1
+                >;
+        };
+
+        pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
+                fsl,pins = <
+                        MX6UL_PAD_JTAG_TDI__GPIO1_IO13          0x1b0b1 /* DCD */
+                        MX6UL_PAD_LCD_DATA18__GPIO3_IO23        0x1b0b1 /* DSR */
+                        MX6UL_PAD_JTAG_TDO__GPIO1_IO12          0x1b0b1 /* DTR */
+                        MX6UL_PAD_LCD_DATA19__GPIO3_IO24        0x1b0b1 /* RI */
+                >;
+        };
+
+        pinctrl_uart2: uart2-grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX   0x1b0b1
+                        MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX   0x1b0b1
+                        MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS    0x1b0b1
+                        MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS    0x1b0b1
+                >;
+        };
+        pinctrl_uart5: uart5-grp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX      0x1b0b1
+                        MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX      0x1b0b1
+                >;
+        };
+
+        pinctrl_usbh_reg: gpio-usbh-reg {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x1b0b1 /* SODIMM 129 USBH PEN */
+                >;
+        };
+
+        pinctrl_usdhc1: usdhc1-grp {
+                fsl,pins = <
+                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x17059
+                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x10059
+                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
+                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
+                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
+                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
+                >;
+        };
+
+        pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
+                fsl,pins = <
+                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x170b9
+                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x100b9
+                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170b9
+                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170b9
+                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170b9
+                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170b9
+                >;
+        };
+
+        pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
+                fsl,pins = <
+                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x170f9
+                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x100f9
+                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170b9
+                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170b9
+                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170b9
+                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170b9
+                >;
+        };
+
+        pinctrl_usdhc2: usdhc2-grp {
+                fsl,pins = <
+                        MX6UL_PAD_CSI_DATA00__USDHC2_DATA0      0x17059
+                        MX6UL_PAD_CSI_DATA01__USDHC2_DATA1      0x17059
+                        MX6UL_PAD_CSI_DATA02__USDHC2_DATA2      0x17059
+                        MX6UL_PAD_CSI_DATA03__USDHC2_DATA3      0x17059
+                        MX6UL_PAD_CSI_HSYNC__USDHC2_CMD         0x17059
+                        MX6UL_PAD_CSI_VSYNC__USDHC2_CLK         0x17059
+
+                        MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT    0x14
+                >;
+        };
+};
+
+&iomuxc_snvs {
+        pinctrl_snvs_gpio1: snvs-gpio1-grp {
+                fsl,pins = <
+                        MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06     0x14 /* SODIMM 93 */
+                        MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03     0x14 /* SODIMM 95 */
+                        MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10       0x74 /* SODIMM 105 */
+                        MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05     0x14 /* SODIMM 131 USBH OC */
+                        MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08     0x74 /* SODIMM 138 */
+                >;
+        };
+
+        pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
+                fsl,pins = <
+                        MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04     0x74 /* SODIMM 107 */
+                >;
+        };
+
+        pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
+                fsl,pins = <
+                        MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11       0x14 /* SODIMM 127 */
+                >;
+        };
+
+        pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
+                fsl,pins = <
+                        MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07     0x1b0b0
+                >;
+        };
+
+        pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
+                fsl,pins = <
+                        MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09     0x4001b8b0
+                >;
+        };
+
+        pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
+                fsl,pins = <
+                        MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02     0x1b0b0
+                >;
+        };
+
+        pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
+                fsl,pins = <
+                        MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01     0x130b0
+                >;
+        };
+
+        pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
+                fsl,pins = <
+                        MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00     0x1b0b0 /* CD */
+                >;
+        };
+
+        pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
+                fsl,pins = <
+                        MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11       0x14
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h b/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h
new file mode 100644
index 000000000000..f6fb6783c193
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ */
+
+#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H
+#define __DTS_IMX6ULL_PINFUNC_SNVS_H
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10                          0x0000 0x0044 0x0000 0x5 0x0
+#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11                          0x0004 0x0048 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00                        0x0008 0x004C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01                        0x000C 0x0050 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02                        0x0010 0x0054 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03                        0x0014 0x0058 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04                        0x0018 0x005C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05                        0x001C 0x0060 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06                        0x0020 0x0064 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07                        0x0024 0x0068 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08                        0x0028 0x006C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09                        0x002C 0x0070 0x0000 0x5 0x0
+
+#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index 0c182917b863..571ddd71cdba 100644
--- a/arch/arm/boot/dts/imx6ull.dtsi
+++ b/arch/arm/boot/dts/imx6ull.dtsi
@@ -41,3 +41,35 @@
 
 #include "imx6ul.dtsi"
 #include "imx6ull-pinfunc.h"
+#include "imx6ull-pinfunc-snvs.h"
+
+/* Delete UART8 in AIPS-1 (i.MX6UL specific) */
+/delete-node/ &uart8;
+
+/ {
+        soc {
+                aips3: aips-bus@2200000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x02200000 0x100000>;
+                        ranges;
+
+                        iomuxc_snvs: iomuxc-snvs@2290000 {
+                                compatible = "fsl,imx6ull-iomuxc-snvs";
+                                reg = <0x02290000 0x4000>;
+                        };
+
+                        uart8: serial@2288000 {
+                                compatible = "fsl,imx6ul-uart",
+                                             "fsl,imx6q-uart";
+                                reg = <0x02288000 0x4000>;
+                                interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX6UL_CLK_UART8_IPG>,
+                                         <&clks IMX6UL_CLK_UART8_SERIAL>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
index ae45af1ad062..7f645683f53b 100644
--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
+++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -18,7 +18,7 @@
         model = "CompuLab CL-SOM-iMX7";
         compatible = "compulab,cl-som-imx7", "fsl,imx7d";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */
         };
 
@@ -213,37 +213,37 @@
 &iomuxc {
         pinctrl_enet1: enet1grp {
                 fsl,pins = <
-                        MX7D_PAD_SD2_CD_B__ENET1_MDIO                   0x3
-                        MX7D_PAD_SD2_WP__ENET1_MDC                      0x3
-                        MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
-                        MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
-                        MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
-                        MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
-                        MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
-                        MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
-                        MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
-                        MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
-                        MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
-                        MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
-                        MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
-                        MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
+                        MX7D_PAD_SD2_CD_B__ENET1_MDIO                   0x30
+                        MX7D_PAD_SD2_WP__ENET1_MDC                      0x30
+                        MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x11
+                        MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x11
+                        MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x11
+                        MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x11
+                        MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x11
+                        MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x11
+                        MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x11
+                        MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x11
+                        MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x11
+                        MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x11
+                        MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x11
+                        MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
                 >;
         };
 
         pinctrl_enet2: enet2grp {
                 fsl,pins = <
-                        MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x1
-                        MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x1
-                        MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x1
-                        MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x1
-                        MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x1
-                        MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x1
-                        MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x1
-                        MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x1
-                        MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x1
-                        MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x1
-                        MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x1
-                        MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x1
+                        MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x11
+                        MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x11
+                        MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x11
+                        MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x11
+                        MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x11
+                        MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x11
+                        MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x11
+                        MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x11
+                        MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x11
+                        MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x11
+                        MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x11
+                        MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x11
                 >;
         };
 
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
index 9b63b9c89e4b..04d24ee17b14 100644
--- a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
@@ -7,7 +7,7 @@
 #include "imx7-colibri.dtsi"
 
 / {
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi
index 6f2bb70c1fbd..d9f8fb69511b 100644
--- a/arch/arm/boot/dts/imx7d-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7d-colibri.dtsi
@@ -44,7 +44,7 @@
 #include "imx7-colibri.dtsi"
 
 / {
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x20000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts
index 2b05898bb3f6..52167298984d 100644
--- a/arch/arm/boot/dts/imx7d-nitrogen7.dts
+++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts
@@ -53,7 +53,7 @@
                 t_lcd = &t_lcd;
         };
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi
index e307462a48ec..21973eb55671 100644
--- a/arch/arm/boot/dts/imx7d-pico.dtsi
+++ b/arch/arm/boot/dts/imx7d-pico.dtsi
@@ -48,7 +48,7 @@
         model = "Technexion Pico i.MX7D Board";
         compatible = "technexion,imx7d-pico", "fsl,imx7d";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index a7a5dc7b2700..7f241afc15ea 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -48,7 +48,7 @@
         model = "Freescale i.MX7 SabreSD Board";
         compatible = "fsl,imx7d-sdb", "fsl,imx7d";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x80000000>;
         };
 
@@ -336,6 +336,11 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_i2c2>;
         status = "okay";
+
+        mpl3115@60 {
+                compatible = "fsl,mpl3115";
+                reg = <0x60>;
+        };
 };
 
 &i2c3 {
diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/imx7s-colibri.dtsi
index b81013455b21..fe8344cee864 100644
--- a/arch/arm/boot/dts/imx7s-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7s-colibri.dtsi
@@ -44,7 +44,7 @@
 #include "imx7-colibri.dtsi"
 
 / {
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x10000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts
index 9bdf121f7e43..8a30b148534d 100644
--- a/arch/arm/boot/dts/imx7s-warp.dts
+++ b/arch/arm/boot/dts/imx7s-warp.dts
@@ -50,7 +50,7 @@
         model = "Warp i.MX7 Board";
         compatible = "warp,imx7s-warp", "fsl,imx7s";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x20000000>;
         };
 
@@ -271,6 +271,15 @@
         status = "okay";
 };
 
+&uart6 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart6>;
+        assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
+        assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+        fsl,dte-mode;
+        status = "okay";
+};
+
 &usbotg1 {
         dr_mode = "peripheral";
         status = "okay";
@@ -379,6 +388,13 @@
                 >;
         };
 
+        pinctrl_uart6: uart6grp {
+                fsl,pins = <
+                        MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX      0x79
+                        MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX      0x79
+                >;
+        };
+
         pinctrl_usdhc1: usdhc1grp {
                 fsl,pins = <
                         MX7D_PAD_SD1_CMD__SD1_CMD       0x59
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 39fae570f230..4d42335c0dee 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -58,7 +58,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 gpio0 = &gpio1;
@@ -130,6 +130,12 @@
                 #phy-cells = <0>;
         };
 
+        pmu {
+                compatible = "arm,cortex-a7-pmu";
+                interrupt-parent = <&gpc>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-affinity = <&cpu0>;
+        };
 
         replicator {
                 /*
@@ -519,9 +525,29 @@
                         };
 
                         ocotp: ocotp-ctrl@30350000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
                                 compatible = "fsl,imx7d-ocotp", "syscon";
                                 reg = <0x30350000 0x10000>;
                                 clocks = <&clks IMX7D_OCOTP_CLK>;
+
+                                tempmon_calib: calib@3c {
+                                        reg = <0x3c 0x4>;
+                                };
+
+                                tempmon_temp_grade: temp-grade@10 {
+                                        reg = <0x10 0x4>;
+                                };
+                        };
+
+                        tempmon: tempmon {
+                                compatible = "fsl,imx7d-tempmon";
+                                interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+                                fsl,tempmon =<&anatop>;
+                                nvmem-cells = <&tempmon_calib>,
+                                        <&tempmon_temp_grade>;
+                                nvmem-cell-names = "calib", "temp_grade";
+                                clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
                         };
 
                         anatop: anatop@30360000 {
@@ -718,118 +744,126 @@
                         reg = <0x30800000 0x400000>;
                         ranges;
 
-                        ecspi1: ecspi@30820000 {
+                        spba-bus@30800000 {
+                                compatible = "fsl,spba-bus", "simple-bus";
                                 #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
-                                reg = <0x30820000 0x10000>;
-                                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
-                                        <&clks IMX7D_ECSPI1_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
+                                #size-cells = <1>;
+                                reg = <0x30800000 0x100000>;
+                                ranges;
 
-                        ecspi2: ecspi@30830000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
-                                reg = <0x30830000 0x10000>;
-                                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
-                                        <&clks IMX7D_ECSPI2_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
+                                ecspi1: ecspi@30820000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x30820000 0x10000>;
+                                        interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
+                                                <&clks IMX7D_ECSPI1_ROOT_CLK>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
 
-                        ecspi3: ecspi@30840000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
-                                reg = <0x30840000 0x10000>;
-                                interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
-                                        <&clks IMX7D_ECSPI3_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
+                                ecspi2: ecspi@30830000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x30830000 0x10000>;
+                                        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
+                                                <&clks IMX7D_ECSPI2_ROOT_CLK>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
 
-                        uart1: serial@30860000 {
-                                compatible = "fsl,imx7d-uart",
-                                             "fsl,imx6q-uart";
-                                reg = <0x30860000 0x10000>;
-                                interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_UART1_ROOT_CLK>,
-                                        <&clks IMX7D_UART1_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
+                                ecspi3: ecspi@30840000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x30840000 0x10000>;
+                                        interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
+                                                <&clks IMX7D_ECSPI3_ROOT_CLK>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
 
-                        uart2: serial@30890000 {
-                                compatible = "fsl,imx7d-uart",
-                                             "fsl,imx6q-uart";
-                                reg = <0x30890000 0x10000>;
-                                interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_UART2_ROOT_CLK>,
-                                        <&clks IMX7D_UART2_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
+                                uart1: serial@30860000 {
+                                        compatible = "fsl,imx7d-uart",
+                                                     "fsl,imx6q-uart";
+                                        reg = <0x30860000 0x10000>;
+                                        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_UART1_ROOT_CLK>,
+                                                <&clks IMX7D_UART1_ROOT_CLK>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
 
-                        uart3: serial@30880000 {
-                                compatible = "fsl,imx7d-uart",
-                                             "fsl,imx6q-uart";
-                                reg = <0x30880000 0x10000>;
-                                interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_UART3_ROOT_CLK>,
-                                        <&clks IMX7D_UART3_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
+                                uart2: serial@30890000 {
+                                        compatible = "fsl,imx7d-uart",
+                                                     "fsl,imx6q-uart";
+                                        reg = <0x30890000 0x10000>;
+                                        interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_UART2_ROOT_CLK>,
+                                                <&clks IMX7D_UART2_ROOT_CLK>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
 
-                        sai1: sai@308a0000 {
-                                #sound-dai-cells = <0>;
-                                compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
-                                reg = <0x308a0000 0x10000>;
-                                interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_SAI1_IPG_CLK>,
-                                         <&clks IMX7D_SAI1_ROOT_CLK>,
-                                         <&clks IMX7D_CLK_DUMMY>,
-                                         <&clks IMX7D_CLK_DUMMY>;
-                                clock-names = "bus", "mclk1", "mclk2", "mclk3";
-                                dma-names = "rx", "tx";
-                                dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
-                                status = "disabled";
-                        };
+                                uart3: serial@30880000 {
+                                        compatible = "fsl,imx7d-uart",
+                                                     "fsl,imx6q-uart";
+                                        reg = <0x30880000 0x10000>;
+                                        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_UART3_ROOT_CLK>,
+                                                <&clks IMX7D_UART3_ROOT_CLK>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
 
-                        sai2: sai@308b0000 {
-                                #sound-dai-cells = <0>;
-                                compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
-                                reg = <0x308b0000 0x10000>;
-                                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_SAI2_IPG_CLK>,
-                                         <&clks IMX7D_SAI2_ROOT_CLK>,
-                                         <&clks IMX7D_CLK_DUMMY>,
-                                         <&clks IMX7D_CLK_DUMMY>;
-                                clock-names = "bus", "mclk1", "mclk2", "mclk3";
-                                dma-names = "rx", "tx";
-                                dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
-                                status = "disabled";
-                        };
+                                sai1: sai@308a0000 {
+                                        #sound-dai-cells = <0>;
+                                        compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+                                        reg = <0x308a0000 0x10000>;
+                                        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_SAI1_IPG_CLK>,
+                                                 <&clks IMX7D_SAI1_ROOT_CLK>,
+                                                 <&clks IMX7D_CLK_DUMMY>,
+                                                 <&clks IMX7D_CLK_DUMMY>;
+                                        clock-names = "bus", "mclk1", "mclk2", "mclk3";
+                                        dma-names = "rx", "tx";
+                                        dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
+                                        status = "disabled";
+                                };
 
-                        sai3: sai@308c0000 {
-                                #sound-dai-cells = <0>;
-                                compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
-                                reg = <0x308c0000 0x10000>;
-                                interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_SAI3_IPG_CLK>,
-                                         <&clks IMX7D_SAI3_ROOT_CLK>,
-                                         <&clks IMX7D_CLK_DUMMY>,
-                                         <&clks IMX7D_CLK_DUMMY>;
-                                clock-names = "bus", "mclk1", "mclk2", "mclk3";
-                                dma-names = "rx", "tx";
-                                dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
-                                status = "disabled";
+                                sai2: sai@308b0000 {
+                                        #sound-dai-cells = <0>;
+                                        compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+                                        reg = <0x308b0000 0x10000>;
+                                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_SAI2_IPG_CLK>,
+                                                 <&clks IMX7D_SAI2_ROOT_CLK>,
+                                                 <&clks IMX7D_CLK_DUMMY>,
+                                                 <&clks IMX7D_CLK_DUMMY>;
+                                        clock-names = "bus", "mclk1", "mclk2", "mclk3";
+                                        dma-names = "rx", "tx";
+                                        dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
+                                        status = "disabled";
+                                };
+
+                                sai3: sai@308c0000 {
+                                        #sound-dai-cells = <0>;
+                                        compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+                                        reg = <0x308c0000 0x10000>;
+                                        interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_SAI3_IPG_CLK>,
+                                                 <&clks IMX7D_SAI3_ROOT_CLK>,
+                                                 <&clks IMX7D_CLK_DUMMY>,
+                                                 <&clks IMX7D_CLK_DUMMY>;
+                                        clock-names = "bus", "mclk1", "mclk2", "mclk3";
+                                        dma-names = "rx", "tx";
+                                        dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
+                                        status = "disabled";
+                                };
                         };
 
                         crypto: caam@30900000 {
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c31dad98f989..fbd2897566c3 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -788,5 +788,21 @@
                         clock-names = "ipg", "per";
                         big-endian;
                 };
+
+                ocram1: sram@10000000 {
+                        compatible = "mmio-sram";
+                        reg = <0x0 0x10000000 0x0 0x10000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x0 0x0 0x10000000 0x10000>;
+                };
+
+                ocram2: sram@10010000 {
+                        compatible = "mmio-sram";
+                        reg = <0x0 0x10010000 0x0 0x10000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x0 0x0 0x10010000 0x10000>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/vf500-colibri.dtsi b/arch/arm/boot/dts/vf500-colibri.dtsi
index 515c4d2f28b0..2e7e3cebba1c 100644
--- a/arch/arm/boot/dts/vf500-colibri.dtsi
+++ b/arch/arm/boot/dts/vf500-colibri.dtsi
@@ -46,7 +46,7 @@
         model = "Toradex Colibri VF50 COM";
         compatible = "toradex,vf610-colibri_vf50", "fsl,vf500";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x8000000>;
         };
 
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index 348bcd30c0f7..bbff0115e2fb 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -39,11 +39,16 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "skeleton.dtsi"
 #include "vfxxx.dtsi"
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        chosen { };
+        aliases { };
+        memory { device_type = "memory"; };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi
index 395812c52933..aeaf99f1f0fc 100644
--- a/arch/arm/boot/dts/vf610-colibri.dtsi
+++ b/arch/arm/boot/dts/vf610-colibri.dtsi
@@ -46,7 +46,7 @@
         model = "Toradex Colibri VF61 COM";
         compatible = "toradex,vf610-colibri_vf61", "fsl,vf610";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x10000000>;
         };
 };
diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts
index 5447f2594659..a3014e8d97a9 100644
--- a/arch/arm/boot/dts/vf610-cosmic.dts
+++ b/arch/arm/boot/dts/vf610-cosmic.dts
@@ -19,7 +19,7 @@
                 bootargs = "console=ttyLP1,115200";
         };
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x10000000>;
         };
 
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index 6f787e67bd2e..6be7a828ae64 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -50,7 +50,7 @@
                 bootargs = "console=ttyLP1,115200";
         };
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x8000000>;
         };
 
diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi
index aadd36db0092..4890b8a5aa44 100644
--- a/arch/arm/boot/dts/vf610-zii-dev.dtsi
+++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi
@@ -49,7 +49,7 @@
                 stdout-path = "serial0:115200n8";
         };
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/vf610m4-colibri.dts b/arch/arm/boot/dts/vf610m4-colibri.dts
index 5532e40e350a..41ec66a96990 100644
--- a/arch/arm/boot/dts/vf610m4-colibri.dts
+++ b/arch/arm/boot/dts/vf610m4-colibri.dts
@@ -54,7 +54,7 @@
                 stdout-path = "&uart2";
         };
 
-        memory {
+        memory@8c000000 {
                 reg = <0x8c000000 0x3000000>;
         };
 };
diff --git a/arch/arm/boot/dts/vf610m4.dtsi b/arch/arm/boot/dts/vf610m4.dtsi
index 1474bd34d0f1..8293276b55a6 100644
--- a/arch/arm/boot/dts/vf610m4.dtsi
+++ b/arch/arm/boot/dts/vf610m4.dtsi
@@ -42,10 +42,17 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "skeleton.dtsi"
 #include "armv7-m.dtsi"
 #include "vfxxx.dtsi"
 
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        chosen { };
+        aliases { };
+        memory { device_type = "memory"; };
+};
+
 &mscm_ir {
         interrupt-parent = <&nvic>;
 };