aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/clk/ti/Makefile4
-rw-r--r--drivers/clk/ti/apll.c3
-rw-r--r--drivers/clk/ti/clk-3xxx-legacy.c4656
-rw-r--r--drivers/clk/ti/clk.c205
-rw-r--r--drivers/clk/ti/clkctrl.c42
-rw-r--r--drivers/clk/ti/clock.h73
-rw-r--r--drivers/clk/ti/composite.c48
-rw-r--r--drivers/clk/ti/dpll.c93
-rw-r--r--drivers/clk/ti/gate.c48
-rw-r--r--drivers/clk/ti/interface.c32
10 files changed, 108 insertions, 5096 deletions
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index a2293ee09440..5ab295d2a3cb 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -19,10 +19,6 @@ obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
19 clk-dra7-atl.o dpll3xxx.o dpll44xx.o 19 clk-dra7-atl.o dpll3xxx.o dpll44xx.o
20obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o 20obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o
21 21
22ifdef CONFIG_ATAGS
23obj-$(CONFIG_ARCH_OMAP3) += clk-3xxx-legacy.o
24endif
25
26endif # CONFIG_ARCH_OMAP2PLUS 22endif # CONFIG_ARCH_OMAP2PLUS
27 23
28obj-$(CONFIG_COMMON_CLK_TI_ADPLL) += adpll.o 24obj-$(CONFIG_COMMON_CLK_TI_ADPLL) += adpll.o
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index 83b148f8037c..9498e9363b57 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -133,9 +133,10 @@ static const struct clk_ops apll_ck_ops = {
133 .get_parent = &dra7_init_apll_parent, 133 .get_parent = &dra7_init_apll_parent,
134}; 134};
135 135
136static void __init omap_clk_register_apll(struct clk_hw *hw, 136static void __init omap_clk_register_apll(void *user,
137 struct device_node *node) 137 struct device_node *node)
138{ 138{
139 struct clk_hw *hw = user;
139 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); 140 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
140 struct dpll_data *ad = clk_hw->dpll_data; 141 struct dpll_data *ad = clk_hw->dpll_data;
141 struct clk *clk; 142 struct clk *clk;
diff --git a/drivers/clk/ti/clk-3xxx-legacy.c b/drivers/clk/ti/clk-3xxx-legacy.c
deleted file mode 100644
index 0fbf8a917955..000000000000
--- a/drivers/clk/ti/clk-3xxx-legacy.c
+++ /dev/null
@@ -1,4656 +0,0 @@
1/*
2 * OMAP3 Legacy clock data
3 *
4 * Copyright (C) 2014 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/clk/ti.h>
21
22#include "clock.h"
23
24static struct ti_clk_fixed virt_12m_ck_data = {
25 .frequency = 12000000,
26};
27
28static struct ti_clk virt_12m_ck = {
29 .name = "virt_12m_ck",
30 .type = TI_CLK_FIXED,
31 .data = &virt_12m_ck_data,
32};
33
34static struct ti_clk_fixed virt_13m_ck_data = {
35 .frequency = 13000000,
36};
37
38static struct ti_clk virt_13m_ck = {
39 .name = "virt_13m_ck",
40 .type = TI_CLK_FIXED,
41 .data = &virt_13m_ck_data,
42};
43
44static struct ti_clk_fixed virt_19200000_ck_data = {
45 .frequency = 19200000,
46};
47
48static struct ti_clk virt_19200000_ck = {
49 .name = "virt_19200000_ck",
50 .type = TI_CLK_FIXED,
51 .data = &virt_19200000_ck_data,
52};
53
54static struct ti_clk_fixed virt_26000000_ck_data = {
55 .frequency = 26000000,
56};
57
58static struct ti_clk virt_26000000_ck = {
59 .name = "virt_26000000_ck",
60 .type = TI_CLK_FIXED,
61 .data = &virt_26000000_ck_data,
62};
63
64static struct ti_clk_fixed virt_38_4m_ck_data = {
65 .frequency = 38400000,
66};
67
68static struct ti_clk virt_38_4m_ck = {
69 .name = "virt_38_4m_ck",
70 .type = TI_CLK_FIXED,
71 .data = &virt_38_4m_ck_data,
72};
73
74static struct ti_clk_fixed virt_16_8m_ck_data = {
75 .frequency = 16800000,
76};
77
78static struct ti_clk virt_16_8m_ck = {
79 .name = "virt_16_8m_ck",
80 .type = TI_CLK_FIXED,
81 .data = &virt_16_8m_ck_data,
82};
83
84static const char *osc_sys_ck_parents[] = {
85 "virt_12m_ck",
86 "virt_13m_ck",
87 "virt_19200000_ck",
88 "virt_26000000_ck",
89 "virt_38_4m_ck",
90 "virt_16_8m_ck",
91};
92
93static struct ti_clk_mux osc_sys_ck_data = {
94 .num_parents = ARRAY_SIZE(osc_sys_ck_parents),
95 .reg = 0xd40,
96 .module = TI_CLKM_PRM,
97 .parents = osc_sys_ck_parents,
98};
99
100static struct ti_clk osc_sys_ck = {
101 .name = "osc_sys_ck",
102 .type = TI_CLK_MUX,
103 .data = &osc_sys_ck_data,
104};
105
106static struct ti_clk_divider sys_ck_data = {
107 .parent = "osc_sys_ck",
108 .bit_shift = 6,
109 .max_div = 3,
110 .reg = 0x1270,
111 .module = TI_CLKM_PRM,
112 .flags = CLKF_INDEX_STARTS_AT_ONE,
113};
114
115static struct ti_clk sys_ck = {
116 .name = "sys_ck",
117 .type = TI_CLK_DIVIDER,
118 .data = &sys_ck_data,
119};
120
121static const char *dpll3_ck_parents[] = {
122 "sys_ck",
123 "sys_ck",
124};
125
126static struct ti_clk_dpll dpll3_ck_data = {
127 .num_parents = ARRAY_SIZE(dpll3_ck_parents),
128 .control_reg = 0xd00,
129 .idlest_reg = 0xd20,
130 .mult_div1_reg = 0xd40,
131 .autoidle_reg = 0xd30,
132 .module = TI_CLKM_CM,
133 .parents = dpll3_ck_parents,
134 .flags = CLKF_CORE,
135 .freqsel_mask = 0xf0,
136 .div1_mask = 0x7f00,
137 .idlest_mask = 0x1,
138 .auto_recal_bit = 0x3,
139 .max_divider = 0x80,
140 .min_divider = 0x1,
141 .recal_en_bit = 0x5,
142 .max_multiplier = 0x7ff,
143 .enable_mask = 0x7,
144 .mult_mask = 0x7ff0000,
145 .recal_st_bit = 0x5,
146 .autoidle_mask = 0x7,
147};
148
149static struct ti_clk dpll3_ck = {
150 .name = "dpll3_ck",
151 .clkdm_name = "dpll3_clkdm",
152 .type = TI_CLK_DPLL,
153 .data = &dpll3_ck_data,
154};
155
156static struct ti_clk_divider dpll3_m2_ck_data = {
157 .parent = "dpll3_ck",
158 .bit_shift = 27,
159 .max_div = 31,
160 .reg = 0xd40,
161 .module = TI_CLKM_CM,
162 .flags = CLKF_INDEX_STARTS_AT_ONE,
163};
164
165static struct ti_clk dpll3_m2_ck = {
166 .name = "dpll3_m2_ck",
167 .type = TI_CLK_DIVIDER,
168 .data = &dpll3_m2_ck_data,
169};
170
171static struct ti_clk_fixed_factor core_ck_data = {
172 .parent = "dpll3_m2_ck",
173 .div = 1,
174 .mult = 1,
175};
176
177static struct ti_clk core_ck = {
178 .name = "core_ck",
179 .type = TI_CLK_FIXED_FACTOR,
180 .data = &core_ck_data,
181};
182
183static struct ti_clk_divider l3_ick_data = {
184 .parent = "core_ck",
185 .max_div = 3,
186 .reg = 0xa40,
187 .module = TI_CLKM_CM,
188 .flags = CLKF_INDEX_STARTS_AT_ONE,
189};
190
191static struct ti_clk l3_ick = {
192 .name = "l3_ick",
193 .type = TI_CLK_DIVIDER,
194 .data = &l3_ick_data,
195};
196
197static struct ti_clk_fixed_factor security_l3_ick_data = {
198 .parent = "l3_ick",
199 .div = 1,
200 .mult = 1,
201};
202
203static struct ti_clk security_l3_ick = {
204 .name = "security_l3_ick",
205 .type = TI_CLK_FIXED_FACTOR,
206 .data = &security_l3_ick_data,
207};
208
209static struct ti_clk_fixed_factor wkup_l4_ick_data = {
210 .parent = "sys_ck",
211 .div = 1,
212 .mult = 1,
213};
214
215static struct ti_clk wkup_l4_ick = {
216 .name = "wkup_l4_ick",
217 .type = TI_CLK_FIXED_FACTOR,
218 .data = &wkup_l4_ick_data,
219};
220
221static struct ti_clk_gate usim_ick_data = {
222 .parent = "wkup_l4_ick",
223 .bit_shift = 9,
224 .reg = 0xc10,
225 .module = TI_CLKM_CM,
226 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
227};
228
229static struct ti_clk usim_ick = {
230 .name = "usim_ick",
231 .clkdm_name = "wkup_clkdm",
232 .type = TI_CLK_GATE,
233 .data = &usim_ick_data,
234};
235
236static struct ti_clk_gate dss2_alwon_fck_data = {
237 .parent = "sys_ck",
238 .bit_shift = 1,
239 .reg = 0xe00,
240 .module = TI_CLKM_CM,
241};
242
243static struct ti_clk dss2_alwon_fck = {
244 .name = "dss2_alwon_fck",
245 .clkdm_name = "dss_clkdm",
246 .type = TI_CLK_GATE,
247 .data = &dss2_alwon_fck_data,
248};
249
250static struct ti_clk_divider l4_ick_data = {
251 .parent = "l3_ick",
252 .bit_shift = 2,
253 .max_div = 3,
254 .reg = 0xa40,
255 .module = TI_CLKM_CM,
256 .flags = CLKF_INDEX_STARTS_AT_ONE,
257};
258
259static struct ti_clk l4_ick = {
260 .name = "l4_ick",
261 .type = TI_CLK_DIVIDER,
262 .data = &l4_ick_data,
263};
264
265static struct ti_clk_fixed_factor core_l4_ick_data = {
266 .parent = "l4_ick",
267 .div = 1,
268 .mult = 1,
269};
270
271static struct ti_clk core_l4_ick = {
272 .name = "core_l4_ick",
273 .type = TI_CLK_FIXED_FACTOR,
274 .data = &core_l4_ick_data,
275};
276
277static struct ti_clk_gate mmchs2_ick_data = {
278 .parent = "core_l4_ick",
279 .bit_shift = 25,
280 .reg = 0xa10,
281 .module = TI_CLKM_CM,
282 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
283};
284
285static struct ti_clk mmchs2_ick = {
286 .name = "mmchs2_ick",
287 .clkdm_name = "core_l4_clkdm",
288 .type = TI_CLK_GATE,
289 .data = &mmchs2_ick_data,
290};
291
292static const char *dpll4_ck_parents[] = {
293 "sys_ck",
294 "sys_ck",
295};
296
297static struct ti_clk_dpll dpll4_ck_data = {
298 .num_parents = ARRAY_SIZE(dpll4_ck_parents),
299 .control_reg = 0xd00,
300 .idlest_reg = 0xd20,
301 .mult_div1_reg = 0xd44,
302 .autoidle_reg = 0xd30,
303 .module = TI_CLKM_CM,
304 .parents = dpll4_ck_parents,
305 .flags = CLKF_PER,
306 .freqsel_mask = 0xf00000,
307 .modes = 0x82,
308 .div1_mask = 0x7f,
309 .idlest_mask = 0x2,
310 .auto_recal_bit = 0x13,
311 .max_divider = 0x80,
312 .min_divider = 0x1,
313 .recal_en_bit = 0x6,
314 .max_multiplier = 0x7ff,
315 .enable_mask = 0x70000,
316 .mult_mask = 0x7ff00,
317 .recal_st_bit = 0x6,
318 .autoidle_mask = 0x38,
319};
320
321static struct ti_clk dpll4_ck = {
322 .name = "dpll4_ck",
323 .clkdm_name = "dpll4_clkdm",
324 .type = TI_CLK_DPLL,
325 .data = &dpll4_ck_data,
326};
327
328static struct ti_clk_divider dpll4_m2_ck_data = {
329 .parent = "dpll4_ck",
330 .max_div = 63,
331 .reg = 0xd48,
332 .module = TI_CLKM_CM,
333 .flags = CLKF_INDEX_STARTS_AT_ONE,
334};
335
336static struct ti_clk dpll4_m2_ck = {
337 .name = "dpll4_m2_ck",
338 .type = TI_CLK_DIVIDER,
339 .data = &dpll4_m2_ck_data,
340};
341
342static struct ti_clk_fixed_factor dpll4_m2x2_mul_ck_data = {
343 .parent = "dpll4_m2_ck",
344 .div = 1,
345 .mult = 2,
346};
347
348static struct ti_clk dpll4_m2x2_mul_ck = {
349 .name = "dpll4_m2x2_mul_ck",
350 .type = TI_CLK_FIXED_FACTOR,
351 .data = &dpll4_m2x2_mul_ck_data,
352};
353
354static struct ti_clk_gate dpll4_m2x2_ck_data = {
355 .parent = "dpll4_m2x2_mul_ck",
356 .bit_shift = 0x1b,
357 .reg = 0xd00,
358 .module = TI_CLKM_CM,
359 .flags = CLKF_SET_BIT_TO_DISABLE,
360};
361
362static struct ti_clk dpll4_m2x2_ck = {
363 .name = "dpll4_m2x2_ck",
364 .type = TI_CLK_GATE,
365 .data = &dpll4_m2x2_ck_data,
366};
367
368static struct ti_clk_fixed_factor omap_96m_alwon_fck_data = {
369 .parent = "dpll4_m2x2_ck",
370 .div = 1,
371 .mult = 1,
372};
373
374static struct ti_clk omap_96m_alwon_fck = {
375 .name = "omap_96m_alwon_fck",
376 .type = TI_CLK_FIXED_FACTOR,
377 .data = &omap_96m_alwon_fck_data,
378};
379
380static struct ti_clk_fixed_factor cm_96m_fck_data = {
381 .parent = "omap_96m_alwon_fck",
382 .div = 1,
383 .mult = 1,
384};
385
386static struct ti_clk cm_96m_fck = {
387 .name = "cm_96m_fck",
388 .type = TI_CLK_FIXED_FACTOR,
389 .data = &cm_96m_fck_data,
390};
391
392static const char *omap_96m_fck_parents[] = {
393 "cm_96m_fck",
394 "sys_ck",
395};
396
397static struct ti_clk_mux omap_96m_fck_data = {
398 .bit_shift = 6,
399 .num_parents = ARRAY_SIZE(omap_96m_fck_parents),
400 .reg = 0xd40,
401 .module = TI_CLKM_CM,
402 .parents = omap_96m_fck_parents,
403};
404
405static struct ti_clk omap_96m_fck = {
406 .name = "omap_96m_fck",
407 .type = TI_CLK_MUX,
408 .data = &omap_96m_fck_data,
409};
410
411static struct ti_clk_fixed_factor core_96m_fck_data = {
412 .parent = "omap_96m_fck",
413 .div = 1,
414 .mult = 1,
415};
416
417static struct ti_clk core_96m_fck = {
418 .name = "core_96m_fck",
419 .type = TI_CLK_FIXED_FACTOR,
420 .data = &core_96m_fck_data,
421};
422
423static struct ti_clk_gate mspro_fck_data = {
424 .parent = "core_96m_fck",
425 .bit_shift = 23,
426 .reg = 0xa00,
427 .module = TI_CLKM_CM,
428 .flags = CLKF_WAIT,
429};
430
431static struct ti_clk mspro_fck = {
432 .name = "mspro_fck",
433 .clkdm_name = "core_l4_clkdm",
434 .type = TI_CLK_GATE,
435 .data = &mspro_fck_data,
436};
437
438static struct ti_clk_gate dss_ick_3430es2_data = {
439 .parent = "l4_ick",
440 .bit_shift = 0,
441 .reg = 0xe10,
442 .module = TI_CLKM_CM,
443 .flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE,
444};
445
446static struct ti_clk dss_ick_3430es2 = {
447 .name = "dss_ick",
448 .clkdm_name = "dss_clkdm",
449 .type = TI_CLK_GATE,
450 .data = &dss_ick_3430es2_data,
451};
452
453static struct ti_clk_gate uart4_ick_am35xx_data = {
454 .parent = "core_l4_ick",
455 .bit_shift = 23,
456 .reg = 0xa10,
457 .module = TI_CLKM_CM,
458 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
459};
460
461static struct ti_clk uart4_ick_am35xx = {
462 .name = "uart4_ick_am35xx",
463 .clkdm_name = "core_l4_clkdm",
464 .type = TI_CLK_GATE,
465 .data = &uart4_ick_am35xx_data,
466};
467
468static struct ti_clk_fixed_factor security_l4_ick2_data = {
469 .parent = "l4_ick",
470 .div = 1,
471 .mult = 1,
472};
473
474static struct ti_clk security_l4_ick2 = {
475 .name = "security_l4_ick2",
476 .type = TI_CLK_FIXED_FACTOR,
477 .data = &security_l4_ick2_data,
478};
479
480static struct ti_clk_gate aes1_ick_data = {
481 .parent = "security_l4_ick2",
482 .bit_shift = 3,
483 .reg = 0xa14,
484 .module = TI_CLKM_CM,
485 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
486};
487
488static struct ti_clk aes1_ick = {
489 .name = "aes1_ick",
490 .type = TI_CLK_GATE,
491 .data = &aes1_ick_data,
492};
493
494static const char *dpll5_ck_parents[] = {
495 "sys_ck",
496 "sys_ck",
497};
498
499static struct ti_clk_dpll dpll5_ck_data = {
500 .num_parents = ARRAY_SIZE(dpll5_ck_parents),
501 .control_reg = 0xd04,
502 .idlest_reg = 0xd24,
503 .mult_div1_reg = 0xd4c,
504 .autoidle_reg = 0xd34,
505 .module = TI_CLKM_CM,
506 .parents = dpll5_ck_parents,
507 .freqsel_mask = 0xf0,
508 .modes = 0x82,
509 .div1_mask = 0x7f,
510 .idlest_mask = 0x1,
511 .auto_recal_bit = 0x3,
512 .max_divider = 0x80,
513 .min_divider = 0x1,
514 .recal_en_bit = 0x19,
515 .max_multiplier = 0x7ff,
516 .enable_mask = 0x7,
517 .mult_mask = 0x7ff00,
518 .recal_st_bit = 0x19,
519 .autoidle_mask = 0x7,
520};
521
522static struct ti_clk dpll5_ck = {
523 .name = "dpll5_ck",
524 .clkdm_name = "dpll5_clkdm",
525 .type = TI_CLK_DPLL,
526 .data = &dpll5_ck_data,
527};
528
529static struct ti_clk_divider dpll5_m2_ck_data = {
530 .parent = "dpll5_ck",
531 .max_div = 31,
532 .reg = 0xd50,
533 .module = TI_CLKM_CM,
534 .flags = CLKF_INDEX_STARTS_AT_ONE,
535};
536
537static struct ti_clk dpll5_m2_ck = {
538 .name = "dpll5_m2_ck",
539 .type = TI_CLK_DIVIDER,
540 .data = &dpll5_m2_ck_data,
541};
542
543static struct ti_clk_gate usbhost_120m_fck_data = {
544 .parent = "dpll5_m2_ck",
545 .bit_shift = 1,
546 .reg = 0x1400,
547 .module = TI_CLKM_CM,
548};
549
550static struct ti_clk usbhost_120m_fck = {
551 .name = "usbhost_120m_fck",
552 .clkdm_name = "usbhost_clkdm",
553 .type = TI_CLK_GATE,
554 .data = &usbhost_120m_fck_data,
555};
556
557static struct ti_clk_fixed_factor cm_96m_d2_fck_data = {
558 .parent = "cm_96m_fck",
559 .div = 2,
560 .mult = 1,
561};
562
563static struct ti_clk cm_96m_d2_fck = {
564 .name = "cm_96m_d2_fck",
565 .type = TI_CLK_FIXED_FACTOR,
566 .data = &cm_96m_d2_fck_data,
567};
568
569static struct ti_clk_fixed sys_altclk_data = {
570 .frequency = 0x0,
571};
572
573static struct ti_clk sys_altclk = {
574 .name = "sys_altclk",
575 .type = TI_CLK_FIXED,
576 .data = &sys_altclk_data,
577};
578
579static const char *omap_48m_fck_parents[] = {
580 "cm_96m_d2_fck",
581 "sys_altclk",
582};
583
584static struct ti_clk_mux omap_48m_fck_data = {
585 .bit_shift = 3,
586 .num_parents = ARRAY_SIZE(omap_48m_fck_parents),
587 .reg = 0xd40,
588 .module = TI_CLKM_CM,
589 .parents = omap_48m_fck_parents,
590};
591
592static struct ti_clk omap_48m_fck = {
593 .name = "omap_48m_fck",
594 .type = TI_CLK_MUX,
595 .data = &omap_48m_fck_data,
596};
597
598static struct ti_clk_fixed_factor core_48m_fck_data = {
599 .parent = "omap_48m_fck",
600 .div = 1,
601 .mult = 1,
602};
603
604static struct ti_clk core_48m_fck = {
605 .name = "core_48m_fck",
606 .type = TI_CLK_FIXED_FACTOR,
607 .data = &core_48m_fck_data,
608};
609
610static struct ti_clk_fixed mcbsp_clks_data = {
611 .frequency = 0x0,
612};
613
614static struct ti_clk mcbsp_clks = {
615 .name = "mcbsp_clks",
616 .type = TI_CLK_FIXED,
617 .data = &mcbsp_clks_data,
618};
619
620static struct ti_clk_gate mcbsp2_gate_fck_data = {
621 .parent = "mcbsp_clks",
622 .bit_shift = 0,
623 .reg = 0x1000,
624 .module = TI_CLKM_CM,
625};
626
627static struct ti_clk_fixed_factor per_96m_fck_data = {
628 .parent = "omap_96m_alwon_fck",
629 .div = 1,
630 .mult = 1,
631};
632
633static struct ti_clk per_96m_fck = {
634 .name = "per_96m_fck",
635 .type = TI_CLK_FIXED_FACTOR,
636 .data = &per_96m_fck_data,
637};
638
639static const char *mcbsp2_mux_fck_parents[] = {
640 "per_96m_fck",
641 "mcbsp_clks",
642};
643
644static struct ti_clk_mux mcbsp2_mux_fck_data = {
645 .bit_shift = 6,
646 .num_parents = ARRAY_SIZE(mcbsp2_mux_fck_parents),
647 .reg = 0x274,
648 .module = TI_CLKM_SCRM,
649 .parents = mcbsp2_mux_fck_parents,
650};
651
652static struct ti_clk_composite mcbsp2_fck_data = {
653 .mux = &mcbsp2_mux_fck_data,
654 .gate = &mcbsp2_gate_fck_data,
655};
656
657static struct ti_clk mcbsp2_fck = {
658 .name = "mcbsp2_fck",
659 .type = TI_CLK_COMPOSITE,
660 .data = &mcbsp2_fck_data,
661};
662
663static struct ti_clk_fixed_factor dpll3_m2x2_ck_data = {
664 .parent = "dpll3_m2_ck",
665 .div = 1,
666 .mult = 2,
667};
668
669static struct ti_clk dpll3_m2x2_ck = {
670 .name = "dpll3_m2x2_ck",
671 .type = TI_CLK_FIXED_FACTOR,
672 .data = &dpll3_m2x2_ck_data,
673};
674
675static struct ti_clk_fixed_factor corex2_fck_data = {
676 .parent = "dpll3_m2x2_ck",
677 .div = 1,
678 .mult = 1,
679};
680
681static struct ti_clk corex2_fck = {
682 .name = "corex2_fck",
683 .type = TI_CLK_FIXED_FACTOR,
684 .data = &corex2_fck_data,
685};
686
687static struct ti_clk_gate ssi_ssr_gate_fck_3430es1_data = {
688 .parent = "corex2_fck",
689 .bit_shift = 0,
690 .reg = 0xa00,
691 .module = TI_CLKM_CM,
692 .flags = CLKF_NO_WAIT,
693};
694
695static int ssi_ssr_div_fck_3430es1_divs[] = {
696 0,
697 1,
698 2,
699 3,
700 4,
701 0,
702 6,
703 0,
704 8,
705};
706
707static struct ti_clk_divider ssi_ssr_div_fck_3430es1_data = {
708 .num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es1_divs),
709 .parent = "corex2_fck",
710 .bit_shift = 8,
711 .dividers = ssi_ssr_div_fck_3430es1_divs,
712 .reg = 0xa40,
713 .module = TI_CLKM_CM,
714};
715
716static struct ti_clk_composite ssi_ssr_fck_3430es1_data = {
717 .gate = &ssi_ssr_gate_fck_3430es1_data,
718 .divider = &ssi_ssr_div_fck_3430es1_data,
719};
720
721static struct ti_clk ssi_ssr_fck_3430es1 = {
722 .name = "ssi_ssr_fck",
723 .type = TI_CLK_COMPOSITE,
724 .data = &ssi_ssr_fck_3430es1_data,
725};
726
727static struct ti_clk_fixed_factor ssi_sst_fck_3430es1_data = {
728 .parent = "ssi_ssr_fck",
729 .div = 2,
730 .mult = 1,
731};
732
733static struct ti_clk ssi_sst_fck_3430es1 = {
734 .name = "ssi_sst_fck",
735 .type = TI_CLK_FIXED_FACTOR,
736 .data = &ssi_sst_fck_3430es1_data,
737};
738
739static struct ti_clk_fixed omap_32k_fck_data = {
740 .frequency = 32768,
741};
742
743static struct ti_clk omap_32k_fck = {
744 .name = "omap_32k_fck",
745 .type = TI_CLK_FIXED,
746 .data = &omap_32k_fck_data,
747};
748
749static struct ti_clk_fixed_factor per_32k_alwon_fck_data = {
750 .parent = "omap_32k_fck",
751 .div = 1,
752 .mult = 1,
753};
754
755static struct ti_clk per_32k_alwon_fck = {
756 .name = "per_32k_alwon_fck",
757 .type = TI_CLK_FIXED_FACTOR,
758 .data = &per_32k_alwon_fck_data,
759};
760
761static struct ti_clk_gate gpio5_dbck_data = {
762 .parent = "per_32k_alwon_fck",
763 .bit_shift = 16,
764 .reg = 0x1000,
765 .module = TI_CLKM_CM,
766};
767
768static struct ti_clk gpio5_dbck = {
769 .name = "gpio5_dbck",
770 .clkdm_name = "per_clkdm",
771 .type = TI_CLK_GATE,
772 .data = &gpio5_dbck_data,
773};
774
775static struct ti_clk_gate gpt1_ick_data = {
776 .parent = "wkup_l4_ick",
777 .bit_shift = 0,
778 .reg = 0xc10,
779 .module = TI_CLKM_CM,
780 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
781};
782
783static struct ti_clk gpt1_ick = {
784 .name = "gpt1_ick",
785 .clkdm_name = "wkup_clkdm",
786 .type = TI_CLK_GATE,
787 .data = &gpt1_ick_data,
788};
789
790static struct ti_clk_gate mcspi3_fck_data = {
791 .parent = "core_48m_fck",
792 .bit_shift = 20,
793 .reg = 0xa00,
794 .module = TI_CLKM_CM,
795 .flags = CLKF_WAIT,
796};
797
798static struct ti_clk mcspi3_fck = {
799 .name = "mcspi3_fck",
800 .clkdm_name = "core_l4_clkdm",
801 .type = TI_CLK_GATE,
802 .data = &mcspi3_fck_data,
803};
804
805static struct ti_clk_gate gpt2_gate_fck_data = {
806 .parent = "sys_ck",
807 .bit_shift = 3,
808 .reg = 0x1000,
809 .module = TI_CLKM_CM,
810};
811
812static const char *gpt2_mux_fck_parents[] = {
813 "omap_32k_fck",
814 "sys_ck",
815};
816
817static struct ti_clk_mux gpt2_mux_fck_data = {
818 .num_parents = ARRAY_SIZE(gpt2_mux_fck_parents),
819 .reg = 0x1040,
820 .module = TI_CLKM_CM,
821 .parents = gpt2_mux_fck_parents,
822};
823
824static struct ti_clk_composite gpt2_fck_data = {
825 .mux = &gpt2_mux_fck_data,
826 .gate = &gpt2_gate_fck_data,
827};
828
829static struct ti_clk gpt2_fck = {
830 .name = "gpt2_fck",
831 .type = TI_CLK_COMPOSITE,
832 .data = &gpt2_fck_data,
833};
834
835static struct ti_clk_gate gpt10_ick_data = {
836 .parent = "core_l4_ick",
837 .bit_shift = 11,
838 .reg = 0xa10,
839 .module = TI_CLKM_CM,
840 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
841};
842
843static struct ti_clk gpt10_ick = {
844 .name = "gpt10_ick",
845 .clkdm_name = "core_l4_clkdm",
846 .type = TI_CLK_GATE,
847 .data = &gpt10_ick_data,
848};
849
850static struct ti_clk_gate uart2_fck_data = {
851 .parent = "core_48m_fck",
852 .bit_shift = 14,
853 .reg = 0xa00,
854 .module = TI_CLKM_CM,
855 .flags = CLKF_WAIT,
856};
857
858static struct ti_clk uart2_fck = {
859 .name = "uart2_fck",
860 .clkdm_name = "core_l4_clkdm",
861 .type = TI_CLK_GATE,
862 .data = &uart2_fck_data,
863};
864
865static struct ti_clk_fixed_factor sr_l4_ick_data = {
866 .parent = "l4_ick",
867 .div = 1,
868 .mult = 1,
869};
870
871static struct ti_clk sr_l4_ick = {
872 .name = "sr_l4_ick",
873 .type = TI_CLK_FIXED_FACTOR,
874 .data = &sr_l4_ick_data,
875};
876
877static struct ti_clk_fixed_factor omap_96m_d8_fck_data = {
878 .parent = "omap_96m_fck",
879 .div = 8,
880 .mult = 1,
881};
882
883static struct ti_clk omap_96m_d8_fck = {
884 .name = "omap_96m_d8_fck",
885 .type = TI_CLK_FIXED_FACTOR,
886 .data = &omap_96m_d8_fck_data,
887};
888
889static struct ti_clk_divider dpll4_m5_ck_data = {
890 .parent = "dpll4_ck",
891 .max_div = 63,
892 .reg = 0xf40,
893 .module = TI_CLKM_CM,
894 .flags = CLKF_INDEX_STARTS_AT_ONE,
895};
896
897static struct ti_clk dpll4_m5_ck = {
898 .name = "dpll4_m5_ck",
899 .type = TI_CLK_DIVIDER,
900 .data = &dpll4_m5_ck_data,
901};
902
903static struct ti_clk_fixed_factor dpll4_m5x2_mul_ck_data = {
904 .parent = "dpll4_m5_ck",
905 .div = 1,
906 .mult = 2,
907 .flags = CLKF_SET_RATE_PARENT,
908};
909
910static struct ti_clk dpll4_m5x2_mul_ck = {
911 .name = "dpll4_m5x2_mul_ck",
912 .type = TI_CLK_FIXED_FACTOR,
913 .data = &dpll4_m5x2_mul_ck_data,
914};
915
916static struct ti_clk_gate dpll4_m5x2_ck_data = {
917 .parent = "dpll4_m5x2_mul_ck",
918 .bit_shift = 0x1e,
919 .reg = 0xd00,
920 .module = TI_CLKM_CM,
921 .flags = CLKF_SET_BIT_TO_DISABLE,
922};
923
924static struct ti_clk dpll4_m5x2_ck = {
925 .name = "dpll4_m5x2_ck",
926 .type = TI_CLK_GATE,
927 .data = &dpll4_m5x2_ck_data,
928};
929
930static struct ti_clk_gate cam_mclk_data = {
931 .parent = "dpll4_m5x2_ck",
932 .bit_shift = 0,
933 .reg = 0xf00,
934 .module = TI_CLKM_CM,
935 .flags = CLKF_SET_RATE_PARENT,
936};
937
938static struct ti_clk cam_mclk = {
939 .name = "cam_mclk",
940 .type = TI_CLK_GATE,
941 .data = &cam_mclk_data,
942};
943
944static struct ti_clk_gate mcbsp3_gate_fck_data = {
945 .parent = "mcbsp_clks",
946 .bit_shift = 1,
947 .reg = 0x1000,
948 .module = TI_CLKM_CM,
949};
950
951static const char *mcbsp3_mux_fck_parents[] = {
952 "per_96m_fck",
953 "mcbsp_clks",
954};
955
956static struct ti_clk_mux mcbsp3_mux_fck_data = {
957 .num_parents = ARRAY_SIZE(mcbsp3_mux_fck_parents),
958 .reg = 0x2d8,
959 .module = TI_CLKM_SCRM,
960 .parents = mcbsp3_mux_fck_parents,
961};
962
963static struct ti_clk_composite mcbsp3_fck_data = {
964 .mux = &mcbsp3_mux_fck_data,
965 .gate = &mcbsp3_gate_fck_data,
966};
967
968static struct ti_clk mcbsp3_fck = {
969 .name = "mcbsp3_fck",
970 .type = TI_CLK_COMPOSITE,
971 .data = &mcbsp3_fck_data,
972};
973
974static struct ti_clk_gate csi2_96m_fck_data = {
975 .parent = "core_96m_fck",
976 .bit_shift = 1,
977 .reg = 0xf00,
978 .module = TI_CLKM_CM,
979};
980
981static struct ti_clk csi2_96m_fck = {
982 .name = "csi2_96m_fck",
983 .clkdm_name = "cam_clkdm",
984 .type = TI_CLK_GATE,
985 .data = &csi2_96m_fck_data,
986};
987
988static struct ti_clk_gate gpt9_gate_fck_data = {
989 .parent = "sys_ck",
990 .bit_shift = 10,
991 .reg = 0x1000,
992 .module = TI_CLKM_CM,
993};
994
995static const char *gpt9_mux_fck_parents[] = {
996 "omap_32k_fck",
997 "sys_ck",
998};
999
1000static struct ti_clk_mux gpt9_mux_fck_data = {
1001 .bit_shift = 7,
1002 .num_parents = ARRAY_SIZE(gpt9_mux_fck_parents),
1003 .reg = 0x1040,
1004 .module = TI_CLKM_CM,
1005 .parents = gpt9_mux_fck_parents,
1006};
1007
1008static struct ti_clk_composite gpt9_fck_data = {
1009 .mux = &gpt9_mux_fck_data,
1010 .gate = &gpt9_gate_fck_data,
1011};
1012
1013static struct ti_clk gpt9_fck = {
1014 .name = "gpt9_fck",
1015 .type = TI_CLK_COMPOSITE,
1016 .data = &gpt9_fck_data,
1017};
1018
1019static struct ti_clk_divider dpll3_m3_ck_data = {
1020 .parent = "dpll3_ck",
1021 .bit_shift = 16,
1022 .max_div = 31,
1023 .reg = 0x1140,
1024 .module = TI_CLKM_CM,
1025 .flags = CLKF_INDEX_STARTS_AT_ONE,
1026};
1027
1028static struct ti_clk dpll3_m3_ck = {
1029 .name = "dpll3_m3_ck",
1030 .type = TI_CLK_DIVIDER,
1031 .data = &dpll3_m3_ck_data,
1032};
1033
1034static struct ti_clk_fixed_factor dpll3_m3x2_mul_ck_data = {
1035 .parent = "dpll3_m3_ck",
1036 .div = 1,
1037 .mult = 2,
1038};
1039
1040static struct ti_clk dpll3_m3x2_mul_ck = {
1041 .name = "dpll3_m3x2_mul_ck",
1042 .type = TI_CLK_FIXED_FACTOR,
1043 .data = &dpll3_m3x2_mul_ck_data,
1044};
1045
1046static struct ti_clk_gate sr2_fck_data = {
1047 .parent = "sys_ck",
1048 .bit_shift = 7,
1049 .reg = 0xc00,
1050 .module = TI_CLKM_CM,
1051 .flags = CLKF_WAIT,
1052};
1053
1054static struct ti_clk sr2_fck = {
1055 .name = "sr2_fck",
1056 .clkdm_name = "wkup_clkdm",
1057 .type = TI_CLK_GATE,
1058 .data = &sr2_fck_data,
1059};
1060
1061static struct ti_clk_fixed pclk_ck_data = {
1062 .frequency = 27000000,
1063};
1064
1065static struct ti_clk pclk_ck = {
1066 .name = "pclk_ck",
1067 .type = TI_CLK_FIXED,
1068 .data = &pclk_ck_data,
1069};
1070
1071static struct ti_clk_gate wdt2_ick_data = {
1072 .parent = "wkup_l4_ick",
1073 .bit_shift = 5,
1074 .reg = 0xc10,
1075 .module = TI_CLKM_CM,
1076 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1077};
1078
1079static struct ti_clk wdt2_ick = {
1080 .name = "wdt2_ick",
1081 .clkdm_name = "wkup_clkdm",
1082 .type = TI_CLK_GATE,
1083 .data = &wdt2_ick_data,
1084};
1085
1086static struct ti_clk_fixed_factor core_l3_ick_data = {
1087 .parent = "l3_ick",
1088 .div = 1,
1089 .mult = 1,
1090};
1091
1092static struct ti_clk core_l3_ick = {
1093 .name = "core_l3_ick",
1094 .type = TI_CLK_FIXED_FACTOR,
1095 .data = &core_l3_ick_data,
1096};
1097
1098static struct ti_clk_gate mcspi4_fck_data = {
1099 .parent = "core_48m_fck",
1100 .bit_shift = 21,
1101 .reg = 0xa00,
1102 .module = TI_CLKM_CM,
1103 .flags = CLKF_WAIT,
1104};
1105
1106static struct ti_clk mcspi4_fck = {
1107 .name = "mcspi4_fck",
1108 .clkdm_name = "core_l4_clkdm",
1109 .type = TI_CLK_GATE,
1110 .data = &mcspi4_fck_data,
1111};
1112
1113static struct ti_clk_fixed_factor per_48m_fck_data = {
1114 .parent = "omap_48m_fck",
1115 .div = 1,
1116 .mult = 1,
1117};
1118
1119static struct ti_clk per_48m_fck = {
1120 .name = "per_48m_fck",
1121 .type = TI_CLK_FIXED_FACTOR,
1122 .data = &per_48m_fck_data,
1123};
1124
1125static struct ti_clk_gate uart4_fck_data = {
1126 .parent = "per_48m_fck",
1127 .bit_shift = 18,
1128 .reg = 0x1000,
1129 .module = TI_CLKM_CM,
1130 .flags = CLKF_WAIT,
1131};
1132
1133static struct ti_clk uart4_fck = {
1134 .name = "uart4_fck",
1135 .clkdm_name = "per_clkdm",
1136 .type = TI_CLK_GATE,
1137 .data = &uart4_fck_data,
1138};
1139
1140static struct ti_clk_fixed_factor omap_96m_d10_fck_data = {
1141 .parent = "omap_96m_fck",
1142 .div = 10,
1143 .mult = 1,
1144};
1145
1146static struct ti_clk omap_96m_d10_fck = {
1147 .name = "omap_96m_d10_fck",
1148 .type = TI_CLK_FIXED_FACTOR,
1149 .data = &omap_96m_d10_fck_data,
1150};
1151
1152static struct ti_clk_gate usim_gate_fck_data = {
1153 .parent = "omap_96m_fck",
1154 .bit_shift = 9,
1155 .reg = 0xc00,
1156 .module = TI_CLKM_CM,
1157};
1158
1159static struct ti_clk_fixed_factor per_l4_ick_data = {
1160 .parent = "l4_ick",
1161 .div = 1,
1162 .mult = 1,
1163};
1164
1165static struct ti_clk per_l4_ick = {
1166 .name = "per_l4_ick",
1167 .type = TI_CLK_FIXED_FACTOR,
1168 .data = &per_l4_ick_data,
1169};
1170
1171static struct ti_clk_gate gpt5_ick_data = {
1172 .parent = "per_l4_ick",
1173 .bit_shift = 6,
1174 .reg = 0x1010,
1175 .module = TI_CLKM_CM,
1176 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1177};
1178
1179static struct ti_clk gpt5_ick = {
1180 .name = "gpt5_ick",
1181 .clkdm_name = "per_clkdm",
1182 .type = TI_CLK_GATE,
1183 .data = &gpt5_ick_data,
1184};
1185
1186static struct ti_clk_gate mcspi2_ick_data = {
1187 .parent = "core_l4_ick",
1188 .bit_shift = 19,
1189 .reg = 0xa10,
1190 .module = TI_CLKM_CM,
1191 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1192};
1193
1194static struct ti_clk mcspi2_ick = {
1195 .name = "mcspi2_ick",
1196 .clkdm_name = "core_l4_clkdm",
1197 .type = TI_CLK_GATE,
1198 .data = &mcspi2_ick_data,
1199};
1200
1201static struct ti_clk_fixed_factor ssi_l4_ick_data = {
1202 .parent = "l4_ick",
1203 .div = 1,
1204 .mult = 1,
1205};
1206
1207static struct ti_clk ssi_l4_ick = {
1208 .name = "ssi_l4_ick",
1209 .clkdm_name = "core_l4_clkdm",
1210 .type = TI_CLK_FIXED_FACTOR,
1211 .data = &ssi_l4_ick_data,
1212};
1213
1214static struct ti_clk_gate ssi_ick_3430es1_data = {
1215 .parent = "ssi_l4_ick",
1216 .bit_shift = 0,
1217 .reg = 0xa10,
1218 .module = TI_CLKM_CM,
1219 .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
1220};
1221
1222static struct ti_clk ssi_ick_3430es1 = {
1223 .name = "ssi_ick",
1224 .clkdm_name = "core_l4_clkdm",
1225 .type = TI_CLK_GATE,
1226 .data = &ssi_ick_3430es1_data,
1227};
1228
1229static struct ti_clk_gate i2c2_fck_data = {
1230 .parent = "core_96m_fck",
1231 .bit_shift = 16,
1232 .reg = 0xa00,
1233 .module = TI_CLKM_CM,
1234 .flags = CLKF_WAIT,
1235};
1236
1237static struct ti_clk i2c2_fck = {
1238 .name = "i2c2_fck",
1239 .clkdm_name = "core_l4_clkdm",
1240 .type = TI_CLK_GATE,
1241 .data = &i2c2_fck_data,
1242};
1243
1244static struct ti_clk_divider dpll1_fck_data = {
1245 .parent = "core_ck",
1246 .bit_shift = 19,
1247 .max_div = 7,
1248 .reg = 0x940,
1249 .module = TI_CLKM_CM,
1250 .flags = CLKF_INDEX_STARTS_AT_ONE,
1251};
1252
1253static struct ti_clk dpll1_fck = {
1254 .name = "dpll1_fck",
1255 .type = TI_CLK_DIVIDER,
1256 .data = &dpll1_fck_data,
1257};
1258
1259static const char *dpll1_ck_parents[] = {
1260 "sys_ck",
1261 "dpll1_fck",
1262};
1263
1264static struct ti_clk_dpll dpll1_ck_data = {
1265 .num_parents = ARRAY_SIZE(dpll1_ck_parents),
1266 .control_reg = 0x904,
1267 .idlest_reg = 0x924,
1268 .mult_div1_reg = 0x940,
1269 .autoidle_reg = 0x934,
1270 .module = TI_CLKM_CM,
1271 .parents = dpll1_ck_parents,
1272 .freqsel_mask = 0xf0,
1273 .modes = 0xa0,
1274 .div1_mask = 0x7f,
1275 .idlest_mask = 0x1,
1276 .auto_recal_bit = 0x3,
1277 .max_divider = 0x80,
1278 .min_divider = 0x1,
1279 .recal_en_bit = 0x7,
1280 .max_multiplier = 0x7ff,
1281 .enable_mask = 0x7,
1282 .mult_mask = 0x7ff00,
1283 .recal_st_bit = 0x7,
1284 .autoidle_mask = 0x7,
1285};
1286
1287static struct ti_clk dpll1_ck = {
1288 .name = "dpll1_ck",
1289 .clkdm_name = "dpll1_clkdm",
1290 .type = TI_CLK_DPLL,
1291 .data = &dpll1_ck_data,
1292};
1293
1294static struct ti_clk_fixed secure_32k_fck_data = {
1295 .frequency = 32768,
1296};
1297
1298static struct ti_clk secure_32k_fck = {
1299 .name = "secure_32k_fck",
1300 .type = TI_CLK_FIXED,
1301 .data = &secure_32k_fck_data,
1302};
1303
1304static struct ti_clk_gate gpio5_ick_data = {
1305 .parent = "per_l4_ick",
1306 .bit_shift = 16,
1307 .reg = 0x1010,
1308 .module = TI_CLKM_CM,
1309 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1310};
1311
1312static struct ti_clk gpio5_ick = {
1313 .name = "gpio5_ick",
1314 .clkdm_name = "per_clkdm",
1315 .type = TI_CLK_GATE,
1316 .data = &gpio5_ick_data,
1317};
1318
1319static struct ti_clk_divider dpll4_m4_ck_data = {
1320 .parent = "dpll4_ck",
1321 .max_div = 32,
1322 .reg = 0xe40,
1323 .module = TI_CLKM_CM,
1324 .flags = CLKF_INDEX_STARTS_AT_ONE,
1325};
1326
1327static struct ti_clk dpll4_m4_ck = {
1328 .name = "dpll4_m4_ck",
1329 .type = TI_CLK_DIVIDER,
1330 .data = &dpll4_m4_ck_data,
1331};
1332
1333static struct ti_clk_fixed_factor dpll4_m4x2_mul_ck_data = {
1334 .parent = "dpll4_m4_ck",
1335 .div = 1,
1336 .mult = 2,
1337 .flags = CLKF_SET_RATE_PARENT,
1338};
1339
1340static struct ti_clk dpll4_m4x2_mul_ck = {
1341 .name = "dpll4_m4x2_mul_ck",
1342 .type = TI_CLK_FIXED_FACTOR,
1343 .data = &dpll4_m4x2_mul_ck_data,
1344};
1345
1346static struct ti_clk_gate dpll4_m4x2_ck_data = {
1347 .parent = "dpll4_m4x2_mul_ck",
1348 .bit_shift = 0x1d,
1349 .reg = 0xd00,
1350 .module = TI_CLKM_CM,
1351 .flags = CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE,
1352};
1353
1354static struct ti_clk dpll4_m4x2_ck = {
1355 .name = "dpll4_m4x2_ck",
1356 .type = TI_CLK_GATE,
1357 .data = &dpll4_m4x2_ck_data,
1358};
1359
1360static struct ti_clk_gate dss1_alwon_fck_3430es2_data = {
1361 .parent = "dpll4_m4x2_ck",
1362 .bit_shift = 0,
1363 .reg = 0xe00,
1364 .module = TI_CLKM_CM,
1365 .flags = CLKF_DSS | CLKF_SET_RATE_PARENT,
1366};
1367
1368static struct ti_clk dss1_alwon_fck_3430es2 = {
1369 .name = "dss1_alwon_fck",
1370 .clkdm_name = "dss_clkdm",
1371 .type = TI_CLK_GATE,
1372 .data = &dss1_alwon_fck_3430es2_data,
1373};
1374
1375static struct ti_clk_gate uart3_ick_data = {
1376 .parent = "per_l4_ick",
1377 .bit_shift = 11,
1378 .reg = 0x1010,
1379 .module = TI_CLKM_CM,
1380 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1381};
1382
1383static struct ti_clk uart3_ick = {
1384 .name = "uart3_ick",
1385 .clkdm_name = "per_clkdm",
1386 .type = TI_CLK_GATE,
1387 .data = &uart3_ick_data,
1388};
1389
1390static struct ti_clk_divider dpll4_m3_ck_data = {
1391 .parent = "dpll4_ck",
1392 .bit_shift = 8,
1393 .max_div = 32,
1394 .reg = 0xe40,
1395 .module = TI_CLKM_CM,
1396 .flags = CLKF_INDEX_STARTS_AT_ONE,
1397};
1398
1399static struct ti_clk dpll4_m3_ck = {
1400 .name = "dpll4_m3_ck",
1401 .type = TI_CLK_DIVIDER,
1402 .data = &dpll4_m3_ck_data,
1403};
1404
1405static struct ti_clk_gate mcbsp3_ick_data = {
1406 .parent = "per_l4_ick",
1407 .bit_shift = 1,
1408 .reg = 0x1010,
1409 .module = TI_CLKM_CM,
1410 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1411};
1412
1413static struct ti_clk mcbsp3_ick = {
1414 .name = "mcbsp3_ick",
1415 .clkdm_name = "per_clkdm",
1416 .type = TI_CLK_GATE,
1417 .data = &mcbsp3_ick_data,
1418};
1419
1420static struct ti_clk_gate gpio3_dbck_data = {
1421 .parent = "per_32k_alwon_fck",
1422 .bit_shift = 14,
1423 .reg = 0x1000,
1424 .module = TI_CLKM_CM,
1425};
1426
1427static struct ti_clk gpio3_dbck = {
1428 .name = "gpio3_dbck",
1429 .clkdm_name = "per_clkdm",
1430 .type = TI_CLK_GATE,
1431 .data = &gpio3_dbck_data,
1432};
1433
1434static struct ti_clk_gate fac_ick_data = {
1435 .parent = "core_l4_ick",
1436 .bit_shift = 8,
1437 .reg = 0xa10,
1438 .module = TI_CLKM_CM,
1439 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1440};
1441
1442static struct ti_clk fac_ick = {
1443 .name = "fac_ick",
1444 .clkdm_name = "core_l4_clkdm",
1445 .type = TI_CLK_GATE,
1446 .data = &fac_ick_data,
1447};
1448
1449static struct ti_clk_gate clkout2_src_gate_ck_data = {
1450 .parent = "core_ck",
1451 .bit_shift = 7,
1452 .reg = 0xd70,
1453 .module = TI_CLKM_CM,
1454 .flags = CLKF_NO_WAIT,
1455};
1456
1457static struct ti_clk_fixed_factor dpll4_m3x2_mul_ck_data = {
1458 .parent = "dpll4_m3_ck",
1459 .div = 1,
1460 .mult = 2,
1461};
1462
1463static struct ti_clk dpll4_m3x2_mul_ck = {
1464 .name = "dpll4_m3x2_mul_ck",
1465 .type = TI_CLK_FIXED_FACTOR,
1466 .data = &dpll4_m3x2_mul_ck_data,
1467};
1468
1469static struct ti_clk_gate dpll4_m3x2_ck_data = {
1470 .parent = "dpll4_m3x2_mul_ck",
1471 .bit_shift = 0x1c,
1472 .reg = 0xd00,
1473 .module = TI_CLKM_CM,
1474 .flags = CLKF_SET_BIT_TO_DISABLE,
1475};
1476
1477static struct ti_clk dpll4_m3x2_ck = {
1478 .name = "dpll4_m3x2_ck",
1479 .type = TI_CLK_GATE,
1480 .data = &dpll4_m3x2_ck_data,
1481};
1482
1483static const char *omap_54m_fck_parents[] = {
1484 "dpll4_m3x2_ck",
1485 "sys_altclk",
1486};
1487
1488static struct ti_clk_mux omap_54m_fck_data = {
1489 .bit_shift = 5,
1490 .num_parents = ARRAY_SIZE(omap_54m_fck_parents),
1491 .reg = 0xd40,
1492 .module = TI_CLKM_CM,
1493 .parents = omap_54m_fck_parents,
1494};
1495
1496static struct ti_clk omap_54m_fck = {
1497 .name = "omap_54m_fck",
1498 .type = TI_CLK_MUX,
1499 .data = &omap_54m_fck_data,
1500};
1501
1502static const char *clkout2_src_mux_ck_parents[] = {
1503 "core_ck",
1504 "sys_ck",
1505 "cm_96m_fck",
1506 "omap_54m_fck",
1507};
1508
1509static struct ti_clk_mux clkout2_src_mux_ck_data = {
1510 .num_parents = ARRAY_SIZE(clkout2_src_mux_ck_parents),
1511 .reg = 0xd70,
1512 .module = TI_CLKM_CM,
1513 .parents = clkout2_src_mux_ck_parents,
1514};
1515
1516static struct ti_clk_composite clkout2_src_ck_data = {
1517 .mux = &clkout2_src_mux_ck_data,
1518 .gate = &clkout2_src_gate_ck_data,
1519};
1520
1521static struct ti_clk clkout2_src_ck = {
1522 .name = "clkout2_src_ck",
1523 .type = TI_CLK_COMPOSITE,
1524 .data = &clkout2_src_ck_data,
1525};
1526
1527static struct ti_clk_gate i2c1_fck_data = {
1528 .parent = "core_96m_fck",
1529 .bit_shift = 15,
1530 .reg = 0xa00,
1531 .module = TI_CLKM_CM,
1532 .flags = CLKF_WAIT,
1533};
1534
1535static struct ti_clk i2c1_fck = {
1536 .name = "i2c1_fck",
1537 .clkdm_name = "core_l4_clkdm",
1538 .type = TI_CLK_GATE,
1539 .data = &i2c1_fck_data,
1540};
1541
1542static struct ti_clk_gate wdt3_fck_data = {
1543 .parent = "per_32k_alwon_fck",
1544 .bit_shift = 12,
1545 .reg = 0x1000,
1546 .module = TI_CLKM_CM,
1547 .flags = CLKF_WAIT,
1548};
1549
1550static struct ti_clk wdt3_fck = {
1551 .name = "wdt3_fck",
1552 .clkdm_name = "per_clkdm",
1553 .type = TI_CLK_GATE,
1554 .data = &wdt3_fck_data,
1555};
1556
1557static struct ti_clk_gate gpt7_gate_fck_data = {
1558 .parent = "sys_ck",
1559 .bit_shift = 8,
1560 .reg = 0x1000,
1561 .module = TI_CLKM_CM,
1562};
1563
1564static const char *gpt7_mux_fck_parents[] = {
1565 "omap_32k_fck",
1566 "sys_ck",
1567};
1568
1569static struct ti_clk_mux gpt7_mux_fck_data = {
1570 .bit_shift = 5,
1571 .num_parents = ARRAY_SIZE(gpt7_mux_fck_parents),
1572 .reg = 0x1040,
1573 .module = TI_CLKM_CM,
1574 .parents = gpt7_mux_fck_parents,
1575};
1576
1577static struct ti_clk_composite gpt7_fck_data = {
1578 .mux = &gpt7_mux_fck_data,
1579 .gate = &gpt7_gate_fck_data,
1580};
1581
1582static struct ti_clk gpt7_fck = {
1583 .name = "gpt7_fck",
1584 .type = TI_CLK_COMPOSITE,
1585 .data = &gpt7_fck_data,
1586};
1587
1588static struct ti_clk_gate usb_l4_gate_ick_data = {
1589 .parent = "l4_ick",
1590 .bit_shift = 5,
1591 .reg = 0xa10,
1592 .module = TI_CLKM_CM,
1593 .flags = CLKF_INTERFACE,
1594};
1595
1596static struct ti_clk_divider usb_l4_div_ick_data = {
1597 .parent = "l4_ick",
1598 .bit_shift = 4,
1599 .max_div = 1,
1600 .reg = 0xa40,
1601 .module = TI_CLKM_CM,
1602 .flags = CLKF_INDEX_STARTS_AT_ONE,
1603};
1604
1605static struct ti_clk_composite usb_l4_ick_data = {
1606 .gate = &usb_l4_gate_ick_data,
1607 .divider = &usb_l4_div_ick_data,
1608};
1609
1610static struct ti_clk usb_l4_ick = {
1611 .name = "usb_l4_ick",
1612 .type = TI_CLK_COMPOSITE,
1613 .data = &usb_l4_ick_data,
1614};
1615
1616static struct ti_clk_gate uart4_ick_data = {
1617 .parent = "per_l4_ick",
1618 .bit_shift = 18,
1619 .reg = 0x1010,
1620 .module = TI_CLKM_CM,
1621 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1622};
1623
1624static struct ti_clk uart4_ick = {
1625 .name = "uart4_ick",
1626 .clkdm_name = "per_clkdm",
1627 .type = TI_CLK_GATE,
1628 .data = &uart4_ick_data,
1629};
1630
1631static struct ti_clk_fixed dummy_ck_data = {
1632 .frequency = 0,
1633};
1634
1635static struct ti_clk dummy_ck = {
1636 .name = "dummy_ck",
1637 .type = TI_CLK_FIXED,
1638 .data = &dummy_ck_data,
1639};
1640
1641static const char *gpt3_mux_fck_parents[] = {
1642 "omap_32k_fck",
1643 "sys_ck",
1644};
1645
1646static struct ti_clk_mux gpt3_mux_fck_data = {
1647 .bit_shift = 1,
1648 .num_parents = ARRAY_SIZE(gpt3_mux_fck_parents),
1649 .reg = 0x1040,
1650 .module = TI_CLKM_CM,
1651 .parents = gpt3_mux_fck_parents,
1652};
1653
1654static struct ti_clk_gate gpt9_ick_data = {
1655 .parent = "per_l4_ick",
1656 .bit_shift = 10,
1657 .reg = 0x1010,
1658 .module = TI_CLKM_CM,
1659 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1660};
1661
1662static struct ti_clk gpt9_ick = {
1663 .name = "gpt9_ick",
1664 .clkdm_name = "per_clkdm",
1665 .type = TI_CLK_GATE,
1666 .data = &gpt9_ick_data,
1667};
1668
1669static struct ti_clk_gate gpt10_gate_fck_data = {
1670 .parent = "sys_ck",
1671 .bit_shift = 11,
1672 .reg = 0xa00,
1673 .module = TI_CLKM_CM,
1674};
1675
1676static struct ti_clk_gate dss_ick_3430es1_data = {
1677 .parent = "l4_ick",
1678 .bit_shift = 0,
1679 .reg = 0xe10,
1680 .module = TI_CLKM_CM,
1681 .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
1682};
1683
1684static struct ti_clk dss_ick_3430es1 = {
1685 .name = "dss_ick",
1686 .clkdm_name = "dss_clkdm",
1687 .type = TI_CLK_GATE,
1688 .data = &dss_ick_3430es1_data,
1689};
1690
1691static struct ti_clk_gate gpt11_ick_data = {
1692 .parent = "core_l4_ick",
1693 .bit_shift = 12,
1694 .reg = 0xa10,
1695 .module = TI_CLKM_CM,
1696 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1697};
1698
1699static struct ti_clk gpt11_ick = {
1700 .name = "gpt11_ick",
1701 .clkdm_name = "core_l4_clkdm",
1702 .type = TI_CLK_GATE,
1703 .data = &gpt11_ick_data,
1704};
1705
1706static struct ti_clk_divider dpll2_fck_data = {
1707 .parent = "core_ck",
1708 .bit_shift = 19,
1709 .max_div = 7,
1710 .reg = 0x40,
1711 .module = TI_CLKM_CM,
1712 .flags = CLKF_INDEX_STARTS_AT_ONE,
1713};
1714
1715static struct ti_clk dpll2_fck = {
1716 .name = "dpll2_fck",
1717 .type = TI_CLK_DIVIDER,
1718 .data = &dpll2_fck_data,
1719};
1720
1721static struct ti_clk_gate uart1_fck_data = {
1722 .parent = "core_48m_fck",
1723 .bit_shift = 13,
1724 .reg = 0xa00,
1725 .module = TI_CLKM_CM,
1726 .flags = CLKF_WAIT,
1727};
1728
1729static struct ti_clk uart1_fck = {
1730 .name = "uart1_fck",
1731 .clkdm_name = "core_l4_clkdm",
1732 .type = TI_CLK_GATE,
1733 .data = &uart1_fck_data,
1734};
1735
1736static struct ti_clk_gate hsotgusb_ick_3430es1_data = {
1737 .parent = "core_l3_ick",
1738 .bit_shift = 4,
1739 .reg = 0xa10,
1740 .module = TI_CLKM_CM,
1741 .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
1742};
1743
1744static struct ti_clk hsotgusb_ick_3430es1 = {
1745 .name = "hsotgusb_ick_3430es1",
1746 .clkdm_name = "core_l3_clkdm",
1747 .type = TI_CLK_GATE,
1748 .data = &hsotgusb_ick_3430es1_data,
1749};
1750
1751static struct ti_clk_gate gpio2_ick_data = {
1752 .parent = "per_l4_ick",
1753 .bit_shift = 13,
1754 .reg = 0x1010,
1755 .module = TI_CLKM_CM,
1756 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1757};
1758
1759static struct ti_clk gpio2_ick = {
1760 .name = "gpio2_ick",
1761 .clkdm_name = "per_clkdm",
1762 .type = TI_CLK_GATE,
1763 .data = &gpio2_ick_data,
1764};
1765
1766static struct ti_clk_gate mmchs1_ick_data = {
1767 .parent = "core_l4_ick",
1768 .bit_shift = 24,
1769 .reg = 0xa10,
1770 .module = TI_CLKM_CM,
1771 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1772};
1773
1774static struct ti_clk mmchs1_ick = {
1775 .name = "mmchs1_ick",
1776 .clkdm_name = "core_l4_clkdm",
1777 .type = TI_CLK_GATE,
1778 .data = &mmchs1_ick_data,
1779};
1780
1781static struct ti_clk_gate modem_fck_data = {
1782 .parent = "sys_ck",
1783 .bit_shift = 31,
1784 .reg = 0xa00,
1785 .module = TI_CLKM_CM,
1786 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1787};
1788
1789static struct ti_clk modem_fck = {
1790 .name = "modem_fck",
1791 .clkdm_name = "d2d_clkdm",
1792 .type = TI_CLK_GATE,
1793 .data = &modem_fck_data,
1794};
1795
1796static struct ti_clk_gate mcbsp4_ick_data = {
1797 .parent = "per_l4_ick",
1798 .bit_shift = 2,
1799 .reg = 0x1010,
1800 .module = TI_CLKM_CM,
1801 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1802};
1803
1804static struct ti_clk mcbsp4_ick = {
1805 .name = "mcbsp4_ick",
1806 .clkdm_name = "per_clkdm",
1807 .type = TI_CLK_GATE,
1808 .data = &mcbsp4_ick_data,
1809};
1810
1811static struct ti_clk_gate gpio1_ick_data = {
1812 .parent = "wkup_l4_ick",
1813 .bit_shift = 3,
1814 .reg = 0xc10,
1815 .module = TI_CLKM_CM,
1816 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1817};
1818
1819static struct ti_clk gpio1_ick = {
1820 .name = "gpio1_ick",
1821 .clkdm_name = "wkup_clkdm",
1822 .type = TI_CLK_GATE,
1823 .data = &gpio1_ick_data,
1824};
1825
1826static const char *gpt6_mux_fck_parents[] = {
1827 "omap_32k_fck",
1828 "sys_ck",
1829};
1830
1831static struct ti_clk_mux gpt6_mux_fck_data = {
1832 .bit_shift = 4,
1833 .num_parents = ARRAY_SIZE(gpt6_mux_fck_parents),
1834 .reg = 0x1040,
1835 .module = TI_CLKM_CM,
1836 .parents = gpt6_mux_fck_parents,
1837};
1838
1839static struct ti_clk_fixed_factor dpll1_x2_ck_data = {
1840 .parent = "dpll1_ck",
1841 .div = 1,
1842 .mult = 2,
1843};
1844
1845static struct ti_clk dpll1_x2_ck = {
1846 .name = "dpll1_x2_ck",
1847 .type = TI_CLK_FIXED_FACTOR,
1848 .data = &dpll1_x2_ck_data,
1849};
1850
1851static struct ti_clk_divider dpll1_x2m2_ck_data = {
1852 .parent = "dpll1_x2_ck",
1853 .max_div = 31,
1854 .reg = 0x944,
1855 .module = TI_CLKM_CM,
1856 .flags = CLKF_INDEX_STARTS_AT_ONE,
1857};
1858
1859static struct ti_clk dpll1_x2m2_ck = {
1860 .name = "dpll1_x2m2_ck",
1861 .type = TI_CLK_DIVIDER,
1862 .data = &dpll1_x2m2_ck_data,
1863};
1864
1865static struct ti_clk_fixed_factor mpu_ck_data = {
1866 .parent = "dpll1_x2m2_ck",
1867 .div = 1,
1868 .mult = 1,
1869};
1870
1871static struct ti_clk mpu_ck = {
1872 .name = "mpu_ck",
1873 .type = TI_CLK_FIXED_FACTOR,
1874 .data = &mpu_ck_data,
1875};
1876
1877static struct ti_clk_divider arm_fck_data = {
1878 .parent = "mpu_ck",
1879 .max_div = 2,
1880 .reg = 0x924,
1881 .module = TI_CLKM_CM,
1882};
1883
1884static struct ti_clk arm_fck = {
1885 .name = "arm_fck",
1886 .type = TI_CLK_DIVIDER,
1887 .data = &arm_fck_data,
1888};
1889
1890static struct ti_clk_fixed_factor core_d3_ck_data = {
1891 .parent = "core_ck",
1892 .div = 3,
1893 .mult = 1,
1894};
1895
1896static struct ti_clk core_d3_ck = {
1897 .name = "core_d3_ck",
1898 .type = TI_CLK_FIXED_FACTOR,
1899 .data = &core_d3_ck_data,
1900};
1901
1902static struct ti_clk_gate gpt11_gate_fck_data = {
1903 .parent = "sys_ck",
1904 .bit_shift = 12,
1905 .reg = 0xa00,
1906 .module = TI_CLKM_CM,
1907};
1908
1909static const char *gpt11_mux_fck_parents[] = {
1910 "omap_32k_fck",
1911 "sys_ck",
1912};
1913
1914static struct ti_clk_mux gpt11_mux_fck_data = {
1915 .bit_shift = 7,
1916 .num_parents = ARRAY_SIZE(gpt11_mux_fck_parents),
1917 .reg = 0xa40,
1918 .module = TI_CLKM_CM,
1919 .parents = gpt11_mux_fck_parents,
1920};
1921
1922static struct ti_clk_composite gpt11_fck_data = {
1923 .mux = &gpt11_mux_fck_data,
1924 .gate = &gpt11_gate_fck_data,
1925};
1926
1927static struct ti_clk gpt11_fck = {
1928 .name = "gpt11_fck",
1929 .type = TI_CLK_COMPOSITE,
1930 .data = &gpt11_fck_data,
1931};
1932
1933static struct ti_clk_fixed_factor core_d6_ck_data = {
1934 .parent = "core_ck",
1935 .div = 6,
1936 .mult = 1,
1937};
1938
1939static struct ti_clk core_d6_ck = {
1940 .name = "core_d6_ck",
1941 .type = TI_CLK_FIXED_FACTOR,
1942 .data = &core_d6_ck_data,
1943};
1944
1945static struct ti_clk_gate uart4_fck_am35xx_data = {
1946 .parent = "core_48m_fck",
1947 .bit_shift = 23,
1948 .reg = 0xa00,
1949 .module = TI_CLKM_CM,
1950 .flags = CLKF_WAIT,
1951};
1952
1953static struct ti_clk uart4_fck_am35xx = {
1954 .name = "uart4_fck_am35xx",
1955 .clkdm_name = "core_l4_clkdm",
1956 .type = TI_CLK_GATE,
1957 .data = &uart4_fck_am35xx_data,
1958};
1959
1960static struct ti_clk_gate dpll3_m3x2_ck_data = {
1961 .parent = "dpll3_m3x2_mul_ck",
1962 .bit_shift = 0xc,
1963 .reg = 0xd00,
1964 .module = TI_CLKM_CM,
1965 .flags = CLKF_SET_BIT_TO_DISABLE,
1966};
1967
1968static struct ti_clk dpll3_m3x2_ck = {
1969 .name = "dpll3_m3x2_ck",
1970 .type = TI_CLK_GATE,
1971 .data = &dpll3_m3x2_ck_data,
1972};
1973
1974static struct ti_clk_fixed_factor emu_core_alwon_ck_data = {
1975 .parent = "dpll3_m3x2_ck",
1976 .div = 1,
1977 .mult = 1,
1978};
1979
1980static struct ti_clk emu_core_alwon_ck = {
1981 .name = "emu_core_alwon_ck",
1982 .type = TI_CLK_FIXED_FACTOR,
1983 .data = &emu_core_alwon_ck_data,
1984};
1985
1986static struct ti_clk_divider dpll4_m6_ck_data = {
1987 .parent = "dpll4_ck",
1988 .bit_shift = 24,
1989 .max_div = 63,
1990 .reg = 0x1140,
1991 .module = TI_CLKM_CM,
1992 .flags = CLKF_INDEX_STARTS_AT_ONE,
1993};
1994
1995static struct ti_clk dpll4_m6_ck = {
1996 .name = "dpll4_m6_ck",
1997 .type = TI_CLK_DIVIDER,
1998 .data = &dpll4_m6_ck_data,
1999};
2000
2001static struct ti_clk_fixed_factor dpll4_m6x2_mul_ck_data = {
2002 .parent = "dpll4_m6_ck",
2003 .div = 1,
2004 .mult = 2,
2005};
2006
2007static struct ti_clk dpll4_m6x2_mul_ck = {
2008 .name = "dpll4_m6x2_mul_ck",
2009 .type = TI_CLK_FIXED_FACTOR,
2010 .data = &dpll4_m6x2_mul_ck_data,
2011};
2012
2013static struct ti_clk_gate dpll4_m6x2_ck_data = {
2014 .parent = "dpll4_m6x2_mul_ck",
2015 .bit_shift = 0x1f,
2016 .reg = 0xd00,
2017 .module = TI_CLKM_CM,
2018 .flags = CLKF_SET_BIT_TO_DISABLE,
2019};
2020
2021static struct ti_clk dpll4_m6x2_ck = {
2022 .name = "dpll4_m6x2_ck",
2023 .type = TI_CLK_GATE,
2024 .data = &dpll4_m6x2_ck_data,
2025};
2026
2027static struct ti_clk_fixed_factor emu_per_alwon_ck_data = {
2028 .parent = "dpll4_m6x2_ck",
2029 .div = 1,
2030 .mult = 1,
2031};
2032
2033static struct ti_clk emu_per_alwon_ck = {
2034 .name = "emu_per_alwon_ck",
2035 .type = TI_CLK_FIXED_FACTOR,
2036 .data = &emu_per_alwon_ck_data,
2037};
2038
2039static struct ti_clk_fixed_factor emu_mpu_alwon_ck_data = {
2040 .parent = "mpu_ck",
2041 .div = 1,
2042 .mult = 1,
2043};
2044
2045static struct ti_clk emu_mpu_alwon_ck = {
2046 .name = "emu_mpu_alwon_ck",
2047 .type = TI_CLK_FIXED_FACTOR,
2048 .data = &emu_mpu_alwon_ck_data,
2049};
2050
2051static const char *emu_src_mux_ck_parents[] = {
2052 "sys_ck",
2053 "emu_core_alwon_ck",
2054 "emu_per_alwon_ck",
2055 "emu_mpu_alwon_ck",
2056};
2057
2058static struct ti_clk_mux emu_src_mux_ck_data = {
2059 .num_parents = ARRAY_SIZE(emu_src_mux_ck_parents),
2060 .reg = 0x1140,
2061 .module = TI_CLKM_CM,
2062 .parents = emu_src_mux_ck_parents,
2063};
2064
2065static struct ti_clk emu_src_mux_ck = {
2066 .name = "emu_src_mux_ck",
2067 .type = TI_CLK_MUX,
2068 .data = &emu_src_mux_ck_data,
2069};
2070
2071static struct ti_clk_gate emu_src_ck_data = {
2072 .parent = "emu_src_mux_ck",
2073 .flags = CLKF_CLKDM,
2074};
2075
2076static struct ti_clk emu_src_ck = {
2077 .name = "emu_src_ck",
2078 .clkdm_name = "emu_clkdm",
2079 .type = TI_CLK_GATE,
2080 .data = &emu_src_ck_data,
2081};
2082
2083static struct ti_clk_divider atclk_fck_data = {
2084 .parent = "emu_src_ck",
2085 .bit_shift = 4,
2086 .max_div = 3,
2087 .reg = 0x1140,
2088 .module = TI_CLKM_CM,
2089 .flags = CLKF_INDEX_STARTS_AT_ONE,
2090};
2091
2092static struct ti_clk atclk_fck = {
2093 .name = "atclk_fck",
2094 .type = TI_CLK_DIVIDER,
2095 .data = &atclk_fck_data,
2096};
2097
2098static struct ti_clk_gate ipss_ick_data = {
2099 .parent = "core_l3_ick",
2100 .bit_shift = 4,
2101 .reg = 0xa10,
2102 .module = TI_CLKM_CM,
2103 .flags = CLKF_AM35XX | CLKF_INTERFACE,
2104};
2105
2106static struct ti_clk ipss_ick = {
2107 .name = "ipss_ick",
2108 .clkdm_name = "core_l3_clkdm",
2109 .type = TI_CLK_GATE,
2110 .data = &ipss_ick_data,
2111};
2112
2113static struct ti_clk_gate emac_ick_data = {
2114 .parent = "ipss_ick",
2115 .bit_shift = 1,
2116 .reg = 0x59c,
2117 .module = TI_CLKM_SCRM,
2118 .flags = CLKF_AM35XX,
2119};
2120
2121static struct ti_clk emac_ick = {
2122 .name = "emac_ick",
2123 .clkdm_name = "core_l3_clkdm",
2124 .type = TI_CLK_GATE,
2125 .data = &emac_ick_data,
2126};
2127
2128static struct ti_clk_gate vpfe_ick_data = {
2129 .parent = "ipss_ick",
2130 .bit_shift = 2,
2131 .reg = 0x59c,
2132 .module = TI_CLKM_SCRM,
2133 .flags = CLKF_AM35XX,
2134};
2135
2136static struct ti_clk vpfe_ick = {
2137 .name = "vpfe_ick",
2138 .clkdm_name = "core_l3_clkdm",
2139 .type = TI_CLK_GATE,
2140 .data = &vpfe_ick_data,
2141};
2142
2143static const char *dpll2_ck_parents[] = {
2144 "sys_ck",
2145 "dpll2_fck",
2146};
2147
2148static struct ti_clk_dpll dpll2_ck_data = {
2149 .num_parents = ARRAY_SIZE(dpll2_ck_parents),
2150 .control_reg = 0x4,
2151 .idlest_reg = 0x24,
2152 .mult_div1_reg = 0x40,
2153 .autoidle_reg = 0x34,
2154 .module = TI_CLKM_CM,
2155 .parents = dpll2_ck_parents,
2156 .freqsel_mask = 0xf0,
2157 .modes = 0xa2,
2158 .div1_mask = 0x7f,
2159 .idlest_mask = 0x1,
2160 .auto_recal_bit = 0x3,
2161 .max_divider = 0x80,
2162 .min_divider = 0x1,
2163 .recal_en_bit = 0x8,
2164 .max_multiplier = 0x7ff,
2165 .enable_mask = 0x7,
2166 .mult_mask = 0x7ff00,
2167 .recal_st_bit = 0x8,
2168 .autoidle_mask = 0x7,
2169};
2170
2171static struct ti_clk dpll2_ck = {
2172 .name = "dpll2_ck",
2173 .clkdm_name = "dpll2_clkdm",
2174 .type = TI_CLK_DPLL,
2175 .data = &dpll2_ck_data,
2176};
2177
2178static struct ti_clk_divider dpll2_m2_ck_data = {
2179 .parent = "dpll2_ck",
2180 .max_div = 31,
2181 .reg = 0x44,
2182 .module = TI_CLKM_CM,
2183 .flags = CLKF_INDEX_STARTS_AT_ONE,
2184};
2185
2186static struct ti_clk dpll2_m2_ck = {
2187 .name = "dpll2_m2_ck",
2188 .type = TI_CLK_DIVIDER,
2189 .data = &dpll2_m2_ck_data,
2190};
2191
2192static const char *mcbsp4_mux_fck_parents[] = {
2193 "per_96m_fck",
2194 "mcbsp_clks",
2195};
2196
2197static struct ti_clk_mux mcbsp4_mux_fck_data = {
2198 .bit_shift = 2,
2199 .num_parents = ARRAY_SIZE(mcbsp4_mux_fck_parents),
2200 .reg = 0x2d8,
2201 .module = TI_CLKM_SCRM,
2202 .parents = mcbsp4_mux_fck_parents,
2203};
2204
2205static const char *mcbsp1_mux_fck_parents[] = {
2206 "core_96m_fck",
2207 "mcbsp_clks",
2208};
2209
2210static struct ti_clk_mux mcbsp1_mux_fck_data = {
2211 .bit_shift = 2,
2212 .num_parents = ARRAY_SIZE(mcbsp1_mux_fck_parents),
2213 .reg = 0x274,
2214 .module = TI_CLKM_SCRM,
2215 .parents = mcbsp1_mux_fck_parents,
2216};
2217
2218static struct ti_clk_gate gpt8_gate_fck_data = {
2219 .parent = "sys_ck",
2220 .bit_shift = 9,
2221 .reg = 0x1000,
2222 .module = TI_CLKM_CM,
2223};
2224
2225static struct ti_clk_gate gpt8_ick_data = {
2226 .parent = "per_l4_ick",
2227 .bit_shift = 9,
2228 .reg = 0x1010,
2229 .module = TI_CLKM_CM,
2230 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2231};
2232
2233static struct ti_clk gpt8_ick = {
2234 .name = "gpt8_ick",
2235 .clkdm_name = "per_clkdm",
2236 .type = TI_CLK_GATE,
2237 .data = &gpt8_ick_data,
2238};
2239
2240static const char *gpt10_mux_fck_parents[] = {
2241 "omap_32k_fck",
2242 "sys_ck",
2243};
2244
2245static struct ti_clk_mux gpt10_mux_fck_data = {
2246 .bit_shift = 6,
2247 .num_parents = ARRAY_SIZE(gpt10_mux_fck_parents),
2248 .reg = 0xa40,
2249 .module = TI_CLKM_CM,
2250 .parents = gpt10_mux_fck_parents,
2251};
2252
2253static struct ti_clk_gate mmchs3_ick_data = {
2254 .parent = "core_l4_ick",
2255 .bit_shift = 30,
2256 .reg = 0xa10,
2257 .module = TI_CLKM_CM,
2258 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2259};
2260
2261static struct ti_clk mmchs3_ick = {
2262 .name = "mmchs3_ick",
2263 .clkdm_name = "core_l4_clkdm",
2264 .type = TI_CLK_GATE,
2265 .data = &mmchs3_ick_data,
2266};
2267
2268static struct ti_clk_gate gpio3_ick_data = {
2269 .parent = "per_l4_ick",
2270 .bit_shift = 14,
2271 .reg = 0x1010,
2272 .module = TI_CLKM_CM,
2273 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2274};
2275
2276static struct ti_clk gpio3_ick = {
2277 .name = "gpio3_ick",
2278 .clkdm_name = "per_clkdm",
2279 .type = TI_CLK_GATE,
2280 .data = &gpio3_ick_data,
2281};
2282
2283static const char *traceclk_src_fck_parents[] = {
2284 "sys_ck",
2285 "emu_core_alwon_ck",
2286 "emu_per_alwon_ck",
2287 "emu_mpu_alwon_ck",
2288};
2289
2290static struct ti_clk_mux traceclk_src_fck_data = {
2291 .bit_shift = 2,
2292 .num_parents = ARRAY_SIZE(traceclk_src_fck_parents),
2293 .reg = 0x1140,
2294 .module = TI_CLKM_CM,
2295 .parents = traceclk_src_fck_parents,
2296};
2297
2298static struct ti_clk traceclk_src_fck = {
2299 .name = "traceclk_src_fck",
2300 .type = TI_CLK_MUX,
2301 .data = &traceclk_src_fck_data,
2302};
2303
2304static struct ti_clk_divider traceclk_fck_data = {
2305 .parent = "traceclk_src_fck",
2306 .bit_shift = 11,
2307 .max_div = 7,
2308 .reg = 0x1140,
2309 .module = TI_CLKM_CM,
2310 .flags = CLKF_INDEX_STARTS_AT_ONE,
2311};
2312
2313static struct ti_clk traceclk_fck = {
2314 .name = "traceclk_fck",
2315 .type = TI_CLK_DIVIDER,
2316 .data = &traceclk_fck_data,
2317};
2318
2319static struct ti_clk_gate mcbsp5_gate_fck_data = {
2320 .parent = "mcbsp_clks",
2321 .bit_shift = 10,
2322 .reg = 0xa00,
2323 .module = TI_CLKM_CM,
2324};
2325
2326static struct ti_clk_gate sad2d_ick_data = {
2327 .parent = "l3_ick",
2328 .bit_shift = 3,
2329 .reg = 0xa10,
2330 .module = TI_CLKM_CM,
2331 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2332};
2333
2334static struct ti_clk sad2d_ick = {
2335 .name = "sad2d_ick",
2336 .clkdm_name = "d2d_clkdm",
2337 .type = TI_CLK_GATE,
2338 .data = &sad2d_ick_data,
2339};
2340
2341static const char *gpt1_mux_fck_parents[] = {
2342 "omap_32k_fck",
2343 "sys_ck",
2344};
2345
2346static struct ti_clk_mux gpt1_mux_fck_data = {
2347 .num_parents = ARRAY_SIZE(gpt1_mux_fck_parents),
2348 .reg = 0xc40,
2349 .module = TI_CLKM_CM,
2350 .parents = gpt1_mux_fck_parents,
2351};
2352
2353static struct ti_clk_gate hecc_ck_data = {
2354 .parent = "sys_ck",
2355 .bit_shift = 3,
2356 .reg = 0x59c,
2357 .module = TI_CLKM_SCRM,
2358 .flags = CLKF_AM35XX,
2359};
2360
2361static struct ti_clk hecc_ck = {
2362 .name = "hecc_ck",
2363 .clkdm_name = "core_l3_clkdm",
2364 .type = TI_CLK_GATE,
2365 .data = &hecc_ck_data,
2366};
2367
2368static struct ti_clk_gate gpt1_gate_fck_data = {
2369 .parent = "sys_ck",
2370 .bit_shift = 0,
2371 .reg = 0xc00,
2372 .module = TI_CLKM_CM,
2373};
2374
2375static struct ti_clk_composite gpt1_fck_data = {
2376 .mux = &gpt1_mux_fck_data,
2377 .gate = &gpt1_gate_fck_data,
2378};
2379
2380static struct ti_clk gpt1_fck = {
2381 .name = "gpt1_fck",
2382 .type = TI_CLK_COMPOSITE,
2383 .data = &gpt1_fck_data,
2384};
2385
2386static struct ti_clk_gate dpll4_m2x2_ck_omap36xx_data = {
2387 .parent = "dpll4_m2x2_mul_ck",
2388 .bit_shift = 0x1b,
2389 .reg = 0xd00,
2390 .module = TI_CLKM_CM,
2391 .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
2392};
2393
2394static struct ti_clk dpll4_m2x2_ck_omap36xx = {
2395 .name = "dpll4_m2x2_ck",
2396 .type = TI_CLK_GATE,
2397 .data = &dpll4_m2x2_ck_omap36xx_data,
2398 .patch = &dpll4_m2x2_ck,
2399};
2400
2401static struct ti_clk_divider gfx_l3_fck_data = {
2402 .parent = "l3_ick",
2403 .max_div = 7,
2404 .reg = 0xb40,
2405 .module = TI_CLKM_CM,
2406 .flags = CLKF_INDEX_STARTS_AT_ONE,
2407};
2408
2409static struct ti_clk gfx_l3_fck = {
2410 .name = "gfx_l3_fck",
2411 .type = TI_CLK_DIVIDER,
2412 .data = &gfx_l3_fck_data,
2413};
2414
2415static struct ti_clk_gate gfx_cg1_ck_data = {
2416 .parent = "gfx_l3_fck",
2417 .bit_shift = 1,
2418 .reg = 0xb00,
2419 .module = TI_CLKM_CM,
2420 .flags = CLKF_WAIT,
2421};
2422
2423static struct ti_clk gfx_cg1_ck = {
2424 .name = "gfx_cg1_ck",
2425 .clkdm_name = "gfx_3430es1_clkdm",
2426 .type = TI_CLK_GATE,
2427 .data = &gfx_cg1_ck_data,
2428};
2429
2430static struct ti_clk_gate mailboxes_ick_data = {
2431 .parent = "core_l4_ick",
2432 .bit_shift = 7,
2433 .reg = 0xa10,
2434 .module = TI_CLKM_CM,
2435 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2436};
2437
2438static struct ti_clk mailboxes_ick = {
2439 .name = "mailboxes_ick",
2440 .clkdm_name = "core_l4_clkdm",
2441 .type = TI_CLK_GATE,
2442 .data = &mailboxes_ick_data,
2443};
2444
2445static struct ti_clk_gate sha11_ick_data = {
2446 .parent = "security_l4_ick2",
2447 .bit_shift = 1,
2448 .reg = 0xa14,
2449 .module = TI_CLKM_CM,
2450 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2451};
2452
2453static struct ti_clk sha11_ick = {
2454 .name = "sha11_ick",
2455 .type = TI_CLK_GATE,
2456 .data = &sha11_ick_data,
2457};
2458
2459static struct ti_clk_gate hsotgusb_ick_am35xx_data = {
2460 .parent = "ipss_ick",
2461 .bit_shift = 0,
2462 .reg = 0x59c,
2463 .module = TI_CLKM_SCRM,
2464 .flags = CLKF_AM35XX,
2465};
2466
2467static struct ti_clk hsotgusb_ick_am35xx = {
2468 .name = "hsotgusb_ick_am35xx",
2469 .clkdm_name = "core_l3_clkdm",
2470 .type = TI_CLK_GATE,
2471 .data = &hsotgusb_ick_am35xx_data,
2472};
2473
2474static struct ti_clk_gate mmchs3_fck_data = {
2475 .parent = "core_96m_fck",
2476 .bit_shift = 30,
2477 .reg = 0xa00,
2478 .module = TI_CLKM_CM,
2479 .flags = CLKF_WAIT,
2480};
2481
2482static struct ti_clk mmchs3_fck = {
2483 .name = "mmchs3_fck",
2484 .clkdm_name = "core_l4_clkdm",
2485 .type = TI_CLK_GATE,
2486 .data = &mmchs3_fck_data,
2487};
2488
2489static struct ti_clk_divider pclk_fck_data = {
2490 .parent = "emu_src_ck",
2491 .bit_shift = 8,
2492 .max_div = 7,
2493 .reg = 0x1140,
2494 .module = TI_CLKM_CM,
2495 .flags = CLKF_INDEX_STARTS_AT_ONE,
2496};
2497
2498static struct ti_clk pclk_fck = {
2499 .name = "pclk_fck",
2500 .type = TI_CLK_DIVIDER,
2501 .data = &pclk_fck_data,
2502};
2503
2504static const char *dpll4_ck_omap36xx_parents[] = {
2505 "sys_ck",
2506 "sys_ck",
2507};
2508
2509static struct ti_clk_dpll dpll4_ck_omap36xx_data = {
2510 .num_parents = ARRAY_SIZE(dpll4_ck_omap36xx_parents),
2511 .control_reg = 0xd00,
2512 .idlest_reg = 0xd20,
2513 .mult_div1_reg = 0xd44,
2514 .autoidle_reg = 0xd30,
2515 .module = TI_CLKM_CM,
2516 .parents = dpll4_ck_omap36xx_parents,
2517 .modes = 0x82,
2518 .div1_mask = 0x7f,
2519 .idlest_mask = 0x2,
2520 .auto_recal_bit = 0x13,
2521 .max_divider = 0x80,
2522 .min_divider = 0x1,
2523 .recal_en_bit = 0x6,
2524 .max_multiplier = 0xfff,
2525 .enable_mask = 0x70000,
2526 .mult_mask = 0xfff00,
2527 .recal_st_bit = 0x6,
2528 .autoidle_mask = 0x38,
2529 .sddiv_mask = 0xff000000,
2530 .dco_mask = 0xe00000,
2531 .flags = CLKF_PER | CLKF_J_TYPE,
2532};
2533
2534static struct ti_clk dpll4_ck_omap36xx = {
2535 .name = "dpll4_ck",
2536 .type = TI_CLK_DPLL,
2537 .data = &dpll4_ck_omap36xx_data,
2538 .patch = &dpll4_ck,
2539};
2540
2541static struct ti_clk_gate uart3_fck_data = {
2542 .parent = "per_48m_fck",
2543 .bit_shift = 11,
2544 .reg = 0x1000,
2545 .module = TI_CLKM_CM,
2546 .flags = CLKF_WAIT,
2547};
2548
2549static struct ti_clk uart3_fck = {
2550 .name = "uart3_fck",
2551 .clkdm_name = "per_clkdm",
2552 .type = TI_CLK_GATE,
2553 .data = &uart3_fck_data,
2554};
2555
2556static struct ti_clk_fixed_factor wkup_32k_fck_data = {
2557 .parent = "omap_32k_fck",
2558 .div = 1,
2559 .mult = 1,
2560};
2561
2562static struct ti_clk wkup_32k_fck = {
2563 .name = "wkup_32k_fck",
2564 .type = TI_CLK_FIXED_FACTOR,
2565 .data = &wkup_32k_fck_data,
2566};
2567
2568static struct ti_clk_gate sys_clkout1_data = {
2569 .parent = "osc_sys_ck",
2570 .bit_shift = 7,
2571 .reg = 0xd70,
2572 .module = TI_CLKM_PRM,
2573};
2574
2575static struct ti_clk sys_clkout1 = {
2576 .name = "sys_clkout1",
2577 .type = TI_CLK_GATE,
2578 .data = &sys_clkout1_data,
2579};
2580
2581static struct ti_clk_fixed_factor gpmc_fck_data = {
2582 .parent = "core_l3_ick",
2583 .div = 1,
2584 .mult = 1,
2585};
2586
2587static struct ti_clk gpmc_fck = {
2588 .name = "gpmc_fck",
2589 .type = TI_CLK_FIXED_FACTOR,
2590 .data = &gpmc_fck_data,
2591};
2592
2593static struct ti_clk_fixed_factor dpll5_m2_d20_ck_data = {
2594 .parent = "dpll5_m2_ck",
2595 .div = 20,
2596 .mult = 1,
2597};
2598
2599static struct ti_clk dpll5_m2_d20_ck = {
2600 .name = "dpll5_m2_d20_ck",
2601 .type = TI_CLK_FIXED_FACTOR,
2602 .data = &dpll5_m2_d20_ck_data,
2603};
2604
2605static struct ti_clk_gate dpll4_m5x2_ck_omap36xx_data = {
2606 .parent = "dpll4_m5x2_mul_ck",
2607 .bit_shift = 0x1e,
2608 .reg = 0xd00,
2609 .module = TI_CLKM_CM,
2610 .flags = CLKF_HSDIV | CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE,
2611};
2612
2613static struct ti_clk dpll4_m5x2_ck_omap36xx = {
2614 .name = "dpll4_m5x2_ck",
2615 .type = TI_CLK_GATE,
2616 .data = &dpll4_m5x2_ck_omap36xx_data,
2617 .patch = &dpll4_m5x2_ck,
2618};
2619
2620static struct ti_clk_gate ssi_ssr_gate_fck_3430es2_data = {
2621 .parent = "corex2_fck",
2622 .bit_shift = 0,
2623 .reg = 0xa00,
2624 .module = TI_CLKM_CM,
2625 .flags = CLKF_NO_WAIT,
2626};
2627
2628static struct ti_clk_gate uart1_ick_data = {
2629 .parent = "core_l4_ick",
2630 .bit_shift = 13,
2631 .reg = 0xa10,
2632 .module = TI_CLKM_CM,
2633 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2634};
2635
2636static struct ti_clk uart1_ick = {
2637 .name = "uart1_ick",
2638 .clkdm_name = "core_l4_clkdm",
2639 .type = TI_CLK_GATE,
2640 .data = &uart1_ick_data,
2641};
2642
2643static struct ti_clk_gate iva2_ck_data = {
2644 .parent = "dpll2_m2_ck",
2645 .bit_shift = 0,
2646 .reg = 0x0,
2647 .module = TI_CLKM_CM,
2648 .flags = CLKF_WAIT,
2649};
2650
2651static struct ti_clk iva2_ck = {
2652 .name = "iva2_ck",
2653 .clkdm_name = "iva2_clkdm",
2654 .type = TI_CLK_GATE,
2655 .data = &iva2_ck_data,
2656};
2657
2658static struct ti_clk_gate pka_ick_data = {
2659 .parent = "security_l3_ick",
2660 .bit_shift = 4,
2661 .reg = 0xa14,
2662 .module = TI_CLKM_CM,
2663 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2664};
2665
2666static struct ti_clk pka_ick = {
2667 .name = "pka_ick",
2668 .type = TI_CLK_GATE,
2669 .data = &pka_ick_data,
2670};
2671
2672static struct ti_clk_gate gpt12_ick_data = {
2673 .parent = "wkup_l4_ick",
2674 .bit_shift = 1,
2675 .reg = 0xc10,
2676 .module = TI_CLKM_CM,
2677 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2678};
2679
2680static struct ti_clk gpt12_ick = {
2681 .name = "gpt12_ick",
2682 .clkdm_name = "wkup_clkdm",
2683 .type = TI_CLK_GATE,
2684 .data = &gpt12_ick_data,
2685};
2686
2687static const char *mcbsp5_mux_fck_parents[] = {
2688 "core_96m_fck",
2689 "mcbsp_clks",
2690};
2691
2692static struct ti_clk_mux mcbsp5_mux_fck_data = {
2693 .bit_shift = 4,
2694 .num_parents = ARRAY_SIZE(mcbsp5_mux_fck_parents),
2695 .reg = 0x2d8,
2696 .module = TI_CLKM_SCRM,
2697 .parents = mcbsp5_mux_fck_parents,
2698};
2699
2700static struct ti_clk_composite mcbsp5_fck_data = {
2701 .mux = &mcbsp5_mux_fck_data,
2702 .gate = &mcbsp5_gate_fck_data,
2703};
2704
2705static struct ti_clk mcbsp5_fck = {
2706 .name = "mcbsp5_fck",
2707 .type = TI_CLK_COMPOSITE,
2708 .data = &mcbsp5_fck_data,
2709};
2710
2711static struct ti_clk_gate usbhost_48m_fck_data = {
2712 .parent = "omap_48m_fck",
2713 .bit_shift = 0,
2714 .reg = 0x1400,
2715 .module = TI_CLKM_CM,
2716 .flags = CLKF_DSS,
2717};
2718
2719static struct ti_clk usbhost_48m_fck = {
2720 .name = "usbhost_48m_fck",
2721 .clkdm_name = "usbhost_clkdm",
2722 .type = TI_CLK_GATE,
2723 .data = &usbhost_48m_fck_data,
2724};
2725
2726static struct ti_clk_gate des1_ick_data = {
2727 .parent = "security_l4_ick2",
2728 .bit_shift = 0,
2729 .reg = 0xa14,
2730 .module = TI_CLKM_CM,
2731 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2732};
2733
2734static struct ti_clk des1_ick = {
2735 .name = "des1_ick",
2736 .type = TI_CLK_GATE,
2737 .data = &des1_ick_data,
2738};
2739
2740static struct ti_clk_gate sgx_gate_fck_data = {
2741 .parent = "core_ck",
2742 .bit_shift = 1,
2743 .reg = 0xb00,
2744 .module = TI_CLKM_CM,
2745};
2746
2747static struct ti_clk_fixed_factor core_d4_ck_data = {
2748 .parent = "core_ck",
2749 .div = 4,
2750 .mult = 1,
2751};
2752
2753static struct ti_clk core_d4_ck = {
2754 .name = "core_d4_ck",
2755 .type = TI_CLK_FIXED_FACTOR,
2756 .data = &core_d4_ck_data,
2757};
2758
2759static struct ti_clk_fixed_factor omap_192m_alwon_fck_data = {
2760 .parent = "dpll4_m2x2_ck",
2761 .div = 1,
2762 .mult = 1,
2763};
2764
2765static struct ti_clk omap_192m_alwon_fck = {
2766 .name = "omap_192m_alwon_fck",
2767 .type = TI_CLK_FIXED_FACTOR,
2768 .data = &omap_192m_alwon_fck_data,
2769};
2770
2771static struct ti_clk_fixed_factor core_d2_ck_data = {
2772 .parent = "core_ck",
2773 .div = 2,
2774 .mult = 1,
2775};
2776
2777static struct ti_clk core_d2_ck = {
2778 .name = "core_d2_ck",
2779 .type = TI_CLK_FIXED_FACTOR,
2780 .data = &core_d2_ck_data,
2781};
2782
2783static struct ti_clk_fixed_factor corex2_d3_fck_data = {
2784 .parent = "corex2_fck",
2785 .div = 3,
2786 .mult = 1,
2787};
2788
2789static struct ti_clk corex2_d3_fck = {
2790 .name = "corex2_d3_fck",
2791 .type = TI_CLK_FIXED_FACTOR,
2792 .data = &corex2_d3_fck_data,
2793};
2794
2795static struct ti_clk_fixed_factor corex2_d5_fck_data = {
2796 .parent = "corex2_fck",
2797 .div = 5,
2798 .mult = 1,
2799};
2800
2801static struct ti_clk corex2_d5_fck = {
2802 .name = "corex2_d5_fck",
2803 .type = TI_CLK_FIXED_FACTOR,
2804 .data = &corex2_d5_fck_data,
2805};
2806
2807static const char *sgx_mux_fck_parents[] = {
2808 "core_d3_ck",
2809 "core_d4_ck",
2810 "core_d6_ck",
2811 "cm_96m_fck",
2812 "omap_192m_alwon_fck",
2813 "core_d2_ck",
2814 "corex2_d3_fck",
2815 "corex2_d5_fck",
2816};
2817
2818static struct ti_clk_mux sgx_mux_fck_data = {
2819 .num_parents = ARRAY_SIZE(sgx_mux_fck_parents),
2820 .reg = 0xb40,
2821 .module = TI_CLKM_CM,
2822 .parents = sgx_mux_fck_parents,
2823};
2824
2825static struct ti_clk_composite sgx_fck_data = {
2826 .mux = &sgx_mux_fck_data,
2827 .gate = &sgx_gate_fck_data,
2828};
2829
2830static struct ti_clk sgx_fck = {
2831 .name = "sgx_fck",
2832 .type = TI_CLK_COMPOSITE,
2833 .data = &sgx_fck_data,
2834};
2835
2836static struct ti_clk_gate mcspi1_fck_data = {
2837 .parent = "core_48m_fck",
2838 .bit_shift = 18,
2839 .reg = 0xa00,
2840 .module = TI_CLKM_CM,
2841 .flags = CLKF_WAIT,
2842};
2843
2844static struct ti_clk mcspi1_fck = {
2845 .name = "mcspi1_fck",
2846 .clkdm_name = "core_l4_clkdm",
2847 .type = TI_CLK_GATE,
2848 .data = &mcspi1_fck_data,
2849};
2850
2851static struct ti_clk_gate mmchs2_fck_data = {
2852 .parent = "core_96m_fck",
2853 .bit_shift = 25,
2854 .reg = 0xa00,
2855 .module = TI_CLKM_CM,
2856 .flags = CLKF_WAIT,
2857};
2858
2859static struct ti_clk mmchs2_fck = {
2860 .name = "mmchs2_fck",
2861 .clkdm_name = "core_l4_clkdm",
2862 .type = TI_CLK_GATE,
2863 .data = &mmchs2_fck_data,
2864};
2865
2866static struct ti_clk_gate mcspi2_fck_data = {
2867 .parent = "core_48m_fck",
2868 .bit_shift = 19,
2869 .reg = 0xa00,
2870 .module = TI_CLKM_CM,
2871 .flags = CLKF_WAIT,
2872};
2873
2874static struct ti_clk mcspi2_fck = {
2875 .name = "mcspi2_fck",
2876 .clkdm_name = "core_l4_clkdm",
2877 .type = TI_CLK_GATE,
2878 .data = &mcspi2_fck_data,
2879};
2880
2881static struct ti_clk_gate vpfe_fck_data = {
2882 .parent = "pclk_ck",
2883 .bit_shift = 10,
2884 .reg = 0x59c,
2885 .module = TI_CLKM_SCRM,
2886};
2887
2888static struct ti_clk vpfe_fck = {
2889 .name = "vpfe_fck",
2890 .type = TI_CLK_GATE,
2891 .data = &vpfe_fck_data,
2892};
2893
2894static struct ti_clk_gate gpt4_gate_fck_data = {
2895 .parent = "sys_ck",
2896 .bit_shift = 5,
2897 .reg = 0x1000,
2898 .module = TI_CLKM_CM,
2899};
2900
2901static struct ti_clk_gate mcbsp1_gate_fck_data = {
2902 .parent = "mcbsp_clks",
2903 .bit_shift = 9,
2904 .reg = 0xa00,
2905 .module = TI_CLKM_CM,
2906};
2907
2908static struct ti_clk_gate gpt5_gate_fck_data = {
2909 .parent = "sys_ck",
2910 .bit_shift = 6,
2911 .reg = 0x1000,
2912 .module = TI_CLKM_CM,
2913};
2914
2915static const char *gpt5_mux_fck_parents[] = {
2916 "omap_32k_fck",
2917 "sys_ck",
2918};
2919
2920static struct ti_clk_mux gpt5_mux_fck_data = {
2921 .bit_shift = 3,
2922 .num_parents = ARRAY_SIZE(gpt5_mux_fck_parents),
2923 .reg = 0x1040,
2924 .module = TI_CLKM_CM,
2925 .parents = gpt5_mux_fck_parents,
2926};
2927
2928static struct ti_clk_composite gpt5_fck_data = {
2929 .mux = &gpt5_mux_fck_data,
2930 .gate = &gpt5_gate_fck_data,
2931};
2932
2933static struct ti_clk gpt5_fck = {
2934 .name = "gpt5_fck",
2935 .type = TI_CLK_COMPOSITE,
2936 .data = &gpt5_fck_data,
2937};
2938
2939static struct ti_clk_gate ts_fck_data = {
2940 .parent = "omap_32k_fck",
2941 .bit_shift = 1,
2942 .reg = 0xa08,
2943 .module = TI_CLKM_CM,
2944};
2945
2946static struct ti_clk ts_fck = {
2947 .name = "ts_fck",
2948 .clkdm_name = "core_l4_clkdm",
2949 .type = TI_CLK_GATE,
2950 .data = &ts_fck_data,
2951};
2952
2953static struct ti_clk_fixed_factor wdt1_fck_data = {
2954 .parent = "secure_32k_fck",
2955 .div = 1,
2956 .mult = 1,
2957};
2958
2959static struct ti_clk wdt1_fck = {
2960 .name = "wdt1_fck",
2961 .type = TI_CLK_FIXED_FACTOR,
2962 .data = &wdt1_fck_data,
2963};
2964
2965static struct ti_clk_gate dpll4_m6x2_ck_omap36xx_data = {
2966 .parent = "dpll4_m6x2_mul_ck",
2967 .bit_shift = 0x1f,
2968 .reg = 0xd00,
2969 .module = TI_CLKM_CM,
2970 .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
2971};
2972
2973static struct ti_clk dpll4_m6x2_ck_omap36xx = {
2974 .name = "dpll4_m6x2_ck",
2975 .type = TI_CLK_GATE,
2976 .data = &dpll4_m6x2_ck_omap36xx_data,
2977 .patch = &dpll4_m6x2_ck,
2978};
2979
2980static const char *gpt4_mux_fck_parents[] = {
2981 "omap_32k_fck",
2982 "sys_ck",
2983};
2984
2985static struct ti_clk_mux gpt4_mux_fck_data = {
2986 .bit_shift = 2,
2987 .num_parents = ARRAY_SIZE(gpt4_mux_fck_parents),
2988 .reg = 0x1040,
2989 .module = TI_CLKM_CM,
2990 .parents = gpt4_mux_fck_parents,
2991};
2992
2993static struct ti_clk_gate usbhost_ick_data = {
2994 .parent = "l4_ick",
2995 .bit_shift = 0,
2996 .reg = 0x1410,
2997 .module = TI_CLKM_CM,
2998 .flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE,
2999};
3000
3001static struct ti_clk usbhost_ick = {
3002 .name = "usbhost_ick",
3003 .clkdm_name = "usbhost_clkdm",
3004 .type = TI_CLK_GATE,
3005 .data = &usbhost_ick_data,
3006};
3007
3008static struct ti_clk_gate mcbsp2_ick_data = {
3009 .parent = "per_l4_ick",
3010 .bit_shift = 0,
3011 .reg = 0x1010,
3012 .module = TI_CLKM_CM,
3013 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3014};
3015
3016static struct ti_clk mcbsp2_ick = {
3017 .name = "mcbsp2_ick",
3018 .clkdm_name = "per_clkdm",
3019 .type = TI_CLK_GATE,
3020 .data = &mcbsp2_ick_data,
3021};
3022
3023static struct ti_clk_gate omapctrl_ick_data = {
3024 .parent = "core_l4_ick",
3025 .bit_shift = 6,
3026 .reg = 0xa10,
3027 .module = TI_CLKM_CM,
3028 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3029};
3030
3031static struct ti_clk omapctrl_ick = {
3032 .name = "omapctrl_ick",
3033 .clkdm_name = "core_l4_clkdm",
3034 .type = TI_CLK_GATE,
3035 .data = &omapctrl_ick_data,
3036};
3037
3038static struct ti_clk_fixed_factor omap_96m_d4_fck_data = {
3039 .parent = "omap_96m_fck",
3040 .div = 4,
3041 .mult = 1,
3042};
3043
3044static struct ti_clk omap_96m_d4_fck = {
3045 .name = "omap_96m_d4_fck",
3046 .type = TI_CLK_FIXED_FACTOR,
3047 .data = &omap_96m_d4_fck_data,
3048};
3049
3050static struct ti_clk_gate gpt6_ick_data = {
3051 .parent = "per_l4_ick",
3052 .bit_shift = 7,
3053 .reg = 0x1010,
3054 .module = TI_CLKM_CM,
3055 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3056};
3057
3058static struct ti_clk gpt6_ick = {
3059 .name = "gpt6_ick",
3060 .clkdm_name = "per_clkdm",
3061 .type = TI_CLK_GATE,
3062 .data = &gpt6_ick_data,
3063};
3064
3065static struct ti_clk_gate dpll3_m3x2_ck_omap36xx_data = {
3066 .parent = "dpll3_m3x2_mul_ck",
3067 .bit_shift = 0xc,
3068 .reg = 0xd00,
3069 .module = TI_CLKM_CM,
3070 .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
3071};
3072
3073static struct ti_clk dpll3_m3x2_ck_omap36xx = {
3074 .name = "dpll3_m3x2_ck",
3075 .type = TI_CLK_GATE,
3076 .data = &dpll3_m3x2_ck_omap36xx_data,
3077 .patch = &dpll3_m3x2_ck,
3078};
3079
3080static struct ti_clk_gate i2c3_ick_data = {
3081 .parent = "core_l4_ick",
3082 .bit_shift = 17,
3083 .reg = 0xa10,
3084 .module = TI_CLKM_CM,
3085 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3086};
3087
3088static struct ti_clk i2c3_ick = {
3089 .name = "i2c3_ick",
3090 .clkdm_name = "core_l4_clkdm",
3091 .type = TI_CLK_GATE,
3092 .data = &i2c3_ick_data,
3093};
3094
3095static struct ti_clk_gate gpio6_ick_data = {
3096 .parent = "per_l4_ick",
3097 .bit_shift = 17,
3098 .reg = 0x1010,
3099 .module = TI_CLKM_CM,
3100 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3101};
3102
3103static struct ti_clk gpio6_ick = {
3104 .name = "gpio6_ick",
3105 .clkdm_name = "per_clkdm",
3106 .type = TI_CLK_GATE,
3107 .data = &gpio6_ick_data,
3108};
3109
3110static struct ti_clk_gate mspro_ick_data = {
3111 .parent = "core_l4_ick",
3112 .bit_shift = 23,
3113 .reg = 0xa10,
3114 .module = TI_CLKM_CM,
3115 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3116};
3117
3118static struct ti_clk mspro_ick = {
3119 .name = "mspro_ick",
3120 .clkdm_name = "core_l4_clkdm",
3121 .type = TI_CLK_GATE,
3122 .data = &mspro_ick_data,
3123};
3124
3125static struct ti_clk_composite mcbsp1_fck_data = {
3126 .mux = &mcbsp1_mux_fck_data,
3127 .gate = &mcbsp1_gate_fck_data,
3128};
3129
3130static struct ti_clk mcbsp1_fck = {
3131 .name = "mcbsp1_fck",
3132 .type = TI_CLK_COMPOSITE,
3133 .data = &mcbsp1_fck_data,
3134};
3135
3136static struct ti_clk_gate gpt3_gate_fck_data = {
3137 .parent = "sys_ck",
3138 .bit_shift = 4,
3139 .reg = 0x1000,
3140 .module = TI_CLKM_CM,
3141};
3142
3143static struct ti_clk_fixed rmii_ck_data = {
3144 .frequency = 50000000,
3145};
3146
3147static struct ti_clk rmii_ck = {
3148 .name = "rmii_ck",
3149 .type = TI_CLK_FIXED,
3150 .data = &rmii_ck_data,
3151};
3152
3153static struct ti_clk_gate gpt6_gate_fck_data = {
3154 .parent = "sys_ck",
3155 .bit_shift = 7,
3156 .reg = 0x1000,
3157 .module = TI_CLKM_CM,
3158};
3159
3160static struct ti_clk_composite gpt6_fck_data = {
3161 .mux = &gpt6_mux_fck_data,
3162 .gate = &gpt6_gate_fck_data,
3163};
3164
3165static struct ti_clk gpt6_fck = {
3166 .name = "gpt6_fck",
3167 .type = TI_CLK_COMPOSITE,
3168 .data = &gpt6_fck_data,
3169};
3170
3171static struct ti_clk_fixed_factor dpll5_m2_d4_ck_data = {
3172 .parent = "dpll5_m2_ck",
3173 .div = 4,
3174 .mult = 1,
3175};
3176
3177static struct ti_clk dpll5_m2_d4_ck = {
3178 .name = "dpll5_m2_d4_ck",
3179 .type = TI_CLK_FIXED_FACTOR,
3180 .data = &dpll5_m2_d4_ck_data,
3181};
3182
3183static struct ti_clk_fixed_factor sys_d2_ck_data = {
3184 .parent = "sys_ck",
3185 .div = 2,
3186 .mult = 1,
3187};
3188
3189static struct ti_clk sys_d2_ck = {
3190 .name = "sys_d2_ck",
3191 .type = TI_CLK_FIXED_FACTOR,
3192 .data = &sys_d2_ck_data,
3193};
3194
3195static struct ti_clk_fixed_factor omap_96m_d2_fck_data = {
3196 .parent = "omap_96m_fck",
3197 .div = 2,
3198 .mult = 1,
3199};
3200
3201static struct ti_clk omap_96m_d2_fck = {
3202 .name = "omap_96m_d2_fck",
3203 .type = TI_CLK_FIXED_FACTOR,
3204 .data = &omap_96m_d2_fck_data,
3205};
3206
3207static struct ti_clk_fixed_factor dpll5_m2_d8_ck_data = {
3208 .parent = "dpll5_m2_ck",
3209 .div = 8,
3210 .mult = 1,
3211};
3212
3213static struct ti_clk dpll5_m2_d8_ck = {
3214 .name = "dpll5_m2_d8_ck",
3215 .type = TI_CLK_FIXED_FACTOR,
3216 .data = &dpll5_m2_d8_ck_data,
3217};
3218
3219static struct ti_clk_fixed_factor dpll5_m2_d16_ck_data = {
3220 .parent = "dpll5_m2_ck",
3221 .div = 16,
3222 .mult = 1,
3223};
3224
3225static struct ti_clk dpll5_m2_d16_ck = {
3226 .name = "dpll5_m2_d16_ck",
3227 .type = TI_CLK_FIXED_FACTOR,
3228 .data = &dpll5_m2_d16_ck_data,
3229};
3230
3231static const char *usim_mux_fck_parents[] = {
3232 "sys_ck",
3233 "sys_d2_ck",
3234 "omap_96m_d2_fck",
3235 "omap_96m_d4_fck",
3236 "omap_96m_d8_fck",
3237 "omap_96m_d10_fck",
3238 "dpll5_m2_d4_ck",
3239 "dpll5_m2_d8_ck",
3240 "dpll5_m2_d16_ck",
3241 "dpll5_m2_d20_ck",
3242};
3243
3244static struct ti_clk_mux usim_mux_fck_data = {
3245 .bit_shift = 3,
3246 .num_parents = ARRAY_SIZE(usim_mux_fck_parents),
3247 .reg = 0xc40,
3248 .module = TI_CLKM_CM,
3249 .parents = usim_mux_fck_parents,
3250 .flags = CLKF_INDEX_STARTS_AT_ONE,
3251};
3252
3253static struct ti_clk_composite usim_fck_data = {
3254 .mux = &usim_mux_fck_data,
3255 .gate = &usim_gate_fck_data,
3256};
3257
3258static struct ti_clk usim_fck = {
3259 .name = "usim_fck",
3260 .type = TI_CLK_COMPOSITE,
3261 .data = &usim_fck_data,
3262};
3263
3264static int ssi_ssr_div_fck_3430es2_divs[] = {
3265 0,
3266 1,
3267 2,
3268 3,
3269 4,
3270 0,
3271 6,
3272 0,
3273 8,
3274};
3275
3276static struct ti_clk_divider ssi_ssr_div_fck_3430es2_data = {
3277 .num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es2_divs),
3278 .parent = "corex2_fck",
3279 .bit_shift = 8,
3280 .dividers = ssi_ssr_div_fck_3430es2_divs,
3281 .reg = 0xa40,
3282 .module = TI_CLKM_CM,
3283};
3284
3285static struct ti_clk_composite ssi_ssr_fck_3430es2_data = {
3286 .gate = &ssi_ssr_gate_fck_3430es2_data,
3287 .divider = &ssi_ssr_div_fck_3430es2_data,
3288};
3289
3290static struct ti_clk ssi_ssr_fck_3430es2 = {
3291 .name = "ssi_ssr_fck",
3292 .type = TI_CLK_COMPOSITE,
3293 .data = &ssi_ssr_fck_3430es2_data,
3294};
3295
3296static struct ti_clk_gate dss1_alwon_fck_3430es1_data = {
3297 .parent = "dpll4_m4x2_ck",
3298 .bit_shift = 0,
3299 .reg = 0xe00,
3300 .module = TI_CLKM_CM,
3301 .flags = CLKF_SET_RATE_PARENT,
3302};
3303
3304static struct ti_clk dss1_alwon_fck_3430es1 = {
3305 .name = "dss1_alwon_fck",
3306 .clkdm_name = "dss_clkdm",
3307 .type = TI_CLK_GATE,
3308 .data = &dss1_alwon_fck_3430es1_data,
3309};
3310
3311static struct ti_clk_gate gpt3_ick_data = {
3312 .parent = "per_l4_ick",
3313 .bit_shift = 4,
3314 .reg = 0x1010,
3315 .module = TI_CLKM_CM,
3316 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3317};
3318
3319static struct ti_clk gpt3_ick = {
3320 .name = "gpt3_ick",
3321 .clkdm_name = "per_clkdm",
3322 .type = TI_CLK_GATE,
3323 .data = &gpt3_ick_data,
3324};
3325
3326static struct ti_clk_fixed_factor omap_12m_fck_data = {
3327 .parent = "omap_48m_fck",
3328 .div = 4,
3329 .mult = 1,
3330};
3331
3332static struct ti_clk omap_12m_fck = {
3333 .name = "omap_12m_fck",
3334 .type = TI_CLK_FIXED_FACTOR,
3335 .data = &omap_12m_fck_data,
3336};
3337
3338static struct ti_clk_fixed_factor core_12m_fck_data = {
3339 .parent = "omap_12m_fck",
3340 .div = 1,
3341 .mult = 1,
3342};
3343
3344static struct ti_clk core_12m_fck = {
3345 .name = "core_12m_fck",
3346 .type = TI_CLK_FIXED_FACTOR,
3347 .data = &core_12m_fck_data,
3348};
3349
3350static struct ti_clk_gate hdq_fck_data = {
3351 .parent = "core_12m_fck",
3352 .bit_shift = 22,
3353 .reg = 0xa00,
3354 .module = TI_CLKM_CM,
3355 .flags = CLKF_WAIT,
3356};
3357
3358static struct ti_clk hdq_fck = {
3359 .name = "hdq_fck",
3360 .clkdm_name = "core_l4_clkdm",
3361 .type = TI_CLK_GATE,
3362 .data = &hdq_fck_data,
3363};
3364
3365static struct ti_clk_gate usbtll_fck_data = {
3366 .parent = "dpll5_m2_ck",
3367 .bit_shift = 2,
3368 .reg = 0xa08,
3369 .module = TI_CLKM_CM,
3370 .flags = CLKF_WAIT,
3371};
3372
3373static struct ti_clk usbtll_fck = {
3374 .name = "usbtll_fck",
3375 .clkdm_name = "core_l4_clkdm",
3376 .type = TI_CLK_GATE,
3377 .data = &usbtll_fck_data,
3378};
3379
3380static struct ti_clk_gate hsotgusb_fck_am35xx_data = {
3381 .parent = "sys_ck",
3382 .bit_shift = 8,
3383 .reg = 0x59c,
3384 .module = TI_CLKM_SCRM,
3385};
3386
3387static struct ti_clk hsotgusb_fck_am35xx = {
3388 .name = "hsotgusb_fck_am35xx",
3389 .clkdm_name = "core_l3_clkdm",
3390 .type = TI_CLK_GATE,
3391 .data = &hsotgusb_fck_am35xx_data,
3392};
3393
3394static struct ti_clk_gate hsotgusb_ick_3430es2_data = {
3395 .parent = "core_l3_ick",
3396 .bit_shift = 4,
3397 .reg = 0xa10,
3398 .module = TI_CLKM_CM,
3399 .flags = CLKF_HSOTGUSB | CLKF_OMAP3 | CLKF_INTERFACE,
3400};
3401
3402static struct ti_clk hsotgusb_ick_3430es2 = {
3403 .name = "hsotgusb_ick_3430es2",
3404 .clkdm_name = "core_l3_clkdm",
3405 .type = TI_CLK_GATE,
3406 .data = &hsotgusb_ick_3430es2_data,
3407};
3408
3409static struct ti_clk_gate gfx_l3_ck_data = {
3410 .parent = "l3_ick",
3411 .bit_shift = 0,
3412 .reg = 0xb10,
3413 .module = TI_CLKM_CM,
3414 .flags = CLKF_WAIT,
3415};
3416
3417static struct ti_clk gfx_l3_ck = {
3418 .name = "gfx_l3_ck",
3419 .clkdm_name = "gfx_3430es1_clkdm",
3420 .type = TI_CLK_GATE,
3421 .data = &gfx_l3_ck_data,
3422};
3423
3424static struct ti_clk_fixed_factor gfx_l3_ick_data = {
3425 .parent = "gfx_l3_ck",
3426 .div = 1,
3427 .mult = 1,
3428};
3429
3430static struct ti_clk gfx_l3_ick = {
3431 .name = "gfx_l3_ick",
3432 .type = TI_CLK_FIXED_FACTOR,
3433 .data = &gfx_l3_ick_data,
3434};
3435
3436static struct ti_clk_gate mcbsp1_ick_data = {
3437 .parent = "core_l4_ick",
3438 .bit_shift = 9,
3439 .reg = 0xa10,
3440 .module = TI_CLKM_CM,
3441 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3442};
3443
3444static struct ti_clk mcbsp1_ick = {
3445 .name = "mcbsp1_ick",
3446 .clkdm_name = "core_l4_clkdm",
3447 .type = TI_CLK_GATE,
3448 .data = &mcbsp1_ick_data,
3449};
3450
3451static struct ti_clk_fixed_factor gpt12_fck_data = {
3452 .parent = "secure_32k_fck",
3453 .div = 1,
3454 .mult = 1,
3455};
3456
3457static struct ti_clk gpt12_fck = {
3458 .name = "gpt12_fck",
3459 .type = TI_CLK_FIXED_FACTOR,
3460 .data = &gpt12_fck_data,
3461};
3462
3463static struct ti_clk_gate gfx_cg2_ck_data = {
3464 .parent = "gfx_l3_fck",
3465 .bit_shift = 2,
3466 .reg = 0xb00,
3467 .module = TI_CLKM_CM,
3468 .flags = CLKF_WAIT,
3469};
3470
3471static struct ti_clk gfx_cg2_ck = {
3472 .name = "gfx_cg2_ck",
3473 .clkdm_name = "gfx_3430es1_clkdm",
3474 .type = TI_CLK_GATE,
3475 .data = &gfx_cg2_ck_data,
3476};
3477
3478static struct ti_clk_gate i2c2_ick_data = {
3479 .parent = "core_l4_ick",
3480 .bit_shift = 16,
3481 .reg = 0xa10,
3482 .module = TI_CLKM_CM,
3483 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3484};
3485
3486static struct ti_clk i2c2_ick = {
3487 .name = "i2c2_ick",
3488 .clkdm_name = "core_l4_clkdm",
3489 .type = TI_CLK_GATE,
3490 .data = &i2c2_ick_data,
3491};
3492
3493static struct ti_clk_gate gpio4_dbck_data = {
3494 .parent = "per_32k_alwon_fck",
3495 .bit_shift = 15,
3496 .reg = 0x1000,
3497 .module = TI_CLKM_CM,
3498};
3499
3500static struct ti_clk gpio4_dbck = {
3501 .name = "gpio4_dbck",
3502 .clkdm_name = "per_clkdm",
3503 .type = TI_CLK_GATE,
3504 .data = &gpio4_dbck_data,
3505};
3506
3507static struct ti_clk_gate i2c3_fck_data = {
3508 .parent = "core_96m_fck",
3509 .bit_shift = 17,
3510 .reg = 0xa00,
3511 .module = TI_CLKM_CM,
3512 .flags = CLKF_WAIT,
3513};
3514
3515static struct ti_clk i2c3_fck = {
3516 .name = "i2c3_fck",
3517 .clkdm_name = "core_l4_clkdm",
3518 .type = TI_CLK_GATE,
3519 .data = &i2c3_fck_data,
3520};
3521
3522static struct ti_clk_composite gpt3_fck_data = {
3523 .mux = &gpt3_mux_fck_data,
3524 .gate = &gpt3_gate_fck_data,
3525};
3526
3527static struct ti_clk gpt3_fck = {
3528 .name = "gpt3_fck",
3529 .type = TI_CLK_COMPOSITE,
3530 .data = &gpt3_fck_data,
3531};
3532
3533static struct ti_clk_gate i2c1_ick_data = {
3534 .parent = "core_l4_ick",
3535 .bit_shift = 15,
3536 .reg = 0xa10,
3537 .module = TI_CLKM_CM,
3538 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3539};
3540
3541static struct ti_clk i2c1_ick = {
3542 .name = "i2c1_ick",
3543 .clkdm_name = "core_l4_clkdm",
3544 .type = TI_CLK_GATE,
3545 .data = &i2c1_ick_data,
3546};
3547
3548static struct ti_clk_gate omap_32ksync_ick_data = {
3549 .parent = "wkup_l4_ick",
3550 .bit_shift = 2,
3551 .reg = 0xc10,
3552 .module = TI_CLKM_CM,
3553 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3554};
3555
3556static struct ti_clk omap_32ksync_ick = {
3557 .name = "omap_32ksync_ick",
3558 .clkdm_name = "wkup_clkdm",
3559 .type = TI_CLK_GATE,
3560 .data = &omap_32ksync_ick_data,
3561};
3562
3563static struct ti_clk_gate aes2_ick_data = {
3564 .parent = "core_l4_ick",
3565 .bit_shift = 28,
3566 .reg = 0xa10,
3567 .module = TI_CLKM_CM,
3568 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3569};
3570
3571static struct ti_clk aes2_ick = {
3572 .name = "aes2_ick",
3573 .clkdm_name = "core_l4_clkdm",
3574 .type = TI_CLK_GATE,
3575 .data = &aes2_ick_data,
3576};
3577
3578static const char *gpt8_mux_fck_parents[] = {
3579 "omap_32k_fck",
3580 "sys_ck",
3581};
3582
3583static struct ti_clk_mux gpt8_mux_fck_data = {
3584 .bit_shift = 6,
3585 .num_parents = ARRAY_SIZE(gpt8_mux_fck_parents),
3586 .reg = 0x1040,
3587 .module = TI_CLKM_CM,
3588 .parents = gpt8_mux_fck_parents,
3589};
3590
3591static struct ti_clk_composite gpt8_fck_data = {
3592 .mux = &gpt8_mux_fck_data,
3593 .gate = &gpt8_gate_fck_data,
3594};
3595
3596static struct ti_clk gpt8_fck = {
3597 .name = "gpt8_fck",
3598 .type = TI_CLK_COMPOSITE,
3599 .data = &gpt8_fck_data,
3600};
3601
3602static struct ti_clk_gate mcbsp4_gate_fck_data = {
3603 .parent = "mcbsp_clks",
3604 .bit_shift = 2,
3605 .reg = 0x1000,
3606 .module = TI_CLKM_CM,
3607};
3608
3609static struct ti_clk_composite mcbsp4_fck_data = {
3610 .mux = &mcbsp4_mux_fck_data,
3611 .gate = &mcbsp4_gate_fck_data,
3612};
3613
3614static struct ti_clk mcbsp4_fck = {
3615 .name = "mcbsp4_fck",
3616 .type = TI_CLK_COMPOSITE,
3617 .data = &mcbsp4_fck_data,
3618};
3619
3620static struct ti_clk_gate gpio2_dbck_data = {
3621 .parent = "per_32k_alwon_fck",
3622 .bit_shift = 13,
3623 .reg = 0x1000,
3624 .module = TI_CLKM_CM,
3625};
3626
3627static struct ti_clk gpio2_dbck = {
3628 .name = "gpio2_dbck",
3629 .clkdm_name = "per_clkdm",
3630 .type = TI_CLK_GATE,
3631 .data = &gpio2_dbck_data,
3632};
3633
3634static struct ti_clk_gate usbtll_ick_data = {
3635 .parent = "core_l4_ick",
3636 .bit_shift = 2,
3637 .reg = 0xa18,
3638 .module = TI_CLKM_CM,
3639 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3640};
3641
3642static struct ti_clk usbtll_ick = {
3643 .name = "usbtll_ick",
3644 .clkdm_name = "core_l4_clkdm",
3645 .type = TI_CLK_GATE,
3646 .data = &usbtll_ick_data,
3647};
3648
3649static struct ti_clk_gate mcspi4_ick_data = {
3650 .parent = "core_l4_ick",
3651 .bit_shift = 21,
3652 .reg = 0xa10,
3653 .module = TI_CLKM_CM,
3654 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3655};
3656
3657static struct ti_clk mcspi4_ick = {
3658 .name = "mcspi4_ick",
3659 .clkdm_name = "core_l4_clkdm",
3660 .type = TI_CLK_GATE,
3661 .data = &mcspi4_ick_data,
3662};
3663
3664static struct ti_clk_gate dss_96m_fck_data = {
3665 .parent = "omap_96m_fck",
3666 .bit_shift = 2,
3667 .reg = 0xe00,
3668 .module = TI_CLKM_CM,
3669};
3670
3671static struct ti_clk dss_96m_fck = {
3672 .name = "dss_96m_fck",
3673 .clkdm_name = "dss_clkdm",
3674 .type = TI_CLK_GATE,
3675 .data = &dss_96m_fck_data,
3676};
3677
3678static struct ti_clk_divider rm_ick_data = {
3679 .parent = "l4_ick",
3680 .bit_shift = 1,
3681 .max_div = 3,
3682 .reg = 0xc40,
3683 .module = TI_CLKM_CM,
3684 .flags = CLKF_INDEX_STARTS_AT_ONE,
3685};
3686
3687static struct ti_clk rm_ick = {
3688 .name = "rm_ick",
3689 .type = TI_CLK_DIVIDER,
3690 .data = &rm_ick_data,
3691};
3692
3693static struct ti_clk_gate hdq_ick_data = {
3694 .parent = "core_l4_ick",
3695 .bit_shift = 22,
3696 .reg = 0xa10,
3697 .module = TI_CLKM_CM,
3698 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3699};
3700
3701static struct ti_clk hdq_ick = {
3702 .name = "hdq_ick",
3703 .clkdm_name = "core_l4_clkdm",
3704 .type = TI_CLK_GATE,
3705 .data = &hdq_ick_data,
3706};
3707
3708static struct ti_clk_fixed_factor dpll3_x2_ck_data = {
3709 .parent = "dpll3_ck",
3710 .div = 1,
3711 .mult = 2,
3712};
3713
3714static struct ti_clk dpll3_x2_ck = {
3715 .name = "dpll3_x2_ck",
3716 .type = TI_CLK_FIXED_FACTOR,
3717 .data = &dpll3_x2_ck_data,
3718};
3719
3720static struct ti_clk_gate mad2d_ick_data = {
3721 .parent = "l3_ick",
3722 .bit_shift = 3,
3723 .reg = 0xa18,
3724 .module = TI_CLKM_CM,
3725 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3726};
3727
3728static struct ti_clk mad2d_ick = {
3729 .name = "mad2d_ick",
3730 .clkdm_name = "d2d_clkdm",
3731 .type = TI_CLK_GATE,
3732 .data = &mad2d_ick_data,
3733};
3734
3735static struct ti_clk_gate fshostusb_fck_data = {
3736 .parent = "core_48m_fck",
3737 .bit_shift = 5,
3738 .reg = 0xa00,
3739 .module = TI_CLKM_CM,
3740 .flags = CLKF_WAIT,
3741};
3742
3743static struct ti_clk fshostusb_fck = {
3744 .name = "fshostusb_fck",
3745 .clkdm_name = "core_l4_clkdm",
3746 .type = TI_CLK_GATE,
3747 .data = &fshostusb_fck_data,
3748};
3749
3750static struct ti_clk_gate sr1_fck_data = {
3751 .parent = "sys_ck",
3752 .bit_shift = 6,
3753 .reg = 0xc00,
3754 .module = TI_CLKM_CM,
3755 .flags = CLKF_WAIT,
3756};
3757
3758static struct ti_clk sr1_fck = {
3759 .name = "sr1_fck",
3760 .clkdm_name = "wkup_clkdm",
3761 .type = TI_CLK_GATE,
3762 .data = &sr1_fck_data,
3763};
3764
3765static struct ti_clk_gate des2_ick_data = {
3766 .parent = "core_l4_ick",
3767 .bit_shift = 26,
3768 .reg = 0xa10,
3769 .module = TI_CLKM_CM,
3770 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3771};
3772
3773static struct ti_clk des2_ick = {
3774 .name = "des2_ick",
3775 .clkdm_name = "core_l4_clkdm",
3776 .type = TI_CLK_GATE,
3777 .data = &des2_ick_data,
3778};
3779
3780static struct ti_clk_gate sdrc_ick_data = {
3781 .parent = "core_l3_ick",
3782 .bit_shift = 1,
3783 .reg = 0xa10,
3784 .module = TI_CLKM_CM,
3785 .flags = CLKF_WAIT,
3786};
3787
3788static struct ti_clk sdrc_ick = {
3789 .name = "sdrc_ick",
3790 .clkdm_name = "core_l3_clkdm",
3791 .type = TI_CLK_GATE,
3792 .data = &sdrc_ick_data,
3793};
3794
3795static struct ti_clk_composite gpt4_fck_data = {
3796 .mux = &gpt4_mux_fck_data,
3797 .gate = &gpt4_gate_fck_data,
3798};
3799
3800static struct ti_clk gpt4_fck = {
3801 .name = "gpt4_fck",
3802 .type = TI_CLK_COMPOSITE,
3803 .data = &gpt4_fck_data,
3804};
3805
3806static struct ti_clk_gate dpll4_m3x2_ck_omap36xx_data = {
3807 .parent = "dpll4_m3x2_mul_ck",
3808 .bit_shift = 0x1c,
3809 .reg = 0xd00,
3810 .module = TI_CLKM_CM,
3811 .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
3812};
3813
3814static struct ti_clk dpll4_m3x2_ck_omap36xx = {
3815 .name = "dpll4_m3x2_ck",
3816 .type = TI_CLK_GATE,
3817 .data = &dpll4_m3x2_ck_omap36xx_data,
3818 .patch = &dpll4_m3x2_ck,
3819};
3820
3821static struct ti_clk_gate cpefuse_fck_data = {
3822 .parent = "sys_ck",
3823 .bit_shift = 0,
3824 .reg = 0xa08,
3825 .module = TI_CLKM_CM,
3826};
3827
3828static struct ti_clk cpefuse_fck = {
3829 .name = "cpefuse_fck",
3830 .clkdm_name = "core_l4_clkdm",
3831 .type = TI_CLK_GATE,
3832 .data = &cpefuse_fck_data,
3833};
3834
3835static struct ti_clk_gate mcspi3_ick_data = {
3836 .parent = "core_l4_ick",
3837 .bit_shift = 20,
3838 .reg = 0xa10,
3839 .module = TI_CLKM_CM,
3840 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3841};
3842
3843static struct ti_clk mcspi3_ick = {
3844 .name = "mcspi3_ick",
3845 .clkdm_name = "core_l4_clkdm",
3846 .type = TI_CLK_GATE,
3847 .data = &mcspi3_ick_data,
3848};
3849
3850static struct ti_clk_fixed_factor ssi_sst_fck_3430es2_data = {
3851 .parent = "ssi_ssr_fck",
3852 .div = 2,
3853 .mult = 1,
3854};
3855
3856static struct ti_clk ssi_sst_fck_3430es2 = {
3857 .name = "ssi_sst_fck",
3858 .type = TI_CLK_FIXED_FACTOR,
3859 .data = &ssi_sst_fck_3430es2_data,
3860};
3861
3862static struct ti_clk_gate gpio1_dbck_data = {
3863 .parent = "wkup_32k_fck",
3864 .bit_shift = 3,
3865 .reg = 0xc00,
3866 .module = TI_CLKM_CM,
3867};
3868
3869static struct ti_clk gpio1_dbck = {
3870 .name = "gpio1_dbck",
3871 .clkdm_name = "wkup_clkdm",
3872 .type = TI_CLK_GATE,
3873 .data = &gpio1_dbck_data,
3874};
3875
3876static struct ti_clk_gate gpt4_ick_data = {
3877 .parent = "per_l4_ick",
3878 .bit_shift = 5,
3879 .reg = 0x1010,
3880 .module = TI_CLKM_CM,
3881 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3882};
3883
3884static struct ti_clk gpt4_ick = {
3885 .name = "gpt4_ick",
3886 .clkdm_name = "per_clkdm",
3887 .type = TI_CLK_GATE,
3888 .data = &gpt4_ick_data,
3889};
3890
3891static struct ti_clk_gate gpt2_ick_data = {
3892 .parent = "per_l4_ick",
3893 .bit_shift = 3,
3894 .reg = 0x1010,
3895 .module = TI_CLKM_CM,
3896 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3897};
3898
3899static struct ti_clk gpt2_ick = {
3900 .name = "gpt2_ick",
3901 .clkdm_name = "per_clkdm",
3902 .type = TI_CLK_GATE,
3903 .data = &gpt2_ick_data,
3904};
3905
3906static struct ti_clk_gate mmchs1_fck_data = {
3907 .parent = "core_96m_fck",
3908 .bit_shift = 24,
3909 .reg = 0xa00,
3910 .module = TI_CLKM_CM,
3911 .flags = CLKF_WAIT,
3912};
3913
3914static struct ti_clk mmchs1_fck = {
3915 .name = "mmchs1_fck",
3916 .clkdm_name = "core_l4_clkdm",
3917 .type = TI_CLK_GATE,
3918 .data = &mmchs1_fck_data,
3919};
3920
3921static struct ti_clk_fixed dummy_apb_pclk_data = {
3922 .frequency = 0x0,
3923};
3924
3925static struct ti_clk dummy_apb_pclk = {
3926 .name = "dummy_apb_pclk",
3927 .type = TI_CLK_FIXED,
3928 .data = &dummy_apb_pclk_data,
3929};
3930
3931static struct ti_clk_gate gpio6_dbck_data = {
3932 .parent = "per_32k_alwon_fck",
3933 .bit_shift = 17,
3934 .reg = 0x1000,
3935 .module = TI_CLKM_CM,
3936};
3937
3938static struct ti_clk gpio6_dbck = {
3939 .name = "gpio6_dbck",
3940 .clkdm_name = "per_clkdm",
3941 .type = TI_CLK_GATE,
3942 .data = &gpio6_dbck_data,
3943};
3944
3945static struct ti_clk_gate uart2_ick_data = {
3946 .parent = "core_l4_ick",
3947 .bit_shift = 14,
3948 .reg = 0xa10,
3949 .module = TI_CLKM_CM,
3950 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3951};
3952
3953static struct ti_clk uart2_ick = {
3954 .name = "uart2_ick",
3955 .clkdm_name = "core_l4_clkdm",
3956 .type = TI_CLK_GATE,
3957 .data = &uart2_ick_data,
3958};
3959
3960static struct ti_clk_fixed_factor dpll4_x2_ck_data = {
3961 .parent = "dpll4_ck",
3962 .div = 1,
3963 .mult = 2,
3964};
3965
3966static struct ti_clk dpll4_x2_ck = {
3967 .name = "dpll4_x2_ck",
3968 .type = TI_CLK_FIXED_FACTOR,
3969 .data = &dpll4_x2_ck_data,
3970};
3971
3972static struct ti_clk_gate gpt7_ick_data = {
3973 .parent = "per_l4_ick",
3974 .bit_shift = 8,
3975 .reg = 0x1010,
3976 .module = TI_CLKM_CM,
3977 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3978};
3979
3980static struct ti_clk gpt7_ick = {
3981 .name = "gpt7_ick",
3982 .clkdm_name = "per_clkdm",
3983 .type = TI_CLK_GATE,
3984 .data = &gpt7_ick_data,
3985};
3986
3987static struct ti_clk_gate dss_tv_fck_data = {
3988 .parent = "omap_54m_fck",
3989 .bit_shift = 2,
3990 .reg = 0xe00,
3991 .module = TI_CLKM_CM,
3992};
3993
3994static struct ti_clk dss_tv_fck = {
3995 .name = "dss_tv_fck",
3996 .clkdm_name = "dss_clkdm",
3997 .type = TI_CLK_GATE,
3998 .data = &dss_tv_fck_data,
3999};
4000
4001static struct ti_clk_gate mcbsp5_ick_data = {
4002 .parent = "core_l4_ick",
4003 .bit_shift = 10,
4004 .reg = 0xa10,
4005 .module = TI_CLKM_CM,
4006 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4007};
4008
4009static struct ti_clk mcbsp5_ick = {
4010 .name = "mcbsp5_ick",
4011 .clkdm_name = "core_l4_clkdm",
4012 .type = TI_CLK_GATE,
4013 .data = &mcbsp5_ick_data,
4014};
4015
4016static struct ti_clk_gate mcspi1_ick_data = {
4017 .parent = "core_l4_ick",
4018 .bit_shift = 18,
4019 .reg = 0xa10,
4020 .module = TI_CLKM_CM,
4021 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4022};
4023
4024static struct ti_clk mcspi1_ick = {
4025 .name = "mcspi1_ick",
4026 .clkdm_name = "core_l4_clkdm",
4027 .type = TI_CLK_GATE,
4028 .data = &mcspi1_ick_data,
4029};
4030
4031static struct ti_clk_gate d2d_26m_fck_data = {
4032 .parent = "sys_ck",
4033 .bit_shift = 3,
4034 .reg = 0xa00,
4035 .module = TI_CLKM_CM,
4036 .flags = CLKF_WAIT,
4037};
4038
4039static struct ti_clk d2d_26m_fck = {
4040 .name = "d2d_26m_fck",
4041 .clkdm_name = "d2d_clkdm",
4042 .type = TI_CLK_GATE,
4043 .data = &d2d_26m_fck_data,
4044};
4045
4046static struct ti_clk_gate wdt3_ick_data = {
4047 .parent = "per_l4_ick",
4048 .bit_shift = 12,
4049 .reg = 0x1010,
4050 .module = TI_CLKM_CM,
4051 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4052};
4053
4054static struct ti_clk wdt3_ick = {
4055 .name = "wdt3_ick",
4056 .clkdm_name = "per_clkdm",
4057 .type = TI_CLK_GATE,
4058 .data = &wdt3_ick_data,
4059};
4060
4061static struct ti_clk_divider pclkx2_fck_data = {
4062 .parent = "emu_src_ck",
4063 .bit_shift = 6,
4064 .max_div = 3,
4065 .reg = 0x1140,
4066 .module = TI_CLKM_CM,
4067 .flags = CLKF_INDEX_STARTS_AT_ONE,
4068};
4069
4070static struct ti_clk pclkx2_fck = {
4071 .name = "pclkx2_fck",
4072 .type = TI_CLK_DIVIDER,
4073 .data = &pclkx2_fck_data,
4074};
4075
4076static struct ti_clk_gate sha12_ick_data = {
4077 .parent = "core_l4_ick",
4078 .bit_shift = 27,
4079 .reg = 0xa10,
4080 .module = TI_CLKM_CM,
4081 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4082};
4083
4084static struct ti_clk sha12_ick = {
4085 .name = "sha12_ick",
4086 .clkdm_name = "core_l4_clkdm",
4087 .type = TI_CLK_GATE,
4088 .data = &sha12_ick_data,
4089};
4090
4091static struct ti_clk_gate emac_fck_data = {
4092 .parent = "rmii_ck",
4093 .bit_shift = 9,
4094 .reg = 0x59c,
4095 .module = TI_CLKM_SCRM,
4096};
4097
4098static struct ti_clk emac_fck = {
4099 .name = "emac_fck",
4100 .type = TI_CLK_GATE,
4101 .data = &emac_fck_data,
4102};
4103
4104static struct ti_clk_composite gpt10_fck_data = {
4105 .mux = &gpt10_mux_fck_data,
4106 .gate = &gpt10_gate_fck_data,
4107};
4108
4109static struct ti_clk gpt10_fck = {
4110 .name = "gpt10_fck",
4111 .type = TI_CLK_COMPOSITE,
4112 .data = &gpt10_fck_data,
4113};
4114
4115static struct ti_clk_gate wdt2_fck_data = {
4116 .parent = "wkup_32k_fck",
4117 .bit_shift = 5,
4118 .reg = 0xc00,
4119 .module = TI_CLKM_CM,
4120 .flags = CLKF_WAIT,
4121};
4122
4123static struct ti_clk wdt2_fck = {
4124 .name = "wdt2_fck",
4125 .clkdm_name = "wkup_clkdm",
4126 .type = TI_CLK_GATE,
4127 .data = &wdt2_fck_data,
4128};
4129
4130static struct ti_clk_gate cam_ick_data = {
4131 .parent = "l4_ick",
4132 .bit_shift = 0,
4133 .reg = 0xf10,
4134 .module = TI_CLKM_CM,
4135 .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
4136};
4137
4138static struct ti_clk cam_ick = {
4139 .name = "cam_ick",
4140 .clkdm_name = "cam_clkdm",
4141 .type = TI_CLK_GATE,
4142 .data = &cam_ick_data,
4143};
4144
4145static struct ti_clk_gate ssi_ick_3430es2_data = {
4146 .parent = "ssi_l4_ick",
4147 .bit_shift = 0,
4148 .reg = 0xa10,
4149 .module = TI_CLKM_CM,
4150 .flags = CLKF_SSI | CLKF_OMAP3 | CLKF_INTERFACE,
4151};
4152
4153static struct ti_clk ssi_ick_3430es2 = {
4154 .name = "ssi_ick",
4155 .clkdm_name = "core_l4_clkdm",
4156 .type = TI_CLK_GATE,
4157 .data = &ssi_ick_3430es2_data,
4158};
4159
4160static struct ti_clk_gate gpio4_ick_data = {
4161 .parent = "per_l4_ick",
4162 .bit_shift = 15,
4163 .reg = 0x1010,
4164 .module = TI_CLKM_CM,
4165 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4166};
4167
4168static struct ti_clk gpio4_ick = {
4169 .name = "gpio4_ick",
4170 .clkdm_name = "per_clkdm",
4171 .type = TI_CLK_GATE,
4172 .data = &gpio4_ick_data,
4173};
4174
4175static struct ti_clk_gate wdt1_ick_data = {
4176 .parent = "wkup_l4_ick",
4177 .bit_shift = 4,
4178 .reg = 0xc10,
4179 .module = TI_CLKM_CM,
4180 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4181};
4182
4183static struct ti_clk wdt1_ick = {
4184 .name = "wdt1_ick",
4185 .clkdm_name = "wkup_clkdm",
4186 .type = TI_CLK_GATE,
4187 .data = &wdt1_ick_data,
4188};
4189
4190static struct ti_clk_gate rng_ick_data = {
4191 .parent = "security_l4_ick2",
4192 .bit_shift = 2,
4193 .reg = 0xa14,
4194 .module = TI_CLKM_CM,
4195 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4196};
4197
4198static struct ti_clk rng_ick = {
4199 .name = "rng_ick",
4200 .type = TI_CLK_GATE,
4201 .data = &rng_ick_data,
4202};
4203
4204static struct ti_clk_gate icr_ick_data = {
4205 .parent = "core_l4_ick",
4206 .bit_shift = 29,
4207 .reg = 0xa10,
4208 .module = TI_CLKM_CM,
4209 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4210};
4211
4212static struct ti_clk icr_ick = {
4213 .name = "icr_ick",
4214 .clkdm_name = "core_l4_clkdm",
4215 .type = TI_CLK_GATE,
4216 .data = &icr_ick_data,
4217};
4218
4219static struct ti_clk_gate sgx_ick_data = {
4220 .parent = "l3_ick",
4221 .bit_shift = 0,
4222 .reg = 0xb10,
4223 .module = TI_CLKM_CM,
4224 .flags = CLKF_WAIT,
4225};
4226
4227static struct ti_clk sgx_ick = {
4228 .name = "sgx_ick",
4229 .clkdm_name = "sgx_clkdm",
4230 .type = TI_CLK_GATE,
4231 .data = &sgx_ick_data,
4232};
4233
4234static struct ti_clk_divider sys_clkout2_data = {
4235 .parent = "clkout2_src_ck",
4236 .bit_shift = 3,
4237 .max_div = 64,
4238 .reg = 0xd70,
4239 .module = TI_CLKM_CM,
4240 .flags = CLKF_INDEX_POWER_OF_TWO,
4241};
4242
4243static struct ti_clk sys_clkout2 = {
4244 .name = "sys_clkout2",
4245 .type = TI_CLK_DIVIDER,
4246 .data = &sys_clkout2_data,
4247};
4248
4249static struct ti_clk_alias omap34xx_omap36xx_clks[] = {
4250 CLK(NULL, "security_l4_ick2", &security_l4_ick2),
4251 CLK(NULL, "aes1_ick", &aes1_ick),
4252 CLK("omap_rng", "ick", &rng_ick),
4253 CLK("omap3-rom-rng", "ick", &rng_ick),
4254 CLK(NULL, "sha11_ick", &sha11_ick),
4255 CLK(NULL, "des1_ick", &des1_ick),
4256 CLK(NULL, "cam_mclk", &cam_mclk),
4257 CLK(NULL, "cam_ick", &cam_ick),
4258 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
4259 CLK(NULL, "security_l3_ick", &security_l3_ick),
4260 CLK(NULL, "pka_ick", &pka_ick),
4261 CLK(NULL, "icr_ick", &icr_ick),
4262 CLK(NULL, "des2_ick", &des2_ick),
4263 CLK(NULL, "mspro_ick", &mspro_ick),
4264 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
4265 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
4266 CLK(NULL, "sr1_fck", &sr1_fck),
4267 CLK(NULL, "sr2_fck", &sr2_fck),
4268 CLK(NULL, "sr_l4_ick", &sr_l4_ick),
4269 CLK(NULL, "dpll2_fck", &dpll2_fck),
4270 CLK(NULL, "dpll2_ck", &dpll2_ck),
4271 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck),
4272 CLK(NULL, "iva2_ck", &iva2_ck),
4273 CLK(NULL, "modem_fck", &modem_fck),
4274 CLK(NULL, "sad2d_ick", &sad2d_ick),
4275 CLK(NULL, "mad2d_ick", &mad2d_ick),
4276 CLK(NULL, "mspro_fck", &mspro_fck),
4277 { NULL },
4278};
4279
4280static struct ti_clk_alias omap36xx_omap3430es2plus_clks[] = {
4281 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2),
4282 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2),
4283 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2),
4284 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2),
4285 CLK(NULL, "ssi_ick", &ssi_ick_3430es2),
4286 CLK(NULL, "sys_d2_ck", &sys_d2_ck),
4287 CLK(NULL, "omap_96m_d2_fck", &omap_96m_d2_fck),
4288 CLK(NULL, "omap_96m_d4_fck", &omap_96m_d4_fck),
4289 CLK(NULL, "omap_96m_d8_fck", &omap_96m_d8_fck),
4290 CLK(NULL, "omap_96m_d10_fck", &omap_96m_d10_fck),
4291 CLK(NULL, "dpll5_m2_d4_ck", &dpll5_m2_d4_ck),
4292 CLK(NULL, "dpll5_m2_d8_ck", &dpll5_m2_d8_ck),
4293 CLK(NULL, "dpll5_m2_d16_ck", &dpll5_m2_d16_ck),
4294 CLK(NULL, "dpll5_m2_d20_ck", &dpll5_m2_d20_ck),
4295 CLK(NULL, "usim_fck", &usim_fck),
4296 CLK(NULL, "usim_ick", &usim_ick),
4297 { NULL },
4298};
4299
4300static struct ti_clk_alias omap3xxx_clks[] = {
4301 CLK(NULL, "apb_pclk", &dummy_apb_pclk),
4302 CLK(NULL, "omap_32k_fck", &omap_32k_fck),
4303 CLK(NULL, "virt_12m_ck", &virt_12m_ck),
4304 CLK(NULL, "virt_13m_ck", &virt_13m_ck),
4305 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
4306 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
4307 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck),
4308 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck),
4309 CLK(NULL, "osc_sys_ck", &osc_sys_ck),
4310 CLK("twl", "fck", &osc_sys_ck),
4311 CLK(NULL, "sys_ck", &sys_ck),
4312 CLK(NULL, "timer_sys_ck", &sys_ck),
4313 CLK(NULL, "dpll4_ck", &dpll4_ck),
4314 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck),
4315 CLK(NULL, "dpll4_m2x2_mul_ck", &dpll4_m2x2_mul_ck),
4316 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck),
4317 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck),
4318 CLK(NULL, "dpll3_ck", &dpll3_ck),
4319 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck),
4320 CLK(NULL, "dpll3_m3x2_mul_ck", &dpll3_m3x2_mul_ck),
4321 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
4322 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
4323 CLK(NULL, "sys_altclk", &sys_altclk),
4324 CLK(NULL, "sys_clkout1", &sys_clkout1),
4325 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
4326 CLK(NULL, "core_ck", &core_ck),
4327 CLK(NULL, "dpll1_fck", &dpll1_fck),
4328 CLK(NULL, "dpll1_ck", &dpll1_ck),
4329 CLK(NULL, "cpufreq_ck", &dpll1_ck),
4330 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck),
4331 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck),
4332 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck),
4333 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck),
4334 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck),
4335 CLK(NULL, "cm_96m_fck", &cm_96m_fck),
4336 CLK(NULL, "omap_96m_fck", &omap_96m_fck),
4337 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck),
4338 CLK(NULL, "dpll4_m3x2_mul_ck", &dpll4_m3x2_mul_ck),
4339 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck),
4340 CLK(NULL, "omap_54m_fck", &omap_54m_fck),
4341 CLK(NULL, "cm_96m_d2_fck", &cm_96m_d2_fck),
4342 CLK(NULL, "omap_48m_fck", &omap_48m_fck),
4343 CLK(NULL, "omap_12m_fck", &omap_12m_fck),
4344 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck),
4345 CLK(NULL, "dpll4_m4x2_mul_ck", &dpll4_m4x2_mul_ck),
4346 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck),
4347 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck),
4348 CLK(NULL, "dpll4_m5x2_mul_ck", &dpll4_m5x2_mul_ck),
4349 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck),
4350 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck),
4351 CLK(NULL, "dpll4_m6x2_mul_ck", &dpll4_m6x2_mul_ck),
4352 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck),
4353 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck),
4354 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck),
4355 CLK(NULL, "sys_clkout2", &sys_clkout2),
4356 CLK(NULL, "corex2_fck", &corex2_fck),
4357 CLK(NULL, "mpu_ck", &mpu_ck),
4358 CLK(NULL, "arm_fck", &arm_fck),
4359 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
4360 CLK(NULL, "l3_ick", &l3_ick),
4361 CLK(NULL, "l4_ick", &l4_ick),
4362 CLK(NULL, "rm_ick", &rm_ick),
4363 CLK(NULL, "timer_32k_ck", &omap_32k_fck),
4364 CLK(NULL, "gpt10_fck", &gpt10_fck),
4365 CLK(NULL, "gpt11_fck", &gpt11_fck),
4366 CLK(NULL, "core_96m_fck", &core_96m_fck),
4367 CLK(NULL, "mmchs2_fck", &mmchs2_fck),
4368 CLK(NULL, "mmchs1_fck", &mmchs1_fck),
4369 CLK(NULL, "i2c3_fck", &i2c3_fck),
4370 CLK(NULL, "i2c2_fck", &i2c2_fck),
4371 CLK(NULL, "i2c1_fck", &i2c1_fck),
4372 CLK(NULL, "core_48m_fck", &core_48m_fck),
4373 CLK(NULL, "mcspi4_fck", &mcspi4_fck),
4374 CLK(NULL, "mcspi3_fck", &mcspi3_fck),
4375 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
4376 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
4377 CLK(NULL, "uart2_fck", &uart2_fck),
4378 CLK(NULL, "uart1_fck", &uart1_fck),
4379 CLK(NULL, "core_12m_fck", &core_12m_fck),
4380 CLK("omap_hdq.0", "fck", &hdq_fck),
4381 CLK(NULL, "hdq_fck", &hdq_fck),
4382 CLK(NULL, "core_l3_ick", &core_l3_ick),
4383 CLK(NULL, "sdrc_ick", &sdrc_ick),
4384 CLK(NULL, "gpmc_fck", &gpmc_fck),
4385 CLK(NULL, "core_l4_ick", &core_l4_ick),
4386 CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
4387 CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
4388 CLK(NULL, "mmchs2_ick", &mmchs2_ick),
4389 CLK(NULL, "mmchs1_ick", &mmchs1_ick),
4390 CLK("omap_hdq.0", "ick", &hdq_ick),
4391 CLK(NULL, "hdq_ick", &hdq_ick),
4392 CLK("omap2_mcspi.4", "ick", &mcspi4_ick),
4393 CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
4394 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
4395 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
4396 CLK(NULL, "mcspi4_ick", &mcspi4_ick),
4397 CLK(NULL, "mcspi3_ick", &mcspi3_ick),
4398 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
4399 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
4400 CLK("omap_i2c.3", "ick", &i2c3_ick),
4401 CLK("omap_i2c.2", "ick", &i2c2_ick),
4402 CLK("omap_i2c.1", "ick", &i2c1_ick),
4403 CLK(NULL, "i2c3_ick", &i2c3_ick),
4404 CLK(NULL, "i2c2_ick", &i2c2_ick),
4405 CLK(NULL, "i2c1_ick", &i2c1_ick),
4406 CLK(NULL, "uart2_ick", &uart2_ick),
4407 CLK(NULL, "uart1_ick", &uart1_ick),
4408 CLK(NULL, "gpt11_ick", &gpt11_ick),
4409 CLK(NULL, "gpt10_ick", &gpt10_ick),
4410 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
4411 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
4412 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
4413 CLK(NULL, "dss_tv_fck", &dss_tv_fck),
4414 CLK(NULL, "dss_96m_fck", &dss_96m_fck),
4415 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck),
4416 CLK(NULL, "init_60m_fclk", &dummy_ck),
4417 CLK(NULL, "gpt1_fck", &gpt1_fck),
4418 CLK(NULL, "aes2_ick", &aes2_ick),
4419 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
4420 CLK(NULL, "gpio1_dbck", &gpio1_dbck),
4421 CLK(NULL, "sha12_ick", &sha12_ick),
4422 CLK(NULL, "wdt2_fck", &wdt2_fck),
4423 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick),
4424 CLK("omap_wdt", "ick", &wdt2_ick),
4425 CLK(NULL, "wdt2_ick", &wdt2_ick),
4426 CLK(NULL, "wdt1_ick", &wdt1_ick),
4427 CLK(NULL, "gpio1_ick", &gpio1_ick),
4428 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick),
4429 CLK(NULL, "gpt12_ick", &gpt12_ick),
4430 CLK(NULL, "gpt1_ick", &gpt1_ick),
4431 CLK(NULL, "per_96m_fck", &per_96m_fck),
4432 CLK(NULL, "per_48m_fck", &per_48m_fck),
4433 CLK(NULL, "uart3_fck", &uart3_fck),
4434 CLK(NULL, "gpt2_fck", &gpt2_fck),
4435 CLK(NULL, "gpt3_fck", &gpt3_fck),
4436 CLK(NULL, "gpt4_fck", &gpt4_fck),
4437 CLK(NULL, "gpt5_fck", &gpt5_fck),
4438 CLK(NULL, "gpt6_fck", &gpt6_fck),
4439 CLK(NULL, "gpt7_fck", &gpt7_fck),
4440 CLK(NULL, "gpt8_fck", &gpt8_fck),
4441 CLK(NULL, "gpt9_fck", &gpt9_fck),
4442 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck),
4443 CLK(NULL, "gpio6_dbck", &gpio6_dbck),
4444 CLK(NULL, "gpio5_dbck", &gpio5_dbck),
4445 CLK(NULL, "gpio4_dbck", &gpio4_dbck),
4446 CLK(NULL, "gpio3_dbck", &gpio3_dbck),
4447 CLK(NULL, "gpio2_dbck", &gpio2_dbck),
4448 CLK(NULL, "wdt3_fck", &wdt3_fck),
4449 CLK(NULL, "per_l4_ick", &per_l4_ick),
4450 CLK(NULL, "gpio6_ick", &gpio6_ick),
4451 CLK(NULL, "gpio5_ick", &gpio5_ick),
4452 CLK(NULL, "gpio4_ick", &gpio4_ick),
4453 CLK(NULL, "gpio3_ick", &gpio3_ick),
4454 CLK(NULL, "gpio2_ick", &gpio2_ick),
4455 CLK(NULL, "wdt3_ick", &wdt3_ick),
4456 CLK(NULL, "uart3_ick", &uart3_ick),
4457 CLK(NULL, "uart4_ick", &uart4_ick),
4458 CLK(NULL, "gpt9_ick", &gpt9_ick),
4459 CLK(NULL, "gpt8_ick", &gpt8_ick),
4460 CLK(NULL, "gpt7_ick", &gpt7_ick),
4461 CLK(NULL, "gpt6_ick", &gpt6_ick),
4462 CLK(NULL, "gpt5_ick", &gpt5_ick),
4463 CLK(NULL, "gpt4_ick", &gpt4_ick),
4464 CLK(NULL, "gpt3_ick", &gpt3_ick),
4465 CLK(NULL, "gpt2_ick", &gpt2_ick),
4466 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
4467 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
4468 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
4469 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
4470 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
4471 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
4472 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
4473 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
4474 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
4475 CLK(NULL, "mcbsp4_ick", &mcbsp4_ick),
4476 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
4477 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
4478 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
4479 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
4480 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
4481 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
4482 CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck),
4483 CLK("etb", "emu_src_ck", &emu_src_ck),
4484 CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck),
4485 CLK(NULL, "emu_src_ck", &emu_src_ck),
4486 CLK(NULL, "pclk_fck", &pclk_fck),
4487 CLK(NULL, "pclkx2_fck", &pclkx2_fck),
4488 CLK(NULL, "atclk_fck", &atclk_fck),
4489 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck),
4490 CLK(NULL, "traceclk_fck", &traceclk_fck),
4491 CLK(NULL, "secure_32k_fck", &secure_32k_fck),
4492 CLK(NULL, "gpt12_fck", &gpt12_fck),
4493 CLK(NULL, "wdt1_fck", &wdt1_fck),
4494 { NULL },
4495};
4496
4497static struct ti_clk_alias omap36xx_am35xx_omap3430es2plus_clks[] = {
4498 CLK(NULL, "dpll5_ck", &dpll5_ck),
4499 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck),
4500 CLK(NULL, "core_d3_ck", &core_d3_ck),
4501 CLK(NULL, "core_d4_ck", &core_d4_ck),
4502 CLK(NULL, "core_d6_ck", &core_d6_ck),
4503 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck),
4504 CLK(NULL, "core_d2_ck", &core_d2_ck),
4505 CLK(NULL, "corex2_d3_fck", &corex2_d3_fck),
4506 CLK(NULL, "corex2_d5_fck", &corex2_d5_fck),
4507 CLK(NULL, "sgx_fck", &sgx_fck),
4508 CLK(NULL, "sgx_ick", &sgx_ick),
4509 CLK(NULL, "cpefuse_fck", &cpefuse_fck),
4510 CLK(NULL, "ts_fck", &ts_fck),
4511 CLK(NULL, "usbtll_fck", &usbtll_fck),
4512 CLK(NULL, "usbtll_ick", &usbtll_ick),
4513 CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
4514 CLK(NULL, "mmchs3_ick", &mmchs3_ick),
4515 CLK(NULL, "mmchs3_fck", &mmchs3_fck),
4516 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2),
4517 CLK("omapdss_dss", "ick", &dss_ick_3430es2),
4518 CLK(NULL, "dss_ick", &dss_ick_3430es2),
4519 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
4520 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
4521 CLK(NULL, "usbhost_ick", &usbhost_ick),
4522 { NULL },
4523};
4524
4525static struct ti_clk_alias omap3430es1_clks[] = {
4526 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck),
4527 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck),
4528 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick),
4529 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck),
4530 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck),
4531 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck),
4532 CLK(NULL, "fshostusb_fck", &fshostusb_fck),
4533 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1),
4534 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1),
4535 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1),
4536 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1),
4537 CLK(NULL, "fac_ick", &fac_ick),
4538 CLK(NULL, "ssi_ick", &ssi_ick_3430es1),
4539 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
4540 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1),
4541 CLK("omapdss_dss", "ick", &dss_ick_3430es1),
4542 CLK(NULL, "dss_ick", &dss_ick_3430es1),
4543 { NULL },
4544};
4545
4546static struct ti_clk_alias omap36xx_clks[] = {
4547 CLK(NULL, "uart4_fck", &uart4_fck),
4548 { NULL },
4549};
4550
4551static struct ti_clk_alias am35xx_clks[] = {
4552 CLK(NULL, "ipss_ick", &ipss_ick),
4553 CLK(NULL, "rmii_ck", &rmii_ck),
4554 CLK(NULL, "pclk_ck", &pclk_ck),
4555 CLK(NULL, "emac_ick", &emac_ick),
4556 CLK(NULL, "emac_fck", &emac_fck),
4557 CLK("davinci_emac.0", NULL, &emac_ick),
4558 CLK("davinci_mdio.0", NULL, &emac_fck),
4559 CLK("vpfe-capture", "master", &vpfe_ick),
4560 CLK("vpfe-capture", "slave", &vpfe_fck),
4561 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx),
4562 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx),
4563 CLK(NULL, "hecc_ck", &hecc_ck),
4564 CLK(NULL, "uart4_ick", &uart4_ick_am35xx),
4565 CLK(NULL, "uart4_fck", &uart4_fck_am35xx),
4566 { NULL },
4567};
4568
4569static struct ti_clk *omap36xx_clk_patches[] = {
4570 &dpll4_m3x2_ck_omap36xx,
4571 &dpll3_m3x2_ck_omap36xx,
4572 &dpll4_m6x2_ck_omap36xx,
4573 &dpll4_m2x2_ck_omap36xx,
4574 &dpll4_m5x2_ck_omap36xx,
4575 &dpll4_ck_omap36xx,
4576 NULL,
4577};
4578
4579static const char *enable_init_clks[] = {
4580 "sdrc_ick",
4581 "gpmc_fck",
4582 "omapctrl_ick",
4583};
4584
4585static void __init omap3_clk_legacy_common_init(void)
4586{
4587 omap2_clk_disable_autoidle_all();
4588
4589 omap2_clk_enable_init_clocks(enable_init_clks,
4590 ARRAY_SIZE(enable_init_clks));
4591
4592 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
4593 (clk_get_rate(osc_sys_ck.clk) / 1000000),
4594 (clk_get_rate(osc_sys_ck.clk) / 100000) % 10,
4595 (clk_get_rate(core_ck.clk) / 1000000),
4596 (clk_get_rate(arm_fck.clk) / 1000000));
4597}
4598
4599int __init omap3430es1_clk_legacy_init(void)
4600{
4601 int r;
4602
4603 r = ti_clk_register_legacy_clks(omap3430es1_clks);
4604 r |= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
4605 r |= ti_clk_register_legacy_clks(omap3xxx_clks);
4606
4607 omap3_clk_legacy_common_init();
4608
4609 return r;
4610}
4611
4612int __init omap3430_clk_legacy_init(void)
4613{
4614 int r;
4615
4616 r = ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
4617 r |= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks);
4618 r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
4619 r |= ti_clk_register_legacy_clks(omap3xxx_clks);
4620
4621 omap3_clk_legacy_common_init();
4622 omap3_clk_lock_dpll5();
4623
4624 return r;
4625}
4626
4627int __init omap36xx_clk_legacy_init(void)
4628{
4629 int r;
4630
4631 ti_clk_patch_legacy_clks(omap36xx_clk_patches);
4632 r = ti_clk_register_legacy_clks(omap36xx_clks);
4633 r |= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks);
4634 r |= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
4635 r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
4636 r |= ti_clk_register_legacy_clks(omap3xxx_clks);
4637
4638 omap3_clk_legacy_common_init();
4639 omap3_clk_lock_dpll5();
4640
4641 return r;
4642}
4643
4644int __init am35xx_clk_legacy_init(void)
4645{
4646 int r;
4647
4648 r = ti_clk_register_legacy_clks(am35xx_clks);
4649 r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
4650 r |= ti_clk_register_legacy_clks(omap3xxx_clks);
4651
4652 omap3_clk_legacy_common_init();
4653 omap3_clk_lock_dpll5();
4654
4655 return r;
4656}
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index e5a1c8297a1d..f4d6802a8544 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -108,25 +108,77 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
108 struct device_node *node; 108 struct device_node *node;
109 struct clk *clk; 109 struct clk *clk;
110 struct of_phandle_args clkspec; 110 struct of_phandle_args clkspec;
111 char buf[64];
112 char *ptr;
113 char *tags[2];
114 int i;
115 int num_args;
116 int ret;
117 static bool clkctrl_nodes_missing;
118 static bool has_clkctrl_data;
111 119
112 for (c = oclks; c->node_name != NULL; c++) { 120 for (c = oclks; c->node_name != NULL; c++) {
113 node = of_find_node_by_name(NULL, c->node_name); 121 strcpy(buf, c->node_name);
122 ptr = buf;
123 for (i = 0; i < 2; i++)
124 tags[i] = NULL;
125 num_args = 0;
126 while (*ptr) {
127 if (*ptr == ':') {
128 if (num_args >= 2) {
129 pr_warn("Bad number of tags on %s\n",
130 c->node_name);
131 return;
132 }
133 tags[num_args++] = ptr + 1;
134 *ptr = 0;
135 }
136 ptr++;
137 }
138
139 if (num_args && clkctrl_nodes_missing)
140 continue;
141
142 node = of_find_node_by_name(NULL, buf);
143 if (num_args)
144 node = of_find_node_by_name(node, "clk");
114 clkspec.np = node; 145 clkspec.np = node;
146 clkspec.args_count = num_args;
147 for (i = 0; i < num_args; i++) {
148 ret = kstrtoint(tags[i], i ? 10 : 16, clkspec.args + i);
149 if (ret) {
150 pr_warn("Bad tag in %s at %d: %s\n",
151 c->node_name, i, tags[i]);
152 return;
153 }
154 }
115 clk = of_clk_get_from_provider(&clkspec); 155 clk = of_clk_get_from_provider(&clkspec);
116 156
117 if (!IS_ERR(clk)) { 157 if (!IS_ERR(clk)) {
118 c->lk.clk = clk; 158 c->lk.clk = clk;
119 clkdev_add(&c->lk); 159 clkdev_add(&c->lk);
120 } else { 160 } else {
121 pr_warn("failed to lookup clock node %s\n", 161 if (num_args && !has_clkctrl_data) {
122 c->node_name); 162 if (of_find_compatible_node(NULL, NULL,
163 "ti,clkctrl")) {
164 has_clkctrl_data = true;
165 } else {
166 clkctrl_nodes_missing = true;
167
168 pr_warn("missing clkctrl nodes, please update your dts.\n");
169 continue;
170 }
171 }
172
173 pr_warn("failed to lookup clock node %s, ret=%ld\n",
174 c->node_name, PTR_ERR(clk));
123 } 175 }
124 } 176 }
125} 177}
126 178
127struct clk_init_item { 179struct clk_init_item {
128 struct device_node *node; 180 struct device_node *node;
129 struct clk_hw *hw; 181 void *user;
130 ti_of_clk_init_cb_t func; 182 ti_of_clk_init_cb_t func;
131 struct list_head link; 183 struct list_head link;
132}; 184};
@@ -136,14 +188,14 @@ static LIST_HEAD(retry_list);
136/** 188/**
137 * ti_clk_retry_init - retries a failed clock init at later phase 189 * ti_clk_retry_init - retries a failed clock init at later phase
138 * @node: device not for the clock 190 * @node: device not for the clock
139 * @hw: partially initialized clk_hw struct for the clock 191 * @user: user data pointer
140 * @func: init function to be called for the clock 192 * @func: init function to be called for the clock
141 * 193 *
142 * Adds a failed clock init to the retry list. The retry list is parsed 194 * Adds a failed clock init to the retry list. The retry list is parsed
143 * once all the other clocks have been initialized. 195 * once all the other clocks have been initialized.
144 */ 196 */
145int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, 197int __init ti_clk_retry_init(struct device_node *node, void *user,
146 ti_of_clk_init_cb_t func) 198 ti_of_clk_init_cb_t func)
147{ 199{
148 struct clk_init_item *retry; 200 struct clk_init_item *retry;
149 201
@@ -154,7 +206,7 @@ int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
154 206
155 retry->node = node; 207 retry->node = node;
156 retry->func = func; 208 retry->func = func;
157 retry->hw = hw; 209 retry->user = user;
158 list_add(&retry->link, &retry_list); 210 list_add(&retry->link, &retry_list);
159 211
160 return 0; 212 return 0;
@@ -276,7 +328,7 @@ void ti_dt_clk_init_retry_clks(void)
276 while (!list_empty(&retry_list) && retries) { 328 while (!list_empty(&retry_list) && retries) {
277 list_for_each_entry_safe(retry, tmp, &retry_list, link) { 329 list_for_each_entry_safe(retry, tmp, &retry_list, link) {
278 pr_debug("retry-init: %s\n", retry->node->name); 330 pr_debug("retry-init: %s\n", retry->node->name);
279 retry->func(retry->hw, retry->node); 331 retry->func(retry->user, retry->node);
280 list_del(&retry->link); 332 list_del(&retry->link);
281 kfree(retry); 333 kfree(retry);
282 } 334 }
@@ -284,141 +336,6 @@ void ti_dt_clk_init_retry_clks(void)
284 } 336 }
285} 337}
286 338
287#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
288void __init ti_clk_patch_legacy_clks(struct ti_clk **patch)
289{
290 while (*patch) {
291 memcpy((*patch)->patch, *patch, sizeof(**patch));
292 patch++;
293 }
294}
295
296struct clk __init *ti_clk_register_clk(struct ti_clk *setup)
297{
298 struct clk *clk;
299 struct ti_clk_fixed *fixed;
300 struct ti_clk_fixed_factor *fixed_factor;
301 struct clk_hw *clk_hw;
302 int ret;
303
304 if (setup->clk)
305 return setup->clk;
306
307 switch (setup->type) {
308 case TI_CLK_FIXED:
309 fixed = setup->data;
310
311 clk = clk_register_fixed_rate(NULL, setup->name, NULL, 0,
312 fixed->frequency);
313 if (!IS_ERR(clk)) {
314 ret = ti_clk_add_alias(NULL, clk, setup->name);
315 if (ret) {
316 clk_unregister(clk);
317 clk = ERR_PTR(ret);
318 }
319 }
320 break;
321 case TI_CLK_MUX:
322 clk = ti_clk_register_mux(setup);
323 break;
324 case TI_CLK_DIVIDER:
325 clk = ti_clk_register_divider(setup);
326 break;
327 case TI_CLK_COMPOSITE:
328 clk = ti_clk_register_composite(setup);
329 break;
330 case TI_CLK_FIXED_FACTOR:
331 fixed_factor = setup->data;
332
333 clk = clk_register_fixed_factor(NULL, setup->name,
334 fixed_factor->parent,
335 0, fixed_factor->mult,
336 fixed_factor->div);
337 if (!IS_ERR(clk)) {
338 ret = ti_clk_add_alias(NULL, clk, setup->name);
339 if (ret) {
340 clk_unregister(clk);
341 clk = ERR_PTR(ret);
342 }
343 }
344 break;
345 case TI_CLK_GATE:
346 clk = ti_clk_register_gate(setup);
347 break;
348 case TI_CLK_DPLL:
349 clk = ti_clk_register_dpll(setup);
350 break;
351 default:
352 pr_err("bad type for %s!\n", setup->name);
353 clk = ERR_PTR(-EINVAL);
354 }
355
356 if (!IS_ERR(clk)) {
357 setup->clk = clk;
358 if (setup->clkdm_name) {
359 clk_hw = __clk_get_hw(clk);
360 if (clk_hw_get_flags(clk_hw) & CLK_IS_BASIC) {
361 pr_warn("can't setup clkdm for basic clk %s\n",
362 setup->name);
363 } else {
364 to_clk_hw_omap(clk_hw)->clkdm_name =
365 setup->clkdm_name;
366 omap2_init_clk_clkdm(clk_hw);
367 }
368 }
369 }
370
371 return clk;
372}
373
374int __init ti_clk_register_legacy_clks(struct ti_clk_alias *clks)
375{
376 struct clk *clk;
377 bool retry;
378 struct ti_clk_alias *retry_clk;
379 struct ti_clk_alias *tmp;
380
381 while (clks->clk) {
382 clk = ti_clk_register_clk(clks->clk);
383 if (IS_ERR(clk)) {
384 if (PTR_ERR(clk) == -EAGAIN) {
385 list_add(&clks->link, &retry_list);
386 } else {
387 pr_err("register for %s failed: %ld\n",
388 clks->clk->name, PTR_ERR(clk));
389 return PTR_ERR(clk);
390 }
391 }
392 clks++;
393 }
394
395 retry = true;
396
397 while (!list_empty(&retry_list) && retry) {
398 retry = false;
399 list_for_each_entry_safe(retry_clk, tmp, &retry_list, link) {
400 pr_debug("retry-init: %s\n", retry_clk->clk->name);
401 clk = ti_clk_register_clk(retry_clk->clk);
402 if (IS_ERR(clk)) {
403 if (PTR_ERR(clk) == -EAGAIN) {
404 continue;
405 } else {
406 pr_err("register for %s failed: %ld\n",
407 retry_clk->clk->name,
408 PTR_ERR(clk));
409 return PTR_ERR(clk);
410 }
411 } else {
412 retry = true;
413 list_del(&retry_clk->link);
414 }
415 }
416 }
417
418 return 0;
419}
420#endif
421
422static const struct of_device_id simple_clk_match_table[] __initconst = { 339static const struct of_device_id simple_clk_match_table[] __initconst = {
423 { .compatible = "fixed-clock" }, 340 { .compatible = "fixed-clock" },
424 { .compatible = "fixed-factor-clock" }, 341 { .compatible = "fixed-factor-clock" },
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
index 53e71d0503ec..38dbcc1b7e2c 100644
--- a/drivers/clk/ti/clkctrl.c
+++ b/drivers/clk/ti/clkctrl.c
@@ -21,6 +21,7 @@
21#include <linux/of_address.h> 21#include <linux/of_address.h>
22#include <linux/clk/ti.h> 22#include <linux/clk/ti.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/timekeeping.h>
24#include "clock.h" 25#include "clock.h"
25 26
26#define NO_IDLEST 0x1 27#define NO_IDLEST 0x1
@@ -46,6 +47,7 @@ static bool _early_timeout = true;
46struct omap_clkctrl_provider { 47struct omap_clkctrl_provider {
47 void __iomem *base; 48 void __iomem *base;
48 struct list_head clocks; 49 struct list_head clocks;
50 char *clkdm_name;
49}; 51};
50 52
51struct omap_clkctrl_clk { 53struct omap_clkctrl_clk {
@@ -89,7 +91,18 @@ static bool _omap4_is_ready(u32 val)
89 91
90static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout) 92static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout)
91{ 93{
92 if (unlikely(_early_timeout)) { 94 /*
95 * There are two special cases where ktime_to_ns() can't be
96 * used to track the timeouts. First one is during early boot
97 * when the timers haven't been initialized yet. The second
98 * one is during suspend-resume cycle while timekeeping is
99 * being suspended / resumed. Clocksource for the system
100 * can be from a timer that requires pm_runtime access, which
101 * will eventually bring us here with timekeeping_suspended,
102 * during both suspend entry and resume paths. This happens
103 * at least on am43xx platform.
104 */
105 if (unlikely(_early_timeout || timekeeping_suspended)) {
93 if (time->cycles++ < timeout) { 106 if (time->cycles++ < timeout) {
94 udelay(1); 107 udelay(1);
95 return false; 108 return false;
@@ -208,6 +221,7 @@ static const struct clk_ops omap4_clkctrl_clk_ops = {
208 .enable = _omap4_clkctrl_clk_enable, 221 .enable = _omap4_clkctrl_clk_enable,
209 .disable = _omap4_clkctrl_clk_disable, 222 .disable = _omap4_clkctrl_clk_disable,
210 .is_enabled = _omap4_clkctrl_clk_is_enabled, 223 .is_enabled = _omap4_clkctrl_clk_is_enabled,
224 .init = omap2_init_clk_clkdm,
211}; 225};
212 226
213static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec, 227static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
@@ -351,8 +365,8 @@ _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
351 if (ti_clk_parse_divider_data((int *)div_data->dividers, 365 if (ti_clk_parse_divider_data((int *)div_data->dividers,
352 div_data->max_div, 0, 0, 366 div_data->max_div, 0, 0,
353 &div->width, &div->table)) { 367 &div->width, &div->table)) {
354 pr_err("%s: Data parsing for %s:%04x:%d failed\n", __func__, 368 pr_err("%s: Data parsing for %pOF:%04x:%d failed\n", __func__,
355 node->name, offset, data->bit); 369 node, offset, data->bit);
356 kfree(div); 370 kfree(div);
357 return; 371 return;
358 } 372 }
@@ -428,7 +442,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
428 } 442 }
429 443
430 if (!data->addr) { 444 if (!data->addr) {
431 pr_err("%s not found from clkctrl data.\n", node->name); 445 pr_err("%pOF not found from clkctrl data.\n", node);
432 return; 446 return;
433 } 447 }
434 448
@@ -438,6 +452,21 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
438 452
439 provider->base = of_iomap(node, 0); 453 provider->base = of_iomap(node, 0);
440 454
455 provider->clkdm_name = kmalloc(strlen(node->parent->name) + 3,
456 GFP_KERNEL);
457 if (!provider->clkdm_name) {
458 kfree(provider);
459 return;
460 }
461
462 /*
463 * Create default clkdm name, replace _cm from end of parent node
464 * name with _clkdm
465 */
466 strcpy(provider->clkdm_name, node->parent->name);
467 provider->clkdm_name[strlen(provider->clkdm_name) - 2] = 0;
468 strcat(provider->clkdm_name, "clkdm");
469
441 INIT_LIST_HEAD(&provider->clocks); 470 INIT_LIST_HEAD(&provider->clocks);
442 471
443 /* Generate clocks */ 472 /* Generate clocks */
@@ -460,6 +489,11 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
460 if (reg_data->flags & CLKF_NO_IDLEST) 489 if (reg_data->flags & CLKF_NO_IDLEST)
461 hw->flags |= NO_IDLEST; 490 hw->flags |= NO_IDLEST;
462 491
492 if (reg_data->clkdm_name)
493 hw->clkdm_name = reg_data->clkdm_name;
494 else
495 hw->clkdm_name = provider->clkdm_name;
496
463 init.parent_names = &reg_data->parent; 497 init.parent_names = &reg_data->parent;
464 init.num_parents = 1; 498 init.num_parents = 1;
465 init.flags = 0; 499 init.flags = 0;
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 561dbe99ced7..1654da96ad65 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -92,17 +92,6 @@ struct ti_clk {
92 struct clk *clk; 92 struct clk *clk;
93}; 93};
94 94
95struct ti_clk_alias {
96 struct ti_clk *clk;
97 struct clk_lookup lk;
98 struct list_head link;
99};
100
101struct ti_clk_fixed {
102 u32 frequency;
103 u16 flags;
104};
105
106struct ti_clk_mux { 95struct ti_clk_mux {
107 u8 bit_shift; 96 u8 bit_shift;
108 int num_parents; 97 int num_parents;
@@ -123,13 +112,6 @@ struct ti_clk_divider {
123 u16 flags; 112 u16 flags;
124}; 113};
125 114
126struct ti_clk_fixed_factor {
127 const char *parent;
128 u16 div;
129 u16 mult;
130 u16 flags;
131};
132
133struct ti_clk_gate { 115struct ti_clk_gate {
134 const char *parent; 116 const char *parent;
135 u8 bit_shift; 117 u8 bit_shift;
@@ -138,44 +120,6 @@ struct ti_clk_gate {
138 u16 flags; 120 u16 flags;
139}; 121};
140 122
141struct ti_clk_composite {
142 struct ti_clk_divider *divider;
143 struct ti_clk_mux *mux;
144 struct ti_clk_gate *gate;
145 u16 flags;
146};
147
148struct ti_clk_clkdm_gate {
149 const char *parent;
150 u16 flags;
151};
152
153struct ti_clk_dpll {
154 int num_parents;
155 u16 control_reg;
156 u16 idlest_reg;
157 u16 autoidle_reg;
158 u16 mult_div1_reg;
159 u8 module;
160 const char **parents;
161 u16 flags;
162 u8 modes;
163 u32 mult_mask;
164 u32 div1_mask;
165 u32 enable_mask;
166 u32 autoidle_mask;
167 u32 freqsel_mask;
168 u32 idlest_mask;
169 u32 dco_mask;
170 u32 sddiv_mask;
171 u16 max_multiplier;
172 u16 max_divider;
173 u8 min_divider;
174 u8 auto_recal_bit;
175 u8 recal_en_bit;
176 u8 recal_st_bit;
177};
178
179/* Composite clock component types */ 123/* Composite clock component types */
180enum { 124enum {
181 CLK_COMPONENT_TYPE_GATE = 0, 125 CLK_COMPONENT_TYPE_GATE = 0,
@@ -221,6 +165,7 @@ struct omap_clkctrl_reg_data {
221 const struct omap_clkctrl_bit_data *bit_data; 165 const struct omap_clkctrl_bit_data *bit_data;
222 u16 flags; 166 u16 flags;
223 const char *parent; 167 const char *parent;
168 const char *clkdm_name;
224}; 169};
225 170
226struct omap_clkctrl_data { 171struct omap_clkctrl_data {
@@ -234,35 +179,23 @@ extern const struct omap_clkctrl_data omap4_clkctrl_data[];
234#define CLKF_HW_SUP BIT(1) 179#define CLKF_HW_SUP BIT(1)
235#define CLKF_NO_IDLEST BIT(2) 180#define CLKF_NO_IDLEST BIT(2)
236 181
237typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *); 182typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
238 183
239struct clk *ti_clk_register_gate(struct ti_clk *setup);
240struct clk *ti_clk_register_interface(struct ti_clk *setup);
241struct clk *ti_clk_register_mux(struct ti_clk *setup);
242struct clk *ti_clk_register_divider(struct ti_clk *setup);
243struct clk *ti_clk_register_composite(struct ti_clk *setup);
244struct clk *ti_clk_register_dpll(struct ti_clk *setup);
245struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, 184struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
246 const char *con); 185 const char *con);
247int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con); 186int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
248void ti_clk_add_aliases(void); 187void ti_clk_add_aliases(void);
249 188
250struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup);
251struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup);
252struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup); 189struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
253 190
254int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, 191int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
255 u8 flags, u8 *width, 192 u8 flags, u8 *width,
256 const struct clk_div_table **table); 193 const struct clk_div_table **table);
257 194
258void ti_clk_patch_legacy_clks(struct ti_clk **patch);
259struct clk *ti_clk_register_clk(struct ti_clk *setup);
260int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
261
262int ti_clk_get_reg_addr(struct device_node *node, int index, 195int ti_clk_get_reg_addr(struct device_node *node, int index,
263 struct clk_omap_reg *reg); 196 struct clk_omap_reg *reg);
264void ti_dt_clocks_register(struct ti_dt_clk *oclks); 197void ti_dt_clocks_register(struct ti_dt_clk *oclks);
265int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, 198int ti_clk_retry_init(struct device_node *node, void *user,
266 ti_of_clk_init_cb_t func); 199 ti_of_clk_init_cb_t func);
267int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); 200int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
268 201
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index beea89463ca2..030e8b2c1050 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -116,54 +116,10 @@ static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx)
116 116
117#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw) 117#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw)
118 118
119#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS) 119static void __init _register_composite(void *user,
120struct clk *ti_clk_register_composite(struct ti_clk *setup)
121{
122 struct ti_clk_composite *comp;
123 struct clk_hw *gate;
124 struct clk_hw *mux;
125 struct clk_hw *div;
126 int num_parents = 1;
127 const char * const *parent_names = NULL;
128 struct clk *clk;
129 int ret;
130
131 comp = setup->data;
132
133 div = ti_clk_build_component_div(comp->divider);
134 gate = ti_clk_build_component_gate(comp->gate);
135 mux = ti_clk_build_component_mux(comp->mux);
136
137 if (div)
138 parent_names = &comp->divider->parent;
139
140 if (gate)
141 parent_names = &comp->gate->parent;
142
143 if (mux) {
144 num_parents = comp->mux->num_parents;
145 parent_names = comp->mux->parents;
146 }
147
148 clk = clk_register_composite(NULL, setup->name,
149 parent_names, num_parents, mux,
150 &ti_clk_mux_ops, div,
151 &ti_composite_divider_ops, gate,
152 &ti_composite_gate_ops, 0);
153
154 ret = ti_clk_add_alias(NULL, clk, setup->name);
155 if (ret) {
156 clk_unregister(clk);
157 return ERR_PTR(ret);
158 }
159
160 return clk;
161}
162#endif
163
164static void __init _register_composite(struct clk_hw *hw,
165 struct device_node *node) 120 struct device_node *node)
166{ 121{
122 struct clk_hw *hw = user;
167 struct clk *clk; 123 struct clk *clk;
168 struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw); 124 struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw);
169 struct component_clk *comp; 125 struct component_clk *comp;
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index d4e4444bc5ca..7d33ca9042cb 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -152,9 +152,10 @@ static const struct clk_ops dpll_x2_ck_ops = {
152 * clk-bypass is missing), the clock is added to retry list and 152 * clk-bypass is missing), the clock is added to retry list and
153 * the initialization is retried on later stage. 153 * the initialization is retried on later stage.
154 */ 154 */
155static void __init _register_dpll(struct clk_hw *hw, 155static void __init _register_dpll(void *user,
156 struct device_node *node) 156 struct device_node *node)
157{ 157{
158 struct clk_hw *hw = user;
158 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); 159 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
159 struct dpll_data *dd = clk_hw->dpll_data; 160 struct dpll_data *dd = clk_hw->dpll_data;
160 struct clk *clk; 161 struct clk *clk;
@@ -202,96 +203,6 @@ cleanup:
202 kfree(clk_hw); 203 kfree(clk_hw);
203} 204}
204 205
205#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
206void _get_reg(u8 module, u16 offset, struct clk_omap_reg *reg)
207{
208 reg->index = module;
209 reg->offset = offset;
210}
211
212struct clk *ti_clk_register_dpll(struct ti_clk *setup)
213{
214 struct clk_hw_omap *clk_hw;
215 struct clk_init_data init = { NULL };
216 struct dpll_data *dd;
217 struct clk *clk;
218 struct ti_clk_dpll *dpll;
219 const struct clk_ops *ops = &omap3_dpll_ck_ops;
220 struct clk *clk_ref;
221 struct clk *clk_bypass;
222
223 dpll = setup->data;
224
225 if (dpll->num_parents < 2)
226 return ERR_PTR(-EINVAL);
227
228 clk_ref = clk_get_sys(NULL, dpll->parents[0]);
229 clk_bypass = clk_get_sys(NULL, dpll->parents[1]);
230
231 if (IS_ERR_OR_NULL(clk_ref) || IS_ERR_OR_NULL(clk_bypass))
232 return ERR_PTR(-EAGAIN);
233
234 dd = kzalloc(sizeof(*dd), GFP_KERNEL);
235 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
236 if (!dd || !clk_hw) {
237 clk = ERR_PTR(-ENOMEM);
238 goto cleanup;
239 }
240
241 clk_hw->dpll_data = dd;
242 clk_hw->ops = &clkhwops_omap3_dpll;
243 clk_hw->hw.init = &init;
244
245 init.name = setup->name;
246 init.ops = ops;
247
248 init.num_parents = dpll->num_parents;
249 init.parent_names = dpll->parents;
250
251 _get_reg(dpll->module, dpll->control_reg, &dd->control_reg);
252 _get_reg(dpll->module, dpll->idlest_reg, &dd->idlest_reg);
253 _get_reg(dpll->module, dpll->mult_div1_reg, &dd->mult_div1_reg);
254 _get_reg(dpll->module, dpll->autoidle_reg, &dd->autoidle_reg);
255
256 dd->modes = dpll->modes;
257 dd->div1_mask = dpll->div1_mask;
258 dd->idlest_mask = dpll->idlest_mask;
259 dd->mult_mask = dpll->mult_mask;
260 dd->autoidle_mask = dpll->autoidle_mask;
261 dd->enable_mask = dpll->enable_mask;
262 dd->sddiv_mask = dpll->sddiv_mask;
263 dd->dco_mask = dpll->dco_mask;
264 dd->max_divider = dpll->max_divider;
265 dd->min_divider = dpll->min_divider;
266 dd->max_multiplier = dpll->max_multiplier;
267 dd->auto_recal_bit = dpll->auto_recal_bit;
268 dd->recal_en_bit = dpll->recal_en_bit;
269 dd->recal_st_bit = dpll->recal_st_bit;
270
271 dd->clk_ref = __clk_get_hw(clk_ref);
272 dd->clk_bypass = __clk_get_hw(clk_bypass);
273
274 if (dpll->flags & CLKF_CORE)
275 ops = &omap3_dpll_core_ck_ops;
276
277 if (dpll->flags & CLKF_PER)
278 ops = &omap3_dpll_per_ck_ops;
279
280 if (dpll->flags & CLKF_J_TYPE)
281 dd->flags |= DPLL_J_TYPE;
282
283 clk = ti_clk_register(NULL, &clk_hw->hw, setup->name);
284
285 if (!IS_ERR(clk))
286 return clk;
287
288cleanup:
289 kfree(dd);
290 kfree(clk_hw);
291 return clk;
292}
293#endif
294
295#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 206#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
296 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \ 207 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
297 defined(CONFIG_SOC_AM43XX) 208 defined(CONFIG_SOC_AM43XX)
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
index 7151ec3a1b07..935b2de5fb88 100644
--- a/drivers/clk/ti/gate.c
+++ b/drivers/clk/ti/gate.c
@@ -128,53 +128,6 @@ static struct clk *_register_gate(struct device *dev, const char *name,
128 return clk; 128 return clk;
129} 129}
130 130
131#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
132struct clk *ti_clk_register_gate(struct ti_clk *setup)
133{
134 const struct clk_ops *ops = &omap_gate_clk_ops;
135 const struct clk_hw_omap_ops *hw_ops = NULL;
136 struct clk_omap_reg reg;
137 u32 flags = 0;
138 u8 clk_gate_flags = 0;
139 struct ti_clk_gate *gate;
140
141 gate = setup->data;
142
143 if (gate->flags & CLKF_INTERFACE)
144 return ti_clk_register_interface(setup);
145
146 if (gate->flags & CLKF_SET_RATE_PARENT)
147 flags |= CLK_SET_RATE_PARENT;
148
149 if (gate->flags & CLKF_SET_BIT_TO_DISABLE)
150 clk_gate_flags |= INVERT_ENABLE;
151
152 if (gate->flags & CLKF_HSDIV) {
153 ops = &omap_gate_clk_hsdiv_restore_ops;
154 hw_ops = &clkhwops_wait;
155 }
156
157 if (gate->flags & CLKF_DSS)
158 hw_ops = &clkhwops_omap3430es2_dss_usbhost_wait;
159
160 if (gate->flags & CLKF_WAIT)
161 hw_ops = &clkhwops_wait;
162
163 if (gate->flags & CLKF_CLKDM)
164 ops = &omap_gate_clkdm_clk_ops;
165
166 if (gate->flags & CLKF_AM35XX)
167 hw_ops = &clkhwops_am35xx_ipss_module_wait;
168
169 reg.index = gate->module;
170 reg.offset = gate->reg;
171 reg.ptr = NULL;
172
173 return _register_gate(NULL, setup->name, gate->parent, flags,
174 &reg, gate->bit_shift,
175 clk_gate_flags, ops, hw_ops);
176}
177
178struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup) 131struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup)
179{ 132{
180 struct clk_hw_omap *gate; 133 struct clk_hw_omap *gate;
@@ -204,7 +157,6 @@ struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup)
204 157
205 return &gate->hw; 158 return &gate->hw;
206} 159}
207#endif
208 160
209static void __init _of_ti_gate_clk_setup(struct device_node *node, 161static void __init _of_ti_gate_clk_setup(struct device_node *node,
210 const struct clk_ops *ops, 162 const struct clk_ops *ops,
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
index 62cf50c1e1e3..41ae7021670e 100644
--- a/drivers/clk/ti/interface.c
+++ b/drivers/clk/ti/interface.c
@@ -67,38 +67,6 @@ static struct clk *_register_interface(struct device *dev, const char *name,
67 return clk; 67 return clk;
68} 68}
69 69
70#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
71struct clk *ti_clk_register_interface(struct ti_clk *setup)
72{
73 const struct clk_hw_omap_ops *ops = &clkhwops_iclk_wait;
74 struct clk_omap_reg reg;
75 struct ti_clk_gate *gate;
76
77 gate = setup->data;
78 reg.index = gate->module;
79 reg.offset = gate->reg;
80 reg.ptr = NULL;
81
82 if (gate->flags & CLKF_NO_WAIT)
83 ops = &clkhwops_iclk;
84
85 if (gate->flags & CLKF_HSOTGUSB)
86 ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait;
87
88 if (gate->flags & CLKF_DSS)
89 ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait;
90
91 if (gate->flags & CLKF_SSI)
92 ops = &clkhwops_omap3430es2_iclk_ssi_wait;
93
94 if (gate->flags & CLKF_AM35XX)
95 ops = &clkhwops_am35xx_ipss_wait;
96
97 return _register_interface(NULL, setup->name, gate->parent,
98 &reg, gate->bit_shift, ops);
99}
100#endif
101
102static void __init _of_ti_interface_clk_setup(struct device_node *node, 70static void __init _of_ti_interface_clk_setup(struct device_node *node,
103 const struct clk_hw_omap_ops *ops) 71 const struct clk_hw_omap_ops *ops)
104{ 72{
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 16:25:41 -0400