2 files changed, 17 insertions, 1 deletions

diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
index 9acccb1e3746..d3842791e1c4 100644
--- a/arch/arm64/include/asm/kvm_emulate.h
+++ b/arch/arm64/include/asm/kvm_emulate.h
@@ -78,7 +78,8 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
         if (!vcpu_el1_is_32bit(vcpu))
                 vcpu->arch.hcr_el2 |= HCR_TID3;
 
-        if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE))
+        if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) ||
+            vcpu_el1_is_32bit(vcpu))
                 vcpu->arch.hcr_el2 |= HCR_TID2;
 }
 
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 45a07cfc57ed..81a342679e60 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1186,6 +1186,21 @@ static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 
         csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
         p->regval = get_ccsidr(csselr);
+
+        /*
+         * Guests should not be doing cache operations by set/way at all, and
+         * for this reason, we trap them and attempt to infer the intent, so
+         * that we can flush the entire guest's address space at the appropriate
+         * time.
+         * To prevent this trapping from causing performance problems, let's
+         * expose the geometry of all data and unified caches (which are
+         * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
+         * [If guests should attempt to infer aliasing properties from the
+         * geometry (which is not permitted by the architecture), they would
+         * only do so for virtually indexed caches.]
+         */
+        if (!(csselr & 1)) // data or unified cache
+                p->regval &= ~GENMASK(27, 3);
         return true;
 }